diff --git a/llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.intersect_ray.ll b/llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.intersect_ray.ll deleted file mode 100644 --- a/llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.intersect_ray.ll +++ /dev/null @@ -1,1099 +0,0 @@ -; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py -; RUN: llc -global-isel -march=amdgcn -mcpu=gfx1030 -verify-machineinstrs < %s | FileCheck -check-prefixes=GCN,GFX10,GFX1030 %s -; RUN: llc -global-isel -march=amdgcn -mcpu=gfx1013 -verify-machineinstrs < %s | FileCheck -check-prefixes=GCN,GFX10,GFX1013 %s -; RUN: llc -global-isel -march=amdgcn -mcpu=gfx1100 -verify-machineinstrs < %s | FileCheck -check-prefixes=GCN,GFX11 %s -; RUN: not --crash llc -global-isel -march=amdgcn -mcpu=gfx1012 -verify-machineinstrs < %s -o /dev/null 2>&1 | FileCheck -check-prefix=ERR %s - -; uint4 llvm.amdgcn.image.bvh.intersect.ray.i32.v4f32(uint node_ptr, float ray_extent, float3 ray_origin, float3 ray_dir, float3 ray_inv_dir, uint4 texture_descr) -; uint4 llvm.amdgcn.image.bvh.intersect.ray.i32.v4f16(uint node_ptr, float ray_extent, float3 ray_origin, half3 ray_dir, half3 ray_inv_dir, uint4 texture_descr) -; uint4 llvm.amdgcn.image.bvh.intersect.ray.i64.v4f32(ulong node_ptr, float ray_extent, float3 ray_origin, float3 ray_dir, float3 ray_inv_dir, uint4 texture_descr) -; uint4 llvm.amdgcn.image.bvh.intersect.ray.i64.v4f16(ulong node_ptr, float ray_extent, float3 ray_origin, half3 ray_dir, half3 ray_inv_dir, uint4 texture_descr) - -declare <4 x i32> @llvm.amdgcn.image.bvh.intersect.ray.i32.v4f32(i32, float, <3 x float>, <3 x float>, <3 x float>, <4 x i32>) -declare <4 x i32> @llvm.amdgcn.image.bvh.intersect.ray.i32.v4f16(i32, float, <3 x float>, <3 x half>, <3 x half>, <4 x i32>) -declare <4 x i32> @llvm.amdgcn.image.bvh.intersect.ray.i64.v4f32(i64, float, <3 x float>, <3 x float>, <3 x float>, <4 x i32>) -declare <4 x i32> @llvm.amdgcn.image.bvh.intersect.ray.i64.v4f16(i64, float, <3 x float>, <3 x half>, <3 x half>, <4 x i32>) -declare i32 @llvm.amdgcn.workitem.id.x() - -define amdgpu_ps <4 x float> @image_bvh_intersect_ray(i32 %node_ptr, float %ray_extent, <3 x float> %ray_origin, <3 x float> %ray_dir, <3 x float> %ray_inv_dir, <4 x i32> inreg %tdescr) { -; GCN-LABEL: image_bvh_intersect_ray: -; GCN: ; %bb.0: -; GCN-NEXT: image_bvh_intersect_ray v[0:3], v[0:10], s[0:3] -; GCN-NEXT: s_waitcnt vmcnt(0) -; GCN-NEXT: ; return to shader part epilog -; ERR: in function image_bvh_intersect_ray{{.*}}intrinsic not supported on subtarget - %v = call <4 x i32> @llvm.amdgcn.image.bvh.intersect.ray.i32.v4f32(i32 %node_ptr, float %ray_extent, <3 x float> %ray_origin, <3 x float> %ray_dir, <3 x float> %ray_inv_dir, <4 x i32> %tdescr) - %r = bitcast <4 x i32> %v to <4 x float> - ret <4 x float> %r -} - -define amdgpu_ps <4 x float> @image_bvh_intersect_ray_flat(i32 %node_ptr, float %ray_extent, float %ray_origin_x, float %ray_origin_y, float %ray_origin_z, float %ray_dir_x, float %ray_dir_y, float %ray_dir_z, float %ray_inv_dir_x, float %ray_inv_dir_y, float %ray_inv_dir_z, <4 x i32> inreg %tdescr) { -; GCN-LABEL: image_bvh_intersect_ray_flat: -; GCN: ; %bb.0: -; GCN-NEXT: image_bvh_intersect_ray v[0:3], v[0:10], s[0:3] -; GCN-NEXT: s_waitcnt vmcnt(0) -; GCN-NEXT: ; return to shader part epilog - %ray_origin0 = insertelement <3 x float> undef, float %ray_origin_x, i32 0 - %ray_origin1 = insertelement <3 x float> %ray_origin0, float %ray_origin_y, i32 1 - %ray_origin = insertelement <3 x float> %ray_origin1, float %ray_origin_z, i32 2 - %ray_dir0 = insertelement <3 x float> undef, float %ray_dir_x, i32 0 - %ray_dir1 = insertelement <3 x float> %ray_dir0, float %ray_dir_y, i32 1 - %ray_dir = insertelement <3 x float> %ray_dir1, float %ray_dir_z, i32 2 - %ray_inv_dir0 = insertelement <3 x float> undef, float %ray_inv_dir_x, i32 0 - %ray_inv_dir1 = insertelement <3 x float> %ray_inv_dir0, float %ray_inv_dir_y, i32 1 - %ray_inv_dir = insertelement <3 x float> %ray_inv_dir1, float %ray_inv_dir_z, i32 2 - %v = call <4 x i32> @llvm.amdgcn.image.bvh.intersect.ray.i32.v4f32(i32 %node_ptr, float %ray_extent, <3 x float> %ray_origin, <3 x float> %ray_dir, <3 x float> %ray_inv_dir, <4 x i32> %tdescr) - %r = bitcast <4 x i32> %v to <4 x float> - ret <4 x float> %r -} - -define amdgpu_ps <4 x float> @image_bvh_intersect_ray_a16(i32 %node_ptr, float %ray_extent, <3 x float> %ray_origin, <3 x half> %ray_dir, <3 x half> %ray_inv_dir, <4 x i32> inreg %tdescr) { -; GFX10-LABEL: image_bvh_intersect_ray_a16: -; GFX10: ; %bb.0: -; GFX10-NEXT: v_lshrrev_b32_e32 v9, 16, v5 -; GFX10-NEXT: v_and_b32_e32 v10, 0xffff, v7 -; GFX10-NEXT: v_and_b32_e32 v8, 0xffff, v8 -; GFX10-NEXT: v_lshlrev_b32_e32 v9, 16, v9 -; GFX10-NEXT: v_lshlrev_b32_e32 v10, 16, v10 -; GFX10-NEXT: v_alignbit_b32 v7, v8, v7, 16 -; GFX10-NEXT: v_and_or_b32 v5, v5, 0xffff, v9 -; GFX10-NEXT: v_and_or_b32 v6, v6, 0xffff, v10 -; GFX10-NEXT: image_bvh_intersect_ray v[0:3], v[0:7], s[0:3] a16 -; GFX10-NEXT: s_waitcnt vmcnt(0) -; GFX10-NEXT: ; return to shader part epilog -; -; GFX11-LABEL: image_bvh_intersect_ray_a16: -; GFX11: ; %bb.0: -; GFX11-NEXT: v_perm_b32 v9, v5, v7, 0x5040100 -; GFX11-NEXT: v_perm_b32 v10, v5, v7, 0x7060302 -; GFX11-NEXT: v_perm_b32 v11, v6, v8, 0x5040100 -; GFX11-NEXT: image_bvh_intersect_ray v[0:3], [v0, v1, v[2:4], v[9:11]], s[0:3] a16 -; GFX11-NEXT: s_waitcnt vmcnt(0) -; GFX11-NEXT: ; return to shader part epilog - %v = call <4 x i32> @llvm.amdgcn.image.bvh.intersect.ray.i32.v4f16(i32 %node_ptr, float %ray_extent, <3 x float> %ray_origin, <3 x half> %ray_dir, <3 x half> %ray_inv_dir, <4 x i32> %tdescr) - %r = bitcast <4 x i32> %v to <4 x float> - ret <4 x float> %r -} - -define amdgpu_ps <4 x float> @image_bvh64_intersect_ray(i64 %node_ptr, float %ray_extent, <3 x float> %ray_origin, <3 x float> %ray_dir, <3 x float> %ray_inv_dir, <4 x i32> inreg %tdescr) { -; GCN-LABEL: image_bvh64_intersect_ray: -; GCN: ; %bb.0: -; GCN-NEXT: image_bvh64_intersect_ray v[0:3], v[0:11], s[0:3] -; GCN-NEXT: s_waitcnt vmcnt(0) -; GCN-NEXT: ; return to shader part epilog - %v = call <4 x i32> @llvm.amdgcn.image.bvh.intersect.ray.i64.v4f32(i64 %node_ptr, float %ray_extent, <3 x float> %ray_origin, <3 x float> %ray_dir, <3 x float> %ray_inv_dir, <4 x i32> %tdescr) - %r = bitcast <4 x i32> %v to <4 x float> - ret <4 x float> %r -} - -define amdgpu_ps <4 x float> @image_bvh64_intersect_ray_flat(<2 x i32> %node_ptr_vec, float %ray_extent, float %ray_origin_x, float %ray_origin_y, float %ray_origin_z, float %ray_dir_x, float %ray_dir_y, float %ray_dir_z, float %ray_inv_dir_x, float %ray_inv_dir_y, float %ray_inv_dir_z, <4 x i32> inreg %tdescr) { -; GCN-LABEL: image_bvh64_intersect_ray_flat: -; GCN: ; %bb.0: -; GCN-NEXT: image_bvh64_intersect_ray v[0:3], v[0:11], s[0:3] -; GCN-NEXT: s_waitcnt vmcnt(0) -; GCN-NEXT: ; return to shader part epilog - %node_ptr = bitcast <2 x i32> %node_ptr_vec to i64 - %ray_origin0 = insertelement <3 x float> undef, float %ray_origin_x, i32 0 - %ray_origin1 = insertelement <3 x float> %ray_origin0, float %ray_origin_y, i32 1 - %ray_origin = insertelement <3 x float> %ray_origin1, float %ray_origin_z, i32 2 - %ray_dir0 = insertelement <3 x float> undef, float %ray_dir_x, i32 0 - %ray_dir1 = insertelement <3 x float> %ray_dir0, float %ray_dir_y, i32 1 - %ray_dir = insertelement <3 x float> %ray_dir1, float %ray_dir_z, i32 2 - %ray_inv_dir0 = insertelement <3 x float> undef, float %ray_inv_dir_x, i32 0 - %ray_inv_dir1 = insertelement <3 x float> %ray_inv_dir0, float %ray_inv_dir_y, i32 1 - %ray_inv_dir = insertelement <3 x float> %ray_inv_dir1, float %ray_inv_dir_z, i32 2 - %v = call <4 x i32> @llvm.amdgcn.image.bvh.intersect.ray.i64.v4f32(i64 %node_ptr, float %ray_extent, <3 x float> %ray_origin, <3 x float> %ray_dir, <3 x float> %ray_inv_dir, <4 x i32> %tdescr) - %r = bitcast <4 x i32> %v to <4 x float> - ret <4 x float> %r -} - -define amdgpu_ps <4 x float> @image_bvh64_intersect_ray_a16(i64 %node_ptr, float %ray_extent, <3 x float> %ray_origin, <3 x half> %ray_dir, <3 x half> %ray_inv_dir, <4 x i32> inreg %tdescr) { -; GFX10-LABEL: image_bvh64_intersect_ray_a16: -; GFX10: ; %bb.0: -; GFX10-NEXT: v_lshrrev_b32_e32 v10, 16, v6 -; GFX10-NEXT: v_and_b32_e32 v11, 0xffff, v8 -; GFX10-NEXT: v_and_b32_e32 v9, 0xffff, v9 -; GFX10-NEXT: v_lshlrev_b32_e32 v10, 16, v10 -; GFX10-NEXT: v_lshlrev_b32_e32 v11, 16, v11 -; GFX10-NEXT: v_alignbit_b32 v8, v9, v8, 16 -; GFX10-NEXT: v_and_or_b32 v6, v6, 0xffff, v10 -; GFX10-NEXT: v_and_or_b32 v7, v7, 0xffff, v11 -; GFX10-NEXT: image_bvh64_intersect_ray v[0:3], v[0:8], s[0:3] a16 -; GFX10-NEXT: s_waitcnt vmcnt(0) -; GFX10-NEXT: ; return to shader part epilog -; -; GFX11-LABEL: image_bvh64_intersect_ray_a16: -; GFX11: ; %bb.0: -; GFX11-NEXT: v_perm_b32 v10, v6, v8, 0x5040100 -; GFX11-NEXT: v_perm_b32 v11, v6, v8, 0x7060302 -; GFX11-NEXT: v_perm_b32 v12, v7, v9, 0x5040100 -; GFX11-NEXT: image_bvh64_intersect_ray v[0:3], [v[0:1], v2, v[3:5], v[10:12]], s[0:3] a16 -; GFX11-NEXT: s_waitcnt vmcnt(0) -; GFX11-NEXT: ; return to shader part epilog - %v = call <4 x i32> @llvm.amdgcn.image.bvh.intersect.ray.i64.v4f16(i64 %node_ptr, float %ray_extent, <3 x float> %ray_origin, <3 x half> %ray_dir, <3 x half> %ray_inv_dir, <4 x i32> %tdescr) - %r = bitcast <4 x i32> %v to <4 x float> - ret <4 x float> %r -} - -define amdgpu_ps <4 x float> @image_bvh_intersect_ray_vgpr_descr(i32 %node_ptr, float %ray_extent, <3 x float> %ray_origin, <3 x float> %ray_dir, <3 x float> %ray_inv_dir, <4 x i32> %tdescr) { -; GFX1030-LABEL: image_bvh_intersect_ray_vgpr_descr: -; GFX1030: ; %bb.0: -; GFX1030-NEXT: v_mov_b32_e32 v15, v0 -; GFX1030-NEXT: v_mov_b32_e32 v16, v1 -; GFX1030-NEXT: v_mov_b32_e32 v17, v2 -; GFX1030-NEXT: v_mov_b32_e32 v18, v3 -; GFX1030-NEXT: v_mov_b32_e32 v19, v4 -; GFX1030-NEXT: v_mov_b32_e32 v20, v5 -; GFX1030-NEXT: v_mov_b32_e32 v21, v6 -; GFX1030-NEXT: v_mov_b32_e32 v22, v7 -; GFX1030-NEXT: v_mov_b32_e32 v23, v8 -; GFX1030-NEXT: v_mov_b32_e32 v24, v9 -; GFX1030-NEXT: v_mov_b32_e32 v25, v10 -; GFX1030-NEXT: s_mov_b32 s1, exec_lo -; GFX1030-NEXT: .LBB6_1: ; =>This Inner Loop Header: Depth=1 -; GFX1030-NEXT: v_readfirstlane_b32 s4, v11 -; GFX1030-NEXT: v_readfirstlane_b32 s5, v12 -; GFX1030-NEXT: v_readfirstlane_b32 s6, v13 -; GFX1030-NEXT: v_readfirstlane_b32 s7, v14 -; GFX1030-NEXT: v_cmp_eq_u64_e32 vcc_lo, s[4:5], v[11:12] -; GFX1030-NEXT: v_cmp_eq_u64_e64 s0, s[6:7], v[13:14] -; GFX1030-NEXT: s_and_b32 s0, vcc_lo, s0 -; GFX1030-NEXT: s_and_saveexec_b32 s0, s0 -; GFX1030-NEXT: image_bvh_intersect_ray v[0:3], v[15:25], s[4:7] -; GFX1030-NEXT: ; implicit-def: $vgpr11 -; GFX1030-NEXT: ; implicit-def: $vgpr15 -; GFX1030-NEXT: ; implicit-def: $vgpr16 -; GFX1030-NEXT: ; implicit-def: $vgpr17 -; GFX1030-NEXT: ; implicit-def: $vgpr18 -; GFX1030-NEXT: ; implicit-def: $vgpr19 -; GFX1030-NEXT: ; implicit-def: $vgpr20 -; GFX1030-NEXT: ; implicit-def: $vgpr21 -; GFX1030-NEXT: ; implicit-def: $vgpr22 -; GFX1030-NEXT: ; implicit-def: $vgpr23 -; GFX1030-NEXT: ; implicit-def: $vgpr24 -; GFX1030-NEXT: ; implicit-def: $vgpr25 -; GFX1030-NEXT: ; implicit-def: $vgpr11_vgpr12_vgpr13_vgpr14 -; GFX1030-NEXT: s_xor_b32 exec_lo, exec_lo, s0 -; GFX1030-NEXT: s_cbranch_execnz .LBB6_1 -; GFX1030-NEXT: ; %bb.2: -; GFX1030-NEXT: s_mov_b32 exec_lo, s1 -; GFX1030-NEXT: s_waitcnt vmcnt(0) -; GFX1030-NEXT: ; return to shader part epilog -; -; GFX1013-LABEL: image_bvh_intersect_ray_vgpr_descr: -; GFX1013: ; %bb.0: -; GFX1013-NEXT: s_mov_b32 s1, exec_lo -; GFX1013-NEXT: .LBB6_1: ; =>This Inner Loop Header: Depth=1 -; GFX1013-NEXT: v_readfirstlane_b32 s4, v11 -; GFX1013-NEXT: v_readfirstlane_b32 s5, v12 -; GFX1013-NEXT: v_readfirstlane_b32 s6, v13 -; GFX1013-NEXT: v_readfirstlane_b32 s7, v14 -; GFX1013-NEXT: v_cmp_eq_u64_e32 vcc_lo, s[4:5], v[11:12] -; GFX1013-NEXT: v_cmp_eq_u64_e64 s0, s[6:7], v[13:14] -; GFX1013-NEXT: s_and_b32 s0, vcc_lo, s0 -; GFX1013-NEXT: s_and_saveexec_b32 s0, s0 -; GFX1013-NEXT: image_bvh_intersect_ray v[15:18], v[0:10], s[4:7] -; GFX1013-NEXT: ; implicit-def: $vgpr11 -; GFX1013-NEXT: ; implicit-def: $vgpr0_vgpr1_vgpr2_vgpr3_vgpr4_vgpr5_vgpr6_vgpr7_vgpr8_vgpr9_vgpr10 -; GFX1013-NEXT: ; implicit-def: $vgpr11_vgpr12_vgpr13_vgpr14 -; GFX1013-NEXT: s_waitcnt_depctr 0xffe3 -; GFX1013-NEXT: s_xor_b32 exec_lo, exec_lo, s0 -; GFX1013-NEXT: s_cbranch_execnz .LBB6_1 -; GFX1013-NEXT: ; %bb.2: -; GFX1013-NEXT: s_mov_b32 exec_lo, s1 -; GFX1013-NEXT: s_waitcnt vmcnt(0) -; GFX1013-NEXT: v_mov_b32_e32 v0, v15 -; GFX1013-NEXT: v_mov_b32_e32 v1, v16 -; GFX1013-NEXT: v_mov_b32_e32 v2, v17 -; GFX1013-NEXT: v_mov_b32_e32 v3, v18 -; GFX1013-NEXT: ; return to shader part epilog -; -; GFX11-LABEL: image_bvh_intersect_ray_vgpr_descr: -; GFX11: ; %bb.0: -; GFX11-NEXT: v_dual_mov_b32 v18, v0 :: v_dual_mov_b32 v19, v1 -; GFX11-NEXT: v_dual_mov_b32 v15, v2 :: v_dual_mov_b32 v16, v3 -; GFX11-NEXT: v_mov_b32_e32 v17, v4 -; GFX11-NEXT: s_mov_b32 s1, exec_lo -; GFX11-NEXT: .LBB6_1: ; =>This Inner Loop Header: Depth=1 -; GFX11-NEXT: v_readfirstlane_b32 s4, v11 -; GFX11-NEXT: v_readfirstlane_b32 s5, v12 -; GFX11-NEXT: v_readfirstlane_b32 s6, v13 -; GFX11-NEXT: v_readfirstlane_b32 s7, v14 -; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2) -; GFX11-NEXT: v_cmp_eq_u64_e32 vcc_lo, s[4:5], v[11:12] -; GFX11-NEXT: v_cmp_eq_u64_e64 s0, s[6:7], v[13:14] -; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(SALU_CYCLE_1) -; GFX11-NEXT: s_and_b32 s0, vcc_lo, s0 -; GFX11-NEXT: s_and_saveexec_b32 s0, s0 -; GFX11-NEXT: image_bvh_intersect_ray v[0:3], [v18, v19, v[15:17], v[5:7], v[8:10]], s[4:7] -; GFX11-NEXT: ; implicit-def: $vgpr11 -; GFX11-NEXT: ; implicit-def: $vgpr18 -; GFX11-NEXT: ; implicit-def: $vgpr19 -; GFX11-NEXT: ; implicit-def: $vgpr15_vgpr16_vgpr17 -; GFX11-NEXT: ; implicit-def: $vgpr5_vgpr6_vgpr7 -; GFX11-NEXT: ; implicit-def: $vgpr8_vgpr9_vgpr10 -; GFX11-NEXT: ; implicit-def: $vgpr11_vgpr12_vgpr13_vgpr14 -; GFX11-NEXT: s_xor_b32 exec_lo, exec_lo, s0 -; GFX11-NEXT: s_cbranch_execnz .LBB6_1 -; GFX11-NEXT: ; %bb.2: -; GFX11-NEXT: s_mov_b32 exec_lo, s1 -; GFX11-NEXT: s_waitcnt vmcnt(0) -; GFX11-NEXT: ; return to shader part epilog - %v = call <4 x i32> @llvm.amdgcn.image.bvh.intersect.ray.i32.v4f32(i32 %node_ptr, float %ray_extent, <3 x float> %ray_origin, <3 x float> %ray_dir, <3 x float> %ray_inv_dir, <4 x i32> %tdescr) - %r = bitcast <4 x i32> %v to <4 x float> - ret <4 x float> %r -} - -define amdgpu_ps <4 x float> @image_bvh_intersect_ray_a16_vgpr_descr(i32 %node_ptr, float %ray_extent, <3 x float> %ray_origin, <3 x half> %ray_dir, <3 x half> %ray_inv_dir, <4 x i32> %tdescr) { -; GFX1030-LABEL: image_bvh_intersect_ray_a16_vgpr_descr: -; GFX1030: ; %bb.0: -; GFX1030-NEXT: v_mov_b32_e32 v13, v0 -; GFX1030-NEXT: v_mov_b32_e32 v14, v1 -; GFX1030-NEXT: v_lshrrev_b32_e32 v0, 16, v5 -; GFX1030-NEXT: v_and_b32_e32 v1, 0xffff, v7 -; GFX1030-NEXT: v_mov_b32_e32 v15, v2 -; GFX1030-NEXT: v_and_b32_e32 v2, 0xffff, v8 -; GFX1030-NEXT: v_mov_b32_e32 v16, v3 -; GFX1030-NEXT: v_lshlrev_b32_e32 v0, 16, v0 -; GFX1030-NEXT: v_lshlrev_b32_e32 v1, 16, v1 -; GFX1030-NEXT: v_mov_b32_e32 v17, v4 -; GFX1030-NEXT: v_alignbit_b32 v20, v2, v7, 16 -; GFX1030-NEXT: s_mov_b32 s1, exec_lo -; GFX1030-NEXT: v_and_or_b32 v18, v5, 0xffff, v0 -; GFX1030-NEXT: v_and_or_b32 v19, v6, 0xffff, v1 -; GFX1030-NEXT: .LBB7_1: ; =>This Inner Loop Header: Depth=1 -; GFX1030-NEXT: v_readfirstlane_b32 s4, v9 -; GFX1030-NEXT: v_readfirstlane_b32 s5, v10 -; GFX1030-NEXT: v_readfirstlane_b32 s6, v11 -; GFX1030-NEXT: v_readfirstlane_b32 s7, v12 -; GFX1030-NEXT: v_cmp_eq_u64_e32 vcc_lo, s[4:5], v[9:10] -; GFX1030-NEXT: v_cmp_eq_u64_e64 s0, s[6:7], v[11:12] -; GFX1030-NEXT: s_and_b32 s0, vcc_lo, s0 -; GFX1030-NEXT: s_and_saveexec_b32 s0, s0 -; GFX1030-NEXT: image_bvh_intersect_ray v[0:3], v[13:20], s[4:7] a16 -; GFX1030-NEXT: ; implicit-def: $vgpr9 -; GFX1030-NEXT: ; implicit-def: $vgpr13 -; GFX1030-NEXT: ; implicit-def: $vgpr14 -; GFX1030-NEXT: ; implicit-def: $vgpr15 -; GFX1030-NEXT: ; implicit-def: $vgpr16 -; GFX1030-NEXT: ; implicit-def: $vgpr17 -; GFX1030-NEXT: ; implicit-def: $vgpr18 -; GFX1030-NEXT: ; implicit-def: $vgpr19 -; GFX1030-NEXT: ; implicit-def: $vgpr20 -; GFX1030-NEXT: ; implicit-def: $vgpr9_vgpr10_vgpr11_vgpr12 -; GFX1030-NEXT: s_xor_b32 exec_lo, exec_lo, s0 -; GFX1030-NEXT: s_cbranch_execnz .LBB7_1 -; GFX1030-NEXT: ; %bb.2: -; GFX1030-NEXT: s_mov_b32 exec_lo, s1 -; GFX1030-NEXT: s_waitcnt vmcnt(0) -; GFX1030-NEXT: ; return to shader part epilog -; -; GFX1013-LABEL: image_bvh_intersect_ray_a16_vgpr_descr: -; GFX1013: ; %bb.0: -; GFX1013-NEXT: v_lshrrev_b32_e32 v13, 16, v5 -; GFX1013-NEXT: v_and_b32_e32 v14, 0xffff, v7 -; GFX1013-NEXT: v_and_b32_e32 v8, 0xffff, v8 -; GFX1013-NEXT: s_mov_b32 s1, exec_lo -; GFX1013-NEXT: v_lshlrev_b32_e32 v13, 16, v13 -; GFX1013-NEXT: v_lshlrev_b32_e32 v14, 16, v14 -; GFX1013-NEXT: v_alignbit_b32 v7, v8, v7, 16 -; GFX1013-NEXT: v_and_or_b32 v5, v5, 0xffff, v13 -; GFX1013-NEXT: v_and_or_b32 v6, v6, 0xffff, v14 -; GFX1013-NEXT: .LBB7_1: ; =>This Inner Loop Header: Depth=1 -; GFX1013-NEXT: v_readfirstlane_b32 s4, v9 -; GFX1013-NEXT: v_readfirstlane_b32 s5, v10 -; GFX1013-NEXT: v_readfirstlane_b32 s6, v11 -; GFX1013-NEXT: v_readfirstlane_b32 s7, v12 -; GFX1013-NEXT: v_cmp_eq_u64_e32 vcc_lo, s[4:5], v[9:10] -; GFX1013-NEXT: v_cmp_eq_u64_e64 s0, s[6:7], v[11:12] -; GFX1013-NEXT: s_and_b32 s0, vcc_lo, s0 -; GFX1013-NEXT: s_and_saveexec_b32 s0, s0 -; GFX1013-NEXT: image_bvh_intersect_ray v[13:16], v[0:7], s[4:7] a16 -; GFX1013-NEXT: ; implicit-def: $vgpr9 -; GFX1013-NEXT: ; implicit-def: $vgpr0_vgpr1_vgpr2_vgpr3_vgpr4_vgpr5_vgpr6_vgpr7 -; GFX1013-NEXT: ; implicit-def: $vgpr9_vgpr10_vgpr11_vgpr12 -; GFX1013-NEXT: s_waitcnt_depctr 0xffe3 -; GFX1013-NEXT: s_xor_b32 exec_lo, exec_lo, s0 -; GFX1013-NEXT: s_cbranch_execnz .LBB7_1 -; GFX1013-NEXT: ; %bb.2: -; GFX1013-NEXT: s_mov_b32 exec_lo, s1 -; GFX1013-NEXT: s_waitcnt vmcnt(0) -; GFX1013-NEXT: v_mov_b32_e32 v0, v13 -; GFX1013-NEXT: v_mov_b32_e32 v1, v14 -; GFX1013-NEXT: v_mov_b32_e32 v2, v15 -; GFX1013-NEXT: v_mov_b32_e32 v3, v16 -; GFX1013-NEXT: ; return to shader part epilog -; -; GFX11-LABEL: image_bvh_intersect_ray_a16_vgpr_descr: -; GFX11: ; %bb.0: -; GFX11-NEXT: v_dual_mov_b32 v16, v0 :: v_dual_mov_b32 v17, v1 -; GFX11-NEXT: v_dual_mov_b32 v13, v2 :: v_dual_mov_b32 v14, v3 -; GFX11-NEXT: v_mov_b32_e32 v15, v4 -; GFX11-NEXT: v_perm_b32 v4, v5, v7, 0x5040100 -; GFX11-NEXT: v_perm_b32 v5, v5, v7, 0x7060302 -; GFX11-NEXT: v_perm_b32 v6, v6, v8, 0x5040100 -; GFX11-NEXT: s_mov_b32 s1, exec_lo -; GFX11-NEXT: .LBB7_1: ; =>This Inner Loop Header: Depth=1 -; GFX11-NEXT: v_readfirstlane_b32 s4, v9 -; GFX11-NEXT: v_readfirstlane_b32 s5, v10 -; GFX11-NEXT: v_readfirstlane_b32 s6, v11 -; GFX11-NEXT: v_readfirstlane_b32 s7, v12 -; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2) -; GFX11-NEXT: v_cmp_eq_u64_e32 vcc_lo, s[4:5], v[9:10] -; GFX11-NEXT: v_cmp_eq_u64_e64 s0, s[6:7], v[11:12] -; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(SALU_CYCLE_1) -; GFX11-NEXT: s_and_b32 s0, vcc_lo, s0 -; GFX11-NEXT: s_and_saveexec_b32 s0, s0 -; GFX11-NEXT: image_bvh_intersect_ray v[0:3], [v16, v17, v[13:15], v[4:6]], s[4:7] a16 -; GFX11-NEXT: ; implicit-def: $vgpr9 -; GFX11-NEXT: ; implicit-def: $vgpr16 -; GFX11-NEXT: ; implicit-def: $vgpr17 -; GFX11-NEXT: ; implicit-def: $vgpr13_vgpr14_vgpr15 -; GFX11-NEXT: ; implicit-def: $vgpr4_vgpr5_vgpr6 -; GFX11-NEXT: ; implicit-def: $vgpr9_vgpr10_vgpr11_vgpr12 -; GFX11-NEXT: s_xor_b32 exec_lo, exec_lo, s0 -; GFX11-NEXT: s_cbranch_execnz .LBB7_1 -; GFX11-NEXT: ; %bb.2: -; GFX11-NEXT: s_mov_b32 exec_lo, s1 -; GFX11-NEXT: s_waitcnt vmcnt(0) -; GFX11-NEXT: ; return to shader part epilog - %v = call <4 x i32> @llvm.amdgcn.image.bvh.intersect.ray.i32.v4f16(i32 %node_ptr, float %ray_extent, <3 x float> %ray_origin, <3 x half> %ray_dir, <3 x half> %ray_inv_dir, <4 x i32> %tdescr) - %r = bitcast <4 x i32> %v to <4 x float> - ret <4 x float> %r -} - -define amdgpu_ps <4 x float> @image_bvh64_intersect_ray_vgpr_descr(i64 %node_ptr, float %ray_extent, <3 x float> %ray_origin, <3 x float> %ray_dir, <3 x float> %ray_inv_dir, <4 x i32> %tdescr) { -; GFX1030-LABEL: image_bvh64_intersect_ray_vgpr_descr: -; GFX1030: ; %bb.0: -; GFX1030-NEXT: v_mov_b32_e32 v16, v0 -; GFX1030-NEXT: v_mov_b32_e32 v17, v1 -; GFX1030-NEXT: v_mov_b32_e32 v18, v2 -; GFX1030-NEXT: v_mov_b32_e32 v19, v3 -; GFX1030-NEXT: v_mov_b32_e32 v20, v4 -; GFX1030-NEXT: v_mov_b32_e32 v21, v5 -; GFX1030-NEXT: v_mov_b32_e32 v22, v6 -; GFX1030-NEXT: v_mov_b32_e32 v23, v7 -; GFX1030-NEXT: v_mov_b32_e32 v24, v8 -; GFX1030-NEXT: v_mov_b32_e32 v25, v9 -; GFX1030-NEXT: v_mov_b32_e32 v26, v10 -; GFX1030-NEXT: v_mov_b32_e32 v27, v11 -; GFX1030-NEXT: s_mov_b32 s1, exec_lo -; GFX1030-NEXT: .LBB8_1: ; =>This Inner Loop Header: Depth=1 -; GFX1030-NEXT: v_readfirstlane_b32 s4, v12 -; GFX1030-NEXT: v_readfirstlane_b32 s5, v13 -; GFX1030-NEXT: v_readfirstlane_b32 s6, v14 -; GFX1030-NEXT: v_readfirstlane_b32 s7, v15 -; GFX1030-NEXT: v_cmp_eq_u64_e32 vcc_lo, s[4:5], v[12:13] -; GFX1030-NEXT: v_cmp_eq_u64_e64 s0, s[6:7], v[14:15] -; GFX1030-NEXT: s_and_b32 s0, vcc_lo, s0 -; GFX1030-NEXT: s_and_saveexec_b32 s0, s0 -; GFX1030-NEXT: image_bvh64_intersect_ray v[0:3], v[16:27], s[4:7] -; GFX1030-NEXT: ; implicit-def: $vgpr12 -; GFX1030-NEXT: ; implicit-def: $vgpr16 -; GFX1030-NEXT: ; implicit-def: $vgpr17 -; GFX1030-NEXT: ; implicit-def: $vgpr18 -; GFX1030-NEXT: ; implicit-def: $vgpr19 -; GFX1030-NEXT: ; implicit-def: $vgpr20 -; GFX1030-NEXT: ; implicit-def: $vgpr21 -; GFX1030-NEXT: ; implicit-def: $vgpr22 -; GFX1030-NEXT: ; implicit-def: $vgpr23 -; GFX1030-NEXT: ; implicit-def: $vgpr24 -; GFX1030-NEXT: ; implicit-def: $vgpr25 -; GFX1030-NEXT: ; implicit-def: $vgpr26 -; GFX1030-NEXT: ; implicit-def: $vgpr27 -; GFX1030-NEXT: ; implicit-def: $vgpr12_vgpr13_vgpr14_vgpr15 -; GFX1030-NEXT: s_xor_b32 exec_lo, exec_lo, s0 -; GFX1030-NEXT: s_cbranch_execnz .LBB8_1 -; GFX1030-NEXT: ; %bb.2: -; GFX1030-NEXT: s_mov_b32 exec_lo, s1 -; GFX1030-NEXT: s_waitcnt vmcnt(0) -; GFX1030-NEXT: ; return to shader part epilog -; -; GFX1013-LABEL: image_bvh64_intersect_ray_vgpr_descr: -; GFX1013: ; %bb.0: -; GFX1013-NEXT: s_mov_b32 s1, exec_lo -; GFX1013-NEXT: .LBB8_1: ; =>This Inner Loop Header: Depth=1 -; GFX1013-NEXT: v_readfirstlane_b32 s4, v12 -; GFX1013-NEXT: v_readfirstlane_b32 s5, v13 -; GFX1013-NEXT: v_readfirstlane_b32 s6, v14 -; GFX1013-NEXT: v_readfirstlane_b32 s7, v15 -; GFX1013-NEXT: v_cmp_eq_u64_e32 vcc_lo, s[4:5], v[12:13] -; GFX1013-NEXT: v_cmp_eq_u64_e64 s0, s[6:7], v[14:15] -; GFX1013-NEXT: s_and_b32 s0, vcc_lo, s0 -; GFX1013-NEXT: s_and_saveexec_b32 s0, s0 -; GFX1013-NEXT: image_bvh64_intersect_ray v[16:19], v[0:11], s[4:7] -; GFX1013-NEXT: ; implicit-def: $vgpr12 -; GFX1013-NEXT: ; implicit-def: $vgpr0_vgpr1_vgpr2_vgpr3_vgpr4_vgpr5_vgpr6_vgpr7_vgpr8_vgpr9_vgpr10_vgpr11 -; GFX1013-NEXT: ; implicit-def: $vgpr12_vgpr13_vgpr14_vgpr15 -; GFX1013-NEXT: s_waitcnt_depctr 0xffe3 -; GFX1013-NEXT: s_xor_b32 exec_lo, exec_lo, s0 -; GFX1013-NEXT: s_cbranch_execnz .LBB8_1 -; GFX1013-NEXT: ; %bb.2: -; GFX1013-NEXT: s_mov_b32 exec_lo, s1 -; GFX1013-NEXT: s_waitcnt vmcnt(0) -; GFX1013-NEXT: v_mov_b32_e32 v0, v16 -; GFX1013-NEXT: v_mov_b32_e32 v1, v17 -; GFX1013-NEXT: v_mov_b32_e32 v2, v18 -; GFX1013-NEXT: v_mov_b32_e32 v3, v19 -; GFX1013-NEXT: ; return to shader part epilog -; -; GFX11-LABEL: image_bvh64_intersect_ray_vgpr_descr: -; GFX11: ; %bb.0: -; GFX11-NEXT: v_dual_mov_b32 v19, v0 :: v_dual_mov_b32 v20, v1 -; GFX11-NEXT: v_dual_mov_b32 v21, v2 :: v_dual_mov_b32 v16, v3 -; GFX11-NEXT: v_dual_mov_b32 v17, v4 :: v_dual_mov_b32 v18, v5 -; GFX11-NEXT: s_mov_b32 s1, exec_lo -; GFX11-NEXT: .LBB8_1: ; =>This Inner Loop Header: Depth=1 -; GFX11-NEXT: v_readfirstlane_b32 s4, v12 -; GFX11-NEXT: v_readfirstlane_b32 s5, v13 -; GFX11-NEXT: v_readfirstlane_b32 s6, v14 -; GFX11-NEXT: v_readfirstlane_b32 s7, v15 -; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2) -; GFX11-NEXT: v_cmp_eq_u64_e32 vcc_lo, s[4:5], v[12:13] -; GFX11-NEXT: v_cmp_eq_u64_e64 s0, s[6:7], v[14:15] -; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(SALU_CYCLE_1) -; GFX11-NEXT: s_and_b32 s0, vcc_lo, s0 -; GFX11-NEXT: s_and_saveexec_b32 s0, s0 -; GFX11-NEXT: image_bvh64_intersect_ray v[0:3], [v[19:20], v21, v[16:18], v[6:8], v[9:11]], s[4:7] -; GFX11-NEXT: ; implicit-def: $vgpr12 -; GFX11-NEXT: ; implicit-def: $vgpr19_vgpr20 -; GFX11-NEXT: ; implicit-def: $vgpr21 -; GFX11-NEXT: ; implicit-def: $vgpr16_vgpr17_vgpr18 -; GFX11-NEXT: ; implicit-def: $vgpr6_vgpr7_vgpr8 -; GFX11-NEXT: ; implicit-def: $vgpr9_vgpr10_vgpr11 -; GFX11-NEXT: ; implicit-def: $vgpr12_vgpr13_vgpr14_vgpr15 -; GFX11-NEXT: s_xor_b32 exec_lo, exec_lo, s0 -; GFX11-NEXT: s_cbranch_execnz .LBB8_1 -; GFX11-NEXT: ; %bb.2: -; GFX11-NEXT: s_mov_b32 exec_lo, s1 -; GFX11-NEXT: s_waitcnt vmcnt(0) -; GFX11-NEXT: ; return to shader part epilog - %v = call <4 x i32> @llvm.amdgcn.image.bvh.intersect.ray.i64.v4f32(i64 %node_ptr, float %ray_extent, <3 x float> %ray_origin, <3 x float> %ray_dir, <3 x float> %ray_inv_dir, <4 x i32> %tdescr) - %r = bitcast <4 x i32> %v to <4 x float> - ret <4 x float> %r -} - -define amdgpu_ps <4 x float> @image_bvh64_intersect_ray_a16_vgpr_descr(i64 %node_ptr, float %ray_extent, <3 x float> %ray_origin, <3 x half> %ray_dir, <3 x half> %ray_inv_dir, <4 x i32> %tdescr) { -; GFX1030-LABEL: image_bvh64_intersect_ray_a16_vgpr_descr: -; GFX1030: ; %bb.0: -; GFX1030-NEXT: v_mov_b32_e32 v14, v0 -; GFX1030-NEXT: v_mov_b32_e32 v15, v1 -; GFX1030-NEXT: v_lshrrev_b32_e32 v0, 16, v6 -; GFX1030-NEXT: v_and_b32_e32 v1, 0xffff, v8 -; GFX1030-NEXT: v_mov_b32_e32 v16, v2 -; GFX1030-NEXT: v_and_b32_e32 v2, 0xffff, v9 -; GFX1030-NEXT: v_mov_b32_e32 v17, v3 -; GFX1030-NEXT: v_lshlrev_b32_e32 v0, 16, v0 -; GFX1030-NEXT: v_lshlrev_b32_e32 v1, 16, v1 -; GFX1030-NEXT: v_mov_b32_e32 v18, v4 -; GFX1030-NEXT: v_mov_b32_e32 v19, v5 -; GFX1030-NEXT: v_alignbit_b32 v22, v2, v8, 16 -; GFX1030-NEXT: v_and_or_b32 v20, v6, 0xffff, v0 -; GFX1030-NEXT: v_and_or_b32 v21, v7, 0xffff, v1 -; GFX1030-NEXT: s_mov_b32 s1, exec_lo -; GFX1030-NEXT: .LBB9_1: ; =>This Inner Loop Header: Depth=1 -; GFX1030-NEXT: v_readfirstlane_b32 s4, v10 -; GFX1030-NEXT: v_readfirstlane_b32 s5, v11 -; GFX1030-NEXT: v_readfirstlane_b32 s6, v12 -; GFX1030-NEXT: v_readfirstlane_b32 s7, v13 -; GFX1030-NEXT: v_cmp_eq_u64_e32 vcc_lo, s[4:5], v[10:11] -; GFX1030-NEXT: v_cmp_eq_u64_e64 s0, s[6:7], v[12:13] -; GFX1030-NEXT: s_and_b32 s0, vcc_lo, s0 -; GFX1030-NEXT: s_and_saveexec_b32 s0, s0 -; GFX1030-NEXT: image_bvh64_intersect_ray v[0:3], v[14:22], s[4:7] a16 -; GFX1030-NEXT: ; implicit-def: $vgpr10 -; GFX1030-NEXT: ; implicit-def: $vgpr14 -; GFX1030-NEXT: ; implicit-def: $vgpr15 -; GFX1030-NEXT: ; implicit-def: $vgpr16 -; GFX1030-NEXT: ; implicit-def: $vgpr17 -; GFX1030-NEXT: ; implicit-def: $vgpr18 -; GFX1030-NEXT: ; implicit-def: $vgpr19 -; GFX1030-NEXT: ; implicit-def: $vgpr20 -; GFX1030-NEXT: ; implicit-def: $vgpr21 -; GFX1030-NEXT: ; implicit-def: $vgpr22 -; GFX1030-NEXT: ; implicit-def: $vgpr10_vgpr11_vgpr12_vgpr13 -; GFX1030-NEXT: s_xor_b32 exec_lo, exec_lo, s0 -; GFX1030-NEXT: s_cbranch_execnz .LBB9_1 -; GFX1030-NEXT: ; %bb.2: -; GFX1030-NEXT: s_mov_b32 exec_lo, s1 -; GFX1030-NEXT: s_waitcnt vmcnt(0) -; GFX1030-NEXT: ; return to shader part epilog -; -; GFX1013-LABEL: image_bvh64_intersect_ray_a16_vgpr_descr: -; GFX1013: ; %bb.0: -; GFX1013-NEXT: v_lshrrev_b32_e32 v14, 16, v6 -; GFX1013-NEXT: v_and_b32_e32 v15, 0xffff, v8 -; GFX1013-NEXT: v_and_b32_e32 v9, 0xffff, v9 -; GFX1013-NEXT: s_mov_b32 s1, exec_lo -; GFX1013-NEXT: v_lshlrev_b32_e32 v14, 16, v14 -; GFX1013-NEXT: v_lshlrev_b32_e32 v15, 16, v15 -; GFX1013-NEXT: v_alignbit_b32 v8, v9, v8, 16 -; GFX1013-NEXT: v_and_or_b32 v6, v6, 0xffff, v14 -; GFX1013-NEXT: v_and_or_b32 v7, v7, 0xffff, v15 -; GFX1013-NEXT: .LBB9_1: ; =>This Inner Loop Header: Depth=1 -; GFX1013-NEXT: v_readfirstlane_b32 s4, v10 -; GFX1013-NEXT: v_readfirstlane_b32 s5, v11 -; GFX1013-NEXT: v_readfirstlane_b32 s6, v12 -; GFX1013-NEXT: v_readfirstlane_b32 s7, v13 -; GFX1013-NEXT: v_cmp_eq_u64_e32 vcc_lo, s[4:5], v[10:11] -; GFX1013-NEXT: v_cmp_eq_u64_e64 s0, s[6:7], v[12:13] -; GFX1013-NEXT: s_and_b32 s0, vcc_lo, s0 -; GFX1013-NEXT: s_and_saveexec_b32 s0, s0 -; GFX1013-NEXT: image_bvh64_intersect_ray v[14:17], v[0:8], s[4:7] a16 -; GFX1013-NEXT: ; implicit-def: $vgpr10 -; GFX1013-NEXT: ; implicit-def: $vgpr0_vgpr1_vgpr2_vgpr3_vgpr4_vgpr5_vgpr6_vgpr7_vgpr8 -; GFX1013-NEXT: ; implicit-def: $vgpr10_vgpr11_vgpr12_vgpr13 -; GFX1013-NEXT: s_waitcnt_depctr 0xffe3 -; GFX1013-NEXT: s_xor_b32 exec_lo, exec_lo, s0 -; GFX1013-NEXT: s_cbranch_execnz .LBB9_1 -; GFX1013-NEXT: ; %bb.2: -; GFX1013-NEXT: s_mov_b32 exec_lo, s1 -; GFX1013-NEXT: s_waitcnt vmcnt(0) -; GFX1013-NEXT: v_mov_b32_e32 v0, v14 -; GFX1013-NEXT: v_mov_b32_e32 v1, v15 -; GFX1013-NEXT: v_mov_b32_e32 v2, v16 -; GFX1013-NEXT: v_mov_b32_e32 v3, v17 -; GFX1013-NEXT: ; return to shader part epilog -; -; GFX11-LABEL: image_bvh64_intersect_ray_a16_vgpr_descr: -; GFX11: ; %bb.0: -; GFX11-NEXT: v_dual_mov_b32 v17, v0 :: v_dual_mov_b32 v18, v1 -; GFX11-NEXT: v_dual_mov_b32 v19, v2 :: v_dual_mov_b32 v14, v3 -; GFX11-NEXT: v_dual_mov_b32 v15, v4 :: v_dual_mov_b32 v16, v5 -; GFX11-NEXT: v_perm_b32 v4, v6, v8, 0x5040100 -; GFX11-NEXT: v_perm_b32 v5, v6, v8, 0x7060302 -; GFX11-NEXT: v_perm_b32 v6, v7, v9, 0x5040100 -; GFX11-NEXT: s_mov_b32 s1, exec_lo -; GFX11-NEXT: .LBB9_1: ; =>This Inner Loop Header: Depth=1 -; GFX11-NEXT: v_readfirstlane_b32 s4, v10 -; GFX11-NEXT: v_readfirstlane_b32 s5, v11 -; GFX11-NEXT: v_readfirstlane_b32 s6, v12 -; GFX11-NEXT: v_readfirstlane_b32 s7, v13 -; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2) -; GFX11-NEXT: v_cmp_eq_u64_e32 vcc_lo, s[4:5], v[10:11] -; GFX11-NEXT: v_cmp_eq_u64_e64 s0, s[6:7], v[12:13] -; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(SALU_CYCLE_1) -; GFX11-NEXT: s_and_b32 s0, vcc_lo, s0 -; GFX11-NEXT: s_and_saveexec_b32 s0, s0 -; GFX11-NEXT: image_bvh64_intersect_ray v[0:3], [v[17:18], v19, v[14:16], v[4:6]], s[4:7] a16 -; GFX11-NEXT: ; implicit-def: $vgpr10 -; GFX11-NEXT: ; implicit-def: $vgpr17_vgpr18 -; GFX11-NEXT: ; implicit-def: $vgpr19 -; GFX11-NEXT: ; implicit-def: $vgpr14_vgpr15_vgpr16 -; GFX11-NEXT: ; implicit-def: $vgpr4_vgpr5_vgpr6 -; GFX11-NEXT: ; implicit-def: $vgpr10_vgpr11_vgpr12_vgpr13 -; GFX11-NEXT: s_xor_b32 exec_lo, exec_lo, s0 -; GFX11-NEXT: s_cbranch_execnz .LBB9_1 -; GFX11-NEXT: ; %bb.2: -; GFX11-NEXT: s_mov_b32 exec_lo, s1 -; GFX11-NEXT: s_waitcnt vmcnt(0) -; GFX11-NEXT: ; return to shader part epilog - %v = call <4 x i32> @llvm.amdgcn.image.bvh.intersect.ray.i64.v4f16(i64 %node_ptr, float %ray_extent, <3 x float> %ray_origin, <3 x half> %ray_dir, <3 x half> %ray_inv_dir, <4 x i32> %tdescr) - %r = bitcast <4 x i32> %v to <4 x float> - ret <4 x float> %r -} - -define amdgpu_kernel void @image_bvh_intersect_ray_nsa_reassign(ptr %p_node_ptr, ptr %p_ray, <4 x i32> inreg %tdescr) { -; GFX1030-LABEL: image_bvh_intersect_ray_nsa_reassign: -; GFX1030: ; %bb.0: -; GFX1030-NEXT: s_load_dwordx8 s[0:7], s[0:1], 0x24 -; GFX1030-NEXT: v_lshlrev_b32_e32 v4, 2, v0 -; GFX1030-NEXT: v_mov_b32_e32 v5, 0x40400000 -; GFX1030-NEXT: v_mov_b32_e32 v6, 4.0 -; GFX1030-NEXT: v_mov_b32_e32 v7, 0x40a00000 -; GFX1030-NEXT: v_mov_b32_e32 v8, 0x40c00000 -; GFX1030-NEXT: v_mov_b32_e32 v9, 0x40e00000 -; GFX1030-NEXT: v_mov_b32_e32 v10, 0x41000000 -; GFX1030-NEXT: s_waitcnt lgkmcnt(0) -; GFX1030-NEXT: v_mov_b32_e32 v0, s0 -; GFX1030-NEXT: v_mov_b32_e32 v1, s1 -; GFX1030-NEXT: v_mov_b32_e32 v2, s2 -; GFX1030-NEXT: v_mov_b32_e32 v3, s3 -; GFX1030-NEXT: v_add_co_u32 v0, vcc_lo, v0, v4 -; GFX1030-NEXT: v_add_co_ci_u32_e32 v1, vcc_lo, 0, v1, vcc_lo -; GFX1030-NEXT: v_add_co_u32 v2, vcc_lo, v2, v4 -; GFX1030-NEXT: v_add_co_ci_u32_e32 v3, vcc_lo, 0, v3, vcc_lo -; GFX1030-NEXT: v_mov_b32_e32 v4, 2.0 -; GFX1030-NEXT: flat_load_dword v0, v[0:1] -; GFX1030-NEXT: flat_load_dword v1, v[2:3] -; GFX1030-NEXT: v_mov_b32_e32 v2, 0 -; GFX1030-NEXT: v_mov_b32_e32 v3, 1.0 -; GFX1030-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0) -; GFX1030-NEXT: image_bvh_intersect_ray v[0:3], v[0:10], s[4:7] -; GFX1030-NEXT: s_waitcnt vmcnt(0) -; GFX1030-NEXT: flat_store_dwordx4 v[0:1], v[0:3] -; GFX1030-NEXT: s_endpgm -; -; GFX1013-LABEL: image_bvh_intersect_ray_nsa_reassign: -; GFX1013: ; %bb.0: -; GFX1013-NEXT: s_load_dwordx8 s[0:7], s[0:1], 0x24 -; GFX1013-NEXT: v_lshlrev_b32_e32 v6, 2, v0 -; GFX1013-NEXT: v_mov_b32_e32 v7, 0x40a00000 -; GFX1013-NEXT: v_mov_b32_e32 v8, 0x40c00000 -; GFX1013-NEXT: v_mov_b32_e32 v9, 0x40e00000 -; GFX1013-NEXT: v_mov_b32_e32 v10, 0x41000000 -; GFX1013-NEXT: s_waitcnt lgkmcnt(0) -; GFX1013-NEXT: v_mov_b32_e32 v0, s0 -; GFX1013-NEXT: v_mov_b32_e32 v1, s1 -; GFX1013-NEXT: v_mov_b32_e32 v2, s2 -; GFX1013-NEXT: v_mov_b32_e32 v3, s3 -; GFX1013-NEXT: v_add_co_u32 v4, vcc_lo, v0, v6 -; GFX1013-NEXT: v_add_co_ci_u32_e32 v5, vcc_lo, 0, v1, vcc_lo -; GFX1013-NEXT: v_add_co_u32 v2, vcc_lo, v2, v6 -; GFX1013-NEXT: v_add_co_ci_u32_e32 v3, vcc_lo, 0, v3, vcc_lo -; GFX1013-NEXT: v_mov_b32_e32 v6, 4.0 -; GFX1013-NEXT: flat_load_dword v0, v[4:5] -; GFX1013-NEXT: flat_load_dword v1, v[2:3] -; GFX1013-NEXT: v_mov_b32_e32 v2, 0 -; GFX1013-NEXT: v_mov_b32_e32 v3, 1.0 -; GFX1013-NEXT: v_mov_b32_e32 v4, 2.0 -; GFX1013-NEXT: v_mov_b32_e32 v5, 0x40400000 -; GFX1013-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0) -; GFX1013-NEXT: image_bvh_intersect_ray v[0:3], v[0:10], s[4:7] -; GFX1013-NEXT: s_waitcnt vmcnt(0) -; GFX1013-NEXT: flat_store_dwordx4 v[0:1], v[0:3] -; GFX1013-NEXT: s_endpgm -; -; GFX11-LABEL: image_bvh_intersect_ray_nsa_reassign: -; GFX11: ; %bb.0: -; GFX11-NEXT: s_load_b256 s[0:7], s[0:1], 0x24 -; GFX11-NEXT: v_lshlrev_b32_e32 v4, 2, v0 -; GFX11-NEXT: s_mov_b32 s9, 0x40400000 -; GFX11-NEXT: s_mov_b32 s12, 0x40c00000 -; GFX11-NEXT: s_mov_b32 s11, 0x40a00000 -; GFX11-NEXT: s_mov_b32 s10, 4.0 -; GFX11-NEXT: s_mov_b32 s14, 0x41000000 -; GFX11-NEXT: s_mov_b32 s13, 0x40e00000 -; GFX11-NEXT: v_mov_b32_e32 v6, s12 -; GFX11-NEXT: v_dual_mov_b32 v8, s14 :: v_dual_mov_b32 v7, s13 -; GFX11-NEXT: s_waitcnt lgkmcnt(0) -; GFX11-NEXT: v_dual_mov_b32 v0, s0 :: v_dual_mov_b32 v1, s1 -; GFX11-NEXT: s_mov_b32 s1, 1.0 -; GFX11-NEXT: s_mov_b32 s0, 0 -; GFX11-NEXT: v_dual_mov_b32 v2, s2 :: v_dual_mov_b32 v3, s3 -; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_3) -; GFX11-NEXT: v_add_co_u32 v0, vcc_lo, v0, v4 -; GFX11-NEXT: v_add_co_ci_u32_e32 v1, vcc_lo, 0, v1, vcc_lo -; GFX11-NEXT: v_add_co_u32 v2, vcc_lo, v2, v4 -; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_4) -; GFX11-NEXT: v_add_co_ci_u32_e32 v3, vcc_lo, 0, v3, vcc_lo -; GFX11-NEXT: flat_load_b32 v9, v[0:1] -; GFX11-NEXT: flat_load_b32 v10, v[2:3] -; GFX11-NEXT: s_mov_b32 s2, 2.0 -; GFX11-NEXT: v_dual_mov_b32 v0, s0 :: v_dual_mov_b32 v3, s9 -; GFX11-NEXT: v_dual_mov_b32 v1, s1 :: v_dual_mov_b32 v2, s2 -; GFX11-NEXT: v_dual_mov_b32 v5, s11 :: v_dual_mov_b32 v4, s10 -; GFX11-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0) -; GFX11-NEXT: image_bvh_intersect_ray v[0:3], [v9, v10, v[0:2], v[3:5], v[6:8]], s[4:7] -; GFX11-NEXT: s_waitcnt vmcnt(0) -; GFX11-NEXT: flat_store_b128 v[0:1], v[0:3] -; GFX11-NEXT: s_sendmsg sendmsg(MSG_DEALLOC_VGPRS) -; GFX11-NEXT: s_endpgm - %lid = tail call i32 @llvm.amdgcn.workitem.id.x() - %gep_node_ptr = getelementptr inbounds i32, ptr %p_node_ptr, i32 %lid - %node_ptr = load i32, ptr %gep_node_ptr, align 4 - %gep_ray = getelementptr inbounds float, ptr %p_ray, i32 %lid - %ray_extent = load float, ptr %gep_ray, align 4 - %ray_origin0 = insertelement <3 x float> undef, float 0.0, i32 0 - %ray_origin1 = insertelement <3 x float> %ray_origin0, float 1.0, i32 1 - %ray_origin = insertelement <3 x float> %ray_origin1, float 2.0, i32 2 - %ray_dir0 = insertelement <3 x float> undef, float 3.0, i32 0 - %ray_dir1 = insertelement <3 x float> %ray_dir0, float 4.0, i32 1 - %ray_dir = insertelement <3 x float> %ray_dir1, float 5.0, i32 2 - %ray_inv_dir0 = insertelement <3 x float> undef, float 6.0, i32 0 - %ray_inv_dir1 = insertelement <3 x float> %ray_inv_dir0, float 7.0, i32 1 - %ray_inv_dir = insertelement <3 x float> %ray_inv_dir1, float 8.0, i32 2 - %v = call <4 x i32> @llvm.amdgcn.image.bvh.intersect.ray.i32.v4f32(i32 %node_ptr, float %ray_extent, <3 x float> %ray_origin, <3 x float> %ray_dir, <3 x float> %ray_inv_dir, <4 x i32> %tdescr) - store <4 x i32> %v, ptr undef - ret void -} - -define amdgpu_kernel void @image_bvh_intersect_ray_a16_nsa_reassign(ptr %p_node_ptr, ptr %p_ray, <4 x i32> inreg %tdescr) { -; GFX1030-LABEL: image_bvh_intersect_ray_a16_nsa_reassign: -; GFX1030: ; %bb.0: -; GFX1030-NEXT: s_load_dwordx8 s[0:7], s[0:1], 0x24 -; GFX1030-NEXT: v_lshlrev_b32_e32 v4, 2, v0 -; GFX1030-NEXT: s_movk_i32 s9, 0x4600 -; GFX1030-NEXT: s_movk_i32 s8, 0x4700 -; GFX1030-NEXT: s_bfe_u32 s8, s8, 0x100000 -; GFX1030-NEXT: s_waitcnt lgkmcnt(0) -; GFX1030-NEXT: v_mov_b32_e32 v0, s0 -; GFX1030-NEXT: v_mov_b32_e32 v1, s1 -; GFX1030-NEXT: v_mov_b32_e32 v2, s2 -; GFX1030-NEXT: v_mov_b32_e32 v3, s3 -; GFX1030-NEXT: s_movk_i32 s1, 0x4400 -; GFX1030-NEXT: v_add_co_u32 v0, vcc_lo, v0, v4 -; GFX1030-NEXT: v_add_co_ci_u32_e32 v1, vcc_lo, 0, v1, vcc_lo -; GFX1030-NEXT: v_add_co_u32 v2, vcc_lo, v2, v4 -; GFX1030-NEXT: v_add_co_ci_u32_e32 v3, vcc_lo, 0, v3, vcc_lo -; GFX1030-NEXT: s_movk_i32 s2, 0x4200 -; GFX1030-NEXT: flat_load_dword v0, v[0:1] -; GFX1030-NEXT: flat_load_dword v1, v[2:3] -; GFX1030-NEXT: s_bfe_u32 s1, s1, 0x100000 -; GFX1030-NEXT: s_movk_i32 s3, 0x4800 -; GFX1030-NEXT: s_bfe_u32 s2, s2, 0x100000 -; GFX1030-NEXT: s_lshl_b32 s1, s1, 16 -; GFX1030-NEXT: s_movk_i32 s0, 0x4500 -; GFX1030-NEXT: s_or_b32 s1, s2, s1 -; GFX1030-NEXT: s_bfe_u32 s2, s9, 0x100000 -; GFX1030-NEXT: s_bfe_u32 s3, s3, 0x100000 -; GFX1030-NEXT: s_bfe_u32 s0, s0, 0x100000 -; GFX1030-NEXT: s_lshl_b32 s2, s2, 16 -; GFX1030-NEXT: s_lshl_b32 s3, s3, 16 -; GFX1030-NEXT: s_or_b32 s0, s0, s2 -; GFX1030-NEXT: s_or_b32 s2, s8, s3 -; GFX1030-NEXT: v_mov_b32_e32 v2, 0 -; GFX1030-NEXT: v_mov_b32_e32 v3, 1.0 -; GFX1030-NEXT: v_mov_b32_e32 v4, 2.0 -; GFX1030-NEXT: v_mov_b32_e32 v5, s1 -; GFX1030-NEXT: v_mov_b32_e32 v6, s0 -; GFX1030-NEXT: v_mov_b32_e32 v7, s2 -; GFX1030-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0) -; GFX1030-NEXT: image_bvh_intersect_ray v[0:3], v[0:7], s[4:7] a16 -; GFX1030-NEXT: s_waitcnt vmcnt(0) -; GFX1030-NEXT: flat_store_dwordx4 v[0:1], v[0:3] -; GFX1030-NEXT: s_endpgm -; -; GFX1013-LABEL: image_bvh_intersect_ray_a16_nsa_reassign: -; GFX1013: ; %bb.0: -; GFX1013-NEXT: s_load_dwordx8 s[0:7], s[0:1], 0x24 -; GFX1013-NEXT: v_lshlrev_b32_e32 v6, 2, v0 -; GFX1013-NEXT: s_movk_i32 s9, 0x4600 -; GFX1013-NEXT: s_movk_i32 s8, 0x4700 -; GFX1013-NEXT: s_bfe_u32 s8, s8, 0x100000 -; GFX1013-NEXT: s_waitcnt lgkmcnt(0) -; GFX1013-NEXT: v_mov_b32_e32 v0, s0 -; GFX1013-NEXT: v_mov_b32_e32 v1, s1 -; GFX1013-NEXT: v_mov_b32_e32 v2, s2 -; GFX1013-NEXT: v_mov_b32_e32 v3, s3 -; GFX1013-NEXT: s_movk_i32 s1, 0x4400 -; GFX1013-NEXT: v_add_co_u32 v4, vcc_lo, v0, v6 -; GFX1013-NEXT: v_add_co_ci_u32_e32 v5, vcc_lo, 0, v1, vcc_lo -; GFX1013-NEXT: v_add_co_u32 v2, vcc_lo, v2, v6 -; GFX1013-NEXT: v_add_co_ci_u32_e32 v3, vcc_lo, 0, v3, vcc_lo -; GFX1013-NEXT: s_movk_i32 s2, 0x4200 -; GFX1013-NEXT: flat_load_dword v0, v[4:5] -; GFX1013-NEXT: flat_load_dword v1, v[2:3] -; GFX1013-NEXT: s_bfe_u32 s1, s1, 0x100000 -; GFX1013-NEXT: s_movk_i32 s3, 0x4800 -; GFX1013-NEXT: s_bfe_u32 s2, s2, 0x100000 -; GFX1013-NEXT: s_lshl_b32 s1, s1, 16 -; GFX1013-NEXT: s_movk_i32 s0, 0x4500 -; GFX1013-NEXT: s_or_b32 s1, s2, s1 -; GFX1013-NEXT: s_bfe_u32 s2, s9, 0x100000 -; GFX1013-NEXT: s_bfe_u32 s3, s3, 0x100000 -; GFX1013-NEXT: s_bfe_u32 s0, s0, 0x100000 -; GFX1013-NEXT: s_lshl_b32 s2, s2, 16 -; GFX1013-NEXT: s_lshl_b32 s3, s3, 16 -; GFX1013-NEXT: s_or_b32 s0, s0, s2 -; GFX1013-NEXT: s_or_b32 s2, s8, s3 -; GFX1013-NEXT: v_mov_b32_e32 v2, 0 -; GFX1013-NEXT: v_mov_b32_e32 v3, 1.0 -; GFX1013-NEXT: v_mov_b32_e32 v4, 2.0 -; GFX1013-NEXT: v_mov_b32_e32 v5, s1 -; GFX1013-NEXT: v_mov_b32_e32 v6, s0 -; GFX1013-NEXT: v_mov_b32_e32 v7, s2 -; GFX1013-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0) -; GFX1013-NEXT: image_bvh_intersect_ray v[0:3], v[0:7], s[4:7] a16 -; GFX1013-NEXT: s_waitcnt vmcnt(0) -; GFX1013-NEXT: flat_store_dwordx4 v[0:1], v[0:3] -; GFX1013-NEXT: s_endpgm -; -; GFX11-LABEL: image_bvh_intersect_ray_a16_nsa_reassign: -; GFX11: ; %bb.0: -; GFX11-NEXT: s_load_b256 s[0:7], s[0:1], 0x24 -; GFX11-NEXT: v_lshlrev_b32_e32 v4, 2, v0 -; GFX11-NEXT: s_mov_b32 s9, 0x42004600 -; GFX11-NEXT: s_mov_b32 s10, 0x44004700 -; GFX11-NEXT: s_mov_b32 s11, 0x45004800 -; GFX11-NEXT: s_waitcnt lgkmcnt(0) -; GFX11-NEXT: v_dual_mov_b32 v0, s0 :: v_dual_mov_b32 v1, s1 -; GFX11-NEXT: s_mov_b32 s1, 1.0 -; GFX11-NEXT: s_mov_b32 s0, 0 -; GFX11-NEXT: v_dual_mov_b32 v2, s2 :: v_dual_mov_b32 v3, s3 -; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_3) -; GFX11-NEXT: v_add_co_u32 v0, vcc_lo, v0, v4 -; GFX11-NEXT: v_add_co_ci_u32_e32 v1, vcc_lo, 0, v1, vcc_lo -; GFX11-NEXT: v_add_co_u32 v2, vcc_lo, v2, v4 -; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_4) -; GFX11-NEXT: v_add_co_ci_u32_e32 v3, vcc_lo, 0, v3, vcc_lo -; GFX11-NEXT: flat_load_b32 v6, v[0:1] -; GFX11-NEXT: flat_load_b32 v7, v[2:3] -; GFX11-NEXT: s_mov_b32 s2, 2.0 -; GFX11-NEXT: v_dual_mov_b32 v0, s0 :: v_dual_mov_b32 v3, s9 -; GFX11-NEXT: v_dual_mov_b32 v1, s1 :: v_dual_mov_b32 v2, s2 -; GFX11-NEXT: v_dual_mov_b32 v5, s11 :: v_dual_mov_b32 v4, s10 -; GFX11-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0) -; GFX11-NEXT: image_bvh_intersect_ray v[0:3], [v6, v7, v[0:2], v[3:5]], s[4:7] a16 -; GFX11-NEXT: s_waitcnt vmcnt(0) -; GFX11-NEXT: flat_store_b128 v[0:1], v[0:3] -; GFX11-NEXT: s_sendmsg sendmsg(MSG_DEALLOC_VGPRS) -; GFX11-NEXT: s_endpgm - %lid = tail call i32 @llvm.amdgcn.workitem.id.x() - %gep_node_ptr = getelementptr inbounds i32, ptr %p_node_ptr, i32 %lid - %node_ptr = load i32, ptr %gep_node_ptr, align 4 - %gep_ray = getelementptr inbounds float, ptr %p_ray, i32 %lid - %ray_extent = load float, ptr %gep_ray, align 4 - %ray_origin0 = insertelement <3 x float> undef, float 0.0, i32 0 - %ray_origin1 = insertelement <3 x float> %ray_origin0, float 1.0, i32 1 - %ray_origin = insertelement <3 x float> %ray_origin1, float 2.0, i32 2 - %ray_dir0 = insertelement <3 x half> undef, half 3.0, i32 0 - %ray_dir1 = insertelement <3 x half> %ray_dir0, half 4.0, i32 1 - %ray_dir = insertelement <3 x half> %ray_dir1, half 5.0, i32 2 - %ray_inv_dir0 = insertelement <3 x half> undef, half 6.0, i32 0 - %ray_inv_dir1 = insertelement <3 x half> %ray_inv_dir0, half 7.0, i32 1 - %ray_inv_dir = insertelement <3 x half> %ray_inv_dir1, half 8.0, i32 2 - %v = call <4 x i32> @llvm.amdgcn.image.bvh.intersect.ray.i32.v4f16(i32 %node_ptr, float %ray_extent, <3 x float> %ray_origin, <3 x half> %ray_dir, <3 x half> %ray_inv_dir, <4 x i32> %tdescr) - store <4 x i32> %v, ptr undef - ret void -} - -define amdgpu_kernel void @image_bvh64_intersect_ray_nsa_reassign(ptr %p_ray, <4 x i32> inreg %tdescr) { -; GFX1030-LABEL: image_bvh64_intersect_ray_nsa_reassign: -; GFX1030: ; %bb.0: -; GFX1030-NEXT: s_clause 0x1 -; GFX1030-NEXT: s_load_dwordx2 s[4:5], s[0:1], 0x24 -; GFX1030-NEXT: s_load_dwordx4 s[0:3], s[0:1], 0x34 -; GFX1030-NEXT: v_lshlrev_b32_e32 v2, 2, v0 -; GFX1030-NEXT: v_mov_b32_e32 v3, 0 -; GFX1030-NEXT: v_mov_b32_e32 v4, 1.0 -; GFX1030-NEXT: v_mov_b32_e32 v5, 2.0 -; GFX1030-NEXT: v_mov_b32_e32 v6, 0x40400000 -; GFX1030-NEXT: v_mov_b32_e32 v7, 4.0 -; GFX1030-NEXT: v_mov_b32_e32 v8, 0x40a00000 -; GFX1030-NEXT: v_mov_b32_e32 v9, 0x40c00000 -; GFX1030-NEXT: v_mov_b32_e32 v10, 0x40e00000 -; GFX1030-NEXT: v_mov_b32_e32 v11, 0x41000000 -; GFX1030-NEXT: s_waitcnt lgkmcnt(0) -; GFX1030-NEXT: v_mov_b32_e32 v0, s4 -; GFX1030-NEXT: v_mov_b32_e32 v1, s5 -; GFX1030-NEXT: v_add_co_u32 v0, vcc_lo, v0, v2 -; GFX1030-NEXT: v_add_co_ci_u32_e32 v1, vcc_lo, 0, v1, vcc_lo -; GFX1030-NEXT: flat_load_dword v2, v[0:1] -; GFX1030-NEXT: v_mov_b32_e32 v0, 0xb36211c7 -; GFX1030-NEXT: v_mov_b32_e32 v1, 0x102 -; GFX1030-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0) -; GFX1030-NEXT: image_bvh64_intersect_ray v[0:3], v[0:11], s[0:3] -; GFX1030-NEXT: s_waitcnt vmcnt(0) -; GFX1030-NEXT: flat_store_dwordx4 v[0:1], v[0:3] -; GFX1030-NEXT: s_endpgm -; -; GFX1013-LABEL: image_bvh64_intersect_ray_nsa_reassign: -; GFX1013: ; %bb.0: -; GFX1013-NEXT: s_clause 0x1 -; GFX1013-NEXT: s_load_dwordx2 s[2:3], s[0:1], 0x24 -; GFX1013-NEXT: s_load_dwordx4 s[4:7], s[0:1], 0x34 -; GFX1013-NEXT: v_lshlrev_b32_e32 v2, 2, v0 -; GFX1013-NEXT: v_mov_b32_e32 v3, 0 -; GFX1013-NEXT: v_mov_b32_e32 v4, 1.0 -; GFX1013-NEXT: v_mov_b32_e32 v5, 2.0 -; GFX1013-NEXT: v_mov_b32_e32 v6, 0x40400000 -; GFX1013-NEXT: v_mov_b32_e32 v7, 4.0 -; GFX1013-NEXT: v_mov_b32_e32 v8, 0x40a00000 -; GFX1013-NEXT: v_mov_b32_e32 v9, 0x40c00000 -; GFX1013-NEXT: v_mov_b32_e32 v10, 0x40e00000 -; GFX1013-NEXT: v_mov_b32_e32 v11, 0x41000000 -; GFX1013-NEXT: s_waitcnt lgkmcnt(0) -; GFX1013-NEXT: v_mov_b32_e32 v0, s2 -; GFX1013-NEXT: v_mov_b32_e32 v1, s3 -; GFX1013-NEXT: v_add_co_u32 v0, vcc_lo, v0, v2 -; GFX1013-NEXT: v_add_co_ci_u32_e32 v1, vcc_lo, 0, v1, vcc_lo -; GFX1013-NEXT: flat_load_dword v2, v[0:1] -; GFX1013-NEXT: v_mov_b32_e32 v0, 0xb36211c7 -; GFX1013-NEXT: v_mov_b32_e32 v1, 0x102 -; GFX1013-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0) -; GFX1013-NEXT: image_bvh64_intersect_ray v[0:3], v[0:11], s[4:7] -; GFX1013-NEXT: s_waitcnt vmcnt(0) -; GFX1013-NEXT: flat_store_dwordx4 v[0:1], v[0:3] -; GFX1013-NEXT: s_endpgm -; -; GFX11-LABEL: image_bvh64_intersect_ray_nsa_reassign: -; GFX11: ; %bb.0: -; GFX11-NEXT: s_clause 0x1 -; GFX11-NEXT: s_load_b64 s[4:5], s[0:1], 0x24 -; GFX11-NEXT: s_load_b128 s[0:3], s[0:1], 0x34 -; GFX11-NEXT: v_lshlrev_b32_e32 v2, 2, v0 -; GFX11-NEXT: s_mov_b32 s8, 2.0 -; GFX11-NEXT: s_mov_b32 s7, 1.0 -; GFX11-NEXT: s_mov_b32 s6, 0 -; GFX11-NEXT: s_mov_b32 s9, 0x40400000 -; GFX11-NEXT: s_mov_b32 s12, 0x40c00000 -; GFX11-NEXT: s_mov_b32 s11, 0x40a00000 -; GFX11-NEXT: s_mov_b32 s10, 4.0 -; GFX11-NEXT: s_mov_b32 s14, 0x41000000 -; GFX11-NEXT: s_mov_b32 s13, 0x40e00000 -; GFX11-NEXT: v_mov_b32_e32 v6, s12 -; GFX11-NEXT: v_dual_mov_b32 v8, s14 :: v_dual_mov_b32 v3, s9 -; GFX11-NEXT: v_dual_mov_b32 v4, s10 :: v_dual_mov_b32 v7, s13 -; GFX11-NEXT: s_waitcnt lgkmcnt(0) -; GFX11-NEXT: v_dual_mov_b32 v5, s11 :: v_dual_mov_b32 v0, s4 -; GFX11-NEXT: v_mov_b32_e32 v1, s5 -; GFX11-NEXT: s_mov_b32 s4, 0xb36211c7 -; GFX11-NEXT: s_movk_i32 s5, 0x102 -; GFX11-NEXT: s_delay_alu instid0(SALU_CYCLE_1) -; GFX11-NEXT: v_dual_mov_b32 v10, s5 :: v_dual_mov_b32 v9, s4 -; GFX11-NEXT: v_add_co_u32 v0, vcc_lo, v0, v2 -; GFX11-NEXT: v_add_co_ci_u32_e32 v1, vcc_lo, 0, v1, vcc_lo -; GFX11-NEXT: flat_load_b32 v11, v[0:1] -; GFX11-NEXT: v_dual_mov_b32 v0, s6 :: v_dual_mov_b32 v1, s7 -; GFX11-NEXT: v_mov_b32_e32 v2, s8 -; GFX11-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0) -; GFX11-NEXT: image_bvh64_intersect_ray v[0:3], [v[9:10], v11, v[0:2], v[3:5], v[6:8]], s[0:3] -; GFX11-NEXT: s_waitcnt vmcnt(0) -; GFX11-NEXT: flat_store_b128 v[0:1], v[0:3] -; GFX11-NEXT: s_sendmsg sendmsg(MSG_DEALLOC_VGPRS) -; GFX11-NEXT: s_endpgm - %lid = tail call i32 @llvm.amdgcn.workitem.id.x() - %gep_ray = getelementptr inbounds float, ptr %p_ray, i32 %lid - %ray_extent = load float, ptr %gep_ray, align 4 - %ray_origin0 = insertelement <3 x float> undef, float 0.0, i32 0 - %ray_origin1 = insertelement <3 x float> %ray_origin0, float 1.0, i32 1 - %ray_origin = insertelement <3 x float> %ray_origin1, float 2.0, i32 2 - %ray_dir0 = insertelement <3 x float> undef, float 3.0, i32 0 - %ray_dir1 = insertelement <3 x float> %ray_dir0, float 4.0, i32 1 - %ray_dir = insertelement <3 x float> %ray_dir1, float 5.0, i32 2 - %ray_inv_dir0 = insertelement <3 x float> undef, float 6.0, i32 0 - %ray_inv_dir1 = insertelement <3 x float> %ray_inv_dir0, float 7.0, i32 1 - %ray_inv_dir = insertelement <3 x float> %ray_inv_dir1, float 8.0, i32 2 - %v = call <4 x i32> @llvm.amdgcn.image.bvh.intersect.ray.i64.v4f32(i64 1111111111111, float %ray_extent, <3 x float> %ray_origin, <3 x float> %ray_dir, <3 x float> %ray_inv_dir, <4 x i32> %tdescr) - store <4 x i32> %v, ptr undef - ret void -} - -define amdgpu_kernel void @image_bvh64_intersect_ray_a16_nsa_reassign(ptr %p_ray, <4 x i32> inreg %tdescr) { -; GFX1030-LABEL: image_bvh64_intersect_ray_a16_nsa_reassign: -; GFX1030: ; %bb.0: -; GFX1030-NEXT: s_clause 0x1 -; GFX1030-NEXT: s_load_dwordx2 s[4:5], s[0:1], 0x24 -; GFX1030-NEXT: s_load_dwordx4 s[0:3], s[0:1], 0x34 -; GFX1030-NEXT: v_lshlrev_b32_e32 v2, 2, v0 -; GFX1030-NEXT: s_movk_i32 s6, 0x4200 -; GFX1030-NEXT: s_movk_i32 s7, 0x4800 -; GFX1030-NEXT: s_bfe_u32 s6, s6, 0x100000 -; GFX1030-NEXT: s_movk_i32 s9, 0x4600 -; GFX1030-NEXT: s_movk_i32 s8, 0x4700 -; GFX1030-NEXT: s_bfe_u32 s7, s7, 0x100000 -; GFX1030-NEXT: s_bfe_u32 s8, s8, 0x100000 -; GFX1030-NEXT: s_lshl_b32 s7, s7, 16 -; GFX1030-NEXT: v_mov_b32_e32 v3, 0 -; GFX1030-NEXT: v_mov_b32_e32 v4, 1.0 -; GFX1030-NEXT: v_mov_b32_e32 v5, 2.0 -; GFX1030-NEXT: s_waitcnt lgkmcnt(0) -; GFX1030-NEXT: v_mov_b32_e32 v0, s4 -; GFX1030-NEXT: v_mov_b32_e32 v1, s5 -; GFX1030-NEXT: s_movk_i32 s5, 0x4400 -; GFX1030-NEXT: s_movk_i32 s4, 0x4500 -; GFX1030-NEXT: s_bfe_u32 s5, s5, 0x100000 -; GFX1030-NEXT: v_add_co_u32 v0, vcc_lo, v0, v2 -; GFX1030-NEXT: v_add_co_ci_u32_e32 v1, vcc_lo, 0, v1, vcc_lo -; GFX1030-NEXT: s_lshl_b32 s5, s5, 16 -; GFX1030-NEXT: s_bfe_u32 s4, s4, 0x100000 -; GFX1030-NEXT: s_or_b32 s5, s6, s5 -; GFX1030-NEXT: flat_load_dword v2, v[0:1] -; GFX1030-NEXT: s_bfe_u32 s6, s9, 0x100000 -; GFX1030-NEXT: v_mov_b32_e32 v0, 0xb36211c6 -; GFX1030-NEXT: s_lshl_b32 s6, s6, 16 -; GFX1030-NEXT: v_mov_b32_e32 v1, 0x102 -; GFX1030-NEXT: s_or_b32 s4, s4, s6 -; GFX1030-NEXT: s_or_b32 s6, s8, s7 -; GFX1030-NEXT: v_mov_b32_e32 v6, s5 -; GFX1030-NEXT: v_mov_b32_e32 v7, s4 -; GFX1030-NEXT: v_mov_b32_e32 v8, s6 -; GFX1030-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0) -; GFX1030-NEXT: image_bvh64_intersect_ray v[0:3], v[0:8], s[0:3] a16 -; GFX1030-NEXT: s_waitcnt vmcnt(0) -; GFX1030-NEXT: flat_store_dwordx4 v[0:1], v[0:3] -; GFX1030-NEXT: s_endpgm -; -; GFX1013-LABEL: image_bvh64_intersect_ray_a16_nsa_reassign: -; GFX1013: ; %bb.0: -; GFX1013-NEXT: s_clause 0x1 -; GFX1013-NEXT: s_load_dwordx2 s[2:3], s[0:1], 0x24 -; GFX1013-NEXT: s_load_dwordx4 s[4:7], s[0:1], 0x34 -; GFX1013-NEXT: v_lshlrev_b32_e32 v2, 2, v0 -; GFX1013-NEXT: s_movk_i32 s1, 0x4400 -; GFX1013-NEXT: s_movk_i32 s9, 0x4600 -; GFX1013-NEXT: s_bfe_u32 s1, s1, 0x100000 -; GFX1013-NEXT: s_movk_i32 s0, 0x4500 -; GFX1013-NEXT: s_lshl_b32 s1, s1, 16 -; GFX1013-NEXT: s_movk_i32 s8, 0x4700 -; GFX1013-NEXT: s_bfe_u32 s0, s0, 0x100000 -; GFX1013-NEXT: s_bfe_u32 s8, s8, 0x100000 -; GFX1013-NEXT: v_mov_b32_e32 v3, 0 -; GFX1013-NEXT: v_mov_b32_e32 v4, 1.0 -; GFX1013-NEXT: v_mov_b32_e32 v5, 2.0 -; GFX1013-NEXT: s_waitcnt lgkmcnt(0) -; GFX1013-NEXT: v_mov_b32_e32 v0, s2 -; GFX1013-NEXT: v_mov_b32_e32 v1, s3 -; GFX1013-NEXT: s_movk_i32 s2, 0x4200 -; GFX1013-NEXT: s_movk_i32 s3, 0x4800 -; GFX1013-NEXT: s_bfe_u32 s2, s2, 0x100000 -; GFX1013-NEXT: v_add_co_u32 v0, vcc_lo, v0, v2 -; GFX1013-NEXT: v_add_co_ci_u32_e32 v1, vcc_lo, 0, v1, vcc_lo -; GFX1013-NEXT: s_or_b32 s1, s2, s1 -; GFX1013-NEXT: s_bfe_u32 s2, s9, 0x100000 -; GFX1013-NEXT: s_bfe_u32 s3, s3, 0x100000 -; GFX1013-NEXT: flat_load_dword v2, v[0:1] -; GFX1013-NEXT: s_lshl_b32 s2, s2, 16 -; GFX1013-NEXT: s_lshl_b32 s3, s3, 16 -; GFX1013-NEXT: s_or_b32 s0, s0, s2 -; GFX1013-NEXT: s_or_b32 s2, s8, s3 -; GFX1013-NEXT: v_mov_b32_e32 v0, 0xb36211c6 -; GFX1013-NEXT: v_mov_b32_e32 v1, 0x102 -; GFX1013-NEXT: v_mov_b32_e32 v6, s1 -; GFX1013-NEXT: v_mov_b32_e32 v7, s0 -; GFX1013-NEXT: v_mov_b32_e32 v8, s2 -; GFX1013-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0) -; GFX1013-NEXT: image_bvh64_intersect_ray v[0:3], v[0:8], s[4:7] a16 -; GFX1013-NEXT: s_waitcnt vmcnt(0) -; GFX1013-NEXT: flat_store_dwordx4 v[0:1], v[0:3] -; GFX1013-NEXT: s_endpgm -; -; GFX11-LABEL: image_bvh64_intersect_ray_a16_nsa_reassign: -; GFX11: ; %bb.0: -; GFX11-NEXT: s_clause 0x1 -; GFX11-NEXT: s_load_b64 s[4:5], s[0:1], 0x24 -; GFX11-NEXT: s_load_b128 s[0:3], s[0:1], 0x34 -; GFX11-NEXT: v_lshlrev_b32_e32 v2, 2, v0 -; GFX11-NEXT: s_mov_b32 s6, 0 -; GFX11-NEXT: s_mov_b32 s9, 0x42004600 -; GFX11-NEXT: s_mov_b32 s8, 2.0 -; GFX11-NEXT: s_mov_b32 s7, 1.0 -; GFX11-NEXT: s_mov_b32 s10, 0x44004700 -; GFX11-NEXT: s_mov_b32 s11, 0x45004800 -; GFX11-NEXT: v_dual_mov_b32 v3, s9 :: v_dual_mov_b32 v4, s10 -; GFX11-NEXT: s_waitcnt lgkmcnt(0) -; GFX11-NEXT: v_dual_mov_b32 v5, s11 :: v_dual_mov_b32 v0, s4 -; GFX11-NEXT: v_mov_b32_e32 v1, s5 -; GFX11-NEXT: s_mov_b32 s4, 0xb36211c6 -; GFX11-NEXT: s_movk_i32 s5, 0x102 -; GFX11-NEXT: s_delay_alu instid0(SALU_CYCLE_1) -; GFX11-NEXT: v_mov_b32_e32 v7, s5 -; GFX11-NEXT: v_add_co_u32 v0, vcc_lo, v0, v2 -; GFX11-NEXT: v_add_co_ci_u32_e32 v1, vcc_lo, 0, v1, vcc_lo -; GFX11-NEXT: v_mov_b32_e32 v6, s4 -; GFX11-NEXT: flat_load_b32 v8, v[0:1] -; GFX11-NEXT: v_dual_mov_b32 v0, s6 :: v_dual_mov_b32 v1, s7 -; GFX11-NEXT: v_mov_b32_e32 v2, s8 -; GFX11-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0) -; GFX11-NEXT: image_bvh64_intersect_ray v[0:3], [v[6:7], v8, v[0:2], v[3:5]], s[0:3] a16 -; GFX11-NEXT: s_waitcnt vmcnt(0) -; GFX11-NEXT: flat_store_b128 v[0:1], v[0:3] -; GFX11-NEXT: s_sendmsg sendmsg(MSG_DEALLOC_VGPRS) -; GFX11-NEXT: s_endpgm - %lid = tail call i32 @llvm.amdgcn.workitem.id.x() - %gep_ray = getelementptr inbounds float, ptr %p_ray, i32 %lid - %ray_extent = load float, ptr %gep_ray, align 4 - %ray_origin0 = insertelement <3 x float> undef, float 0.0, i32 0 - %ray_origin1 = insertelement <3 x float> %ray_origin0, float 1.0, i32 1 - %ray_origin = insertelement <3 x float> %ray_origin1, float 2.0, i32 2 - %ray_dir0 = insertelement <3 x half> undef, half 3.0, i32 0 - %ray_dir1 = insertelement <3 x half> %ray_dir0, half 4.0, i32 1 - %ray_dir = insertelement <3 x half> %ray_dir1, half 5.0, i32 2 - %ray_inv_dir0 = insertelement <3 x half> undef, half 6.0, i32 0 - %ray_inv_dir1 = insertelement <3 x half> %ray_inv_dir0, half 7.0, i32 1 - %ray_inv_dir = insertelement <3 x half> %ray_inv_dir1, half 8.0, i32 2 - %v = call <4 x i32> @llvm.amdgcn.image.bvh.intersect.ray.i64.v4f16(i64 1111111111110, float %ray_extent, <3 x float> %ray_origin, <3 x half> %ray_dir, <3 x half> %ray_inv_dir, <4 x i32> %tdescr) - store <4 x i32> %v, ptr undef - ret void -} diff --git a/llvm/test/CodeGen/AMDGPU/llvm.amdgcn.intersect_ray.ll b/llvm/test/CodeGen/AMDGPU/llvm.amdgcn.intersect_ray.ll --- a/llvm/test/CodeGen/AMDGPU/llvm.amdgcn.intersect_ray.ll +++ b/llvm/test/CodeGen/AMDGPU/llvm.amdgcn.intersect_ray.ll @@ -1,8 +1,12 @@ ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py -; RUN: llc -march=amdgcn -mcpu=gfx1013 -verify-machineinstrs < %s | FileCheck -check-prefixes=GCN,GFX10,GFX1013 %s -; RUN: llc -march=amdgcn -mcpu=gfx1030 -verify-machineinstrs < %s | FileCheck -check-prefixes=GCN,GFX10,GFX1030 %s -; RUN: not --crash llc -march=amdgcn -mcpu=gfx1012 -verify-machineinstrs < %s 2>&1 | FileCheck -check-prefix=ERR %s -; RUN: llc -march=amdgcn -mcpu=gfx1100 -verify-machineinstrs < %s | FileCheck -check-prefixes=GCN,GFX11 %s +; RUN: llc -march=amdgcn -mcpu=gfx1013 -global-isel=0 -verify-machineinstrs < %s | FileCheck -check-prefixes=GCN,GFX10-SDAG,GFX1013-SDAG %s +; RUN: llc -march=amdgcn -mcpu=gfx1013 -global-isel=1 -verify-machineinstrs < %s | FileCheck -check-prefixes=GCN,GFX10-GISEL,GFX1013-GISEL %s +; RUN: llc -march=amdgcn -mcpu=gfx1030 -global-isel=0 -verify-machineinstrs < %s | FileCheck -check-prefixes=GCN,GFX10-SDAG,GFX1030-SDAG %s +; RUN: llc -march=amdgcn -mcpu=gfx1030 -global-isel=1 -verify-machineinstrs < %s | FileCheck -check-prefixes=GCN,GFX10-GISEL,GFX1030-GISEL %s +; RUN: not --crash llc -march=amdgcn -mcpu=gfx1012 -global-isel=0 -verify-machineinstrs < %s 2>&1 | FileCheck -check-prefix=ERR %s +; RUN: not --crash llc -march=amdgcn -mcpu=gfx1012 -global-isel=1 -verify-machineinstrs < %s 2>&1 | FileCheck -check-prefix=ERR %s +; RUN: llc -march=amdgcn -mcpu=gfx1100 -global-isel=0 -verify-machineinstrs < %s | FileCheck -check-prefixes=GCN,GFX11-SDAG %s +; RUN: llc -march=amdgcn -mcpu=gfx1100 -global-isel=1 -verify-machineinstrs < %s | FileCheck -check-prefixes=GCN,GFX11-GISEL %s ; uint4 llvm.amdgcn.image.bvh.intersect.ray.i32.v4f32(uint node_ptr, float ray_extent, float3 ray_origin, float3 ray_dir, float3 ray_inv_dir, uint4 texture_descr) ; uint4 llvm.amdgcn.image.bvh.intersect.ray.i32.v4f16(uint node_ptr, float ray_extent, float3 ray_origin, half3 ray_dir, half3 ray_inv_dir, uint4 texture_descr) @@ -13,8 +17,8 @@ declare <4 x i32> @llvm.amdgcn.image.bvh.intersect.ray.i32.v4f16(i32, float, <3 x float>, <3 x half>, <3 x half>, <4 x i32>) declare <4 x i32> @llvm.amdgcn.image.bvh.intersect.ray.i64.v4f32(i64, float, <3 x float>, <3 x float>, <3 x float>, <4 x i32>) declare <4 x i32> @llvm.amdgcn.image.bvh.intersect.ray.i64.v4f16(i64, float, <3 x float>, <3 x half>, <3 x half>, <4 x i32>) +declare i32 @llvm.amdgcn.workitem.id.x() -; ERR: in function image_bvh_intersect_ray{{.*}}intrinsic not supported on subtarget ; Arguments are flattened to represent the actual VGPR_A layout, so we have no ; extra moves in the generated kernel. define amdgpu_ps <4 x float> @image_bvh_intersect_ray(i32 %node_ptr, float %ray_extent, float %ray_origin_x, float %ray_origin_y, float %ray_origin_z, float %ray_dir_x, float %ray_dir_y, float %ray_dir_z, float %ray_inv_dir_x, float %ray_inv_dir_y, float %ray_inv_dir_z, <4 x i32> inreg %tdescr) { @@ -23,6 +27,7 @@ ; GCN-NEXT: image_bvh_intersect_ray v[0:3], v[0:10], s[0:3] ; GCN-NEXT: s_waitcnt vmcnt(0) ; GCN-NEXT: ; return to shader part epilog +; ERR: in function image_bvh_intersect_ray{{.*}}intrinsic not supported on subtarget main_body: %ray_origin0 = insertelement <3 x float> undef, float %ray_origin_x, i32 0 %ray_origin1 = insertelement <3 x float> %ray_origin0, float %ray_origin_y, i32 1 @@ -34,51 +39,98 @@ %ray_inv_dir1 = insertelement <3 x float> %ray_inv_dir0, float %ray_inv_dir_y, i32 1 %ray_inv_dir = insertelement <3 x float> %ray_inv_dir1, float %ray_inv_dir_z, i32 2 %v = call <4 x i32> @llvm.amdgcn.image.bvh.intersect.ray.i32.v4f32(i32 %node_ptr, float %ray_extent, <3 x float> %ray_origin, <3 x float> %ray_dir, <3 x float> %ray_inv_dir, <4 x i32> %tdescr) - %r = bitcast <4 x i32> %v to <4 x float> - ret <4 x float> %r + %r = bitcast <4 x i32> %v to <4 x float> + ret <4 x float> %r } define amdgpu_ps <4 x float> @image_bvh_intersect_ray_a16(i32 inreg %node_ptr, float inreg %ray_extent, <3 x float> inreg %ray_origin, <3 x half> inreg %ray_dir, <3 x half> inreg %ray_inv_dir, <4 x i32> inreg %tdescr) { -; GFX10-LABEL: image_bvh_intersect_ray_a16: -; GFX10: ; %bb.0: ; %main_body -; GFX10-NEXT: s_mov_b32 s15, s12 -; GFX10-NEXT: s_mov_b32 s12, s9 -; GFX10-NEXT: s_lshr_b32 s9, s7, 16 -; GFX10-NEXT: s_pack_ll_b32_b16 s6, s6, s7 -; GFX10-NEXT: s_pack_ll_b32_b16 s7, s9, s8 -; GFX10-NEXT: v_mov_b32_e32 v0, s0 -; GFX10-NEXT: v_mov_b32_e32 v1, s1 -; GFX10-NEXT: v_mov_b32_e32 v2, s2 -; GFX10-NEXT: v_mov_b32_e32 v3, s3 -; GFX10-NEXT: v_mov_b32_e32 v4, s4 -; GFX10-NEXT: v_mov_b32_e32 v5, s5 -; GFX10-NEXT: v_mov_b32_e32 v6, s6 -; GFX10-NEXT: v_mov_b32_e32 v7, s7 -; GFX10-NEXT: s_mov_b32 s14, s11 -; GFX10-NEXT: s_mov_b32 s13, s10 -; GFX10-NEXT: image_bvh_intersect_ray v[0:3], v[0:7], s[12:15] a16 -; GFX10-NEXT: s_waitcnt vmcnt(0) -; GFX10-NEXT: ; return to shader part epilog +; GFX10-SDAG-LABEL: image_bvh_intersect_ray_a16: +; GFX10-SDAG: ; %bb.0: ; %main_body +; GFX10-SDAG-NEXT: s_mov_b32 s15, s12 +; GFX10-SDAG-NEXT: s_mov_b32 s12, s9 +; GFX10-SDAG-NEXT: s_lshr_b32 s9, s7, 16 +; GFX10-SDAG-NEXT: s_pack_ll_b32_b16 s6, s6, s7 +; GFX10-SDAG-NEXT: s_pack_ll_b32_b16 s7, s9, s8 +; GFX10-SDAG-NEXT: v_mov_b32_e32 v0, s0 +; GFX10-SDAG-NEXT: v_mov_b32_e32 v1, s1 +; GFX10-SDAG-NEXT: v_mov_b32_e32 v2, s2 +; GFX10-SDAG-NEXT: v_mov_b32_e32 v3, s3 +; GFX10-SDAG-NEXT: v_mov_b32_e32 v4, s4 +; GFX10-SDAG-NEXT: v_mov_b32_e32 v5, s5 +; GFX10-SDAG-NEXT: v_mov_b32_e32 v6, s6 +; GFX10-SDAG-NEXT: v_mov_b32_e32 v7, s7 +; GFX10-SDAG-NEXT: s_mov_b32 s14, s11 +; GFX10-SDAG-NEXT: s_mov_b32 s13, s10 +; GFX10-SDAG-NEXT: image_bvh_intersect_ray v[0:3], v[0:7], s[12:15] a16 +; GFX10-SDAG-NEXT: s_waitcnt vmcnt(0) +; GFX10-SDAG-NEXT: ; return to shader part epilog +; +; GFX10-GISEL-LABEL: image_bvh_intersect_ray_a16: +; GFX10-GISEL: ; %bb.0: ; %main_body +; GFX10-GISEL-NEXT: s_mov_b32 s16, s9 +; GFX10-GISEL-NEXT: s_lshr_b32 s9, s5, 16 +; GFX10-GISEL-NEXT: s_and_b32 s5, s5, 0xffff +; GFX10-GISEL-NEXT: s_lshl_b32 s9, s9, 16 +; GFX10-GISEL-NEXT: s_and_b32 s6, s6, 0xffff +; GFX10-GISEL-NEXT: s_or_b32 s5, s5, s9 +; GFX10-GISEL-NEXT: s_and_b32 s9, s7, 0xffff +; GFX10-GISEL-NEXT: s_and_b32 s8, s8, 0xffff +; GFX10-GISEL-NEXT: s_lshl_b32 s9, s9, 16 +; GFX10-GISEL-NEXT: v_alignbit_b32 v7, s8, s7, 16 +; GFX10-GISEL-NEXT: s_or_b32 s6, s6, s9 +; GFX10-GISEL-NEXT: v_mov_b32_e32 v0, s0 +; GFX10-GISEL-NEXT: v_mov_b32_e32 v1, s1 +; GFX10-GISEL-NEXT: v_mov_b32_e32 v2, s2 +; GFX10-GISEL-NEXT: v_mov_b32_e32 v3, s3 +; GFX10-GISEL-NEXT: v_mov_b32_e32 v4, s4 +; GFX10-GISEL-NEXT: v_mov_b32_e32 v5, s5 +; GFX10-GISEL-NEXT: v_mov_b32_e32 v6, s6 +; GFX10-GISEL-NEXT: s_mov_b32 s17, s10 +; GFX10-GISEL-NEXT: s_mov_b32 s18, s11 +; GFX10-GISEL-NEXT: s_mov_b32 s19, s12 +; GFX10-GISEL-NEXT: image_bvh_intersect_ray v[0:3], v[0:7], s[16:19] a16 +; GFX10-GISEL-NEXT: s_waitcnt vmcnt(0) +; GFX10-GISEL-NEXT: ; return to shader part epilog +; +; GFX11-SDAG-LABEL: image_bvh_intersect_ray_a16: +; GFX11-SDAG: ; %bb.0: ; %main_body +; GFX11-SDAG-NEXT: v_dual_mov_b32 v0, s2 :: v_dual_mov_b32 v1, s3 +; GFX11-SDAG-NEXT: s_lshr_b32 s2, s7, 16 +; GFX11-SDAG-NEXT: s_lshr_b32 s3, s5, 16 +; GFX11-SDAG-NEXT: v_dual_mov_b32 v6, s0 :: v_dual_mov_b32 v7, s1 +; GFX11-SDAG-NEXT: s_pack_ll_b32_b16 s2, s3, s2 +; GFX11-SDAG-NEXT: s_pack_ll_b32_b16 s3, s5, s7 +; GFX11-SDAG-NEXT: s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_1) | instid1(SALU_CYCLE_1) +; GFX11-SDAG-NEXT: v_dual_mov_b32 v2, s4 :: v_dual_mov_b32 v3, s3 +; GFX11-SDAG-NEXT: s_pack_ll_b32_b16 s4, s6, s8 +; GFX11-SDAG-NEXT: v_dual_mov_b32 v4, s2 :: v_dual_mov_b32 v5, s4 +; GFX11-SDAG-NEXT: s_mov_b32 s15, s12 +; GFX11-SDAG-NEXT: s_mov_b32 s14, s11 +; GFX11-SDAG-NEXT: s_mov_b32 s13, s10 +; GFX11-SDAG-NEXT: s_mov_b32 s12, s9 +; GFX11-SDAG-NEXT: image_bvh_intersect_ray v[0:3], [v6, v7, v[0:2], v[3:5]], s[12:15] a16 +; GFX11-SDAG-NEXT: s_waitcnt vmcnt(0) +; GFX11-SDAG-NEXT: ; return to shader part epilog ; -; GFX11-LABEL: image_bvh_intersect_ray_a16: -; GFX11: ; %bb.0: ; %main_body -; GFX11-NEXT: v_dual_mov_b32 v0, s2 :: v_dual_mov_b32 v1, s3 -; GFX11-NEXT: s_lshr_b32 s2, s7, 16 -; GFX11-NEXT: s_lshr_b32 s3, s5, 16 -; GFX11-NEXT: v_dual_mov_b32 v6, s0 :: v_dual_mov_b32 v7, s1 -; GFX11-NEXT: s_pack_ll_b32_b16 s2, s3, s2 -; GFX11-NEXT: s_pack_ll_b32_b16 s3, s5, s7 -; GFX11-NEXT: s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_1) | instid1(SALU_CYCLE_1) -; GFX11-NEXT: v_dual_mov_b32 v2, s4 :: v_dual_mov_b32 v3, s3 -; GFX11-NEXT: s_pack_ll_b32_b16 s4, s6, s8 -; GFX11-NEXT: v_dual_mov_b32 v4, s2 :: v_dual_mov_b32 v5, s4 -; GFX11-NEXT: s_mov_b32 s15, s12 -; GFX11-NEXT: s_mov_b32 s14, s11 -; GFX11-NEXT: s_mov_b32 s13, s10 -; GFX11-NEXT: s_mov_b32 s12, s9 -; GFX11-NEXT: image_bvh_intersect_ray v[0:3], [v6, v7, v[0:2], v[3:5]], s[12:15] a16 -; GFX11-NEXT: s_waitcnt vmcnt(0) -; GFX11-NEXT: ; return to shader part epilog +; GFX11-GISEL-LABEL: image_bvh_intersect_ray_a16: +; GFX11-GISEL: ; %bb.0: ; %main_body +; GFX11-GISEL-NEXT: s_mov_b32 s21, s2 +; GFX11-GISEL-NEXT: s_mov_b32 s22, s3 +; GFX11-GISEL-NEXT: s_mov_b32 s23, s4 +; GFX11-GISEL-NEXT: s_pack_ll_b32_b16 s3, s7, s5 +; GFX11-GISEL-NEXT: s_pack_hh_b32_b16 s4, s7, s5 +; GFX11-GISEL-NEXT: s_pack_ll_b32_b16 s5, s8, s6 +; GFX11-GISEL-NEXT: v_dual_mov_b32 v0, s21 :: v_dual_mov_b32 v1, s22 +; GFX11-GISEL-NEXT: v_dual_mov_b32 v2, s23 :: v_dual_mov_b32 v3, s3 +; GFX11-GISEL-NEXT: v_dual_mov_b32 v6, s0 :: v_dual_mov_b32 v7, s1 +; GFX11-GISEL-NEXT: v_dual_mov_b32 v4, s4 :: v_dual_mov_b32 v5, s5 +; GFX11-GISEL-NEXT: s_mov_b32 s16, s9 +; GFX11-GISEL-NEXT: s_mov_b32 s17, s10 +; GFX11-GISEL-NEXT: s_mov_b32 s18, s11 +; GFX11-GISEL-NEXT: s_mov_b32 s19, s12 +; GFX11-GISEL-NEXT: image_bvh_intersect_ray v[0:3], [v6, v7, v[0:2], v[3:5]], s[16:19] a16 +; GFX11-GISEL-NEXT: s_waitcnt vmcnt(0) +; GFX11-GISEL-NEXT: ; return to shader part epilog main_body: %v = call <4 x i32> @llvm.amdgcn.image.bvh.intersect.ray.i32.v4f16(i32 %node_ptr, float %ray_extent, <3 x float> %ray_origin, <3 x half> %ray_dir, <3 x half> %ray_inv_dir, <4 x i32> %tdescr) %r = bitcast <4 x i32> %v to <4 x float> @@ -105,53 +157,99 @@ %ray_inv_dir1 = insertelement <3 x float> %ray_inv_dir0, float %ray_inv_dir_y, i32 1 %ray_inv_dir = insertelement <3 x float> %ray_inv_dir1, float %ray_inv_dir_z, i32 2 %v = call <4 x i32> @llvm.amdgcn.image.bvh.intersect.ray.i64.v4f32(i64 %node_ptr, float %ray_extent, <3 x float> %ray_origin, <3 x float> %ray_dir, <3 x float> %ray_inv_dir, <4 x i32> %tdescr) - %r = bitcast <4 x i32> %v to <4 x float> - ret <4 x float> %r + %r = bitcast <4 x i32> %v to <4 x float> + ret <4 x float> %r } define amdgpu_ps <4 x float> @image_bvh64_intersect_ray_a16(i64 inreg %node_ptr, float inreg %ray_extent, <3 x float> inreg %ray_origin, <3 x half> inreg %ray_dir, <3 x half> inreg %ray_inv_dir, <4 x i32> inreg %tdescr) { -; GFX10-LABEL: image_bvh64_intersect_ray_a16: -; GFX10: ; %bb.0: ; %main_body -; GFX10-NEXT: s_mov_b32 s14, s12 -; GFX10-NEXT: s_mov_b32 s12, s10 -; GFX10-NEXT: s_lshr_b32 s10, s8, 16 -; GFX10-NEXT: s_pack_ll_b32_b16 s7, s7, s8 -; GFX10-NEXT: s_pack_ll_b32_b16 s8, s10, s9 -; GFX10-NEXT: v_mov_b32_e32 v0, s0 -; GFX10-NEXT: v_mov_b32_e32 v1, s1 -; GFX10-NEXT: v_mov_b32_e32 v2, s2 -; GFX10-NEXT: v_mov_b32_e32 v3, s3 -; GFX10-NEXT: v_mov_b32_e32 v4, s4 -; GFX10-NEXT: v_mov_b32_e32 v5, s5 -; GFX10-NEXT: v_mov_b32_e32 v6, s6 -; GFX10-NEXT: v_mov_b32_e32 v7, s7 -; GFX10-NEXT: v_mov_b32_e32 v8, s8 -; GFX10-NEXT: s_mov_b32 s15, s13 -; GFX10-NEXT: s_mov_b32 s13, s11 -; GFX10-NEXT: image_bvh64_intersect_ray v[0:3], v[0:8], s[12:15] a16 -; GFX10-NEXT: s_waitcnt vmcnt(0) -; GFX10-NEXT: ; return to shader part epilog +; GFX10-SDAG-LABEL: image_bvh64_intersect_ray_a16: +; GFX10-SDAG: ; %bb.0: ; %main_body +; GFX10-SDAG-NEXT: s_mov_b32 s14, s12 +; GFX10-SDAG-NEXT: s_mov_b32 s12, s10 +; GFX10-SDAG-NEXT: s_lshr_b32 s10, s8, 16 +; GFX10-SDAG-NEXT: s_pack_ll_b32_b16 s7, s7, s8 +; GFX10-SDAG-NEXT: s_pack_ll_b32_b16 s8, s10, s9 +; GFX10-SDAG-NEXT: v_mov_b32_e32 v0, s0 +; GFX10-SDAG-NEXT: v_mov_b32_e32 v1, s1 +; GFX10-SDAG-NEXT: v_mov_b32_e32 v2, s2 +; GFX10-SDAG-NEXT: v_mov_b32_e32 v3, s3 +; GFX10-SDAG-NEXT: v_mov_b32_e32 v4, s4 +; GFX10-SDAG-NEXT: v_mov_b32_e32 v5, s5 +; GFX10-SDAG-NEXT: v_mov_b32_e32 v6, s6 +; GFX10-SDAG-NEXT: v_mov_b32_e32 v7, s7 +; GFX10-SDAG-NEXT: v_mov_b32_e32 v8, s8 +; GFX10-SDAG-NEXT: s_mov_b32 s15, s13 +; GFX10-SDAG-NEXT: s_mov_b32 s13, s11 +; GFX10-SDAG-NEXT: image_bvh64_intersect_ray v[0:3], v[0:8], s[12:15] a16 +; GFX10-SDAG-NEXT: s_waitcnt vmcnt(0) +; GFX10-SDAG-NEXT: ; return to shader part epilog +; +; GFX10-GISEL-LABEL: image_bvh64_intersect_ray_a16: +; GFX10-GISEL: ; %bb.0: ; %main_body +; GFX10-GISEL-NEXT: s_mov_b32 s16, s10 +; GFX10-GISEL-NEXT: s_lshr_b32 s10, s6, 16 +; GFX10-GISEL-NEXT: s_and_b32 s6, s6, 0xffff +; GFX10-GISEL-NEXT: s_lshl_b32 s10, s10, 16 +; GFX10-GISEL-NEXT: s_and_b32 s7, s7, 0xffff +; GFX10-GISEL-NEXT: s_or_b32 s6, s6, s10 +; GFX10-GISEL-NEXT: s_and_b32 s10, s8, 0xffff +; GFX10-GISEL-NEXT: s_and_b32 s9, s9, 0xffff +; GFX10-GISEL-NEXT: s_lshl_b32 s10, s10, 16 +; GFX10-GISEL-NEXT: v_alignbit_b32 v8, s9, s8, 16 +; GFX10-GISEL-NEXT: s_or_b32 s7, s7, s10 +; GFX10-GISEL-NEXT: v_mov_b32_e32 v0, s0 +; GFX10-GISEL-NEXT: v_mov_b32_e32 v1, s1 +; GFX10-GISEL-NEXT: v_mov_b32_e32 v2, s2 +; GFX10-GISEL-NEXT: v_mov_b32_e32 v3, s3 +; GFX10-GISEL-NEXT: v_mov_b32_e32 v4, s4 +; GFX10-GISEL-NEXT: v_mov_b32_e32 v5, s5 +; GFX10-GISEL-NEXT: v_mov_b32_e32 v6, s6 +; GFX10-GISEL-NEXT: v_mov_b32_e32 v7, s7 +; GFX10-GISEL-NEXT: s_mov_b32 s17, s11 +; GFX10-GISEL-NEXT: s_mov_b32 s18, s12 +; GFX10-GISEL-NEXT: s_mov_b32 s19, s13 +; GFX10-GISEL-NEXT: image_bvh64_intersect_ray v[0:3], v[0:8], s[16:19] a16 +; GFX10-GISEL-NEXT: s_waitcnt vmcnt(0) +; GFX10-GISEL-NEXT: ; return to shader part epilog ; -; GFX11-LABEL: image_bvh64_intersect_ray_a16: -; GFX11: ; %bb.0: ; %main_body -; GFX11-NEXT: v_dual_mov_b32 v0, s3 :: v_dual_mov_b32 v1, s4 -; GFX11-NEXT: v_dual_mov_b32 v2, s5 :: v_dual_mov_b32 v7, s1 -; GFX11-NEXT: s_lshr_b32 s3, s6, 16 -; GFX11-NEXT: s_pack_ll_b32_b16 s1, s6, s8 -; GFX11-NEXT: s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_4) | instid1(SALU_CYCLE_1) -; GFX11-NEXT: v_dual_mov_b32 v6, s0 :: v_dual_mov_b32 v3, s1 -; GFX11-NEXT: s_lshr_b32 s0, s8, 16 -; GFX11-NEXT: v_mov_b32_e32 v8, s2 -; GFX11-NEXT: s_pack_ll_b32_b16 s0, s3, s0 -; GFX11-NEXT: s_pack_ll_b32_b16 s3, s7, s9 -; GFX11-NEXT: v_dual_mov_b32 v4, s0 :: v_dual_mov_b32 v5, s3 -; GFX11-NEXT: s_mov_b32 s15, s13 -; GFX11-NEXT: s_mov_b32 s14, s12 -; GFX11-NEXT: s_mov_b32 s13, s11 -; GFX11-NEXT: s_mov_b32 s12, s10 -; GFX11-NEXT: image_bvh64_intersect_ray v[0:3], [v[6:7], v8, v[0:2], v[3:5]], s[12:15] a16 -; GFX11-NEXT: s_waitcnt vmcnt(0) -; GFX11-NEXT: ; return to shader part epilog +; GFX11-SDAG-LABEL: image_bvh64_intersect_ray_a16: +; GFX11-SDAG: ; %bb.0: ; %main_body +; GFX11-SDAG-NEXT: v_dual_mov_b32 v0, s3 :: v_dual_mov_b32 v1, s4 +; GFX11-SDAG-NEXT: v_dual_mov_b32 v2, s5 :: v_dual_mov_b32 v7, s1 +; GFX11-SDAG-NEXT: s_lshr_b32 s3, s6, 16 +; GFX11-SDAG-NEXT: s_pack_ll_b32_b16 s1, s6, s8 +; GFX11-SDAG-NEXT: s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_4) | instid1(SALU_CYCLE_1) +; GFX11-SDAG-NEXT: v_dual_mov_b32 v6, s0 :: v_dual_mov_b32 v3, s1 +; GFX11-SDAG-NEXT: s_lshr_b32 s0, s8, 16 +; GFX11-SDAG-NEXT: v_mov_b32_e32 v8, s2 +; GFX11-SDAG-NEXT: s_pack_ll_b32_b16 s0, s3, s0 +; GFX11-SDAG-NEXT: s_pack_ll_b32_b16 s3, s7, s9 +; GFX11-SDAG-NEXT: v_dual_mov_b32 v4, s0 :: v_dual_mov_b32 v5, s3 +; GFX11-SDAG-NEXT: s_mov_b32 s15, s13 +; GFX11-SDAG-NEXT: s_mov_b32 s14, s12 +; GFX11-SDAG-NEXT: s_mov_b32 s13, s11 +; GFX11-SDAG-NEXT: s_mov_b32 s12, s10 +; GFX11-SDAG-NEXT: image_bvh64_intersect_ray v[0:3], [v[6:7], v8, v[0:2], v[3:5]], s[12:15] a16 +; GFX11-SDAG-NEXT: s_waitcnt vmcnt(0) +; GFX11-SDAG-NEXT: ; return to shader part epilog +; +; GFX11-GISEL-LABEL: image_bvh64_intersect_ray_a16: +; GFX11-GISEL: ; %bb.0: ; %main_body +; GFX11-GISEL-NEXT: s_mov_b32 s18, s12 +; GFX11-GISEL-NEXT: s_pack_ll_b32_b16 s12, s8, s6 +; GFX11-GISEL-NEXT: s_mov_b32 s19, s13 +; GFX11-GISEL-NEXT: s_pack_hh_b32_b16 s13, s8, s6 +; GFX11-GISEL-NEXT: s_pack_ll_b32_b16 s14, s9, s7 +; GFX11-GISEL-NEXT: v_dual_mov_b32 v0, s3 :: v_dual_mov_b32 v3, s12 +; GFX11-GISEL-NEXT: v_dual_mov_b32 v7, s1 :: v_dual_mov_b32 v6, s0 +; GFX11-GISEL-NEXT: v_dual_mov_b32 v8, s2 :: v_dual_mov_b32 v1, s4 +; GFX11-GISEL-NEXT: v_dual_mov_b32 v2, s5 :: v_dual_mov_b32 v5, s14 +; GFX11-GISEL-NEXT: v_mov_b32_e32 v4, s13 +; GFX11-GISEL-NEXT: s_mov_b32 s16, s10 +; GFX11-GISEL-NEXT: s_mov_b32 s17, s11 +; GFX11-GISEL-NEXT: image_bvh64_intersect_ray v[0:3], [v[6:7], v8, v[0:2], v[3:5]], s[16:19] a16 +; GFX11-GISEL-NEXT: s_waitcnt vmcnt(0) +; GFX11-GISEL-NEXT: ; return to shader part epilog main_body: %v = call <4 x i32> @llvm.amdgcn.image.bvh.intersect.ray.i64.v4f16(i64 %node_ptr, float %ray_extent, <3 x float> %ray_origin, <3 x half> %ray_dir, <3 x half> %ray_inv_dir, <4 x i32> %tdescr) %r = bitcast <4 x i32> %v to <4 x float> @@ -161,83 +259,179 @@ ; TODO: NSA reassign is very limited and cannot work with VGPR tuples and subregs. define amdgpu_kernel void @image_bvh_intersect_ray_nsa_reassign(ptr %p_node_ptr, ptr %p_ray, <4 x i32> inreg %tdescr) { -; GFX1013-LABEL: image_bvh_intersect_ray_nsa_reassign: -; GFX1013: ; %bb.0: ; %main_body -; GFX1013-NEXT: s_load_dwordx8 s[0:7], s[0:1], 0x24 -; GFX1013-NEXT: v_lshlrev_b32_e32 v0, 2, v0 -; GFX1013-NEXT: v_mov_b32_e32 v6, 4.0 -; GFX1013-NEXT: v_mov_b32_e32 v7, 0x40a00000 -; GFX1013-NEXT: v_mov_b32_e32 v8, 0x40c00000 -; GFX1013-NEXT: v_mov_b32_e32 v9, 0x40e00000 -; GFX1013-NEXT: v_mov_b32_e32 v10, 0x41000000 -; GFX1013-NEXT: s_waitcnt lgkmcnt(0) -; GFX1013-NEXT: v_add_co_u32 v2, s0, s0, v0 -; GFX1013-NEXT: v_add_co_ci_u32_e64 v3, s0, s1, 0, s0 -; GFX1013-NEXT: v_add_co_u32 v4, s0, s2, v0 -; GFX1013-NEXT: v_add_co_ci_u32_e64 v5, s0, s3, 0, s0 -; GFX1013-NEXT: flat_load_dword v0, v[2:3] -; GFX1013-NEXT: flat_load_dword v1, v[4:5] -; GFX1013-NEXT: v_mov_b32_e32 v2, 0 -; GFX1013-NEXT: v_mov_b32_e32 v3, 1.0 -; GFX1013-NEXT: v_mov_b32_e32 v4, 2.0 -; GFX1013-NEXT: v_mov_b32_e32 v5, 0x40400000 -; GFX1013-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0) -; GFX1013-NEXT: image_bvh_intersect_ray v[0:3], v[0:10], s[4:7] -; GFX1013-NEXT: s_waitcnt vmcnt(0) -; GFX1013-NEXT: flat_store_dwordx4 v[0:1], v[0:3] -; GFX1013-NEXT: s_endpgm +; GFX1013-SDAG-LABEL: image_bvh_intersect_ray_nsa_reassign: +; GFX1013-SDAG: ; %bb.0: ; %main_body +; GFX1013-SDAG-NEXT: s_load_dwordx8 s[0:7], s[0:1], 0x24 +; GFX1013-SDAG-NEXT: v_lshlrev_b32_e32 v0, 2, v0 +; GFX1013-SDAG-NEXT: v_mov_b32_e32 v6, 4.0 +; GFX1013-SDAG-NEXT: v_mov_b32_e32 v7, 0x40a00000 +; GFX1013-SDAG-NEXT: v_mov_b32_e32 v8, 0x40c00000 +; GFX1013-SDAG-NEXT: v_mov_b32_e32 v9, 0x40e00000 +; GFX1013-SDAG-NEXT: v_mov_b32_e32 v10, 0x41000000 +; GFX1013-SDAG-NEXT: s_waitcnt lgkmcnt(0) +; GFX1013-SDAG-NEXT: v_add_co_u32 v2, s0, s0, v0 +; GFX1013-SDAG-NEXT: v_add_co_ci_u32_e64 v3, s0, s1, 0, s0 +; GFX1013-SDAG-NEXT: v_add_co_u32 v4, s0, s2, v0 +; GFX1013-SDAG-NEXT: v_add_co_ci_u32_e64 v5, s0, s3, 0, s0 +; GFX1013-SDAG-NEXT: flat_load_dword v0, v[2:3] +; GFX1013-SDAG-NEXT: flat_load_dword v1, v[4:5] +; GFX1013-SDAG-NEXT: v_mov_b32_e32 v2, 0 +; GFX1013-SDAG-NEXT: v_mov_b32_e32 v3, 1.0 +; GFX1013-SDAG-NEXT: v_mov_b32_e32 v4, 2.0 +; GFX1013-SDAG-NEXT: v_mov_b32_e32 v5, 0x40400000 +; GFX1013-SDAG-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0) +; GFX1013-SDAG-NEXT: image_bvh_intersect_ray v[0:3], v[0:10], s[4:7] +; GFX1013-SDAG-NEXT: s_waitcnt vmcnt(0) +; GFX1013-SDAG-NEXT: flat_store_dwordx4 v[0:1], v[0:3] +; GFX1013-SDAG-NEXT: s_endpgm +; +; GFX1013-GISEL-LABEL: image_bvh_intersect_ray_nsa_reassign: +; GFX1013-GISEL: ; %bb.0: ; %main_body +; GFX1013-GISEL-NEXT: s_load_dwordx8 s[0:7], s[0:1], 0x24 +; GFX1013-GISEL-NEXT: v_lshlrev_b32_e32 v6, 2, v0 +; GFX1013-GISEL-NEXT: v_mov_b32_e32 v7, 0x40a00000 +; GFX1013-GISEL-NEXT: v_mov_b32_e32 v8, 0x40c00000 +; GFX1013-GISEL-NEXT: v_mov_b32_e32 v9, 0x40e00000 +; GFX1013-GISEL-NEXT: v_mov_b32_e32 v10, 0x41000000 +; GFX1013-GISEL-NEXT: s_waitcnt lgkmcnt(0) +; GFX1013-GISEL-NEXT: v_mov_b32_e32 v0, s0 +; GFX1013-GISEL-NEXT: v_mov_b32_e32 v1, s1 +; GFX1013-GISEL-NEXT: v_mov_b32_e32 v2, s2 +; GFX1013-GISEL-NEXT: v_mov_b32_e32 v3, s3 +; GFX1013-GISEL-NEXT: v_add_co_u32 v4, vcc_lo, v0, v6 +; GFX1013-GISEL-NEXT: v_add_co_ci_u32_e32 v5, vcc_lo, 0, v1, vcc_lo +; GFX1013-GISEL-NEXT: v_add_co_u32 v2, vcc_lo, v2, v6 +; GFX1013-GISEL-NEXT: v_add_co_ci_u32_e32 v3, vcc_lo, 0, v3, vcc_lo +; GFX1013-GISEL-NEXT: v_mov_b32_e32 v6, 4.0 +; GFX1013-GISEL-NEXT: flat_load_dword v0, v[4:5] +; GFX1013-GISEL-NEXT: flat_load_dword v1, v[2:3] +; GFX1013-GISEL-NEXT: v_mov_b32_e32 v2, 0 +; GFX1013-GISEL-NEXT: v_mov_b32_e32 v3, 1.0 +; GFX1013-GISEL-NEXT: v_mov_b32_e32 v4, 2.0 +; GFX1013-GISEL-NEXT: v_mov_b32_e32 v5, 0x40400000 +; GFX1013-GISEL-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0) +; GFX1013-GISEL-NEXT: image_bvh_intersect_ray v[0:3], v[0:10], s[4:7] +; GFX1013-GISEL-NEXT: s_waitcnt vmcnt(0) +; GFX1013-GISEL-NEXT: flat_store_dwordx4 v[0:1], v[0:3] +; GFX1013-GISEL-NEXT: s_endpgm +; +; GFX1030-SDAG-LABEL: image_bvh_intersect_ray_nsa_reassign: +; GFX1030-SDAG: ; %bb.0: ; %main_body +; GFX1030-SDAG-NEXT: s_load_dwordx8 s[0:7], s[0:1], 0x24 +; GFX1030-SDAG-NEXT: v_lshlrev_b32_e32 v2, 2, v0 +; GFX1030-SDAG-NEXT: v_mov_b32_e32 v10, 0x41000000 +; GFX1030-SDAG-NEXT: v_mov_b32_e32 v9, 0x40e00000 +; GFX1030-SDAG-NEXT: v_mov_b32_e32 v8, 0x40c00000 +; GFX1030-SDAG-NEXT: v_mov_b32_e32 v7, 0x40a00000 +; GFX1030-SDAG-NEXT: v_mov_b32_e32 v6, 4.0 +; GFX1030-SDAG-NEXT: v_mov_b32_e32 v5, 0x40400000 +; GFX1030-SDAG-NEXT: v_mov_b32_e32 v4, 2.0 +; GFX1030-SDAG-NEXT: s_waitcnt lgkmcnt(0) +; GFX1030-SDAG-NEXT: v_add_co_u32 v0, s0, s0, v2 +; GFX1030-SDAG-NEXT: v_add_co_ci_u32_e64 v1, null, s1, 0, s0 +; GFX1030-SDAG-NEXT: v_add_co_u32 v2, s0, s2, v2 +; GFX1030-SDAG-NEXT: v_add_co_ci_u32_e64 v3, null, s3, 0, s0 +; GFX1030-SDAG-NEXT: flat_load_dword v0, v[0:1] +; GFX1030-SDAG-NEXT: flat_load_dword v1, v[2:3] +; GFX1030-SDAG-NEXT: v_mov_b32_e32 v2, 0 +; GFX1030-SDAG-NEXT: v_mov_b32_e32 v3, 1.0 +; GFX1030-SDAG-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0) +; GFX1030-SDAG-NEXT: image_bvh_intersect_ray v[0:3], v[0:10], s[4:7] +; GFX1030-SDAG-NEXT: s_waitcnt vmcnt(0) +; GFX1030-SDAG-NEXT: flat_store_dwordx4 v[0:1], v[0:3] +; GFX1030-SDAG-NEXT: s_endpgm ; -; GFX1030-LABEL: image_bvh_intersect_ray_nsa_reassign: -; GFX1030: ; %bb.0: ; %main_body -; GFX1030-NEXT: s_load_dwordx8 s[0:7], s[0:1], 0x24 -; GFX1030-NEXT: v_lshlrev_b32_e32 v2, 2, v0 -; GFX1030-NEXT: v_mov_b32_e32 v10, 0x41000000 -; GFX1030-NEXT: v_mov_b32_e32 v9, 0x40e00000 -; GFX1030-NEXT: v_mov_b32_e32 v8, 0x40c00000 -; GFX1030-NEXT: v_mov_b32_e32 v7, 0x40a00000 -; GFX1030-NEXT: v_mov_b32_e32 v6, 4.0 -; GFX1030-NEXT: v_mov_b32_e32 v5, 0x40400000 -; GFX1030-NEXT: v_mov_b32_e32 v4, 2.0 -; GFX1030-NEXT: s_waitcnt lgkmcnt(0) -; GFX1030-NEXT: v_add_co_u32 v0, s0, s0, v2 -; GFX1030-NEXT: v_add_co_ci_u32_e64 v1, null, s1, 0, s0 -; GFX1030-NEXT: v_add_co_u32 v2, s0, s2, v2 -; GFX1030-NEXT: v_add_co_ci_u32_e64 v3, null, s3, 0, s0 -; GFX1030-NEXT: flat_load_dword v0, v[0:1] -; GFX1030-NEXT: flat_load_dword v1, v[2:3] -; GFX1030-NEXT: v_mov_b32_e32 v2, 0 -; GFX1030-NEXT: v_mov_b32_e32 v3, 1.0 -; GFX1030-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0) -; GFX1030-NEXT: image_bvh_intersect_ray v[0:3], v[0:10], s[4:7] -; GFX1030-NEXT: s_waitcnt vmcnt(0) -; GFX1030-NEXT: flat_store_dwordx4 v[0:1], v[0:3] -; GFX1030-NEXT: s_endpgm +; GFX1030-GISEL-LABEL: image_bvh_intersect_ray_nsa_reassign: +; GFX1030-GISEL: ; %bb.0: ; %main_body +; GFX1030-GISEL-NEXT: s_load_dwordx8 s[0:7], s[0:1], 0x24 +; GFX1030-GISEL-NEXT: v_lshlrev_b32_e32 v4, 2, v0 +; GFX1030-GISEL-NEXT: v_mov_b32_e32 v5, 0x40400000 +; GFX1030-GISEL-NEXT: v_mov_b32_e32 v6, 4.0 +; GFX1030-GISEL-NEXT: v_mov_b32_e32 v7, 0x40a00000 +; GFX1030-GISEL-NEXT: v_mov_b32_e32 v8, 0x40c00000 +; GFX1030-GISEL-NEXT: v_mov_b32_e32 v9, 0x40e00000 +; GFX1030-GISEL-NEXT: v_mov_b32_e32 v10, 0x41000000 +; GFX1030-GISEL-NEXT: s_waitcnt lgkmcnt(0) +; GFX1030-GISEL-NEXT: v_mov_b32_e32 v0, s0 +; GFX1030-GISEL-NEXT: v_mov_b32_e32 v1, s1 +; GFX1030-GISEL-NEXT: v_mov_b32_e32 v2, s2 +; GFX1030-GISEL-NEXT: v_mov_b32_e32 v3, s3 +; GFX1030-GISEL-NEXT: v_add_co_u32 v0, vcc_lo, v0, v4 +; GFX1030-GISEL-NEXT: v_add_co_ci_u32_e32 v1, vcc_lo, 0, v1, vcc_lo +; GFX1030-GISEL-NEXT: v_add_co_u32 v2, vcc_lo, v2, v4 +; GFX1030-GISEL-NEXT: v_add_co_ci_u32_e32 v3, vcc_lo, 0, v3, vcc_lo +; GFX1030-GISEL-NEXT: v_mov_b32_e32 v4, 2.0 +; GFX1030-GISEL-NEXT: flat_load_dword v0, v[0:1] +; GFX1030-GISEL-NEXT: flat_load_dword v1, v[2:3] +; GFX1030-GISEL-NEXT: v_mov_b32_e32 v2, 0 +; GFX1030-GISEL-NEXT: v_mov_b32_e32 v3, 1.0 +; GFX1030-GISEL-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0) +; GFX1030-GISEL-NEXT: image_bvh_intersect_ray v[0:3], v[0:10], s[4:7] +; GFX1030-GISEL-NEXT: s_waitcnt vmcnt(0) +; GFX1030-GISEL-NEXT: flat_store_dwordx4 v[0:1], v[0:3] +; GFX1030-GISEL-NEXT: s_endpgm ; -; GFX11-LABEL: image_bvh_intersect_ray_nsa_reassign: -; GFX11: ; %bb.0: ; %main_body -; GFX11-NEXT: s_load_b256 s[0:7], s[0:1], 0x24 -; GFX11-NEXT: v_dual_mov_b32 v5, 0x40a00000 :: v_dual_lshlrev_b32 v2, 2, v0 -; GFX11-NEXT: v_mov_b32_e32 v6, 0 -; GFX11-NEXT: v_mov_b32_e32 v8, 2.0 -; GFX11-NEXT: v_dual_mov_b32 v4, 4.0 :: v_dual_mov_b32 v7, 1.0 -; GFX11-NEXT: s_waitcnt lgkmcnt(0) -; GFX11-NEXT: v_add_co_u32 v0, s0, s0, v2 -; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1) -; GFX11-NEXT: v_add_co_ci_u32_e64 v1, null, s1, 0, s0 -; GFX11-NEXT: v_add_co_u32 v2, s0, s2, v2 -; GFX11-NEXT: v_add_co_ci_u32_e64 v3, null, s3, 0, s0 -; GFX11-NEXT: flat_load_b32 v9, v[0:1] -; GFX11-NEXT: flat_load_b32 v10, v[2:3] -; GFX11-NEXT: v_mov_b32_e32 v0, 0x40c00000 -; GFX11-NEXT: v_mov_b32_e32 v1, 0x40e00000 -; GFX11-NEXT: v_mov_b32_e32 v2, 0x41000000 -; GFX11-NEXT: v_mov_b32_e32 v3, 0x40400000 -; GFX11-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0) -; GFX11-NEXT: image_bvh_intersect_ray v[0:3], [v9, v10, v[6:8], v[3:5], v[0:2]], s[4:7] -; GFX11-NEXT: s_waitcnt vmcnt(0) -; GFX11-NEXT: flat_store_b128 v[0:1], v[0:3] -; GFX11-NEXT: s_sendmsg sendmsg(MSG_DEALLOC_VGPRS) -; GFX11-NEXT: s_endpgm +; GFX11-SDAG-LABEL: image_bvh_intersect_ray_nsa_reassign: +; GFX11-SDAG: ; %bb.0: ; %main_body +; GFX11-SDAG-NEXT: s_load_b256 s[0:7], s[0:1], 0x24 +; GFX11-SDAG-NEXT: v_dual_mov_b32 v5, 0x40a00000 :: v_dual_lshlrev_b32 v2, 2, v0 +; GFX11-SDAG-NEXT: v_mov_b32_e32 v6, 0 +; GFX11-SDAG-NEXT: v_mov_b32_e32 v8, 2.0 +; GFX11-SDAG-NEXT: v_dual_mov_b32 v4, 4.0 :: v_dual_mov_b32 v7, 1.0 +; GFX11-SDAG-NEXT: s_waitcnt lgkmcnt(0) +; GFX11-SDAG-NEXT: v_add_co_u32 v0, s0, s0, v2 +; GFX11-SDAG-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1) +; GFX11-SDAG-NEXT: v_add_co_ci_u32_e64 v1, null, s1, 0, s0 +; GFX11-SDAG-NEXT: v_add_co_u32 v2, s0, s2, v2 +; GFX11-SDAG-NEXT: v_add_co_ci_u32_e64 v3, null, s3, 0, s0 +; GFX11-SDAG-NEXT: flat_load_b32 v9, v[0:1] +; GFX11-SDAG-NEXT: flat_load_b32 v10, v[2:3] +; GFX11-SDAG-NEXT: v_mov_b32_e32 v0, 0x40c00000 +; GFX11-SDAG-NEXT: v_mov_b32_e32 v1, 0x40e00000 +; GFX11-SDAG-NEXT: v_mov_b32_e32 v2, 0x41000000 +; GFX11-SDAG-NEXT: v_mov_b32_e32 v3, 0x40400000 +; GFX11-SDAG-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0) +; GFX11-SDAG-NEXT: image_bvh_intersect_ray v[0:3], [v9, v10, v[6:8], v[3:5], v[0:2]], s[4:7] +; GFX11-SDAG-NEXT: s_waitcnt vmcnt(0) +; GFX11-SDAG-NEXT: flat_store_b128 v[0:1], v[0:3] +; GFX11-SDAG-NEXT: s_sendmsg sendmsg(MSG_DEALLOC_VGPRS) +; GFX11-SDAG-NEXT: s_endpgm +; +; GFX11-GISEL-LABEL: image_bvh_intersect_ray_nsa_reassign: +; GFX11-GISEL: ; %bb.0: ; %main_body +; GFX11-GISEL-NEXT: s_load_b256 s[0:7], s[0:1], 0x24 +; GFX11-GISEL-NEXT: v_lshlrev_b32_e32 v4, 2, v0 +; GFX11-GISEL-NEXT: s_mov_b32 s9, 0x40400000 +; GFX11-GISEL-NEXT: s_mov_b32 s12, 0x40c00000 +; GFX11-GISEL-NEXT: s_mov_b32 s11, 0x40a00000 +; GFX11-GISEL-NEXT: s_mov_b32 s10, 4.0 +; GFX11-GISEL-NEXT: s_mov_b32 s14, 0x41000000 +; GFX11-GISEL-NEXT: s_mov_b32 s13, 0x40e00000 +; GFX11-GISEL-NEXT: v_mov_b32_e32 v6, s12 +; GFX11-GISEL-NEXT: v_dual_mov_b32 v8, s14 :: v_dual_mov_b32 v7, s13 +; GFX11-GISEL-NEXT: s_waitcnt lgkmcnt(0) +; GFX11-GISEL-NEXT: v_dual_mov_b32 v0, s0 :: v_dual_mov_b32 v1, s1 +; GFX11-GISEL-NEXT: s_mov_b32 s1, 1.0 +; GFX11-GISEL-NEXT: s_mov_b32 s0, 0 +; GFX11-GISEL-NEXT: v_dual_mov_b32 v2, s2 :: v_dual_mov_b32 v3, s3 +; GFX11-GISEL-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_3) +; GFX11-GISEL-NEXT: v_add_co_u32 v0, vcc_lo, v0, v4 +; GFX11-GISEL-NEXT: v_add_co_ci_u32_e32 v1, vcc_lo, 0, v1, vcc_lo +; GFX11-GISEL-NEXT: v_add_co_u32 v2, vcc_lo, v2, v4 +; GFX11-GISEL-NEXT: s_delay_alu instid0(VALU_DEP_4) +; GFX11-GISEL-NEXT: v_add_co_ci_u32_e32 v3, vcc_lo, 0, v3, vcc_lo +; GFX11-GISEL-NEXT: flat_load_b32 v9, v[0:1] +; GFX11-GISEL-NEXT: flat_load_b32 v10, v[2:3] +; GFX11-GISEL-NEXT: s_mov_b32 s2, 2.0 +; GFX11-GISEL-NEXT: v_dual_mov_b32 v0, s0 :: v_dual_mov_b32 v3, s9 +; GFX11-GISEL-NEXT: v_dual_mov_b32 v1, s1 :: v_dual_mov_b32 v2, s2 +; GFX11-GISEL-NEXT: v_dual_mov_b32 v5, s11 :: v_dual_mov_b32 v4, s10 +; GFX11-GISEL-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0) +; GFX11-GISEL-NEXT: image_bvh_intersect_ray v[0:3], [v9, v10, v[0:2], v[3:5], v[6:8]], s[4:7] +; GFX11-GISEL-NEXT: s_waitcnt vmcnt(0) +; GFX11-GISEL-NEXT: flat_store_b128 v[0:1], v[0:3] +; GFX11-GISEL-NEXT: s_sendmsg sendmsg(MSG_DEALLOC_VGPRS) +; GFX11-GISEL-NEXT: s_endpgm main_body: %lid = tail call i32 @llvm.amdgcn.workitem.id.x() %gep_node_ptr = getelementptr inbounds i32, ptr %p_node_ptr, i32 %lid @@ -259,75 +453,196 @@ } define amdgpu_kernel void @image_bvh_intersect_ray_a16_nsa_reassign(ptr %p_node_ptr, ptr %p_ray, <4 x i32> inreg %tdescr) { -; GFX1013-LABEL: image_bvh_intersect_ray_a16_nsa_reassign: -; GFX1013: ; %bb.0: ; %main_body -; GFX1013-NEXT: s_load_dwordx8 s[0:7], s[0:1], 0x24 -; GFX1013-NEXT: v_lshlrev_b32_e32 v0, 2, v0 -; GFX1013-NEXT: v_mov_b32_e32 v6, 0x46004500 -; GFX1013-NEXT: v_mov_b32_e32 v7, 0x48004700 -; GFX1013-NEXT: s_waitcnt lgkmcnt(0) -; GFX1013-NEXT: v_add_co_u32 v2, s0, s0, v0 -; GFX1013-NEXT: v_add_co_ci_u32_e64 v3, s0, s1, 0, s0 -; GFX1013-NEXT: v_add_co_u32 v4, s0, s2, v0 -; GFX1013-NEXT: v_add_co_ci_u32_e64 v5, s0, s3, 0, s0 -; GFX1013-NEXT: flat_load_dword v0, v[2:3] -; GFX1013-NEXT: flat_load_dword v1, v[4:5] -; GFX1013-NEXT: v_mov_b32_e32 v2, 0 -; GFX1013-NEXT: v_mov_b32_e32 v3, 1.0 -; GFX1013-NEXT: v_mov_b32_e32 v4, 2.0 -; GFX1013-NEXT: v_mov_b32_e32 v5, 0x44004200 -; GFX1013-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0) -; GFX1013-NEXT: image_bvh_intersect_ray v[0:3], v[0:7], s[4:7] a16 -; GFX1013-NEXT: s_waitcnt vmcnt(0) -; GFX1013-NEXT: flat_store_dwordx4 v[0:1], v[0:3] -; GFX1013-NEXT: s_endpgm +; GFX1013-SDAG-LABEL: image_bvh_intersect_ray_a16_nsa_reassign: +; GFX1013-SDAG: ; %bb.0: ; %main_body +; GFX1013-SDAG-NEXT: s_load_dwordx8 s[0:7], s[0:1], 0x24 +; GFX1013-SDAG-NEXT: v_lshlrev_b32_e32 v0, 2, v0 +; GFX1013-SDAG-NEXT: v_mov_b32_e32 v6, 0x46004500 +; GFX1013-SDAG-NEXT: v_mov_b32_e32 v7, 0x48004700 +; GFX1013-SDAG-NEXT: s_waitcnt lgkmcnt(0) +; GFX1013-SDAG-NEXT: v_add_co_u32 v2, s0, s0, v0 +; GFX1013-SDAG-NEXT: v_add_co_ci_u32_e64 v3, s0, s1, 0, s0 +; GFX1013-SDAG-NEXT: v_add_co_u32 v4, s0, s2, v0 +; GFX1013-SDAG-NEXT: v_add_co_ci_u32_e64 v5, s0, s3, 0, s0 +; GFX1013-SDAG-NEXT: flat_load_dword v0, v[2:3] +; GFX1013-SDAG-NEXT: flat_load_dword v1, v[4:5] +; GFX1013-SDAG-NEXT: v_mov_b32_e32 v2, 0 +; GFX1013-SDAG-NEXT: v_mov_b32_e32 v3, 1.0 +; GFX1013-SDAG-NEXT: v_mov_b32_e32 v4, 2.0 +; GFX1013-SDAG-NEXT: v_mov_b32_e32 v5, 0x44004200 +; GFX1013-SDAG-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0) +; GFX1013-SDAG-NEXT: image_bvh_intersect_ray v[0:3], v[0:7], s[4:7] a16 +; GFX1013-SDAG-NEXT: s_waitcnt vmcnt(0) +; GFX1013-SDAG-NEXT: flat_store_dwordx4 v[0:1], v[0:3] +; GFX1013-SDAG-NEXT: s_endpgm +; +; GFX1013-GISEL-LABEL: image_bvh_intersect_ray_a16_nsa_reassign: +; GFX1013-GISEL: ; %bb.0: ; %main_body +; GFX1013-GISEL-NEXT: s_load_dwordx8 s[0:7], s[0:1], 0x24 +; GFX1013-GISEL-NEXT: v_lshlrev_b32_e32 v6, 2, v0 +; GFX1013-GISEL-NEXT: s_movk_i32 s9, 0x4600 +; GFX1013-GISEL-NEXT: s_movk_i32 s8, 0x4700 +; GFX1013-GISEL-NEXT: s_bfe_u32 s8, s8, 0x100000 +; GFX1013-GISEL-NEXT: s_waitcnt lgkmcnt(0) +; GFX1013-GISEL-NEXT: v_mov_b32_e32 v0, s0 +; GFX1013-GISEL-NEXT: v_mov_b32_e32 v1, s1 +; GFX1013-GISEL-NEXT: v_mov_b32_e32 v2, s2 +; GFX1013-GISEL-NEXT: v_mov_b32_e32 v3, s3 +; GFX1013-GISEL-NEXT: s_movk_i32 s1, 0x4400 +; GFX1013-GISEL-NEXT: v_add_co_u32 v4, vcc_lo, v0, v6 +; GFX1013-GISEL-NEXT: v_add_co_ci_u32_e32 v5, vcc_lo, 0, v1, vcc_lo +; GFX1013-GISEL-NEXT: v_add_co_u32 v2, vcc_lo, v2, v6 +; GFX1013-GISEL-NEXT: v_add_co_ci_u32_e32 v3, vcc_lo, 0, v3, vcc_lo +; GFX1013-GISEL-NEXT: s_movk_i32 s2, 0x4200 +; GFX1013-GISEL-NEXT: flat_load_dword v0, v[4:5] +; GFX1013-GISEL-NEXT: flat_load_dword v1, v[2:3] +; GFX1013-GISEL-NEXT: s_bfe_u32 s1, s1, 0x100000 +; GFX1013-GISEL-NEXT: s_movk_i32 s3, 0x4800 +; GFX1013-GISEL-NEXT: s_bfe_u32 s2, s2, 0x100000 +; GFX1013-GISEL-NEXT: s_lshl_b32 s1, s1, 16 +; GFX1013-GISEL-NEXT: s_movk_i32 s0, 0x4500 +; GFX1013-GISEL-NEXT: s_or_b32 s1, s2, s1 +; GFX1013-GISEL-NEXT: s_bfe_u32 s2, s9, 0x100000 +; GFX1013-GISEL-NEXT: s_bfe_u32 s3, s3, 0x100000 +; GFX1013-GISEL-NEXT: s_bfe_u32 s0, s0, 0x100000 +; GFX1013-GISEL-NEXT: s_lshl_b32 s2, s2, 16 +; GFX1013-GISEL-NEXT: s_lshl_b32 s3, s3, 16 +; GFX1013-GISEL-NEXT: s_or_b32 s0, s0, s2 +; GFX1013-GISEL-NEXT: s_or_b32 s2, s8, s3 +; GFX1013-GISEL-NEXT: v_mov_b32_e32 v2, 0 +; GFX1013-GISEL-NEXT: v_mov_b32_e32 v3, 1.0 +; GFX1013-GISEL-NEXT: v_mov_b32_e32 v4, 2.0 +; GFX1013-GISEL-NEXT: v_mov_b32_e32 v5, s1 +; GFX1013-GISEL-NEXT: v_mov_b32_e32 v6, s0 +; GFX1013-GISEL-NEXT: v_mov_b32_e32 v7, s2 +; GFX1013-GISEL-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0) +; GFX1013-GISEL-NEXT: image_bvh_intersect_ray v[0:3], v[0:7], s[4:7] a16 +; GFX1013-GISEL-NEXT: s_waitcnt vmcnt(0) +; GFX1013-GISEL-NEXT: flat_store_dwordx4 v[0:1], v[0:3] +; GFX1013-GISEL-NEXT: s_endpgm +; +; GFX1030-SDAG-LABEL: image_bvh_intersect_ray_a16_nsa_reassign: +; GFX1030-SDAG: ; %bb.0: ; %main_body +; GFX1030-SDAG-NEXT: s_load_dwordx8 s[0:7], s[0:1], 0x24 +; GFX1030-SDAG-NEXT: v_lshlrev_b32_e32 v2, 2, v0 +; GFX1030-SDAG-NEXT: v_mov_b32_e32 v4, 2.0 +; GFX1030-SDAG-NEXT: v_mov_b32_e32 v5, 0x44004200 +; GFX1030-SDAG-NEXT: v_mov_b32_e32 v6, 0x46004500 +; GFX1030-SDAG-NEXT: v_mov_b32_e32 v7, 0x48004700 +; GFX1030-SDAG-NEXT: s_waitcnt lgkmcnt(0) +; GFX1030-SDAG-NEXT: v_add_co_u32 v0, s0, s0, v2 +; GFX1030-SDAG-NEXT: v_add_co_ci_u32_e64 v1, null, s1, 0, s0 +; GFX1030-SDAG-NEXT: v_add_co_u32 v2, s0, s2, v2 +; GFX1030-SDAG-NEXT: v_add_co_ci_u32_e64 v3, null, s3, 0, s0 +; GFX1030-SDAG-NEXT: flat_load_dword v0, v[0:1] +; GFX1030-SDAG-NEXT: flat_load_dword v1, v[2:3] +; GFX1030-SDAG-NEXT: v_mov_b32_e32 v2, 0 +; GFX1030-SDAG-NEXT: v_mov_b32_e32 v3, 1.0 +; GFX1030-SDAG-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0) +; GFX1030-SDAG-NEXT: image_bvh_intersect_ray v[0:3], v[0:7], s[4:7] a16 +; GFX1030-SDAG-NEXT: s_waitcnt vmcnt(0) +; GFX1030-SDAG-NEXT: flat_store_dwordx4 v[0:1], v[0:3] +; GFX1030-SDAG-NEXT: s_endpgm ; -; GFX1030-LABEL: image_bvh_intersect_ray_a16_nsa_reassign: -; GFX1030: ; %bb.0: ; %main_body -; GFX1030-NEXT: s_load_dwordx8 s[0:7], s[0:1], 0x24 -; GFX1030-NEXT: v_lshlrev_b32_e32 v2, 2, v0 -; GFX1030-NEXT: v_mov_b32_e32 v4, 2.0 -; GFX1030-NEXT: v_mov_b32_e32 v5, 0x44004200 -; GFX1030-NEXT: v_mov_b32_e32 v6, 0x46004500 -; GFX1030-NEXT: v_mov_b32_e32 v7, 0x48004700 -; GFX1030-NEXT: s_waitcnt lgkmcnt(0) -; GFX1030-NEXT: v_add_co_u32 v0, s0, s0, v2 -; GFX1030-NEXT: v_add_co_ci_u32_e64 v1, null, s1, 0, s0 -; GFX1030-NEXT: v_add_co_u32 v2, s0, s2, v2 -; GFX1030-NEXT: v_add_co_ci_u32_e64 v3, null, s3, 0, s0 -; GFX1030-NEXT: flat_load_dword v0, v[0:1] -; GFX1030-NEXT: flat_load_dword v1, v[2:3] -; GFX1030-NEXT: v_mov_b32_e32 v2, 0 -; GFX1030-NEXT: v_mov_b32_e32 v3, 1.0 -; GFX1030-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0) -; GFX1030-NEXT: image_bvh_intersect_ray v[0:3], v[0:7], s[4:7] a16 -; GFX1030-NEXT: s_waitcnt vmcnt(0) -; GFX1030-NEXT: flat_store_dwordx4 v[0:1], v[0:3] -; GFX1030-NEXT: s_endpgm +; GFX1030-GISEL-LABEL: image_bvh_intersect_ray_a16_nsa_reassign: +; GFX1030-GISEL: ; %bb.0: ; %main_body +; GFX1030-GISEL-NEXT: s_load_dwordx8 s[0:7], s[0:1], 0x24 +; GFX1030-GISEL-NEXT: v_lshlrev_b32_e32 v4, 2, v0 +; GFX1030-GISEL-NEXT: s_movk_i32 s9, 0x4600 +; GFX1030-GISEL-NEXT: s_movk_i32 s8, 0x4700 +; GFX1030-GISEL-NEXT: s_bfe_u32 s8, s8, 0x100000 +; GFX1030-GISEL-NEXT: s_waitcnt lgkmcnt(0) +; GFX1030-GISEL-NEXT: v_mov_b32_e32 v0, s0 +; GFX1030-GISEL-NEXT: v_mov_b32_e32 v1, s1 +; GFX1030-GISEL-NEXT: v_mov_b32_e32 v2, s2 +; GFX1030-GISEL-NEXT: v_mov_b32_e32 v3, s3 +; GFX1030-GISEL-NEXT: s_movk_i32 s1, 0x4400 +; GFX1030-GISEL-NEXT: v_add_co_u32 v0, vcc_lo, v0, v4 +; GFX1030-GISEL-NEXT: v_add_co_ci_u32_e32 v1, vcc_lo, 0, v1, vcc_lo +; GFX1030-GISEL-NEXT: v_add_co_u32 v2, vcc_lo, v2, v4 +; GFX1030-GISEL-NEXT: v_add_co_ci_u32_e32 v3, vcc_lo, 0, v3, vcc_lo +; GFX1030-GISEL-NEXT: s_movk_i32 s2, 0x4200 +; GFX1030-GISEL-NEXT: flat_load_dword v0, v[0:1] +; GFX1030-GISEL-NEXT: flat_load_dword v1, v[2:3] +; GFX1030-GISEL-NEXT: s_bfe_u32 s1, s1, 0x100000 +; GFX1030-GISEL-NEXT: s_movk_i32 s3, 0x4800 +; GFX1030-GISEL-NEXT: s_bfe_u32 s2, s2, 0x100000 +; GFX1030-GISEL-NEXT: s_lshl_b32 s1, s1, 16 +; GFX1030-GISEL-NEXT: s_movk_i32 s0, 0x4500 +; GFX1030-GISEL-NEXT: s_or_b32 s1, s2, s1 +; GFX1030-GISEL-NEXT: s_bfe_u32 s2, s9, 0x100000 +; GFX1030-GISEL-NEXT: s_bfe_u32 s3, s3, 0x100000 +; GFX1030-GISEL-NEXT: s_bfe_u32 s0, s0, 0x100000 +; GFX1030-GISEL-NEXT: s_lshl_b32 s2, s2, 16 +; GFX1030-GISEL-NEXT: s_lshl_b32 s3, s3, 16 +; GFX1030-GISEL-NEXT: s_or_b32 s0, s0, s2 +; GFX1030-GISEL-NEXT: s_or_b32 s2, s8, s3 +; GFX1030-GISEL-NEXT: v_mov_b32_e32 v2, 0 +; GFX1030-GISEL-NEXT: v_mov_b32_e32 v3, 1.0 +; GFX1030-GISEL-NEXT: v_mov_b32_e32 v4, 2.0 +; GFX1030-GISEL-NEXT: v_mov_b32_e32 v5, s1 +; GFX1030-GISEL-NEXT: v_mov_b32_e32 v6, s0 +; GFX1030-GISEL-NEXT: v_mov_b32_e32 v7, s2 +; GFX1030-GISEL-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0) +; GFX1030-GISEL-NEXT: image_bvh_intersect_ray v[0:3], v[0:7], s[4:7] a16 +; GFX1030-GISEL-NEXT: s_waitcnt vmcnt(0) +; GFX1030-GISEL-NEXT: flat_store_dwordx4 v[0:1], v[0:3] +; GFX1030-GISEL-NEXT: s_endpgm ; -; GFX11-LABEL: image_bvh_intersect_ray_a16_nsa_reassign: -; GFX11: ; %bb.0: ; %main_body -; GFX11-NEXT: s_load_b256 s[0:7], s[0:1], 0x24 -; GFX11-NEXT: v_lshlrev_b32_e32 v2, 2, v0 -; GFX11-NEXT: v_dual_mov_b32 v4, 1.0 :: v_dual_mov_b32 v5, 2.0 -; GFX11-NEXT: s_waitcnt lgkmcnt(0) -; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1) -; GFX11-NEXT: v_add_co_u32 v0, s0, s0, v2 -; GFX11-NEXT: v_add_co_ci_u32_e64 v1, null, s1, 0, s0 -; GFX11-NEXT: v_add_co_u32 v2, s0, s2, v2 -; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1) -; GFX11-NEXT: v_add_co_ci_u32_e64 v3, null, s3, 0, s0 -; GFX11-NEXT: flat_load_b32 v6, v[0:1] -; GFX11-NEXT: flat_load_b32 v7, v[2:3] -; GFX11-NEXT: v_mov_b32_e32 v1, 0x47004400 -; GFX11-NEXT: v_dual_mov_b32 v0, 0x46004200 :: v_dual_mov_b32 v3, 0 -; GFX11-NEXT: v_mov_b32_e32 v2, 0x48004500 -; GFX11-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0) -; GFX11-NEXT: image_bvh_intersect_ray v[0:3], [v6, v7, v[3:5], v[0:2]], s[4:7] a16 -; GFX11-NEXT: s_waitcnt vmcnt(0) -; GFX11-NEXT: flat_store_b128 v[0:1], v[0:3] -; GFX11-NEXT: s_sendmsg sendmsg(MSG_DEALLOC_VGPRS) -; GFX11-NEXT: s_endpgm +; GFX11-SDAG-LABEL: image_bvh_intersect_ray_a16_nsa_reassign: +; GFX11-SDAG: ; %bb.0: ; %main_body +; GFX11-SDAG-NEXT: s_load_b256 s[0:7], s[0:1], 0x24 +; GFX11-SDAG-NEXT: v_lshlrev_b32_e32 v2, 2, v0 +; GFX11-SDAG-NEXT: v_dual_mov_b32 v4, 1.0 :: v_dual_mov_b32 v5, 2.0 +; GFX11-SDAG-NEXT: s_waitcnt lgkmcnt(0) +; GFX11-SDAG-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1) +; GFX11-SDAG-NEXT: v_add_co_u32 v0, s0, s0, v2 +; GFX11-SDAG-NEXT: v_add_co_ci_u32_e64 v1, null, s1, 0, s0 +; GFX11-SDAG-NEXT: v_add_co_u32 v2, s0, s2, v2 +; GFX11-SDAG-NEXT: s_delay_alu instid0(VALU_DEP_1) +; GFX11-SDAG-NEXT: v_add_co_ci_u32_e64 v3, null, s3, 0, s0 +; GFX11-SDAG-NEXT: flat_load_b32 v6, v[0:1] +; GFX11-SDAG-NEXT: flat_load_b32 v7, v[2:3] +; GFX11-SDAG-NEXT: v_mov_b32_e32 v1, 0x47004400 +; GFX11-SDAG-NEXT: v_dual_mov_b32 v0, 0x46004200 :: v_dual_mov_b32 v3, 0 +; GFX11-SDAG-NEXT: v_mov_b32_e32 v2, 0x48004500 +; GFX11-SDAG-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0) +; GFX11-SDAG-NEXT: image_bvh_intersect_ray v[0:3], [v6, v7, v[3:5], v[0:2]], s[4:7] a16 +; GFX11-SDAG-NEXT: s_waitcnt vmcnt(0) +; GFX11-SDAG-NEXT: flat_store_b128 v[0:1], v[0:3] +; GFX11-SDAG-NEXT: s_sendmsg sendmsg(MSG_DEALLOC_VGPRS) +; GFX11-SDAG-NEXT: s_endpgm +; +; GFX11-GISEL-LABEL: image_bvh_intersect_ray_a16_nsa_reassign: +; GFX11-GISEL: ; %bb.0: ; %main_body +; GFX11-GISEL-NEXT: s_load_b256 s[0:7], s[0:1], 0x24 +; GFX11-GISEL-NEXT: v_lshlrev_b32_e32 v4, 2, v0 +; GFX11-GISEL-NEXT: s_mov_b32 s9, 0x42004600 +; GFX11-GISEL-NEXT: s_mov_b32 s10, 0x44004700 +; GFX11-GISEL-NEXT: s_mov_b32 s11, 0x45004800 +; GFX11-GISEL-NEXT: s_waitcnt lgkmcnt(0) +; GFX11-GISEL-NEXT: v_dual_mov_b32 v0, s0 :: v_dual_mov_b32 v1, s1 +; GFX11-GISEL-NEXT: s_mov_b32 s1, 1.0 +; GFX11-GISEL-NEXT: s_mov_b32 s0, 0 +; GFX11-GISEL-NEXT: v_dual_mov_b32 v2, s2 :: v_dual_mov_b32 v3, s3 +; GFX11-GISEL-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_3) +; GFX11-GISEL-NEXT: v_add_co_u32 v0, vcc_lo, v0, v4 +; GFX11-GISEL-NEXT: v_add_co_ci_u32_e32 v1, vcc_lo, 0, v1, vcc_lo +; GFX11-GISEL-NEXT: v_add_co_u32 v2, vcc_lo, v2, v4 +; GFX11-GISEL-NEXT: s_delay_alu instid0(VALU_DEP_4) +; GFX11-GISEL-NEXT: v_add_co_ci_u32_e32 v3, vcc_lo, 0, v3, vcc_lo +; GFX11-GISEL-NEXT: flat_load_b32 v6, v[0:1] +; GFX11-GISEL-NEXT: flat_load_b32 v7, v[2:3] +; GFX11-GISEL-NEXT: s_mov_b32 s2, 2.0 +; GFX11-GISEL-NEXT: v_dual_mov_b32 v0, s0 :: v_dual_mov_b32 v3, s9 +; GFX11-GISEL-NEXT: v_dual_mov_b32 v1, s1 :: v_dual_mov_b32 v2, s2 +; GFX11-GISEL-NEXT: v_dual_mov_b32 v5, s11 :: v_dual_mov_b32 v4, s10 +; GFX11-GISEL-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0) +; GFX11-GISEL-NEXT: image_bvh_intersect_ray v[0:3], [v6, v7, v[0:2], v[3:5]], s[4:7] a16 +; GFX11-GISEL-NEXT: s_waitcnt vmcnt(0) +; GFX11-GISEL-NEXT: flat_store_b128 v[0:1], v[0:3] +; GFX11-GISEL-NEXT: s_sendmsg sendmsg(MSG_DEALLOC_VGPRS) +; GFX11-GISEL-NEXT: s_endpgm main_body: %lid = tail call i32 @llvm.amdgcn.workitem.id.x() %gep_node_ptr = getelementptr inbounds i32, ptr %p_node_ptr, i32 %lid @@ -349,81 +664,176 @@ } define amdgpu_kernel void @image_bvh64_intersect_ray_nsa_reassign(ptr %p_ray, <4 x i32> inreg %tdescr) { -; GFX1013-LABEL: image_bvh64_intersect_ray_nsa_reassign: -; GFX1013: ; %bb.0: ; %main_body -; GFX1013-NEXT: s_load_dwordx2 s[4:5], s[0:1], 0x24 -; GFX1013-NEXT: v_lshlrev_b32_e32 v0, 2, v0 -; GFX1013-NEXT: s_load_dwordx4 s[0:3], s[0:1], 0x34 -; GFX1013-NEXT: v_mov_b32_e32 v3, 0 -; GFX1013-NEXT: v_mov_b32_e32 v4, 1.0 -; GFX1013-NEXT: v_mov_b32_e32 v5, 2.0 -; GFX1013-NEXT: v_mov_b32_e32 v6, 0x40400000 -; GFX1013-NEXT: v_mov_b32_e32 v7, 4.0 -; GFX1013-NEXT: v_mov_b32_e32 v8, 0x40a00000 -; GFX1013-NEXT: v_mov_b32_e32 v9, 0x40c00000 -; GFX1013-NEXT: v_mov_b32_e32 v10, 0x40e00000 -; GFX1013-NEXT: v_mov_b32_e32 v11, 0x41000000 -; GFX1013-NEXT: s_waitcnt lgkmcnt(0) -; GFX1013-NEXT: v_add_co_u32 v0, s4, s4, v0 -; GFX1013-NEXT: v_add_co_ci_u32_e64 v1, s4, s5, 0, s4 -; GFX1013-NEXT: flat_load_dword v2, v[0:1] -; GFX1013-NEXT: v_mov_b32_e32 v0, 0xb36211c7 -; GFX1013-NEXT: v_mov_b32_e32 v1, 0x102 -; GFX1013-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0) -; GFX1013-NEXT: image_bvh64_intersect_ray v[0:3], v[0:11], s[0:3] -; GFX1013-NEXT: s_waitcnt vmcnt(0) -; GFX1013-NEXT: flat_store_dwordx4 v[0:1], v[0:3] -; GFX1013-NEXT: s_endpgm +; GFX1013-SDAG-LABEL: image_bvh64_intersect_ray_nsa_reassign: +; GFX1013-SDAG: ; %bb.0: ; %main_body +; GFX1013-SDAG-NEXT: s_load_dwordx2 s[4:5], s[0:1], 0x24 +; GFX1013-SDAG-NEXT: v_lshlrev_b32_e32 v0, 2, v0 +; GFX1013-SDAG-NEXT: s_load_dwordx4 s[0:3], s[0:1], 0x34 +; GFX1013-SDAG-NEXT: v_mov_b32_e32 v3, 0 +; GFX1013-SDAG-NEXT: v_mov_b32_e32 v4, 1.0 +; GFX1013-SDAG-NEXT: v_mov_b32_e32 v5, 2.0 +; GFX1013-SDAG-NEXT: v_mov_b32_e32 v6, 0x40400000 +; GFX1013-SDAG-NEXT: v_mov_b32_e32 v7, 4.0 +; GFX1013-SDAG-NEXT: v_mov_b32_e32 v8, 0x40a00000 +; GFX1013-SDAG-NEXT: v_mov_b32_e32 v9, 0x40c00000 +; GFX1013-SDAG-NEXT: v_mov_b32_e32 v10, 0x40e00000 +; GFX1013-SDAG-NEXT: v_mov_b32_e32 v11, 0x41000000 +; GFX1013-SDAG-NEXT: s_waitcnt lgkmcnt(0) +; GFX1013-SDAG-NEXT: v_add_co_u32 v0, s4, s4, v0 +; GFX1013-SDAG-NEXT: v_add_co_ci_u32_e64 v1, s4, s5, 0, s4 +; GFX1013-SDAG-NEXT: flat_load_dword v2, v[0:1] +; GFX1013-SDAG-NEXT: v_mov_b32_e32 v0, 0xb36211c7 +; GFX1013-SDAG-NEXT: v_mov_b32_e32 v1, 0x102 +; GFX1013-SDAG-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0) +; GFX1013-SDAG-NEXT: image_bvh64_intersect_ray v[0:3], v[0:11], s[0:3] +; GFX1013-SDAG-NEXT: s_waitcnt vmcnt(0) +; GFX1013-SDAG-NEXT: flat_store_dwordx4 v[0:1], v[0:3] +; GFX1013-SDAG-NEXT: s_endpgm +; +; GFX1013-GISEL-LABEL: image_bvh64_intersect_ray_nsa_reassign: +; GFX1013-GISEL: ; %bb.0: ; %main_body +; GFX1013-GISEL-NEXT: s_clause 0x1 +; GFX1013-GISEL-NEXT: s_load_dwordx2 s[2:3], s[0:1], 0x24 +; GFX1013-GISEL-NEXT: s_load_dwordx4 s[4:7], s[0:1], 0x34 +; GFX1013-GISEL-NEXT: v_lshlrev_b32_e32 v2, 2, v0 +; GFX1013-GISEL-NEXT: v_mov_b32_e32 v3, 0 +; GFX1013-GISEL-NEXT: v_mov_b32_e32 v4, 1.0 +; GFX1013-GISEL-NEXT: v_mov_b32_e32 v5, 2.0 +; GFX1013-GISEL-NEXT: v_mov_b32_e32 v6, 0x40400000 +; GFX1013-GISEL-NEXT: v_mov_b32_e32 v7, 4.0 +; GFX1013-GISEL-NEXT: v_mov_b32_e32 v8, 0x40a00000 +; GFX1013-GISEL-NEXT: v_mov_b32_e32 v9, 0x40c00000 +; GFX1013-GISEL-NEXT: v_mov_b32_e32 v10, 0x40e00000 +; GFX1013-GISEL-NEXT: v_mov_b32_e32 v11, 0x41000000 +; GFX1013-GISEL-NEXT: s_waitcnt lgkmcnt(0) +; GFX1013-GISEL-NEXT: v_mov_b32_e32 v0, s2 +; GFX1013-GISEL-NEXT: v_mov_b32_e32 v1, s3 +; GFX1013-GISEL-NEXT: v_add_co_u32 v0, vcc_lo, v0, v2 +; GFX1013-GISEL-NEXT: v_add_co_ci_u32_e32 v1, vcc_lo, 0, v1, vcc_lo +; GFX1013-GISEL-NEXT: flat_load_dword v2, v[0:1] +; GFX1013-GISEL-NEXT: v_mov_b32_e32 v0, 0xb36211c7 +; GFX1013-GISEL-NEXT: v_mov_b32_e32 v1, 0x102 +; GFX1013-GISEL-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0) +; GFX1013-GISEL-NEXT: image_bvh64_intersect_ray v[0:3], v[0:11], s[4:7] +; GFX1013-GISEL-NEXT: s_waitcnt vmcnt(0) +; GFX1013-GISEL-NEXT: flat_store_dwordx4 v[0:1], v[0:3] +; GFX1013-GISEL-NEXT: s_endpgm +; +; GFX1030-SDAG-LABEL: image_bvh64_intersect_ray_nsa_reassign: +; GFX1030-SDAG: ; %bb.0: ; %main_body +; GFX1030-SDAG-NEXT: s_load_dwordx2 s[4:5], s[0:1], 0x24 +; GFX1030-SDAG-NEXT: v_lshlrev_b32_e32 v0, 2, v0 +; GFX1030-SDAG-NEXT: s_load_dwordx4 s[0:3], s[0:1], 0x34 +; GFX1030-SDAG-NEXT: v_mov_b32_e32 v3, 0 +; GFX1030-SDAG-NEXT: v_mov_b32_e32 v11, 0x41000000 +; GFX1030-SDAG-NEXT: v_mov_b32_e32 v10, 0x40e00000 +; GFX1030-SDAG-NEXT: v_mov_b32_e32 v9, 0x40c00000 +; GFX1030-SDAG-NEXT: v_mov_b32_e32 v8, 0x40a00000 +; GFX1030-SDAG-NEXT: v_mov_b32_e32 v7, 4.0 +; GFX1030-SDAG-NEXT: v_mov_b32_e32 v6, 0x40400000 +; GFX1030-SDAG-NEXT: v_mov_b32_e32 v5, 2.0 +; GFX1030-SDAG-NEXT: v_mov_b32_e32 v4, 1.0 +; GFX1030-SDAG-NEXT: s_waitcnt lgkmcnt(0) +; GFX1030-SDAG-NEXT: v_add_co_u32 v0, s4, s4, v0 +; GFX1030-SDAG-NEXT: v_add_co_ci_u32_e64 v1, null, s5, 0, s4 +; GFX1030-SDAG-NEXT: flat_load_dword v2, v[0:1] +; GFX1030-SDAG-NEXT: v_mov_b32_e32 v1, 0x102 +; GFX1030-SDAG-NEXT: v_mov_b32_e32 v0, 0xb36211c7 +; GFX1030-SDAG-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0) +; GFX1030-SDAG-NEXT: image_bvh64_intersect_ray v[0:3], v[0:11], s[0:3] +; GFX1030-SDAG-NEXT: s_waitcnt vmcnt(0) +; GFX1030-SDAG-NEXT: flat_store_dwordx4 v[0:1], v[0:3] +; GFX1030-SDAG-NEXT: s_endpgm ; -; GFX1030-LABEL: image_bvh64_intersect_ray_nsa_reassign: -; GFX1030: ; %bb.0: ; %main_body -; GFX1030-NEXT: s_load_dwordx2 s[4:5], s[0:1], 0x24 -; GFX1030-NEXT: v_lshlrev_b32_e32 v0, 2, v0 -; GFX1030-NEXT: s_load_dwordx4 s[0:3], s[0:1], 0x34 -; GFX1030-NEXT: v_mov_b32_e32 v3, 0 -; GFX1030-NEXT: v_mov_b32_e32 v11, 0x41000000 -; GFX1030-NEXT: v_mov_b32_e32 v10, 0x40e00000 -; GFX1030-NEXT: v_mov_b32_e32 v9, 0x40c00000 -; GFX1030-NEXT: v_mov_b32_e32 v8, 0x40a00000 -; GFX1030-NEXT: v_mov_b32_e32 v7, 4.0 -; GFX1030-NEXT: v_mov_b32_e32 v6, 0x40400000 -; GFX1030-NEXT: v_mov_b32_e32 v5, 2.0 -; GFX1030-NEXT: v_mov_b32_e32 v4, 1.0 -; GFX1030-NEXT: s_waitcnt lgkmcnt(0) -; GFX1030-NEXT: v_add_co_u32 v0, s4, s4, v0 -; GFX1030-NEXT: v_add_co_ci_u32_e64 v1, null, s5, 0, s4 -; GFX1030-NEXT: flat_load_dword v2, v[0:1] -; GFX1030-NEXT: v_mov_b32_e32 v1, 0x102 -; GFX1030-NEXT: v_mov_b32_e32 v0, 0xb36211c7 -; GFX1030-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0) -; GFX1030-NEXT: image_bvh64_intersect_ray v[0:3], v[0:11], s[0:3] -; GFX1030-NEXT: s_waitcnt vmcnt(0) -; GFX1030-NEXT: flat_store_dwordx4 v[0:1], v[0:3] -; GFX1030-NEXT: s_endpgm +; GFX1030-GISEL-LABEL: image_bvh64_intersect_ray_nsa_reassign: +; GFX1030-GISEL: ; %bb.0: ; %main_body +; GFX1030-GISEL-NEXT: s_clause 0x1 +; GFX1030-GISEL-NEXT: s_load_dwordx2 s[4:5], s[0:1], 0x24 +; GFX1030-GISEL-NEXT: s_load_dwordx4 s[0:3], s[0:1], 0x34 +; GFX1030-GISEL-NEXT: v_lshlrev_b32_e32 v2, 2, v0 +; GFX1030-GISEL-NEXT: v_mov_b32_e32 v3, 0 +; GFX1030-GISEL-NEXT: v_mov_b32_e32 v4, 1.0 +; GFX1030-GISEL-NEXT: v_mov_b32_e32 v5, 2.0 +; GFX1030-GISEL-NEXT: v_mov_b32_e32 v6, 0x40400000 +; GFX1030-GISEL-NEXT: v_mov_b32_e32 v7, 4.0 +; GFX1030-GISEL-NEXT: v_mov_b32_e32 v8, 0x40a00000 +; GFX1030-GISEL-NEXT: v_mov_b32_e32 v9, 0x40c00000 +; GFX1030-GISEL-NEXT: v_mov_b32_e32 v10, 0x40e00000 +; GFX1030-GISEL-NEXT: v_mov_b32_e32 v11, 0x41000000 +; GFX1030-GISEL-NEXT: s_waitcnt lgkmcnt(0) +; GFX1030-GISEL-NEXT: v_mov_b32_e32 v0, s4 +; GFX1030-GISEL-NEXT: v_mov_b32_e32 v1, s5 +; GFX1030-GISEL-NEXT: v_add_co_u32 v0, vcc_lo, v0, v2 +; GFX1030-GISEL-NEXT: v_add_co_ci_u32_e32 v1, vcc_lo, 0, v1, vcc_lo +; GFX1030-GISEL-NEXT: flat_load_dword v2, v[0:1] +; GFX1030-GISEL-NEXT: v_mov_b32_e32 v0, 0xb36211c7 +; GFX1030-GISEL-NEXT: v_mov_b32_e32 v1, 0x102 +; GFX1030-GISEL-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0) +; GFX1030-GISEL-NEXT: image_bvh64_intersect_ray v[0:3], v[0:11], s[0:3] +; GFX1030-GISEL-NEXT: s_waitcnt vmcnt(0) +; GFX1030-GISEL-NEXT: flat_store_dwordx4 v[0:1], v[0:3] +; GFX1030-GISEL-NEXT: s_endpgm ; -; GFX11-LABEL: image_bvh64_intersect_ray_nsa_reassign: -; GFX11: ; %bb.0: ; %main_body -; GFX11-NEXT: s_load_b64 s[4:5], s[0:1], 0x24 -; GFX11-NEXT: v_lshlrev_b32_e32 v0, 2, v0 -; GFX11-NEXT: s_load_b128 s[0:3], s[0:1], 0x34 -; GFX11-NEXT: v_mov_b32_e32 v2, 0x41000000 -; GFX11-NEXT: v_dual_mov_b32 v3, 0x40400000 :: v_dual_mov_b32 v4, 4.0 -; GFX11-NEXT: v_dual_mov_b32 v5, 0x40a00000 :: v_dual_mov_b32 v6, 0 -; GFX11-NEXT: v_dual_mov_b32 v8, 2.0 :: v_dual_mov_b32 v9, 0xb36211c7 -; GFX11-NEXT: v_dual_mov_b32 v10, 0x102 :: v_dual_mov_b32 v7, 1.0 -; GFX11-NEXT: s_waitcnt lgkmcnt(0) -; GFX11-NEXT: v_add_co_u32 v0, s4, s4, v0 -; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1) -; GFX11-NEXT: v_add_co_ci_u32_e64 v1, null, s5, 0, s4 -; GFX11-NEXT: flat_load_b32 v11, v[0:1] -; GFX11-NEXT: v_mov_b32_e32 v0, 0x40c00000 -; GFX11-NEXT: v_mov_b32_e32 v1, 0x40e00000 -; GFX11-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0) -; GFX11-NEXT: image_bvh64_intersect_ray v[0:3], [v[9:10], v11, v[6:8], v[3:5], v[0:2]], s[0:3] -; GFX11-NEXT: s_waitcnt vmcnt(0) -; GFX11-NEXT: flat_store_b128 v[0:1], v[0:3] -; GFX11-NEXT: s_sendmsg sendmsg(MSG_DEALLOC_VGPRS) -; GFX11-NEXT: s_endpgm +; GFX11-SDAG-LABEL: image_bvh64_intersect_ray_nsa_reassign: +; GFX11-SDAG: ; %bb.0: ; %main_body +; GFX11-SDAG-NEXT: s_load_b64 s[4:5], s[0:1], 0x24 +; GFX11-SDAG-NEXT: v_lshlrev_b32_e32 v0, 2, v0 +; GFX11-SDAG-NEXT: s_load_b128 s[0:3], s[0:1], 0x34 +; GFX11-SDAG-NEXT: v_mov_b32_e32 v2, 0x41000000 +; GFX11-SDAG-NEXT: v_dual_mov_b32 v3, 0x40400000 :: v_dual_mov_b32 v4, 4.0 +; GFX11-SDAG-NEXT: v_dual_mov_b32 v5, 0x40a00000 :: v_dual_mov_b32 v6, 0 +; GFX11-SDAG-NEXT: v_dual_mov_b32 v8, 2.0 :: v_dual_mov_b32 v9, 0xb36211c7 +; GFX11-SDAG-NEXT: v_dual_mov_b32 v10, 0x102 :: v_dual_mov_b32 v7, 1.0 +; GFX11-SDAG-NEXT: s_waitcnt lgkmcnt(0) +; GFX11-SDAG-NEXT: v_add_co_u32 v0, s4, s4, v0 +; GFX11-SDAG-NEXT: s_delay_alu instid0(VALU_DEP_1) +; GFX11-SDAG-NEXT: v_add_co_ci_u32_e64 v1, null, s5, 0, s4 +; GFX11-SDAG-NEXT: flat_load_b32 v11, v[0:1] +; GFX11-SDAG-NEXT: v_mov_b32_e32 v0, 0x40c00000 +; GFX11-SDAG-NEXT: v_mov_b32_e32 v1, 0x40e00000 +; GFX11-SDAG-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0) +; GFX11-SDAG-NEXT: image_bvh64_intersect_ray v[0:3], [v[9:10], v11, v[6:8], v[3:5], v[0:2]], s[0:3] +; GFX11-SDAG-NEXT: s_waitcnt vmcnt(0) +; GFX11-SDAG-NEXT: flat_store_b128 v[0:1], v[0:3] +; GFX11-SDAG-NEXT: s_sendmsg sendmsg(MSG_DEALLOC_VGPRS) +; GFX11-SDAG-NEXT: s_endpgm +; +; GFX11-GISEL-LABEL: image_bvh64_intersect_ray_nsa_reassign: +; GFX11-GISEL: ; %bb.0: ; %main_body +; GFX11-GISEL-NEXT: s_clause 0x1 +; GFX11-GISEL-NEXT: s_load_b64 s[4:5], s[0:1], 0x24 +; GFX11-GISEL-NEXT: s_load_b128 s[0:3], s[0:1], 0x34 +; GFX11-GISEL-NEXT: v_lshlrev_b32_e32 v2, 2, v0 +; GFX11-GISEL-NEXT: s_mov_b32 s8, 2.0 +; GFX11-GISEL-NEXT: s_mov_b32 s7, 1.0 +; GFX11-GISEL-NEXT: s_mov_b32 s6, 0 +; GFX11-GISEL-NEXT: s_mov_b32 s9, 0x40400000 +; GFX11-GISEL-NEXT: s_mov_b32 s12, 0x40c00000 +; GFX11-GISEL-NEXT: s_mov_b32 s11, 0x40a00000 +; GFX11-GISEL-NEXT: s_mov_b32 s10, 4.0 +; GFX11-GISEL-NEXT: s_mov_b32 s14, 0x41000000 +; GFX11-GISEL-NEXT: s_mov_b32 s13, 0x40e00000 +; GFX11-GISEL-NEXT: v_mov_b32_e32 v6, s12 +; GFX11-GISEL-NEXT: v_dual_mov_b32 v8, s14 :: v_dual_mov_b32 v3, s9 +; GFX11-GISEL-NEXT: v_dual_mov_b32 v4, s10 :: v_dual_mov_b32 v7, s13 +; GFX11-GISEL-NEXT: s_waitcnt lgkmcnt(0) +; GFX11-GISEL-NEXT: v_dual_mov_b32 v5, s11 :: v_dual_mov_b32 v0, s4 +; GFX11-GISEL-NEXT: v_mov_b32_e32 v1, s5 +; GFX11-GISEL-NEXT: s_mov_b32 s4, 0xb36211c7 +; GFX11-GISEL-NEXT: s_movk_i32 s5, 0x102 +; GFX11-GISEL-NEXT: s_delay_alu instid0(SALU_CYCLE_1) +; GFX11-GISEL-NEXT: v_dual_mov_b32 v10, s5 :: v_dual_mov_b32 v9, s4 +; GFX11-GISEL-NEXT: v_add_co_u32 v0, vcc_lo, v0, v2 +; GFX11-GISEL-NEXT: v_add_co_ci_u32_e32 v1, vcc_lo, 0, v1, vcc_lo +; GFX11-GISEL-NEXT: flat_load_b32 v11, v[0:1] +; GFX11-GISEL-NEXT: v_dual_mov_b32 v0, s6 :: v_dual_mov_b32 v1, s7 +; GFX11-GISEL-NEXT: v_mov_b32_e32 v2, s8 +; GFX11-GISEL-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0) +; GFX11-GISEL-NEXT: image_bvh64_intersect_ray v[0:3], [v[9:10], v11, v[0:2], v[3:5], v[6:8]], s[0:3] +; GFX11-GISEL-NEXT: s_waitcnt vmcnt(0) +; GFX11-GISEL-NEXT: flat_store_b128 v[0:1], v[0:3] +; GFX11-GISEL-NEXT: s_sendmsg sendmsg(MSG_DEALLOC_VGPRS) +; GFX11-GISEL-NEXT: s_endpgm main_body: %lid = tail call i32 @llvm.amdgcn.workitem.id.x() %gep_ray = getelementptr inbounds float, ptr %p_ray, i32 %lid @@ -443,73 +853,194 @@ } define amdgpu_kernel void @image_bvh64_intersect_ray_a16_nsa_reassign(ptr %p_ray, <4 x i32> inreg %tdescr) { -; GFX1013-LABEL: image_bvh64_intersect_ray_a16_nsa_reassign: -; GFX1013: ; %bb.0: ; %main_body -; GFX1013-NEXT: s_load_dwordx2 s[4:5], s[0:1], 0x24 -; GFX1013-NEXT: v_lshlrev_b32_e32 v0, 2, v0 -; GFX1013-NEXT: s_load_dwordx4 s[0:3], s[0:1], 0x34 -; GFX1013-NEXT: v_mov_b32_e32 v3, 0 -; GFX1013-NEXT: v_mov_b32_e32 v4, 1.0 -; GFX1013-NEXT: v_mov_b32_e32 v5, 2.0 -; GFX1013-NEXT: v_mov_b32_e32 v6, 0x44004200 -; GFX1013-NEXT: v_mov_b32_e32 v7, 0x46004500 -; GFX1013-NEXT: v_mov_b32_e32 v8, 0x48004700 -; GFX1013-NEXT: s_waitcnt lgkmcnt(0) -; GFX1013-NEXT: v_add_co_u32 v0, s4, s4, v0 -; GFX1013-NEXT: v_add_co_ci_u32_e64 v1, s4, s5, 0, s4 -; GFX1013-NEXT: flat_load_dword v2, v[0:1] -; GFX1013-NEXT: v_mov_b32_e32 v0, 0xb36211c6 -; GFX1013-NEXT: v_mov_b32_e32 v1, 0x102 -; GFX1013-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0) -; GFX1013-NEXT: image_bvh64_intersect_ray v[0:3], v[0:8], s[0:3] a16 -; GFX1013-NEXT: s_waitcnt vmcnt(0) -; GFX1013-NEXT: flat_store_dwordx4 v[0:1], v[0:3] -; GFX1013-NEXT: s_endpgm +; GFX1013-SDAG-LABEL: image_bvh64_intersect_ray_a16_nsa_reassign: +; GFX1013-SDAG: ; %bb.0: ; %main_body +; GFX1013-SDAG-NEXT: s_load_dwordx2 s[4:5], s[0:1], 0x24 +; GFX1013-SDAG-NEXT: v_lshlrev_b32_e32 v0, 2, v0 +; GFX1013-SDAG-NEXT: s_load_dwordx4 s[0:3], s[0:1], 0x34 +; GFX1013-SDAG-NEXT: v_mov_b32_e32 v3, 0 +; GFX1013-SDAG-NEXT: v_mov_b32_e32 v4, 1.0 +; GFX1013-SDAG-NEXT: v_mov_b32_e32 v5, 2.0 +; GFX1013-SDAG-NEXT: v_mov_b32_e32 v6, 0x44004200 +; GFX1013-SDAG-NEXT: v_mov_b32_e32 v7, 0x46004500 +; GFX1013-SDAG-NEXT: v_mov_b32_e32 v8, 0x48004700 +; GFX1013-SDAG-NEXT: s_waitcnt lgkmcnt(0) +; GFX1013-SDAG-NEXT: v_add_co_u32 v0, s4, s4, v0 +; GFX1013-SDAG-NEXT: v_add_co_ci_u32_e64 v1, s4, s5, 0, s4 +; GFX1013-SDAG-NEXT: flat_load_dword v2, v[0:1] +; GFX1013-SDAG-NEXT: v_mov_b32_e32 v0, 0xb36211c6 +; GFX1013-SDAG-NEXT: v_mov_b32_e32 v1, 0x102 +; GFX1013-SDAG-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0) +; GFX1013-SDAG-NEXT: image_bvh64_intersect_ray v[0:3], v[0:8], s[0:3] a16 +; GFX1013-SDAG-NEXT: s_waitcnt vmcnt(0) +; GFX1013-SDAG-NEXT: flat_store_dwordx4 v[0:1], v[0:3] +; GFX1013-SDAG-NEXT: s_endpgm +; +; GFX1013-GISEL-LABEL: image_bvh64_intersect_ray_a16_nsa_reassign: +; GFX1013-GISEL: ; %bb.0: ; %main_body +; GFX1013-GISEL-NEXT: s_clause 0x1 +; GFX1013-GISEL-NEXT: s_load_dwordx2 s[2:3], s[0:1], 0x24 +; GFX1013-GISEL-NEXT: s_load_dwordx4 s[4:7], s[0:1], 0x34 +; GFX1013-GISEL-NEXT: v_lshlrev_b32_e32 v2, 2, v0 +; GFX1013-GISEL-NEXT: s_movk_i32 s1, 0x4400 +; GFX1013-GISEL-NEXT: s_movk_i32 s9, 0x4600 +; GFX1013-GISEL-NEXT: s_bfe_u32 s1, s1, 0x100000 +; GFX1013-GISEL-NEXT: s_movk_i32 s0, 0x4500 +; GFX1013-GISEL-NEXT: s_lshl_b32 s1, s1, 16 +; GFX1013-GISEL-NEXT: s_movk_i32 s8, 0x4700 +; GFX1013-GISEL-NEXT: s_bfe_u32 s0, s0, 0x100000 +; GFX1013-GISEL-NEXT: s_bfe_u32 s8, s8, 0x100000 +; GFX1013-GISEL-NEXT: v_mov_b32_e32 v3, 0 +; GFX1013-GISEL-NEXT: v_mov_b32_e32 v4, 1.0 +; GFX1013-GISEL-NEXT: v_mov_b32_e32 v5, 2.0 +; GFX1013-GISEL-NEXT: s_waitcnt lgkmcnt(0) +; GFX1013-GISEL-NEXT: v_mov_b32_e32 v0, s2 +; GFX1013-GISEL-NEXT: v_mov_b32_e32 v1, s3 +; GFX1013-GISEL-NEXT: s_movk_i32 s2, 0x4200 +; GFX1013-GISEL-NEXT: s_movk_i32 s3, 0x4800 +; GFX1013-GISEL-NEXT: s_bfe_u32 s2, s2, 0x100000 +; GFX1013-GISEL-NEXT: v_add_co_u32 v0, vcc_lo, v0, v2 +; GFX1013-GISEL-NEXT: v_add_co_ci_u32_e32 v1, vcc_lo, 0, v1, vcc_lo +; GFX1013-GISEL-NEXT: s_or_b32 s1, s2, s1 +; GFX1013-GISEL-NEXT: s_bfe_u32 s2, s9, 0x100000 +; GFX1013-GISEL-NEXT: s_bfe_u32 s3, s3, 0x100000 +; GFX1013-GISEL-NEXT: flat_load_dword v2, v[0:1] +; GFX1013-GISEL-NEXT: s_lshl_b32 s2, s2, 16 +; GFX1013-GISEL-NEXT: s_lshl_b32 s3, s3, 16 +; GFX1013-GISEL-NEXT: s_or_b32 s0, s0, s2 +; GFX1013-GISEL-NEXT: s_or_b32 s2, s8, s3 +; GFX1013-GISEL-NEXT: v_mov_b32_e32 v0, 0xb36211c6 +; GFX1013-GISEL-NEXT: v_mov_b32_e32 v1, 0x102 +; GFX1013-GISEL-NEXT: v_mov_b32_e32 v6, s1 +; GFX1013-GISEL-NEXT: v_mov_b32_e32 v7, s0 +; GFX1013-GISEL-NEXT: v_mov_b32_e32 v8, s2 +; GFX1013-GISEL-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0) +; GFX1013-GISEL-NEXT: image_bvh64_intersect_ray v[0:3], v[0:8], s[4:7] a16 +; GFX1013-GISEL-NEXT: s_waitcnt vmcnt(0) +; GFX1013-GISEL-NEXT: flat_store_dwordx4 v[0:1], v[0:3] +; GFX1013-GISEL-NEXT: s_endpgm +; +; GFX1030-SDAG-LABEL: image_bvh64_intersect_ray_a16_nsa_reassign: +; GFX1030-SDAG: ; %bb.0: ; %main_body +; GFX1030-SDAG-NEXT: s_load_dwordx2 s[4:5], s[0:1], 0x24 +; GFX1030-SDAG-NEXT: v_lshlrev_b32_e32 v0, 2, v0 +; GFX1030-SDAG-NEXT: s_load_dwordx4 s[0:3], s[0:1], 0x34 +; GFX1030-SDAG-NEXT: v_mov_b32_e32 v3, 0 +; GFX1030-SDAG-NEXT: v_mov_b32_e32 v5, 2.0 +; GFX1030-SDAG-NEXT: v_mov_b32_e32 v4, 1.0 +; GFX1030-SDAG-NEXT: v_mov_b32_e32 v6, 0x44004200 +; GFX1030-SDAG-NEXT: v_mov_b32_e32 v7, 0x46004500 +; GFX1030-SDAG-NEXT: v_mov_b32_e32 v8, 0x48004700 +; GFX1030-SDAG-NEXT: s_waitcnt lgkmcnt(0) +; GFX1030-SDAG-NEXT: v_add_co_u32 v0, s4, s4, v0 +; GFX1030-SDAG-NEXT: v_add_co_ci_u32_e64 v1, null, s5, 0, s4 +; GFX1030-SDAG-NEXT: flat_load_dword v2, v[0:1] +; GFX1030-SDAG-NEXT: v_mov_b32_e32 v1, 0x102 +; GFX1030-SDAG-NEXT: v_mov_b32_e32 v0, 0xb36211c6 +; GFX1030-SDAG-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0) +; GFX1030-SDAG-NEXT: image_bvh64_intersect_ray v[0:3], v[0:8], s[0:3] a16 +; GFX1030-SDAG-NEXT: s_waitcnt vmcnt(0) +; GFX1030-SDAG-NEXT: flat_store_dwordx4 v[0:1], v[0:3] +; GFX1030-SDAG-NEXT: s_endpgm ; -; GFX1030-LABEL: image_bvh64_intersect_ray_a16_nsa_reassign: -; GFX1030: ; %bb.0: ; %main_body -; GFX1030-NEXT: s_load_dwordx2 s[4:5], s[0:1], 0x24 -; GFX1030-NEXT: v_lshlrev_b32_e32 v0, 2, v0 -; GFX1030-NEXT: s_load_dwordx4 s[0:3], s[0:1], 0x34 -; GFX1030-NEXT: v_mov_b32_e32 v3, 0 -; GFX1030-NEXT: v_mov_b32_e32 v5, 2.0 -; GFX1030-NEXT: v_mov_b32_e32 v4, 1.0 -; GFX1030-NEXT: v_mov_b32_e32 v6, 0x44004200 -; GFX1030-NEXT: v_mov_b32_e32 v7, 0x46004500 -; GFX1030-NEXT: v_mov_b32_e32 v8, 0x48004700 -; GFX1030-NEXT: s_waitcnt lgkmcnt(0) -; GFX1030-NEXT: v_add_co_u32 v0, s4, s4, v0 -; GFX1030-NEXT: v_add_co_ci_u32_e64 v1, null, s5, 0, s4 -; GFX1030-NEXT: flat_load_dword v2, v[0:1] -; GFX1030-NEXT: v_mov_b32_e32 v1, 0x102 -; GFX1030-NEXT: v_mov_b32_e32 v0, 0xb36211c6 -; GFX1030-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0) -; GFX1030-NEXT: image_bvh64_intersect_ray v[0:3], v[0:8], s[0:3] a16 -; GFX1030-NEXT: s_waitcnt vmcnt(0) -; GFX1030-NEXT: flat_store_dwordx4 v[0:1], v[0:3] -; GFX1030-NEXT: s_endpgm +; GFX1030-GISEL-LABEL: image_bvh64_intersect_ray_a16_nsa_reassign: +; GFX1030-GISEL: ; %bb.0: ; %main_body +; GFX1030-GISEL-NEXT: s_clause 0x1 +; GFX1030-GISEL-NEXT: s_load_dwordx2 s[4:5], s[0:1], 0x24 +; GFX1030-GISEL-NEXT: s_load_dwordx4 s[0:3], s[0:1], 0x34 +; GFX1030-GISEL-NEXT: v_lshlrev_b32_e32 v2, 2, v0 +; GFX1030-GISEL-NEXT: s_movk_i32 s6, 0x4200 +; GFX1030-GISEL-NEXT: s_movk_i32 s7, 0x4800 +; GFX1030-GISEL-NEXT: s_bfe_u32 s6, s6, 0x100000 +; GFX1030-GISEL-NEXT: s_movk_i32 s9, 0x4600 +; GFX1030-GISEL-NEXT: s_movk_i32 s8, 0x4700 +; GFX1030-GISEL-NEXT: s_bfe_u32 s7, s7, 0x100000 +; GFX1030-GISEL-NEXT: s_bfe_u32 s8, s8, 0x100000 +; GFX1030-GISEL-NEXT: s_lshl_b32 s7, s7, 16 +; GFX1030-GISEL-NEXT: v_mov_b32_e32 v3, 0 +; GFX1030-GISEL-NEXT: v_mov_b32_e32 v4, 1.0 +; GFX1030-GISEL-NEXT: v_mov_b32_e32 v5, 2.0 +; GFX1030-GISEL-NEXT: s_waitcnt lgkmcnt(0) +; GFX1030-GISEL-NEXT: v_mov_b32_e32 v0, s4 +; GFX1030-GISEL-NEXT: v_mov_b32_e32 v1, s5 +; GFX1030-GISEL-NEXT: s_movk_i32 s5, 0x4400 +; GFX1030-GISEL-NEXT: s_movk_i32 s4, 0x4500 +; GFX1030-GISEL-NEXT: s_bfe_u32 s5, s5, 0x100000 +; GFX1030-GISEL-NEXT: v_add_co_u32 v0, vcc_lo, v0, v2 +; GFX1030-GISEL-NEXT: v_add_co_ci_u32_e32 v1, vcc_lo, 0, v1, vcc_lo +; GFX1030-GISEL-NEXT: s_lshl_b32 s5, s5, 16 +; GFX1030-GISEL-NEXT: s_bfe_u32 s4, s4, 0x100000 +; GFX1030-GISEL-NEXT: s_or_b32 s5, s6, s5 +; GFX1030-GISEL-NEXT: flat_load_dword v2, v[0:1] +; GFX1030-GISEL-NEXT: s_bfe_u32 s6, s9, 0x100000 +; GFX1030-GISEL-NEXT: v_mov_b32_e32 v0, 0xb36211c6 +; GFX1030-GISEL-NEXT: s_lshl_b32 s6, s6, 16 +; GFX1030-GISEL-NEXT: v_mov_b32_e32 v1, 0x102 +; GFX1030-GISEL-NEXT: s_or_b32 s4, s4, s6 +; GFX1030-GISEL-NEXT: s_or_b32 s6, s8, s7 +; GFX1030-GISEL-NEXT: v_mov_b32_e32 v6, s5 +; GFX1030-GISEL-NEXT: v_mov_b32_e32 v7, s4 +; GFX1030-GISEL-NEXT: v_mov_b32_e32 v8, s6 +; GFX1030-GISEL-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0) +; GFX1030-GISEL-NEXT: image_bvh64_intersect_ray v[0:3], v[0:8], s[0:3] a16 +; GFX1030-GISEL-NEXT: s_waitcnt vmcnt(0) +; GFX1030-GISEL-NEXT: flat_store_dwordx4 v[0:1], v[0:3] +; GFX1030-GISEL-NEXT: s_endpgm ; -; GFX11-LABEL: image_bvh64_intersect_ray_a16_nsa_reassign: -; GFX11: ; %bb.0: ; %main_body -; GFX11-NEXT: s_load_b64 s[4:5], s[0:1], 0x24 -; GFX11-NEXT: v_lshlrev_b32_e32 v0, 2, v0 -; GFX11-NEXT: s_load_b128 s[0:3], s[0:1], 0x34 -; GFX11-NEXT: v_dual_mov_b32 v2, 0x48004500 :: v_dual_mov_b32 v5, 2.0 -; GFX11-NEXT: v_dual_mov_b32 v4, 1.0 :: v_dual_mov_b32 v7, 0x102 -; GFX11-NEXT: v_dual_mov_b32 v6, 0xb36211c6 :: v_dual_mov_b32 v3, 0 -; GFX11-NEXT: s_waitcnt lgkmcnt(0) -; GFX11-NEXT: v_add_co_u32 v0, s4, s4, v0 -; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1) -; GFX11-NEXT: v_add_co_ci_u32_e64 v1, null, s5, 0, s4 -; GFX11-NEXT: flat_load_b32 v8, v[0:1] -; GFX11-NEXT: v_mov_b32_e32 v0, 0x46004200 -; GFX11-NEXT: v_mov_b32_e32 v1, 0x47004400 -; GFX11-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0) -; GFX11-NEXT: image_bvh64_intersect_ray v[0:3], [v[6:7], v8, v[3:5], v[0:2]], s[0:3] a16 -; GFX11-NEXT: s_waitcnt vmcnt(0) -; GFX11-NEXT: flat_store_b128 v[0:1], v[0:3] -; GFX11-NEXT: s_sendmsg sendmsg(MSG_DEALLOC_VGPRS) -; GFX11-NEXT: s_endpgm +; GFX11-SDAG-LABEL: image_bvh64_intersect_ray_a16_nsa_reassign: +; GFX11-SDAG: ; %bb.0: ; %main_body +; GFX11-SDAG-NEXT: s_load_b64 s[4:5], s[0:1], 0x24 +; GFX11-SDAG-NEXT: v_lshlrev_b32_e32 v0, 2, v0 +; GFX11-SDAG-NEXT: s_load_b128 s[0:3], s[0:1], 0x34 +; GFX11-SDAG-NEXT: v_dual_mov_b32 v2, 0x48004500 :: v_dual_mov_b32 v5, 2.0 +; GFX11-SDAG-NEXT: v_dual_mov_b32 v4, 1.0 :: v_dual_mov_b32 v7, 0x102 +; GFX11-SDAG-NEXT: v_dual_mov_b32 v6, 0xb36211c6 :: v_dual_mov_b32 v3, 0 +; GFX11-SDAG-NEXT: s_waitcnt lgkmcnt(0) +; GFX11-SDAG-NEXT: v_add_co_u32 v0, s4, s4, v0 +; GFX11-SDAG-NEXT: s_delay_alu instid0(VALU_DEP_1) +; GFX11-SDAG-NEXT: v_add_co_ci_u32_e64 v1, null, s5, 0, s4 +; GFX11-SDAG-NEXT: flat_load_b32 v8, v[0:1] +; GFX11-SDAG-NEXT: v_mov_b32_e32 v0, 0x46004200 +; GFX11-SDAG-NEXT: v_mov_b32_e32 v1, 0x47004400 +; GFX11-SDAG-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0) +; GFX11-SDAG-NEXT: image_bvh64_intersect_ray v[0:3], [v[6:7], v8, v[3:5], v[0:2]], s[0:3] a16 +; GFX11-SDAG-NEXT: s_waitcnt vmcnt(0) +; GFX11-SDAG-NEXT: flat_store_b128 v[0:1], v[0:3] +; GFX11-SDAG-NEXT: s_sendmsg sendmsg(MSG_DEALLOC_VGPRS) +; GFX11-SDAG-NEXT: s_endpgm +; +; GFX11-GISEL-LABEL: image_bvh64_intersect_ray_a16_nsa_reassign: +; GFX11-GISEL: ; %bb.0: ; %main_body +; GFX11-GISEL-NEXT: s_clause 0x1 +; GFX11-GISEL-NEXT: s_load_b64 s[4:5], s[0:1], 0x24 +; GFX11-GISEL-NEXT: s_load_b128 s[0:3], s[0:1], 0x34 +; GFX11-GISEL-NEXT: v_lshlrev_b32_e32 v2, 2, v0 +; GFX11-GISEL-NEXT: s_mov_b32 s6, 0 +; GFX11-GISEL-NEXT: s_mov_b32 s9, 0x42004600 +; GFX11-GISEL-NEXT: s_mov_b32 s8, 2.0 +; GFX11-GISEL-NEXT: s_mov_b32 s7, 1.0 +; GFX11-GISEL-NEXT: s_mov_b32 s10, 0x44004700 +; GFX11-GISEL-NEXT: s_mov_b32 s11, 0x45004800 +; GFX11-GISEL-NEXT: v_dual_mov_b32 v3, s9 :: v_dual_mov_b32 v4, s10 +; GFX11-GISEL-NEXT: s_waitcnt lgkmcnt(0) +; GFX11-GISEL-NEXT: v_dual_mov_b32 v5, s11 :: v_dual_mov_b32 v0, s4 +; GFX11-GISEL-NEXT: v_mov_b32_e32 v1, s5 +; GFX11-GISEL-NEXT: s_mov_b32 s4, 0xb36211c6 +; GFX11-GISEL-NEXT: s_movk_i32 s5, 0x102 +; GFX11-GISEL-NEXT: s_delay_alu instid0(SALU_CYCLE_1) +; GFX11-GISEL-NEXT: v_mov_b32_e32 v7, s5 +; GFX11-GISEL-NEXT: v_add_co_u32 v0, vcc_lo, v0, v2 +; GFX11-GISEL-NEXT: v_add_co_ci_u32_e32 v1, vcc_lo, 0, v1, vcc_lo +; GFX11-GISEL-NEXT: v_mov_b32_e32 v6, s4 +; GFX11-GISEL-NEXT: flat_load_b32 v8, v[0:1] +; GFX11-GISEL-NEXT: v_dual_mov_b32 v0, s6 :: v_dual_mov_b32 v1, s7 +; GFX11-GISEL-NEXT: v_mov_b32_e32 v2, s8 +; GFX11-GISEL-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0) +; GFX11-GISEL-NEXT: image_bvh64_intersect_ray v[0:3], [v[6:7], v8, v[0:2], v[3:5]], s[0:3] a16 +; GFX11-GISEL-NEXT: s_waitcnt vmcnt(0) +; GFX11-GISEL-NEXT: flat_store_b128 v[0:1], v[0:3] +; GFX11-GISEL-NEXT: s_sendmsg sendmsg(MSG_DEALLOC_VGPRS) +; GFX11-GISEL-NEXT: s_endpgm main_body: %lid = tail call i32 @llvm.amdgcn.workitem.id.x() %gep_ray = getelementptr inbounds float, ptr %p_ray, i32 %lid @@ -527,5 +1058,3 @@ store <4 x i32> %v, ptr undef ret void } - -declare i32 @llvm.amdgcn.workitem.id.x()