diff --git a/llvm/include/llvm/DWARFLinker/DWARFStreamer.h b/llvm/include/llvm/DWARFLinker/DWARFStreamer.h --- a/llvm/include/llvm/DWARFLinker/DWARFStreamer.h +++ b/llvm/include/llvm/DWARFLinker/DWARFStreamer.h @@ -194,7 +194,7 @@ /// \defgroup MCObjects MC layer objects constructed by the streamer /// @{ - std::unique_ptr MRI; + std::unique_ptr MCRI; std::unique_ptr MAI; std::unique_ptr MOFI; std::unique_ptr MC; diff --git a/llvm/include/llvm/DebugInfo/LogicalView/Readers/LVBinaryReader.h b/llvm/include/llvm/DebugInfo/LogicalView/Readers/LVBinaryReader.h --- a/llvm/include/llvm/DebugInfo/LogicalView/Readers/LVBinaryReader.h +++ b/llvm/include/llvm/DebugInfo/LogicalView/Readers/LVBinaryReader.h @@ -105,7 +105,7 @@ // the current compile unit, created by parsing the debug line section. LVLines CULines; - std::unique_ptr MRI; + std::unique_ptr MCRI; std::unique_ptr MAI; std::unique_ptr STI; std::unique_ptr MII; diff --git a/llvm/include/llvm/MC/MCContext.h b/llvm/include/llvm/MC/MCContext.h --- a/llvm/include/llvm/MC/MCContext.h +++ b/llvm/include/llvm/MC/MCContext.h @@ -113,7 +113,7 @@ const MCAsmInfo *MAI; /// The MCRegisterInfo for this target. - const MCRegisterInfo *MRI; + const MCRegisterInfo *MCRI; /// The MCObjectFileInfo for this target. const MCObjectFileInfo *MOFI; @@ -417,7 +417,7 @@ public: explicit MCContext(const Triple &TheTriple, const MCAsmInfo *MAI, - const MCRegisterInfo *MRI, const MCSubtargetInfo *MSTI, + const MCRegisterInfo *MCRI, const MCSubtargetInfo *MSTI, const SourceMgr *Mgr = nullptr, MCTargetOptions const *TargetOpts = nullptr, bool DoAutoReset = true, @@ -445,7 +445,7 @@ const MCAsmInfo *getAsmInfo() const { return MAI; } - const MCRegisterInfo *getRegisterInfo() const { return MRI; } + const MCRegisterInfo *getRegisterInfo() const { return MCRI; } const MCObjectFileInfo *getObjectFileInfo() const { return MOFI; } diff --git a/llvm/include/llvm/MC/MCInstPrinter.h b/llvm/include/llvm/MC/MCInstPrinter.h --- a/llvm/include/llvm/MC/MCInstPrinter.h +++ b/llvm/include/llvm/MC/MCInstPrinter.h @@ -49,7 +49,7 @@ raw_ostream *CommentStream = nullptr; const MCAsmInfo &MAI; const MCInstrInfo &MII; - const MCRegisterInfo &MRI; + const MCRegisterInfo &MCRI; const MCInstrAnalysis *MIA = nullptr; /// True if we are printing marked up assembly. @@ -81,7 +81,8 @@ public: MCInstPrinter(const MCAsmInfo &mai, const MCInstrInfo &mii, - const MCRegisterInfo &mri) : MAI(mai), MII(mii), MRI(mri) {} + const MCRegisterInfo &mri) + : MAI(mai), MII(mii), MCRI(mri) {} virtual ~MCInstPrinter(); diff --git a/llvm/include/llvm/MC/MCInstrAnalysis.h b/llvm/include/llvm/MC/MCInstrAnalysis.h --- a/llvm/include/llvm/MC/MCInstrAnalysis.h +++ b/llvm/include/llvm/MC/MCInstrAnalysis.h @@ -85,9 +85,8 @@ /// The assumption is that the bit-width of the APInt is correctly set by /// the caller. The default implementation conservatively assumes that none of /// the writes clears the upper portion of a super-register. - virtual bool clearsSuperRegisters(const MCRegisterInfo &MRI, - const MCInst &Inst, - APInt &Writes) const; + virtual bool clearsSuperRegisters(const MCRegisterInfo &MCRI, + const MCInst &Inst, APInt &Writes) const; /// Returns true if MI is a dependency breaking zero-idiom for the given /// subtarget. diff --git a/llvm/include/llvm/MC/MCInstrDesc.h b/llvm/include/llvm/MC/MCInstrDesc.h --- a/llvm/include/llvm/MC/MCInstrDesc.h +++ b/llvm/include/llvm/MC/MCInstrDesc.h @@ -618,7 +618,7 @@ /// Return true if this instruction implicitly /// defines the specified physical register. bool hasImplicitDefOfPhysReg(unsigned Reg, - const MCRegisterInfo *MRI = nullptr) const; + const MCRegisterInfo *MCRI = nullptr) const; /// Return the scheduling class for this instruction. The /// scheduling class is an index into the InstrItineraryData table. This diff --git a/llvm/include/llvm/MC/TargetRegistry.h b/llvm/include/llvm/MC/TargetRegistry.h --- a/llvm/include/llvm/MC/TargetRegistry.h +++ b/llvm/include/llvm/MC/TargetRegistry.h @@ -152,7 +152,7 @@ using ArchMatchFnTy = bool (*)(Triple::ArchType Arch); - using MCAsmInfoCtorFnTy = MCAsmInfo *(*)(const MCRegisterInfo &MRI, + using MCAsmInfoCtorFnTy = MCAsmInfo *(*)(const MCRegisterInfo &MCRI, const Triple &TT, const MCTargetOptions &Options); using MCObjectFileInfoCtorFnTy = MCObjectFileInfo *(*)(MCContext &Ctx, @@ -175,7 +175,7 @@ TargetMachine &TM, std::unique_ptr &&Streamer); using MCAsmBackendCtorTy = MCAsmBackend *(*)(const Target &T, const MCSubtargetInfo &STI, - const MCRegisterInfo &MRI, + const MCRegisterInfo &MCRI, const MCTargetOptions &Options); using MCAsmParserCtorTy = MCTargetAsmParser *(*)( const MCSubtargetInfo &STI, MCAsmParser &P, const MCInstrInfo &MII, @@ -187,7 +187,7 @@ unsigned SyntaxVariant, const MCAsmInfo &MAI, const MCInstrInfo &MII, - const MCRegisterInfo &MRI); + const MCRegisterInfo &MCRI); using MCCodeEmitterCtorTy = MCCodeEmitter *(*)(const MCInstrInfo &II, MCContext &Ctx); using ELFStreamerCtorTy = @@ -411,11 +411,11 @@ /// feature set; it should always be provided. Generally this should be /// either the target triple from the module, or the target triple of the /// host if that does not exist. - MCAsmInfo *createMCAsmInfo(const MCRegisterInfo &MRI, StringRef TheTriple, + MCAsmInfo *createMCAsmInfo(const MCRegisterInfo &MCRI, StringRef TheTriple, const MCTargetOptions &Options) const { if (!MCAsmInfoCtorFn) return nullptr; - return MCAsmInfoCtorFn(MRI, Triple(TheTriple), Options); + return MCAsmInfoCtorFn(MCRI, Triple(TheTriple), Options); } /// Create a MCObjectFileInfo implementation for the specified target @@ -491,11 +491,11 @@ /// createMCAsmBackend - Create a target specific assembly parser. MCAsmBackend *createMCAsmBackend(const MCSubtargetInfo &STI, - const MCRegisterInfo &MRI, + const MCRegisterInfo &MCRI, const MCTargetOptions &Options) const { if (!MCAsmBackendCtorFn) return nullptr; - return MCAsmBackendCtorFn(*this, STI, MRI, Options); + return MCAsmBackendCtorFn(*this, STI, MCRI, Options); } /// createMCAsmParser - Create a target specific assembly parser. @@ -530,10 +530,10 @@ MCInstPrinter *createMCInstPrinter(const Triple &T, unsigned SyntaxVariant, const MCAsmInfo &MAI, const MCInstrInfo &MII, - const MCRegisterInfo &MRI) const { + const MCRegisterInfo &MCRI) const { if (!MCInstPrinterCtorFn) return nullptr; - return MCInstPrinterCtorFn(T, SyntaxVariant, MAI, MII, MRI); + return MCInstPrinterCtorFn(T, SyntaxVariant, MAI, MII, MCRI); } /// createMCCodeEmitter - Create a target specific code emitter. @@ -1159,7 +1159,7 @@ } private: - static MCAsmInfo *Allocator(const MCRegisterInfo & /*MRI*/, const Triple &TT, + static MCAsmInfo *Allocator(const MCRegisterInfo & /*MCRI*/, const Triple &TT, const MCTargetOptions &Options) { return new MCAsmInfoImpl(TT, Options); } @@ -1381,9 +1381,9 @@ private: static MCAsmBackend *Allocator(const Target &T, const MCSubtargetInfo &STI, - const MCRegisterInfo &MRI, + const MCRegisterInfo &MCRI, const MCTargetOptions &Options) { - return new MCAsmBackendImpl(T, STI, MRI); + return new MCAsmBackendImpl(T, STI, MCRI); } }; diff --git a/llvm/include/llvm/MCA/Context.h b/llvm/include/llvm/MCA/Context.h --- a/llvm/include/llvm/MCA/Context.h +++ b/llvm/include/llvm/MCA/Context.h @@ -50,15 +50,16 @@ class Context { SmallVector, 4> Hardware; - const MCRegisterInfo &MRI; + const MCRegisterInfo &MCRI; const MCSubtargetInfo &STI; public: - Context(const MCRegisterInfo &R, const MCSubtargetInfo &S) : MRI(R), STI(S) {} + Context(const MCRegisterInfo &R, const MCSubtargetInfo &S) + : MCRI(R), STI(S) {} Context(const Context &C) = delete; Context &operator=(const Context &C) = delete; - const MCRegisterInfo &getMCRegisterInfo() const { return MRI; } + const MCRegisterInfo &getMCRegisterInfo() const { return MCRI; } const MCSubtargetInfo &getMCSubtargetInfo() const { return STI; } void addHardwareUnit(std::unique_ptr H) { diff --git a/llvm/include/llvm/MCA/HardwareUnits/RegisterFile.h b/llvm/include/llvm/MCA/HardwareUnits/RegisterFile.h --- a/llvm/include/llvm/MCA/HardwareUnits/RegisterFile.h +++ b/llvm/include/llvm/MCA/HardwareUnits/RegisterFile.h @@ -81,7 +81,7 @@ /// Manages hardware register files, and tracks register definitions for /// register renaming purposes. class RegisterFile : public HardwareUnit { - const MCRegisterInfo &MRI; + const MCRegisterInfo &MCRI; // class RegisterMappingTracker is a physical register file (PRF) descriptor. // There is one RegisterMappingTracker for every PRF definition in the diff --git a/llvm/include/llvm/MCA/InstrBuilder.h b/llvm/include/llvm/MCA/InstrBuilder.h --- a/llvm/include/llvm/MCA/InstrBuilder.h +++ b/llvm/include/llvm/MCA/InstrBuilder.h @@ -61,7 +61,7 @@ class InstrBuilder { const MCSubtargetInfo &STI; const MCInstrInfo &MCII; - const MCRegisterInfo &MRI; + const MCRegisterInfo &MCRI; const MCInstrAnalysis *MCIA; const InstrumentManager &IM; SmallVector ProcResourceMasks; diff --git a/llvm/include/llvm/MCA/Stages/DispatchStage.h b/llvm/include/llvm/MCA/Stages/DispatchStage.h --- a/llvm/include/llvm/MCA/Stages/DispatchStage.h +++ b/llvm/include/llvm/MCA/Stages/DispatchStage.h @@ -65,7 +65,7 @@ unsigned uOps) const; public: - DispatchStage(const MCSubtargetInfo &Subtarget, const MCRegisterInfo &MRI, + DispatchStage(const MCSubtargetInfo &Subtarget, const MCRegisterInfo &MCRI, unsigned MaxDispatchWidth, RetireControlUnit &R, RegisterFile &F); diff --git a/llvm/include/llvm/Target/TargetMachine.h b/llvm/include/llvm/Target/TargetMachine.h --- a/llvm/include/llvm/Target/TargetMachine.h +++ b/llvm/include/llvm/Target/TargetMachine.h @@ -104,7 +104,7 @@ /// Contains target specific asm information. std::unique_ptr AsmInfo; - std::unique_ptr MRI; + std::unique_ptr MCRI; std::unique_ptr MII; std::unique_ptr STI; @@ -212,7 +212,7 @@ /// Return target specific asm information. const MCAsmInfo *getMCAsmInfo() const { return AsmInfo.get(); } - const MCRegisterInfo *getMCRegisterInfo() const { return MRI.get(); } + const MCRegisterInfo *getMCRegisterInfo() const { return MCRI.get(); } const MCInstrInfo *getMCInstrInfo() const { return MII.get(); } const MCSubtargetInfo *getMCSubtargetInfo() const { return STI.get(); } diff --git a/llvm/lib/CodeGen/LLVMTargetMachine.cpp b/llvm/lib/CodeGen/LLVMTargetMachine.cpp --- a/llvm/lib/CodeGen/LLVMTargetMachine.cpp +++ b/llvm/lib/CodeGen/LLVMTargetMachine.cpp @@ -38,8 +38,8 @@ cl::desc("Enable generating trap for unreachable")); void LLVMTargetMachine::initAsmInfo() { - MRI.reset(TheTarget.createMCRegInfo(getTargetTriple().str())); - assert(MRI && "Unable to create reg info"); + MCRI.reset(TheTarget.createMCRegInfo(getTargetTriple().str())); + assert(MCRI && "Unable to create reg info"); MII.reset(TheTarget.createMCInstrInfo()); assert(MII && "Unable to create instruction info"); // FIXME: Having an MCSubtargetInfo on the target machine is a hack due @@ -51,7 +51,7 @@ assert(STI && "Unable to create subtarget info"); MCAsmInfo *TmpAsmInfo = TheTarget.createMCAsmInfo( - *MRI, getTargetTriple().str(), Options.MCOptions); + *MCRI, getTargetTriple().str(), Options.MCOptions); // TargetSelect.h moved to a different directory between LLVM 2.9 and 3.0, // and if the old one gets included then MCAsmInfo will be NULL and // we'll crash later. @@ -150,7 +150,7 @@ const MCSubtargetInfo &STI = *getMCSubtargetInfo(); const MCAsmInfo &MAI = *getMCAsmInfo(); - const MCRegisterInfo &MRI = *getMCRegisterInfo(); + const MCRegisterInfo &MCRI = *getMCRegisterInfo(); const MCInstrInfo &MII = *getMCInstrInfo(); std::unique_ptr AsmStreamer; @@ -158,7 +158,7 @@ switch (FileType) { case CGFT_AssemblyFile: { MCInstPrinter *InstPrinter = getTarget().createMCInstPrinter( - getTargetTriple(), MAI.getAssemblerDialect(), MAI, MII, MRI); + getTargetTriple(), MAI.getAssemblerDialect(), MAI, MII, MCRI); // Create a code emitter if asked to show the encoding. std::unique_ptr MCE; @@ -179,7 +179,7 @@ } std::unique_ptr MAB( - getTarget().createMCAsmBackend(STI, MRI, Options.MCOptions)); + getTarget().createMCAsmBackend(STI, MCRI, Options.MCOptions)); auto FOut = std::make_unique(Out); MCStreamer *S = getTarget().createAsmStreamer( Context, std::move(FOut), Options.MCOptions.AsmVerbose, @@ -196,7 +196,7 @@ return make_error("createMCCodeEmitter failed", inconvertibleErrorCode()); MCAsmBackend *MAB = - getTarget().createMCAsmBackend(STI, MRI, Options.MCOptions); + getTarget().createMCAsmBackend(STI, MCRI, Options.MCOptions); if (!MAB) return make_error("createMCAsmBackend failed", inconvertibleErrorCode()); @@ -273,10 +273,10 @@ // Create the code emitter for the target if it exists. If not, .o file // emission fails. const MCSubtargetInfo &STI = *getMCSubtargetInfo(); - const MCRegisterInfo &MRI = *getMCRegisterInfo(); + const MCRegisterInfo &MCRI = *getMCRegisterInfo(); MCCodeEmitter *MCE = getTarget().createMCCodeEmitter(*getMCInstrInfo(), *Ctx); MCAsmBackend *MAB = - getTarget().createMCAsmBackend(STI, MRI, Options.MCOptions); + getTarget().createMCAsmBackend(STI, MCRI, Options.MCOptions); if (!MCE || !MAB) return true; diff --git a/llvm/lib/DWARFLinker/DWARFStreamer.cpp b/llvm/lib/DWARFLinker/DWARFStreamer.cpp --- a/llvm/lib/DWARFLinker/DWARFStreamer.cpp +++ b/llvm/lib/DWARFLinker/DWARFStreamer.cpp @@ -42,13 +42,13 @@ TripleName = TheTriple.getTriple(); // Create all the MC Objects. - MRI.reset(TheTarget->createMCRegInfo(TripleName)); - if (!MRI) + MCRI.reset(TheTarget->createMCRegInfo(TripleName)); + if (!MCRI) return error(Twine("no register info for target ") + TripleName, Context), false; MCTargetOptions MCOptions = mc::InitMCTargetOptionsFromFlags(); - MAI.reset(TheTarget->createMCAsmInfo(*MRI, TripleName, MCOptions)); + MAI.reset(TheTarget->createMCAsmInfo(*MCRI, TripleName, MCOptions)); if (!MAI) return error("no asm info for target " + TripleName, Context), false; @@ -56,12 +56,12 @@ if (!MSTI) return error("no subtarget info for target " + TripleName, Context), false; - MC.reset(new MCContext(TheTriple, MAI.get(), MRI.get(), MSTI.get(), nullptr, + MC.reset(new MCContext(TheTriple, MAI.get(), MCRI.get(), MSTI.get(), nullptr, nullptr, true, Swift5ReflectionSegmentName)); MOFI.reset(TheTarget->createMCObjectFileInfo(*MC, /*PIC=*/false, false)); MC->setObjectFileInfo(MOFI.get()); - MAB = TheTarget->createMCAsmBackend(*MSTI, *MRI, MCOptions); + MAB = TheTarget->createMCAsmBackend(*MSTI, *MCRI, MCOptions); if (!MAB) return error("no asm backend for target " + TripleName, Context), false; @@ -76,7 +76,7 @@ switch (OutFileType) { case OutputFileType::Assembly: { MIP = TheTarget->createMCInstPrinter(TheTriple, MAI->getAssemblerDialect(), - *MAI, *MII, *MRI); + *MAI, *MII, *MCRI); MS = TheTarget->createAsmStreamer( *MC, std::make_unique(OutFile), true, true, MIP, std::unique_ptr(MCE), std::unique_ptr(MAB), diff --git a/llvm/lib/DebugInfo/LogicalView/Readers/LVBinaryReader.cpp b/llvm/lib/DebugInfo/LogicalView/Readers/LVBinaryReader.cpp --- a/llvm/lib/DebugInfo/LogicalView/Readers/LVBinaryReader.cpp +++ b/llvm/lib/DebugInfo/LogicalView/Readers/LVBinaryReader.cpp @@ -203,11 +203,11 @@ if (!RegisterInfo) return createStringError(errc::invalid_argument, "no register info for target " + TheTriple); - MRI.reset(RegisterInfo); + MCRI.reset(RegisterInfo); // Assembler properties and features. MCTargetOptions MCOptions; - MCAsmInfo *AsmInfo(TheTarget->createMCAsmInfo(*MRI, TheTriple, MCOptions)); + MCAsmInfo *AsmInfo(TheTarget->createMCAsmInfo(*MCRI, TheTriple, MCOptions)); if (!AsmInfo) return createStringError(errc::invalid_argument, "no assembly info for target " + TheTriple); @@ -229,7 +229,7 @@ "no instruction info for target " + TheTriple); MII.reset(InstructionInfo); - MC = std::make_unique(Triple(TheTriple), MAI.get(), MRI.get(), + MC = std::make_unique(Triple(TheTriple), MAI.get(), MCRI.get(), STI.get()); // Assembler. @@ -240,7 +240,7 @@ MD.reset(DisAsm); MCInstPrinter *InstructionPrinter(TheTarget->createMCInstPrinter( - Triple(TheTriple), AsmInfo->getAssemblerDialect(), *MAI, *MII, *MRI)); + Triple(TheTriple), AsmInfo->getAssemblerDialect(), *MAI, *MII, *MCRI)); if (!InstructionPrinter) return createStringError(errc::invalid_argument, "no target assembly language printer for target " + diff --git a/llvm/lib/DebugInfo/LogicalView/Readers/LVELFReader.cpp b/llvm/lib/DebugInfo/LogicalView/Readers/LVELFReader.cpp --- a/llvm/lib/DebugInfo/LogicalView/Readers/LVELFReader.cpp +++ b/llvm/lib/DebugInfo/LogicalView/Readers/LVELFReader.cpp @@ -770,7 +770,7 @@ std::string string; raw_string_ostream Stream(string); DIDumpOptions DumpOpts; - auto *MCRegInfo = MRI.get(); + auto *MCRegInfo = MCRI.get(); auto GetRegName = [&MCRegInfo](uint64_t DwarfRegNum, bool IsEH) -> StringRef { if (!MCRegInfo) return {}; diff --git a/llvm/lib/MC/MCAsmStreamer.cpp b/llvm/lib/MC/MCAsmStreamer.cpp --- a/llvm/lib/MC/MCAsmStreamer.cpp +++ b/llvm/lib/MC/MCAsmStreamer.cpp @@ -1882,9 +1882,9 @@ // User .cfi_* directives can use arbitrary DWARF register numbers, not // just ones that map to LLVM register numbers and have known names. // Fall back to using the original number directly if no name is known. - const MCRegisterInfo *MRI = getContext().getRegisterInfo(); + const MCRegisterInfo *MCRI = getContext().getRegisterInfo(); if (std::optional LLVMRegister = - MRI->getLLVMRegNum(Register, true)) { + MCRI->getLLVMRegNum(Register, true)) { InstPrinter->printRegName(OS, *LLVMRegister); return; } diff --git a/llvm/lib/MC/MCContext.cpp b/llvm/lib/MC/MCContext.cpp --- a/llvm/lib/MC/MCContext.cpp +++ b/llvm/lib/MC/MCContext.cpp @@ -70,7 +70,7 @@ bool DoAutoReset, StringRef Swift5ReflSegmentName) : Swift5ReflectionSegmentName(Swift5ReflSegmentName), TT(TheTriple), SrcMgr(mgr), InlineSrcMgr(nullptr), DiagHandler(defaultDiagHandler), - MAI(mai), MRI(mri), MSTI(msti), Symbols(Allocator), UsedNames(Allocator), + MAI(mai), MCRI(mri), MSTI(msti), Symbols(Allocator), UsedNames(Allocator), InlineAsmUsedLabelNames(Allocator), CurrentDwarfLoc(0, 0, 0, DWARF2_FLAG_IS_STMT, 0, 0), AutoReset(DoAutoReset), TargetOptions(TargetOpts) { diff --git a/llvm/lib/MC/MCDisassembler/Disassembler.h b/llvm/lib/MC/MCDisassembler/Disassembler.h --- a/llvm/lib/MC/MCDisassembler/Disassembler.h +++ b/llvm/lib/MC/MCDisassembler/Disassembler.h @@ -61,7 +61,7 @@ // The assembly information for the target architecture. std::unique_ptr MAI; // The register information for the target architecture. - std::unique_ptr MRI; + std::unique_ptr MCRI; // The subtarget information for the target architecture. std::unique_ptr MSI; // The instruction information for the target architecture. @@ -87,7 +87,7 @@ LLVMSymbolLookupCallback SymbolLookUp, const Target *TheTarget, std::unique_ptr &&MAI, - std::unique_ptr &&MRI, + std::unique_ptr &&MCRI, std::unique_ptr &&MSI, std::unique_ptr &&MII, std::unique_ptr &&Ctx, @@ -95,7 +95,7 @@ std::unique_ptr &&IP) : TripleName(std::move(TripleName)), DisInfo(DisInfo), TagType(TagType), GetOpInfo(GetOpInfo), SymbolLookUp(SymbolLookUp), TheTarget(TheTarget), - MAI(std::move(MAI)), MRI(std::move(MRI)), MSI(std::move(MSI)), + MAI(std::move(MAI)), MCRI(std::move(MCRI)), MSI(std::move(MSI)), MII(std::move(MII)), Ctx(std::move(Ctx)), DisAsm(std::move(DisAsm)), IP(std::move(IP)), Options(0), CommentStream(CommentsToEmit) {} const std::string &getTripleName() const { return TripleName; } @@ -109,7 +109,7 @@ const MCDisassembler *getDisAsm() const { return DisAsm.get(); } const MCAsmInfo *getAsmInfo() const { return MAI.get(); } const MCInstrInfo *getInstrInfo() const { return MII.get(); } - const MCRegisterInfo *getRegisterInfo() const { return MRI.get(); } + const MCRegisterInfo *getRegisterInfo() const { return MCRI.get(); } const MCSubtargetInfo *getSubtargetInfo() const { return MSI.get(); } MCInstPrinter *getIP() { return IP.get(); } void setIP(MCInstPrinter *NewIP) { IP.reset(NewIP); } diff --git a/llvm/lib/MC/MCDisassembler/Disassembler.cpp b/llvm/lib/MC/MCDisassembler/Disassembler.cpp --- a/llvm/lib/MC/MCDisassembler/Disassembler.cpp +++ b/llvm/lib/MC/MCDisassembler/Disassembler.cpp @@ -52,14 +52,14 @@ if (!TheTarget) return nullptr; - std::unique_ptr MRI(TheTarget->createMCRegInfo(TT)); - if (!MRI) + std::unique_ptr MCRI(TheTarget->createMCRegInfo(TT)); + if (!MCRI) return nullptr; MCTargetOptions MCOptions; // Get the assembler info needed to setup the MCContext. std::unique_ptr MAI( - TheTarget->createMCAsmInfo(*MRI, TT, MCOptions)); + TheTarget->createMCAsmInfo(*MCRI, TT, MCOptions)); if (!MAI) return nullptr; @@ -74,7 +74,7 @@ // Set up the MCContext for creating symbols and MCExpr's. std::unique_ptr Ctx( - new MCContext(Triple(TT), MAI.get(), MRI.get(), STI.get())); + new MCContext(Triple(TT), MAI.get(), MCRI.get(), STI.get())); if (!Ctx) return nullptr; @@ -96,13 +96,13 @@ // Set up the instruction printer. int AsmPrinterVariant = MAI->getAssemblerDialect(); std::unique_ptr IP(TheTarget->createMCInstPrinter( - Triple(TT), AsmPrinterVariant, *MAI, *MII, *MRI)); + Triple(TT), AsmPrinterVariant, *MAI, *MII, *MCRI)); if (!IP) return nullptr; LLVMDisasmContext *DC = new LLVMDisasmContext( TT, DisInfo, TagType, GetOpInfo, SymbolLookUp, TheTarget, std::move(MAI), - std::move(MRI), std::move(STI), std::move(MII), std::move(Ctx), + std::move(MCRI), std::move(STI), std::move(MII), std::move(Ctx), std::move(DisAsm), std::move(IP)); if (!DC) return nullptr; @@ -319,11 +319,11 @@ // Try to set up the new instruction printer. const MCAsmInfo *MAI = DC->getAsmInfo(); const MCInstrInfo *MII = DC->getInstrInfo(); - const MCRegisterInfo *MRI = DC->getRegisterInfo(); + const MCRegisterInfo *MCRI = DC->getRegisterInfo(); int AsmPrinterVariant = MAI->getAssemblerDialect(); AsmPrinterVariant = AsmPrinterVariant == 0 ? 1 : 0; MCInstPrinter *IP = DC->getTarget()->createMCInstPrinter( - Triple(DC->getTripleName()), AsmPrinterVariant, *MAI, *MII, *MRI); + Triple(DC->getTripleName()), AsmPrinterVariant, *MAI, *MII, *MCRI); if (IP) { DC->setIP(IP); DC->addOptions(LLVMDisassembler_Option_AsmPrinterVariant); diff --git a/llvm/lib/MC/MCDwarf.cpp b/llvm/lib/MC/MCDwarf.cpp --- a/llvm/lib/MC/MCDwarf.cpp +++ b/llvm/lib/MC/MCDwarf.cpp @@ -1319,15 +1319,15 @@ void FrameEmitterImpl::emitCFIInstruction(const MCCFIInstruction &Instr) { int dataAlignmentFactor = getDataAlignmentFactor(Streamer); - auto *MRI = Streamer.getContext().getRegisterInfo(); + auto *MCRI = Streamer.getContext().getRegisterInfo(); switch (Instr.getOperation()) { case MCCFIInstruction::OpRegister: { unsigned Reg1 = Instr.getRegister(); unsigned Reg2 = Instr.getRegister2(); if (!IsEH) { - Reg1 = MRI->getDwarfRegNumFromDwarfEHRegNum(Reg1); - Reg2 = MRI->getDwarfRegNumFromDwarfEHRegNum(Reg2); + Reg1 = MCRI->getDwarfRegNumFromDwarfEHRegNum(Reg1); + Reg2 = MCRI->getDwarfRegNumFromDwarfEHRegNum(Reg2); } Streamer.emitInt8(dwarf::DW_CFA_register); Streamer.emitULEB128IntValue(Reg1); @@ -1367,7 +1367,7 @@ case MCCFIInstruction::OpDefCfa: { unsigned Reg = Instr.getRegister(); if (!IsEH) - Reg = MRI->getDwarfRegNumFromDwarfEHRegNum(Reg); + Reg = MCRI->getDwarfRegNumFromDwarfEHRegNum(Reg); Streamer.emitInt8(dwarf::DW_CFA_def_cfa); Streamer.emitULEB128IntValue(Reg); CFAOffset = Instr.getOffset(); @@ -1378,7 +1378,7 @@ case MCCFIInstruction::OpDefCfaRegister: { unsigned Reg = Instr.getRegister(); if (!IsEH) - Reg = MRI->getDwarfRegNumFromDwarfEHRegNum(Reg); + Reg = MCRI->getDwarfRegNumFromDwarfEHRegNum(Reg); Streamer.emitInt8(dwarf::DW_CFA_def_cfa_register); Streamer.emitULEB128IntValue(Reg); @@ -1388,7 +1388,7 @@ case MCCFIInstruction::OpLLVMDefAspaceCfa: { unsigned Reg = Instr.getRegister(); if (!IsEH) - Reg = MRI->getDwarfRegNumFromDwarfEHRegNum(Reg); + Reg = MCRI->getDwarfRegNumFromDwarfEHRegNum(Reg); Streamer.emitIntValue(dwarf::DW_CFA_LLVM_def_aspace_cfa, 1); Streamer.emitULEB128IntValue(Reg); CFAOffset = Instr.getOffset(); @@ -1404,7 +1404,7 @@ unsigned Reg = Instr.getRegister(); if (!IsEH) - Reg = MRI->getDwarfRegNumFromDwarfEHRegNum(Reg); + Reg = MCRI->getDwarfRegNumFromDwarfEHRegNum(Reg); int Offset = Instr.getOffset(); if (IsRelative) @@ -1440,7 +1440,7 @@ case MCCFIInstruction::OpRestore: { unsigned Reg = Instr.getRegister(); if (!IsEH) - Reg = MRI->getDwarfRegNumFromDwarfEHRegNum(Reg); + Reg = MCRI->getDwarfRegNumFromDwarfEHRegNum(Reg); if (Reg < 64) { Streamer.emitInt8(dwarf::DW_CFA_restore | Reg); } else { @@ -1563,7 +1563,7 @@ const MCSymbol &FrameEmitterImpl::EmitCIE(const MCDwarfFrameInfo &Frame) { MCContext &context = Streamer.getContext(); - const MCRegisterInfo *MRI = context.getRegisterInfo(); + const MCRegisterInfo *MCRI = context.getRegisterInfo(); const MCObjectFileInfo *MOFI = context.getObjectFileInfo(); MCSymbol *sectionStart = context.createTempSymbol(); @@ -1629,7 +1629,7 @@ // Return Address Register unsigned RAReg = Frame.RAReg; if (RAReg == static_cast(INT_MAX)) - RAReg = MRI->getDwarfRegNum(MRI->getRARegister(), IsEH); + RAReg = MCRI->getDwarfRegNum(MCRI->getRARegister(), IsEH); if (CIEVersion == 1) { assert(RAReg <= 255 && diff --git a/llvm/lib/MC/MCInstPrinter.cpp b/llvm/lib/MC/MCInstPrinter.cpp --- a/llvm/lib/MC/MCInstPrinter.cpp +++ b/llvm/lib/MC/MCInstPrinter.cpp @@ -61,7 +61,7 @@ } static bool matchAliasCondition(const MCInst &MI, const MCSubtargetInfo *STI, - const MCRegisterInfo &MRI, unsigned &OpIdx, + const MCRegisterInfo &MCRI, unsigned &OpIdx, const AliasMatchingData &M, const AliasPatternCond &C, bool &OrPredicateResult) { @@ -104,7 +104,7 @@ return Opnd.isReg() && Opnd.getReg() == MI.getOperand(C.Value).getReg(); case AliasPatternCond::K_RegClass: // Operand must be a register in this class. Value is a register class id. - return Opnd.isReg() && MRI.getRegClass(C.Value).contains(Opnd.getReg()); + return Opnd.isReg() && MCRI.getRegClass(C.Value).contains(Opnd.getReg()); case AliasPatternCond::K_Custom: // Operand must match some custom criteria. return M.ValidateMCOperand(Opnd, *STI, C.Value); @@ -148,7 +148,7 @@ unsigned OpIdx = 0; bool OrPredicateResult = false; if (llvm::all_of(Conds, [&](const AliasPatternCond &C) { - return matchAliasCondition(*MI, STI, MRI, OpIdx, M, C, + return matchAliasCondition(*MI, STI, MCRI, OpIdx, M, C, OrPredicateResult); })) { // If all conditions matched, use this asm string. diff --git a/llvm/lib/MC/MCInstrAnalysis.cpp b/llvm/lib/MC/MCInstrAnalysis.cpp --- a/llvm/lib/MC/MCInstrAnalysis.cpp +++ b/llvm/lib/MC/MCInstrAnalysis.cpp @@ -17,7 +17,7 @@ using namespace llvm; -bool MCInstrAnalysis::clearsSuperRegisters(const MCRegisterInfo &MRI, +bool MCInstrAnalysis::clearsSuperRegisters(const MCRegisterInfo &MCRI, const MCInst &Inst, APInt &Writes) const { Writes.clearAllBits(); diff --git a/llvm/lib/MC/MCInstrDesc.cpp b/llvm/lib/MC/MCInstrDesc.cpp --- a/llvm/lib/MC/MCInstrDesc.cpp +++ b/llvm/lib/MC/MCInstrDesc.cpp @@ -30,10 +30,10 @@ } bool MCInstrDesc::hasImplicitDefOfPhysReg(unsigned Reg, - const MCRegisterInfo *MRI) const { + const MCRegisterInfo *MCRI) const { if (const MCPhysReg *ImpDefs = getImplicitDefs()) for (; *ImpDefs; ++ImpDefs) - if (*ImpDefs == Reg || (MRI && MRI->isSubRegister(Reg, *ImpDefs))) + if (*ImpDefs == Reg || (MCRI && MCRI->isSubRegister(Reg, *ImpDefs))) return true; return false; } diff --git a/llvm/lib/MCA/Context.cpp b/llvm/lib/MCA/Context.cpp --- a/llvm/lib/MCA/Context.cpp +++ b/llvm/lib/MCA/Context.cpp @@ -38,15 +38,15 @@ // Create the hardware units defining the backend. auto RCU = std::make_unique(SM); - auto PRF = std::make_unique(SM, MRI, Opts.RegisterFileSize); + auto PRF = std::make_unique(SM, MCRI, Opts.RegisterFileSize); auto LSU = std::make_unique(SM, Opts.LoadQueueSize, Opts.StoreQueueSize, Opts.AssumeNoAlias); auto HWS = std::make_unique(SM, *LSU); // Create the pipeline stages. auto Fetch = std::make_unique(SrcMgr); - auto Dispatch = - std::make_unique(STI, MRI, Opts.DispatchWidth, *RCU, *PRF); + auto Dispatch = std::make_unique(STI, MCRI, Opts.DispatchWidth, + *RCU, *PRF); auto Execute = std::make_unique(*HWS, Opts.EnableBottleneckAnalysis); auto Retire = std::make_unique(*RCU, *PRF, *LSU); @@ -73,7 +73,7 @@ Context::createInOrderPipeline(const PipelineOptions &Opts, SourceMgr &SrcMgr, CustomBehaviour &CB) { const MCSchedModel &SM = STI.getSchedModel(); - auto PRF = std::make_unique(SM, MRI, Opts.RegisterFileSize); + auto PRF = std::make_unique(SM, MCRI, Opts.RegisterFileSize); auto LSU = std::make_unique(SM, Opts.LoadQueueSize, Opts.StoreQueueSize, Opts.AssumeNoAlias); diff --git a/llvm/lib/MCA/HardwareUnits/RegisterFile.cpp b/llvm/lib/MCA/HardwareUnits/RegisterFile.cpp --- a/llvm/lib/MCA/HardwareUnits/RegisterFile.cpp +++ b/llvm/lib/MCA/HardwareUnits/RegisterFile.cpp @@ -63,7 +63,7 @@ RegisterFile::RegisterFile(const MCSchedModel &SM, const MCRegisterInfo &mri, unsigned NumRegs) - : MRI(mri), + : MCRI(mri), RegisterMappings(mri.getNumRegs(), {WriteRef(), RegisterRenamingInfo()}), ZeroRegisters(mri.getNumRegs(), false), CurrentCycle() { initialize(SM, NumRegs); @@ -127,7 +127,7 @@ if (WR.getWriteState() == &WS) WR.notifyExecuted(CurrentCycle); - for (MCSubRegIterator I(RegID, &MRI); I.isValid(); ++I) { + for (MCSubRegIterator I(RegID, &MCRI); I.isValid(); ++I) { WriteRef &OtherWR = RegisterMappings[*I].first; if (OtherWR.getWriteState() == &WS) OtherWR.notifyExecuted(CurrentCycle); @@ -136,7 +136,7 @@ if (!WS.clearsSuperRegisters()) continue; - for (MCSuperRegIterator I(RegID, &MRI); I.isValid(); ++I) { + for (MCSuperRegIterator I(RegID, &MCRI); I.isValid(); ++I) { WriteRef &OtherWR = RegisterMappings[*I].first; if (OtherWR.getWriteState() == &WS) OtherWR.notifyExecuted(CurrentCycle); @@ -166,7 +166,7 @@ // Now update the cost of individual registers. for (const MCRegisterCostEntry &RCE : Entries) { - const MCRegisterClass &RC = MRI.getRegClass(RCE.RegisterClassID); + const MCRegisterClass &RC = MCRI.getRegClass(RCE.RegisterClassID); for (const MCPhysReg Reg : RC) { RegisterRenamingInfo &Entry = RegisterMappings[Reg].second; IndexPlusCostPairTy &IPC = Entry.IndexPlusCost; @@ -174,7 +174,7 @@ // The only register file that is allowed to overlap is the default // register file at index #0. The analysis is inaccurate if register // files overlap. - errs() << "warning: register " << MRI.getName(Reg) + errs() << "warning: register " << MCRI.getName(Reg) << " defined in multiple register files."; } IPC = std::make_pair(RegisterFileIndex, RCE.Cost); @@ -182,11 +182,11 @@ Entry.AllowMoveElimination = RCE.AllowMoveElimination; // Assume the same cost for each sub-register. - for (MCSubRegIterator I(Reg, &MRI); I.isValid(); ++I) { + for (MCSubRegIterator I(Reg, &MCRI); I.isValid(); ++I) { RegisterRenamingInfo &OtherEntry = RegisterMappings[*I].second; if (!OtherEntry.IndexPlusCost.first && (!OtherEntry.RenameAs || - MRI.isSuperRegister(*I, OtherEntry.RenameAs))) { + MCRI.isSuperRegister(*I, OtherEntry.RenameAs))) { OtherEntry.IndexPlusCost = IPC; OtherEntry.RenameAs = Reg; } @@ -237,7 +237,7 @@ LLVM_DEBUG({ dbgs() << "[PRF] addRegisterWrite [ " << Write.getSourceIndex() << ", " - << MRI.getName(RegID) << "]\n"; + << MCRI.getName(RegID) << "]\n"; }); // If RenameAs is equal to RegID, then RegID is subject to register renaming @@ -282,7 +282,7 @@ MCPhysReg ZeroRegisterID = WS.clearsSuperRegisters() ? RegID : WS.getRegisterID(); ZeroRegisters.setBitVal(ZeroRegisterID, IsWriteZero); - for (MCSubRegIterator I(ZeroRegisterID, &MRI); I.isValid(); ++I) + for (MCSubRegIterator I(ZeroRegisterID, &MCRI); I.isValid(); ++I) ZeroRegisters.setBitVal(*I, IsWriteZero); // If this move has been eliminated, then method tryEliminateMoveOrSwap should @@ -304,7 +304,7 @@ // Update the mapping for register RegID including its sub-registers. RegisterMappings[RegID].first = Write; RegisterMappings[RegID].second.AliasRegID = 0U; - for (MCSubRegIterator I(RegID, &MRI); I.isValid(); ++I) { + for (MCSubRegIterator I(RegID, &MCRI); I.isValid(); ++I) { RegisterMappings[*I].first = Write; RegisterMappings[*I].second.AliasRegID = 0U; } @@ -319,7 +319,7 @@ if (!WS.clearsSuperRegisters()) return; - for (MCSuperRegIterator I(RegID, &MRI); I.isValid(); ++I) { + for (MCSuperRegIterator I(RegID, &MCRI); I.isValid(); ++I) { if (!IsEliminated) { RegisterMappings[*I].first = Write; RegisterMappings[*I].second.AliasRegID = 0U; @@ -365,7 +365,7 @@ if (WR.getWriteState() == &WS) WR.commit(); - for (MCSubRegIterator I(RegID, &MRI); I.isValid(); ++I) { + for (MCSubRegIterator I(RegID, &MCRI); I.isValid(); ++I) { WriteRef &OtherWR = RegisterMappings[*I].first; if (OtherWR.getWriteState() == &WS) OtherWR.commit(); @@ -374,7 +374,7 @@ if (!WS.clearsSuperRegisters()) return; - for (MCSuperRegIterator I(RegID, &MRI); I.isValid(); ++I) { + for (MCSuperRegIterator I(RegID, &MCRI); I.isValid(); ++I) { WriteRef &OtherWR = RegisterMappings[*I].first; if (OtherWR.getWriteState() == &WS) OtherWR.commit(); @@ -472,7 +472,7 @@ AliasedReg = RMAlias.AliasRegID; RegisterMappings[AliasReg].second.AliasRegID = AliasedReg; - for (MCSubRegIterator I(AliasReg, &MRI); I.isValid(); ++I) + for (MCSubRegIterator I(AliasReg, &MCRI); I.isValid(); ++I) RegisterMappings[*I].second.AliasRegID = AliasedReg; if (ZeroRegisters[RS.getRegisterID()]) { @@ -509,7 +509,7 @@ MCPhysReg RegID = RS.getRegisterID(); assert(RegID && RegID < RegisterMappings.size()); LLVM_DEBUG(dbgs() << "[PRF] collecting writes for register " - << MRI.getName(RegID) << '\n'); + << MCRI.getName(RegID) << '\n'); // Check if this is an alias. const RegisterRenamingInfo &RRI = RegisterMappings[RegID].second; @@ -530,7 +530,7 @@ } // Handle potential partial register updates. - for (MCSubRegIterator I(RegID, &MRI); I.isValid(); ++I) { + for (MCSubRegIterator I(RegID, &MCRI); I.isValid(); ++I) { const WriteRef &WR = RegisterMappings[*I].first; if (WR.getWriteState()) { Writes.push_back(WR); @@ -558,7 +558,7 @@ for (const WriteRef &WR : Writes) { const WriteState &WS = *WR.getWriteState(); dbgs() << "[PRF] Found a dependent use of Register " - << MRI.getName(WS.getRegisterID()) << " (defined by instruction #" + << MCRI.getName(WS.getRegisterID()) << " (defined by instruction #" << WR.getSourceIndex() << ")\n"; } }); @@ -715,11 +715,11 @@ } void RegisterFile::dump() const { - for (unsigned I = 0, E = MRI.getNumRegs(); I < E; ++I) { + for (unsigned I = 0, E = MCRI.getNumRegs(); I < E; ++I) { const RegisterMapping &RM = RegisterMappings[I]; const RegisterRenamingInfo &RRI = RM.second; if (ZeroRegisters[I]) { - dbgs() << MRI.getName(I) << ", " << I + dbgs() << MCRI.getName(I) << ", " << I << ", PRF=" << RRI.IndexPlusCost.first << ", Cost=" << RRI.IndexPlusCost.second << ", RenameAs=" << RRI.RenameAs << ", IsZero=" << ZeroRegisters[I] diff --git a/llvm/lib/MCA/InstrBuilder.cpp b/llvm/lib/MCA/InstrBuilder.cpp --- a/llvm/lib/MCA/InstrBuilder.cpp +++ b/llvm/lib/MCA/InstrBuilder.cpp @@ -32,7 +32,7 @@ const llvm::MCRegisterInfo &mri, const llvm::MCInstrAnalysis *mcia, const mca::InstrumentManager &im) - : STI(sti), MCII(mcii), MRI(mri), MCIA(mcia), IM(im), FirstCallInst(true), + : STI(sti), MCII(mcii), MCRI(mri), MCIA(mcia), IM(im), FirstCallInst(true), FirstReturnInst(true) { const MCSchedModel &SM = STI.getSchedModel(); ProcResourceMasks.resize(SM.getNumProcResourceKinds()); @@ -383,7 +383,7 @@ assert(Write.RegisterID != 0 && "Expected a valid phys register!"); LLVM_DEBUG({ dbgs() << "\t\t[Def][I] OpIdx=" << ~Write.OpIndex - << ", PhysReg=" << MRI.getName(Write.RegisterID) + << ", PhysReg=" << MCRI.getName(Write.RegisterID) << ", Latency=" << Write.Latency << ", WriteResourceID=" << Write.SClassOrWriteResourceID << '\n'; }); @@ -468,7 +468,7 @@ Read.SchedClassID = SchedClassID; LLVM_DEBUG(dbgs() << "\t\t[Use][I] OpIdx=" << ~Read.OpIndex << ", UseIndex=" << Read.UseIndex << ", RegisterID=" - << MRI.getName(Read.RegisterID) << '\n'); + << MCRI.getName(Read.RegisterID) << '\n'); } CurrentUse += NumImplicitUses; @@ -740,7 +740,7 @@ // Now query the MCInstrAnalysis object to obtain information about which // register writes implicitly clear the upper portion of a super-register. if (MCIA) - MCIA->clearsSuperRegisters(MRI, MCI, WriteMask); + MCIA->clearsSuperRegisters(MCRI, MCI, WriteMask); // Initialize writes. unsigned WriteIndex = 0; diff --git a/llvm/lib/MCA/Stages/DispatchStage.cpp b/llvm/lib/MCA/Stages/DispatchStage.cpp --- a/llvm/lib/MCA/Stages/DispatchStage.cpp +++ b/llvm/lib/MCA/Stages/DispatchStage.cpp @@ -26,7 +26,7 @@ namespace mca { DispatchStage::DispatchStage(const MCSubtargetInfo &Subtarget, - const MCRegisterInfo &MRI, + const MCRegisterInfo &MCRI, unsigned MaxDispatchWidth, RetireControlUnit &R, RegisterFile &F) : DispatchWidth(MaxDispatchWidth), AvailableEntries(MaxDispatchWidth), diff --git a/llvm/lib/Object/ModuleSymbolTable.cpp b/llvm/lib/Object/ModuleSymbolTable.cpp --- a/llvm/lib/Object/ModuleSymbolTable.cpp +++ b/llvm/lib/Object/ModuleSymbolTable.cpp @@ -78,12 +78,13 @@ const Target *T = TargetRegistry::lookupTarget(TT.str(), Err); assert(T && T->hasMCAsmParser()); - std::unique_ptr MRI(T->createMCRegInfo(TT.str())); - if (!MRI) + std::unique_ptr MCRI(T->createMCRegInfo(TT.str())); + if (!MCRI) return; MCTargetOptions MCOptions; - std::unique_ptr MAI(T->createMCAsmInfo(*MRI, TT.str(), MCOptions)); + std::unique_ptr MAI( + T->createMCAsmInfo(*MCRI, TT.str(), MCOptions)); if (!MAI) return; @@ -100,7 +101,7 @@ SourceMgr SrcMgr; SrcMgr.AddNewSourceBuffer(std::move(Buffer), SMLoc()); - MCContext MCCtx(TT, MAI.get(), MRI.get(), STI.get(), &SrcMgr); + MCContext MCCtx(TT, MAI.get(), MCRI.get(), STI.get(), &SrcMgr); std::unique_ptr MOFI( T->createMCObjectFileInfo(MCCtx, /*PIC=*/false)); MOFI->setSDKVersion(M.getSDKVersion()); diff --git a/llvm/lib/Target/AArch64/AArch64ISelLowering.cpp b/llvm/lib/Target/AArch64/AArch64ISelLowering.cpp --- a/llvm/lib/Target/AArch64/AArch64ISelLowering.cpp +++ b/llvm/lib/Target/AArch64/AArch64ISelLowering.cpp @@ -9650,8 +9650,8 @@ getRegisterByName(const char* RegName, LLT VT, const MachineFunction &MF) const { Register Reg = MatchRegisterName(RegName); if (AArch64::X1 <= Reg && Reg <= AArch64::X28) { - const MCRegisterInfo *MRI = Subtarget->getRegisterInfo(); - unsigned DwarfRegNum = MRI->getDwarfRegNum(Reg, false); + const MCRegisterInfo *MCRI = Subtarget->getRegisterInfo(); + unsigned DwarfRegNum = MCRI->getDwarfRegNum(Reg, false); if (!Subtarget->isXRegisterReserved(DwarfRegNum)) Reg = 0; } diff --git a/llvm/lib/Target/AArch64/AArch64InstrInfo.cpp b/llvm/lib/Target/AArch64/AArch64InstrInfo.cpp --- a/llvm/lib/Target/AArch64/AArch64InstrInfo.cpp +++ b/llvm/lib/Target/AArch64/AArch64InstrInfo.cpp @@ -7996,8 +7996,8 @@ if (MF.getInfo()->needsDwarfUnwindInfo(MF)) { const TargetSubtargetInfo &STI = MF.getSubtarget(); - const MCRegisterInfo *MRI = STI.getRegisterInfo(); - unsigned DwarfReg = MRI->getDwarfRegNum(AArch64::LR, true); + const MCRegisterInfo *MCRI = STI.getRegisterInfo(); + unsigned DwarfReg = MCRI->getDwarfRegNum(AArch64::LR, true); // Add a CFI saying the stack was moved 16 B down. int64_t StackPosEntry = diff --git a/llvm/lib/Target/AArch64/MCTargetDesc/AArch64AsmBackend.cpp b/llvm/lib/Target/AArch64/MCTargetDesc/AArch64AsmBackend.cpp --- a/llvm/lib/Target/AArch64/MCTargetDesc/AArch64AsmBackend.cpp +++ b/llvm/lib/Target/AArch64/MCTargetDesc/AArch64AsmBackend.cpp @@ -541,7 +541,7 @@ // FIXME: This should be in a separate file. class DarwinAArch64AsmBackend : public AArch64AsmBackend { - const MCRegisterInfo &MRI; + const MCRegisterInfo &MCRI; /// Encode compact unwind stack adjustment for frameless functions. /// See UNWIND_ARM64_FRAMELESS_STACK_SIZE_MASK in compact_unwind_encoding.h. @@ -552,8 +552,8 @@ public: DarwinAArch64AsmBackend(const Target &T, const Triple &TT, - const MCRegisterInfo &MRI) - : AArch64AsmBackend(T, TT, /*IsLittleEndian*/ true), MRI(MRI) {} + const MCRegisterInfo &MCRI) + : AArch64AsmBackend(T, TT, /*IsLittleEndian*/ true), MCRI(MCRI) {} std::unique_ptr createObjectTargetWriter() const override { @@ -584,7 +584,7 @@ case MCCFIInstruction::OpDefCfa: { // Defines a frame pointer. unsigned XReg = - getXRegFromWReg(*MRI.getLLVMRegNum(Inst.getRegister(), true)); + getXRegFromWReg(*MCRI.getLLVMRegNum(Inst.getRegister(), true)); // Other CFA registers than FP are not supported by compact unwind. // Fallback on DWARF. @@ -607,8 +607,8 @@ return CU::UNWIND_ARM64_MODE_DWARF; CurOffset = FPPush.getOffset(); - unsigned LRReg = *MRI.getLLVMRegNum(LRPush.getRegister(), true); - unsigned FPReg = *MRI.getLLVMRegNum(FPPush.getRegister(), true); + unsigned LRReg = *MCRI.getLLVMRegNum(LRPush.getRegister(), true); + unsigned FPReg = *MCRI.getLLVMRegNum(FPPush.getRegister(), true); LRReg = getXRegFromWReg(LRReg); FPReg = getXRegFromWReg(FPReg); @@ -630,7 +630,7 @@ case MCCFIInstruction::OpOffset: { // Registers are saved in pairs. We expect there to be two consecutive // `.cfi_offset' instructions with the appropriate registers specified. - unsigned Reg1 = *MRI.getLLVMRegNum(Inst.getRegister(), true); + unsigned Reg1 = *MCRI.getLLVMRegNum(Inst.getRegister(), true); if (i + 1 == e) return CU::UNWIND_ARM64_MODE_DWARF; @@ -641,7 +641,7 @@ const MCCFIInstruction &Inst2 = Instrs[++i]; if (Inst2.getOperation() != MCCFIInstruction::OpOffset) return CU::UNWIND_ARM64_MODE_DWARF; - unsigned Reg2 = *MRI.getLLVMRegNum(Inst2.getRegister(), true); + unsigned Reg2 = *MCRI.getLLVMRegNum(Inst2.getRegister(), true); if (Inst2.getOffset() != CurOffset - 8) return CU::UNWIND_ARM64_MODE_DWARF; @@ -753,11 +753,11 @@ MCAsmBackend *llvm::createAArch64leAsmBackend(const Target &T, const MCSubtargetInfo &STI, - const MCRegisterInfo &MRI, + const MCRegisterInfo &MCRI, const MCTargetOptions &Options) { const Triple &TheTriple = STI.getTargetTriple(); if (TheTriple.isOSBinFormatMachO()) { - return new DarwinAArch64AsmBackend(T, TheTriple, MRI); + return new DarwinAArch64AsmBackend(T, TheTriple, MCRI); } if (TheTriple.isOSBinFormatCOFF()) @@ -773,7 +773,7 @@ MCAsmBackend *llvm::createAArch64beAsmBackend(const Target &T, const MCSubtargetInfo &STI, - const MCRegisterInfo &MRI, + const MCRegisterInfo &MCRI, const MCTargetOptions &Options) { const Triple &TheTriple = STI.getTargetTriple(); assert(TheTriple.isOSBinFormatELF() && diff --git a/llvm/lib/Target/AArch64/MCTargetDesc/AArch64InstPrinter.h b/llvm/lib/Target/AArch64/MCTargetDesc/AArch64InstPrinter.h --- a/llvm/lib/Target/AArch64/MCTargetDesc/AArch64InstPrinter.h +++ b/llvm/lib/Target/AArch64/MCTargetDesc/AArch64InstPrinter.h @@ -23,7 +23,7 @@ class AArch64InstPrinter : public MCInstPrinter { public: AArch64InstPrinter(const MCAsmInfo &MAI, const MCInstrInfo &MII, - const MCRegisterInfo &MRI); + const MCRegisterInfo &MCRI); bool applyTargetSpecificCLOption(StringRef Opt) override; @@ -240,7 +240,7 @@ class AArch64AppleInstPrinter : public AArch64InstPrinter { public: AArch64AppleInstPrinter(const MCAsmInfo &MAI, const MCInstrInfo &MII, - const MCRegisterInfo &MRI); + const MCRegisterInfo &MCRI); void printInst(const MCInst *MI, uint64_t Address, StringRef Annot, const MCSubtargetInfo &STI, raw_ostream &O) override; diff --git a/llvm/lib/Target/AArch64/MCTargetDesc/AArch64InstPrinter.cpp b/llvm/lib/Target/AArch64/MCTargetDesc/AArch64InstPrinter.cpp --- a/llvm/lib/Target/AArch64/MCTargetDesc/AArch64InstPrinter.cpp +++ b/llvm/lib/Target/AArch64/MCTargetDesc/AArch64InstPrinter.cpp @@ -43,13 +43,13 @@ AArch64InstPrinter::AArch64InstPrinter(const MCAsmInfo &MAI, const MCInstrInfo &MII, - const MCRegisterInfo &MRI) - : MCInstPrinter(MAI, MII, MRI) {} + const MCRegisterInfo &MCRI) + : MCInstPrinter(MAI, MII, MCRI) {} AArch64AppleInstPrinter::AArch64AppleInstPrinter(const MCAsmInfo &MAI, const MCInstrInfo &MII, - const MCRegisterInfo &MRI) - : AArch64InstPrinter(MAI, MII, MRI) {} + const MCRegisterInfo &MCRI) + : AArch64InstPrinter(MAI, MII, MCRI) {} bool AArch64InstPrinter::applyTargetSpecificCLOption(StringRef Opt) { if (Opt == "no-aliases") { @@ -841,9 +841,9 @@ unsigned Rm = MI->getOperand(2).getReg(); // "Rm" must be a 64-bit GPR for RPRFM. - if (MRI.getRegClass(AArch64::GPR32RegClassID).contains(Rm)) - Rm = MRI.getMatchingSuperReg(Rm, AArch64::sub_32, - &MRI.getRegClass(AArch64::GPR64RegClassID)); + if (MCRI.getRegClass(AArch64::GPR32RegClassID).contains(Rm)) + Rm = MCRI.getMatchingSuperReg(Rm, AArch64::sub_32, + &MCRI.getRegClass(AArch64::GPR64RegClassID)); unsigned SignExtend = MI->getOperand(3).getImm(); // encoded in "option<2>". unsigned Shift = MI->getOperand(4).getImm(); // encoded in "S". @@ -1593,8 +1593,8 @@ unsigned Sube = (size == 32) ? AArch64::sube32 : AArch64::sube64; unsigned Subo = (size == 32) ? AArch64::subo32 : AArch64::subo64; - unsigned Even = MRI.getSubReg(Reg, Sube); - unsigned Odd = MRI.getSubReg(Reg, Subo); + unsigned Even = MCRI.getSubReg(Reg, Sube); + unsigned Odd = MCRI.getSubReg(Reg, Subo); printRegName(O, Even); O << ", "; printRegName(O, Odd); @@ -1636,48 +1636,48 @@ // Work out how many registers there are in the list (if there is an actual // list). unsigned NumRegs = 1; - if (MRI.getRegClass(AArch64::DDRegClassID).contains(Reg) || - MRI.getRegClass(AArch64::ZPR2RegClassID).contains(Reg) || - MRI.getRegClass(AArch64::QQRegClassID).contains(Reg) || - MRI.getRegClass(AArch64::PPR2RegClassID).contains(Reg) || - MRI.getRegClass(AArch64::ZPR2StridedRegClassID).contains(Reg)) + if (MCRI.getRegClass(AArch64::DDRegClassID).contains(Reg) || + MCRI.getRegClass(AArch64::ZPR2RegClassID).contains(Reg) || + MCRI.getRegClass(AArch64::QQRegClassID).contains(Reg) || + MCRI.getRegClass(AArch64::PPR2RegClassID).contains(Reg) || + MCRI.getRegClass(AArch64::ZPR2StridedRegClassID).contains(Reg)) NumRegs = 2; - else if (MRI.getRegClass(AArch64::DDDRegClassID).contains(Reg) || - MRI.getRegClass(AArch64::ZPR3RegClassID).contains(Reg) || - MRI.getRegClass(AArch64::QQQRegClassID).contains(Reg)) + else if (MCRI.getRegClass(AArch64::DDDRegClassID).contains(Reg) || + MCRI.getRegClass(AArch64::ZPR3RegClassID).contains(Reg) || + MCRI.getRegClass(AArch64::QQQRegClassID).contains(Reg)) NumRegs = 3; - else if (MRI.getRegClass(AArch64::DDDDRegClassID).contains(Reg) || - MRI.getRegClass(AArch64::ZPR4RegClassID).contains(Reg) || - MRI.getRegClass(AArch64::QQQQRegClassID).contains(Reg) || - MRI.getRegClass(AArch64::ZPR4StridedRegClassID).contains(Reg)) + else if (MCRI.getRegClass(AArch64::DDDDRegClassID).contains(Reg) || + MCRI.getRegClass(AArch64::ZPR4RegClassID).contains(Reg) || + MCRI.getRegClass(AArch64::QQQQRegClassID).contains(Reg) || + MCRI.getRegClass(AArch64::ZPR4StridedRegClassID).contains(Reg)) NumRegs = 4; unsigned Stride = 1; - if (MRI.getRegClass(AArch64::ZPR2StridedRegClassID).contains(Reg)) + if (MCRI.getRegClass(AArch64::ZPR2StridedRegClassID).contains(Reg)) Stride = 8; - else if (MRI.getRegClass(AArch64::ZPR4StridedRegClassID).contains(Reg)) + else if (MCRI.getRegClass(AArch64::ZPR4StridedRegClassID).contains(Reg)) Stride = 4; // Now forget about the list and find out what the first register is. - if (unsigned FirstReg = MRI.getSubReg(Reg, AArch64::dsub0)) + if (unsigned FirstReg = MCRI.getSubReg(Reg, AArch64::dsub0)) Reg = FirstReg; - else if (unsigned FirstReg = MRI.getSubReg(Reg, AArch64::qsub0)) + else if (unsigned FirstReg = MCRI.getSubReg(Reg, AArch64::qsub0)) Reg = FirstReg; - else if (unsigned FirstReg = MRI.getSubReg(Reg, AArch64::zsub0)) + else if (unsigned FirstReg = MCRI.getSubReg(Reg, AArch64::zsub0)) Reg = FirstReg; - else if (unsigned FirstReg = MRI.getSubReg(Reg, AArch64::psub0)) + else if (unsigned FirstReg = MCRI.getSubReg(Reg, AArch64::psub0)) Reg = FirstReg; // If it's a D-reg, we need to promote it to the equivalent Q-reg before // printing (otherwise getRegisterName fails). - if (MRI.getRegClass(AArch64::FPR64RegClassID).contains(Reg)) { + if (MCRI.getRegClass(AArch64::FPR64RegClassID).contains(Reg)) { const MCRegisterClass &FPR128RC = - MRI.getRegClass(AArch64::FPR128RegClassID); - Reg = MRI.getMatchingSuperReg(Reg, AArch64::dsub, &FPR128RC); + MCRI.getRegClass(AArch64::FPR128RegClassID); + Reg = MCRI.getMatchingSuperReg(Reg, AArch64::dsub, &FPR128RC); } - if ((MRI.getRegClass(AArch64::ZPRRegClassID).contains(Reg) || - MRI.getRegClass(AArch64::PPRRegClassID).contains(Reg)) && + if ((MCRI.getRegClass(AArch64::ZPRRegClassID).contains(Reg) || + MCRI.getRegClass(AArch64::PPRRegClassID).contains(Reg)) && NumRegs > 1 && Stride == 1 && // Do not print the range when the last register is lower than the first. // Because it is a wrap-around register. @@ -1695,8 +1695,8 @@ for (unsigned i = 0; i < NumRegs; ++i, Reg = getNextVectorRegister(Reg, Stride)) { // wrap-around sve register - if (MRI.getRegClass(AArch64::ZPRRegClassID).contains(Reg) || - MRI.getRegClass(AArch64::PPRRegClassID).contains(Reg)) + if (MCRI.getRegClass(AArch64::ZPRRegClassID).contains(Reg) || + MCRI.getRegClass(AArch64::PPRRegClassID).contains(Reg)) printRegName(O, Reg); else printRegName(O, Reg, AArch64::vreg); @@ -2090,7 +2090,7 @@ const MCSubtargetInfo &STI, raw_ostream &O) { unsigned Reg = MI->getOperand(OpNum).getReg(); - printRegName(O, MRI.getSubReg(Reg, AArch64::x8sub_0)); + printRegName(O, MCRI.getSubReg(Reg, AArch64::x8sub_0)); } void AArch64InstPrinter::printSyspXzrPair(const MCInst *MI, unsigned OpNum, diff --git a/llvm/lib/Target/AArch64/MCTargetDesc/AArch64MCTargetDesc.h b/llvm/lib/Target/AArch64/MCTargetDesc/AArch64MCTargetDesc.h --- a/llvm/lib/Target/AArch64/MCTargetDesc/AArch64MCTargetDesc.h +++ b/llvm/lib/Target/AArch64/MCTargetDesc/AArch64MCTargetDesc.h @@ -39,11 +39,11 @@ MCContext &Ctx); MCAsmBackend *createAArch64leAsmBackend(const Target &T, const MCSubtargetInfo &STI, - const MCRegisterInfo &MRI, + const MCRegisterInfo &MCRI, const MCTargetOptions &Options); MCAsmBackend *createAArch64beAsmBackend(const Target &T, const MCSubtargetInfo &STI, - const MCRegisterInfo &MRI, + const MCRegisterInfo &MCRI, const MCTargetOptions &Options); std::unique_ptr @@ -62,7 +62,7 @@ bool isVerboseAsm); namespace AArch64_MC { -void initLLVMToCVRegMapping(MCRegisterInfo *MRI); +void initLLVMToCVRegMapping(MCRegisterInfo *MCRI); bool isQForm(const MCInst &MI, const MCInstrInfo *MCII); bool isFpOrNEON(const MCInst &MI, const MCInstrInfo *MCII); } diff --git a/llvm/lib/Target/AArch64/MCTargetDesc/AArch64MCTargetDesc.cpp b/llvm/lib/Target/AArch64/MCTargetDesc/AArch64MCTargetDesc.cpp --- a/llvm/lib/Target/AArch64/MCTargetDesc/AArch64MCTargetDesc.cpp +++ b/llvm/lib/Target/AArch64/MCTargetDesc/AArch64MCTargetDesc.cpp @@ -63,7 +63,7 @@ return createAArch64MCSubtargetInfoImpl(TT, CPU, /*TuneCPU*/ CPU, FS); } -void AArch64_MC::initLLVMToCVRegMapping(MCRegisterInfo *MRI) { +void AArch64_MC::initLLVMToCVRegMapping(MCRegisterInfo *MCRI) { // Mapping from CodeView to MC register id. static const struct { codeview::RegisterId CVReg; @@ -297,7 +297,7 @@ {codeview::RegisterId::ARM64_H31, AArch64::H31}, }; for (const auto &I : RegMap) - MRI->mapLLVMRegToCVReg(I.Reg, static_cast(I.CVReg)); + MCRI->mapLLVMRegToCVReg(I.Reg, static_cast(I.CVReg)); } bool AArch64_MC::isQForm(const MCInst &MI, const MCInstrInfo *MCII) { @@ -332,7 +332,7 @@ return X; } -static MCAsmInfo *createAArch64MCAsmInfo(const MCRegisterInfo &MRI, +static MCAsmInfo *createAArch64MCAsmInfo(const MCRegisterInfo &MCRI, const Triple &TheTriple, const MCTargetOptions &Options) { MCAsmInfo *MAI; @@ -348,7 +348,7 @@ } // Initial state of the frame pointer is SP. - unsigned Reg = MRI.getDwarfRegNum(AArch64::SP, true); + unsigned Reg = MCRI.getDwarfRegNum(AArch64::SP, true); MCCFIInstruction Inst = MCCFIInstruction::cfiDefCfa(nullptr, Reg, 0); MAI->addInitialFrameState(Inst); @@ -359,11 +359,11 @@ unsigned SyntaxVariant, const MCAsmInfo &MAI, const MCInstrInfo &MII, - const MCRegisterInfo &MRI) { + const MCRegisterInfo &MCRI) { if (SyntaxVariant == 0) - return new AArch64InstPrinter(MAI, MII, MRI); + return new AArch64InstPrinter(MAI, MII, MCRI); if (SyntaxVariant == 1) - return new AArch64AppleInstPrinter(MAI, MII, MRI); + return new AArch64AppleInstPrinter(MAI, MII, MCRI); return nullptr; } diff --git a/llvm/lib/Target/AMDGPU/AMDGPUTargetMachine.cpp b/llvm/lib/Target/AMDGPU/AMDGPUTargetMachine.cpp --- a/llvm/lib/Target/AMDGPU/AMDGPUTargetMachine.cpp +++ b/llvm/lib/Target/AMDGPU/AMDGPUTargetMachine.cpp @@ -543,9 +543,9 @@ initAsmInfo(); if (TT.getArch() == Triple::amdgcn) { if (getMCSubtargetInfo()->checkFeatures("+wavefrontsize64")) - MRI.reset(llvm::createGCNMCRegisterInfo(AMDGPUDwarfFlavour::Wave64)); + MCRI.reset(llvm::createGCNMCRegisterInfo(AMDGPUDwarfFlavour::Wave64)); else if (getMCSubtargetInfo()->checkFeatures("+wavefrontsize32")) - MRI.reset(llvm::createGCNMCRegisterInfo(AMDGPUDwarfFlavour::Wave32)); + MCRI.reset(llvm::createGCNMCRegisterInfo(AMDGPUDwarfFlavour::Wave32)); } } diff --git a/llvm/lib/Target/AMDGPU/AsmParser/AMDGPUAsmParser.cpp b/llvm/lib/Target/AMDGPU/AsmParser/AMDGPUAsmParser.cpp --- a/llvm/lib/Target/AMDGPU/AsmParser/AMDGPUAsmParser.cpp +++ b/llvm/lib/Target/AMDGPU/AsmParser/AMDGPUAsmParser.cpp @@ -1294,7 +1294,7 @@ bool ParseAMDKernelCodeTValue(StringRef ID, amd_kernel_code_t &Header); bool ParseDirectiveAMDKernelCodeT(); // TODO: Possibly make subtargetHasRegister const. - bool subtargetHasRegister(const MCRegisterInfo &MRI, unsigned RegNo); + bool subtargetHasRegister(const MCRegisterInfo &MCRI, unsigned RegNo); bool ParseDirectiveAMDGPUHsaKernel(); bool ParseDirectiveISAVersion(); @@ -1486,7 +1486,7 @@ return static_cast(TS); } - const MCRegisterInfo *getMRI() const { + const MCRegisterInfo *getMCRI() const { // We need this const_cast because for some reason getContext() is not const // in MCAsmParser. return const_cast(this)->getContext().getRegisterInfo(); @@ -2026,7 +2026,8 @@ } bool AMDGPUOperand::isRegClass(unsigned RCID) const { - return isRegKind() && AsmParser->getMRI()->getRegClass(RCID).contains(getReg()); + return isRegKind() && + AsmParser->getMCRI()->getRegClass(RCID).contains(getReg()); } bool AMDGPUOperand::isVRegWithInputMods() const { @@ -3620,7 +3621,7 @@ if ((DMaskIdx == -1 || TFEIdx == -1) && isGFX10_AEncoding()) // intersect_ray return true; - unsigned VDataSize = AMDGPU::getRegOperandSize(getMRI(), Desc, VDataIdx); + unsigned VDataSize = AMDGPU::getRegOperandSize(getMCRI(), Desc, VDataIdx); unsigned TFESize = (TFEIdx != -1 && Inst.getOperand(TFEIdx).getImm()) ? 1 : 0; unsigned DMask = Inst.getOperand(DMaskIdx).getImm() & 0xf; if (DMask == 0) @@ -3677,7 +3678,7 @@ bool IsNSA = SrsrcIdx - VAddr0Idx > 1; unsigned ActualAddrSize = IsNSA ? SrsrcIdx - VAddr0Idx - : AMDGPU::getRegOperandSize(getMRI(), Desc, VAddr0Idx) / 4; + : AMDGPU::getRegOperandSize(getMCRI(), Desc, VAddr0Idx) / 4; bool IsA16 = (A16Idx != -1 && Inst.getOperand(A16Idx).getImm()); unsigned ExpectedAddrSize = @@ -4260,7 +4261,7 @@ // DPP64 is supported for row_newbcast only. int Src0Idx = AMDGPU::getNamedOperandIdx(Opc, AMDGPU::OpName::src0); if (Src0Idx >= 0 && - getMRI()->getSubReg(Inst.getOperand(Src0Idx).getReg(), AMDGPU::sub1)) { + getMCRI()->getSubReg(Inst.getOperand(Src0Idx).getReg(), AMDGPU::sub1)) { SMLoc S = getImmLoc(AMDGPUOperand::ImmTyDppCtrl, Operands); Error(S, "64 bit dpp only supports row_newbcast"); return false; @@ -4333,7 +4334,7 @@ // Returns -1 if not a register, 0 if VGPR and 1 if AGPR. static int IsAGPROperand(const MCInst &Inst, uint16_t NameIdx, - const MCRegisterInfo *MRI) { + const MCRegisterInfo *MCRI) { int OpIdx = AMDGPU::getNamedOperandIdx(Inst.getOpcode(), NameIdx); if (OpIdx < 0) return -1; @@ -4342,9 +4343,9 @@ if (!Op.isReg()) return -1; - unsigned Sub = MRI->getSubReg(Op.getReg(), AMDGPU::sub0); + unsigned Sub = MCRI->getSubReg(Op.getReg(), AMDGPU::sub0); auto Reg = Sub ? Sub : Op.getReg(); - const MCRegisterClass &AGPR32 = MRI->getRegClass(AMDGPU::AGPR_32RegClassID); + const MCRegisterClass &AGPR32 = MCRI->getRegClass(AMDGPU::AGPR_32RegClassID); return AGPR32.contains(Reg) ? 1 : 0; } @@ -4358,12 +4359,12 @@ uint16_t DataNameIdx = (TSFlags & SIInstrFlags::DS) ? AMDGPU::OpName::data0 : AMDGPU::OpName::vdata; - const MCRegisterInfo *MRI = getMRI(); - int DstAreg = IsAGPROperand(Inst, AMDGPU::OpName::vdst, MRI); - int DataAreg = IsAGPROperand(Inst, DataNameIdx, MRI); + const MCRegisterInfo *MCRI = getMCRI(); + int DstAreg = IsAGPROperand(Inst, AMDGPU::OpName::vdst, MCRI); + int DataAreg = IsAGPROperand(Inst, DataNameIdx, MCRI); if ((TSFlags & SIInstrFlags::DS) && DataAreg >= 0) { - int Data2Areg = IsAGPROperand(Inst, AMDGPU::OpName::data1, MRI); + int Data2Areg = IsAGPROperand(Inst, AMDGPU::OpName::data1, MCRI); if (Data2Areg >= 0 && Data2Areg != DataAreg) return false; } @@ -4383,15 +4384,15 @@ if (!FB[AMDGPU::FeatureGFX90AInsts]) return true; - const MCRegisterInfo *MRI = getMRI(); - const MCRegisterClass &VGPR32 = MRI->getRegClass(AMDGPU::VGPR_32RegClassID); - const MCRegisterClass &AGPR32 = MRI->getRegClass(AMDGPU::AGPR_32RegClassID); + const MCRegisterInfo *MCRI = getMCRI(); + const MCRegisterClass &VGPR32 = MCRI->getRegClass(AMDGPU::VGPR_32RegClassID); + const MCRegisterClass &AGPR32 = MCRI->getRegClass(AMDGPU::AGPR_32RegClassID); for (unsigned I = 0, E = Inst.getNumOperands(); I != E; ++I) { const MCOperand &Op = Inst.getOperand(I); if (!Op.isReg()) continue; - unsigned Sub = MRI->getSubReg(Op.getReg(), AMDGPU::sub0); + unsigned Sub = MCRI->getSubReg(Op.getReg(), AMDGPU::sub0); if (!Sub) continue; @@ -4480,8 +4481,8 @@ Opc != AMDGPU::DS_GWS_SEMA_BR_vi) return true; - const MCRegisterInfo *MRI = getMRI(); - const MCRegisterClass &VGPR32 = MRI->getRegClass(AMDGPU::VGPR_32RegClassID); + const MCRegisterInfo *MCRI = getMCRI(); + const MCRegisterClass &VGPR32 = MCRI->getRegClass(AMDGPU::VGPR_32RegClassID); int Data0Pos = AMDGPU::getNamedOperandIdx(Inst.getOpcode(), AMDGPU::OpName::data0); assert(Data0Pos != -1); @@ -5696,14 +5697,14 @@ return true; } -bool AMDGPUAsmParser::subtargetHasRegister(const MCRegisterInfo &MRI, +bool AMDGPUAsmParser::subtargetHasRegister(const MCRegisterInfo &MCRI, unsigned RegNo) { - if (MRI.regsOverlap(AMDGPU::TTMP12_TTMP13_TTMP14_TTMP15, RegNo)) + if (MCRI.regsOverlap(AMDGPU::TTMP12_TTMP13_TTMP14_TTMP15, RegNo)) return isGFX9Plus(); // GFX10+ has 2 more SGPRs 104 and 105. - if (MRI.regsOverlap(AMDGPU::SGPR104_SGPR105, RegNo)) + if (MCRI.regsOverlap(AMDGPU::SGPR104_SGPR105, RegNo)) return hasSGPR104_SGPR105(); switch (RegNo) { @@ -5754,7 +5755,7 @@ // VI only has 102 SGPRs, so make sure we aren't trying to use the 2 more that // SI/CI have. - if (MRI.regsOverlap(AMDGPU::SGPR102_SGPR103, RegNo)) + if (MCRI.regsOverlap(AMDGPU::SGPR102_SGPR103, RegNo)) return hasSGPR102_SGPR103(); return true; diff --git a/llvm/lib/Target/AMDGPU/Disassembler/AMDGPUDisassembler.h b/llvm/lib/Target/AMDGPU/Disassembler/AMDGPUDisassembler.h --- a/llvm/lib/Target/AMDGPU/Disassembler/AMDGPUDisassembler.h +++ b/llvm/lib/Target/AMDGPU/Disassembler/AMDGPUDisassembler.h @@ -90,7 +90,7 @@ class AMDGPUDisassembler : public MCDisassembler { private: std::unique_ptr const MCII; - const MCRegisterInfo &MRI; + const MCRegisterInfo &MCRI; const unsigned TargetMaxInstBytes; mutable ArrayRef Bytes; mutable uint32_t Literal; diff --git a/llvm/lib/Target/AMDGPU/Disassembler/AMDGPUDisassembler.cpp b/llvm/lib/Target/AMDGPU/Disassembler/AMDGPUDisassembler.cpp --- a/llvm/lib/Target/AMDGPU/Disassembler/AMDGPUDisassembler.cpp +++ b/llvm/lib/Target/AMDGPU/Disassembler/AMDGPUDisassembler.cpp @@ -45,10 +45,9 @@ using DecodeStatus = llvm::MCDisassembler::DecodeStatus; AMDGPUDisassembler::AMDGPUDisassembler(const MCSubtargetInfo &STI, - MCContext &Ctx, - MCInstrInfo const *MCII) : - MCDisassembler(STI, Ctx), MCII(MCII), MRI(*Ctx.getRegisterInfo()), - TargetMaxInstBytes(Ctx.getAsmInfo()->getMaxInstLength(&STI)) { + MCContext &Ctx, MCInstrInfo const *MCII) + : MCDisassembler(STI, Ctx), MCII(MCII), MCRI(*Ctx.getRegisterInfo()), + TargetMaxInstBytes(Ctx.getAsmInfo()->getMaxInstLength(&STI)) { // ToDo: AMDGPUDisassembler supports only VI ISA. if (!STI.getFeatureBits()[AMDGPU::FeatureGCN3Encoding] && !isGFX10Plus()) @@ -299,7 +298,7 @@ } static bool IsAGPROperand(const MCInst &Inst, int OpIdx, - const MCRegisterInfo *MRI) { + const MCRegisterInfo *MCRI) { if (OpIdx < 0) return false; @@ -307,7 +306,7 @@ if (!Op.isReg()) return false; - unsigned Sub = MRI->getSubReg(Op.getReg(), AMDGPU::sub0); + unsigned Sub = MCRI->getSubReg(Op.getReg(), AMDGPU::sub0); auto Reg = Sub ? Sub : Op.getReg(); return Reg >= AMDGPU::AGPR0 && Reg <= AMDGPU::AGPR255; } @@ -328,18 +327,18 @@ uint64_t TSFlags = DAsm->getMCII()->get(Opc).TSFlags; uint16_t DataNameIdx = (TSFlags & SIInstrFlags::DS) ? AMDGPU::OpName::data0 : AMDGPU::OpName::vdata; - const MCRegisterInfo *MRI = DAsm->getContext().getRegisterInfo(); + const MCRegisterInfo *MCRI = DAsm->getContext().getRegisterInfo(); int DataIdx = AMDGPU::getNamedOperandIdx(Opc, DataNameIdx); if ((int)Inst.getNumOperands() == DataIdx) { int DstIdx = AMDGPU::getNamedOperandIdx(Opc, AMDGPU::OpName::vdst); - if (IsAGPROperand(Inst, DstIdx, MRI)) + if (IsAGPROperand(Inst, DstIdx, MCRI)) Imm |= 512; } if (TSFlags & SIInstrFlags::DS) { int Data2Idx = AMDGPU::getNamedOperandIdx(Opc, AMDGPU::OpName::data1); if ((int)Inst.getNumOperands() == Data2Idx && - IsAGPROperand(Inst, DataIdx, MRI)) + IsAGPROperand(Inst, DataIdx, MCRI)) Imm |= 512; } } @@ -960,11 +959,11 @@ // Get first subregister of VData unsigned Vdata0 = MI.getOperand(VDataIdx).getReg(); - unsigned VdataSub0 = MRI.getSubReg(Vdata0, AMDGPU::sub0); + unsigned VdataSub0 = MCRI.getSubReg(Vdata0, AMDGPU::sub0); Vdata0 = (VdataSub0 != 0)? VdataSub0 : Vdata0; - NewVdata = MRI.getMatchingSuperReg(Vdata0, AMDGPU::sub0, - &MRI.getRegClass(DataRCID)); + NewVdata = MCRI.getMatchingSuperReg(Vdata0, AMDGPU::sub0, + &MCRI.getRegClass(DataRCID)); if (NewVdata == AMDGPU::NoRegister) { // It's possible to encode this such that the low register + enabled // components exceeds the register count. @@ -976,12 +975,12 @@ unsigned NewVAddr0 = AMDGPU::NoRegister; if (isGFX10Plus() && !IsNSA && AddrSize != Info->VAddrDwords) { unsigned VAddr0 = MI.getOperand(VAddr0Idx).getReg(); - unsigned VAddrSub0 = MRI.getSubReg(VAddr0, AMDGPU::sub0); + unsigned VAddrSub0 = MCRI.getSubReg(VAddr0, AMDGPU::sub0); VAddr0 = (VAddrSub0 != 0) ? VAddrSub0 : VAddr0; auto AddrRCID = MCII->get(NewOpcode).operands()[VAddr0Idx].RegClass; - NewVAddr0 = MRI.getMatchingSuperReg(VAddr0, AMDGPU::sub0, - &MRI.getRegClass(AddrRCID)); + NewVAddr0 = MCRI.getMatchingSuperReg(VAddr0, AMDGPU::sub0, + &MCRI.getRegClass(AddrRCID)); if (NewVAddr0 == AMDGPU::NoRegister) return MCDisassembler::Success; } @@ -1690,7 +1689,7 @@ AMDGPU::getNamedOperandIdx(Inst.getOpcode(), AMDGPU::OpName::vdstX); assert(VDstXInd != -1); assert(Inst.getOperand(VDstXInd).isReg()); - unsigned XDstReg = MRI.getEncodingValue(Inst.getOperand(VDstXInd).getReg()); + unsigned XDstReg = MCRI.getEncodingValue(Inst.getOperand(VDstXInd).getReg()); Val |= ~XDstReg & 1; auto Width = llvm::AMDGPUDisassembler::OPW32; return createRegOperand(getVgprClassId(Width), Val); diff --git a/llvm/lib/Target/AMDGPU/MCTargetDesc/AMDGPUAsmBackend.cpp b/llvm/lib/Target/AMDGPU/MCTargetDesc/AMDGPUAsmBackend.cpp --- a/llvm/lib/Target/AMDGPU/MCTargetDesc/AMDGPUAsmBackend.cpp +++ b/llvm/lib/Target/AMDGPU/MCTargetDesc/AMDGPUAsmBackend.cpp @@ -261,7 +261,7 @@ MCAsmBackend *llvm::createAMDGPUAsmBackend(const Target &T, const MCSubtargetInfo &STI, - const MCRegisterInfo &MRI, + const MCRegisterInfo &MCRI, const MCTargetOptions &Options) { return new ELFAMDGPUAsmBackend(T, STI.getTargetTriple(), getHsaAbiVersion(&STI).value_or(0)); diff --git a/llvm/lib/Target/AMDGPU/MCTargetDesc/AMDGPUInstPrinter.h b/llvm/lib/Target/AMDGPU/MCTargetDesc/AMDGPUInstPrinter.h --- a/llvm/lib/Target/AMDGPU/MCTargetDesc/AMDGPUInstPrinter.h +++ b/llvm/lib/Target/AMDGPU/MCTargetDesc/AMDGPUInstPrinter.h @@ -19,9 +19,9 @@ class AMDGPUInstPrinter : public MCInstPrinter { public: - AMDGPUInstPrinter(const MCAsmInfo &MAI, - const MCInstrInfo &MII, const MCRegisterInfo &MRI) - : MCInstPrinter(MAI, MII, MRI) {} + AMDGPUInstPrinter(const MCAsmInfo &MAI, const MCInstrInfo &MII, + const MCRegisterInfo &MCRI) + : MCInstPrinter(MAI, MII, MCRI) {} // Autogenerated by tblgen std::pair getMnemonic(const MCInst *MI) override; @@ -33,7 +33,7 @@ void printInst(const MCInst *MI, uint64_t Address, StringRef Annot, const MCSubtargetInfo &STI, raw_ostream &O) override; static void printRegOperand(unsigned RegNo, raw_ostream &O, - const MCRegisterInfo &MRI); + const MCRegisterInfo &MCRI); private: void printU4ImmOperand(const MCInst *MI, unsigned OpNo, diff --git a/llvm/lib/Target/AMDGPU/MCTargetDesc/AMDGPUInstPrinter.cpp b/llvm/lib/Target/AMDGPU/MCTargetDesc/AMDGPUInstPrinter.cpp --- a/llvm/lib/Target/AMDGPU/MCTargetDesc/AMDGPUInstPrinter.cpp +++ b/llvm/lib/Target/AMDGPU/MCTargetDesc/AMDGPUInstPrinter.cpp @@ -340,7 +340,7 @@ } void AMDGPUInstPrinter::printRegOperand(unsigned RegNo, raw_ostream &O, - const MCRegisterInfo &MRI) { + const MCRegisterInfo &MCRI) { #if !defined(NDEBUG) switch (RegNo) { case AMDGPU::FP_REG: @@ -600,7 +600,7 @@ printRegOperand(STI.getFeatureBits()[AMDGPU::FeatureWavefrontSize64] ? AMDGPU::VCC : AMDGPU::VCC_LO, - O, MRI); + O, MCRI); if (FirstOperand) O << ", "; } @@ -666,17 +666,17 @@ const MCOperand &Op = MI->getOperand(OpNo); if (Op.isReg()) { - printRegOperand(Op.getReg(), O, MRI); + printRegOperand(Op.getReg(), O, MCRI); // Check if operand register class contains register used. // Intention: print disassembler message when invalid code is decoded, // for example sgpr register used in VReg or VISrc(VReg or imm) operand. int RCID = Desc.operands()[OpNo].RegClass; if (RCID != -1) { - const MCRegisterClass RC = MRI.getRegClass(RCID); + const MCRegisterClass RC = MCRI.getRegClass(RCID); auto Reg = mc2PseudoReg(Op.getReg()); if (!RC.contains(Reg) && !isInlineValue(Reg)) { - O << "/*Invalid register, operand has \'" << MRI.getRegClassName(&RC) + O << "/*Invalid register, operand has \'" << MCRI.getRegClassName(&RC) << "\' register class*/"; } } @@ -759,7 +759,7 @@ else { const MCInstrDesc &Desc = MII.get(MI->getOpcode()); int RCID = Desc.operands()[OpNo].RegClass; - unsigned RCBits = AMDGPU::getRegBitWidth(MRI.getRegClass(RCID)); + unsigned RCBits = AMDGPU::getRegBitWidth(MCRI.getRegClass(RCID)); if (RCBits == 32) printImmediate32(FloatToBits(Value), STI, O); else if (RCBits == 64) @@ -1112,7 +1112,7 @@ OpNo = OpNo - N + N / 2; if (En & (1 << N)) - printRegOperand(MI->getOperand(OpNo).getReg(), O, MRI); + printRegOperand(MI->getOperand(OpNo).getReg(), O, MCRI); else O << "off"; } diff --git a/llvm/lib/Target/AMDGPU/MCTargetDesc/AMDGPUMCTargetDesc.h b/llvm/lib/Target/AMDGPU/MCTargetDesc/AMDGPUMCTargetDesc.h --- a/llvm/lib/Target/AMDGPU/MCTargetDesc/AMDGPUMCTargetDesc.h +++ b/llvm/lib/Target/AMDGPU/MCTargetDesc/AMDGPUMCTargetDesc.h @@ -37,7 +37,7 @@ MCAsmBackend *createAMDGPUAsmBackend(const Target &T, const MCSubtargetInfo &STI, - const MCRegisterInfo &MRI, + const MCRegisterInfo &MCRI, const MCTargetOptions &Options); std::unique_ptr diff --git a/llvm/lib/Target/AMDGPU/MCTargetDesc/AMDGPUMCTargetDesc.cpp b/llvm/lib/Target/AMDGPU/MCTargetDesc/AMDGPUMCTargetDesc.cpp --- a/llvm/lib/Target/AMDGPU/MCTargetDesc/AMDGPUMCTargetDesc.cpp +++ b/llvm/lib/Target/AMDGPU/MCTargetDesc/AMDGPUMCTargetDesc.cpp @@ -85,11 +85,11 @@ unsigned SyntaxVariant, const MCAsmInfo &MAI, const MCInstrInfo &MII, - const MCRegisterInfo &MRI) { + const MCRegisterInfo &MCRI) { if (T.getArch() == Triple::r600) - return new R600InstPrinter(MAI, MII, MRI); + return new R600InstPrinter(MAI, MII, MCRI); else - return new AMDGPUInstPrinter(MAI, MII, MRI); + return new AMDGPUInstPrinter(MAI, MII, MCRI); } static MCTargetStreamer *createAMDGPUAsmTargetStreamer(MCStreamer &S, diff --git a/llvm/lib/Target/AMDGPU/MCTargetDesc/R600InstPrinter.h b/llvm/lib/Target/AMDGPU/MCTargetDesc/R600InstPrinter.h --- a/llvm/lib/Target/AMDGPU/MCTargetDesc/R600InstPrinter.h +++ b/llvm/lib/Target/AMDGPU/MCTargetDesc/R600InstPrinter.h @@ -16,8 +16,8 @@ class R600InstPrinter : public MCInstPrinter { public: R600InstPrinter(const MCAsmInfo &MAI, const MCInstrInfo &MII, - const MCRegisterInfo &MRI) - : MCInstPrinter(MAI, MII, MRI) {} + const MCRegisterInfo &MCRI) + : MCInstPrinter(MAI, MII, MCRI) {} void printInst(const MCInst *MI, uint64_t Address, StringRef Annot, const MCSubtargetInfo &STI, raw_ostream &O) override; diff --git a/llvm/lib/Target/AMDGPU/MCTargetDesc/R600MCCodeEmitter.cpp b/llvm/lib/Target/AMDGPU/MCTargetDesc/R600MCCodeEmitter.cpp --- a/llvm/lib/Target/AMDGPU/MCTargetDesc/R600MCCodeEmitter.cpp +++ b/llvm/lib/Target/AMDGPU/MCTargetDesc/R600MCCodeEmitter.cpp @@ -29,12 +29,12 @@ namespace { class R600MCCodeEmitter : public MCCodeEmitter { - const MCRegisterInfo &MRI; + const MCRegisterInfo &MCRI; const MCInstrInfo &MCII; public: R600MCCodeEmitter(const MCInstrInfo &mcii, const MCRegisterInfo &mri) - : MRI(mri), MCII(mcii) {} + : MCRI(mri), MCII(mcii) {} R600MCCodeEmitter(const R600MCCodeEmitter &) = delete; R600MCCodeEmitter &operator=(const R600MCCodeEmitter &) = delete; @@ -150,7 +150,7 @@ } unsigned R600MCCodeEmitter::getHWReg(unsigned RegNo) const { - return MRI.getEncodingValue(RegNo) & HW_REG_MASK; + return MCRI.getEncodingValue(RegNo) & HW_REG_MASK; } uint64_t R600MCCodeEmitter::getMachineOpValue(const MCInst &MI, @@ -159,7 +159,7 @@ const MCSubtargetInfo &STI) const { if (MO.isReg()) { if (HAS_NATIVE_OPERANDS(MCII.get(MI.getOpcode()).TSFlags)) - return MRI.getEncodingValue(MO.getReg()); + return MCRI.getEncodingValue(MO.getReg()); return getHWReg(MO.getReg()); } diff --git a/llvm/lib/Target/AMDGPU/MCTargetDesc/SIMCCodeEmitter.cpp b/llvm/lib/Target/AMDGPU/MCTargetDesc/SIMCCodeEmitter.cpp --- a/llvm/lib/Target/AMDGPU/MCTargetDesc/SIMCCodeEmitter.cpp +++ b/llvm/lib/Target/AMDGPU/MCTargetDesc/SIMCCodeEmitter.cpp @@ -33,7 +33,7 @@ namespace { class SIMCCodeEmitter : public AMDGPUMCCodeEmitter { - const MCRegisterInfo &MRI; + const MCRegisterInfo &MCRI; /// Encode an fp or int literal std::optional getLitEncoding(const MCOperand &MO, @@ -42,7 +42,7 @@ public: SIMCCodeEmitter(const MCInstrInfo &mcii, MCContext &ctx) - : AMDGPUMCCodeEmitter(mcii), MRI(*ctx.getRegisterInfo()) {} + : AMDGPUMCCodeEmitter(mcii), MCRI(*ctx.getRegisterInfo()) {} SIMCCodeEmitter(const SIMCCodeEmitter &) = delete; SIMCCodeEmitter &operator=(const SIMCCodeEmitter &) = delete; @@ -341,7 +341,7 @@ // However, dst is encoded as EXEC for compatibility with SP3. if (AMDGPU::isGFX10Plus(STI) && isVCMPX64(Desc)) { assert((Encoding & 0xFF) == 0); - Encoding |= MRI.getEncodingValue(AMDGPU::EXEC_LO); + Encoding |= MCRI.getEncodingValue(AMDGPU::EXEC_LO); } for (unsigned i = 0; i < bytes; i++) { @@ -447,9 +447,9 @@ if (MO.isReg()) { unsigned Reg = MO.getReg(); - RegEnc |= MRI.getEncodingValue(Reg); + RegEnc |= MCRI.getEncodingValue(Reg); RegEnc &= SDWA9EncValues::SRC_VGPR_MASK; - if (AMDGPU::isSGPR(AMDGPU::mc2PseudoReg(Reg), &MRI)) { + if (AMDGPU::isSGPR(AMDGPU::mc2PseudoReg(Reg), &MCRI)) { RegEnc |= SDWA9EncValues::SRC_SGPR_MASK; } Op = RegEnc; @@ -478,7 +478,7 @@ unsigned Reg = MO.getReg(); if (Reg != AMDGPU::VCC && Reg != AMDGPU::VCC_LO) { - RegEnc |= MRI.getEncodingValue(Reg); + RegEnc |= MCRI.getEncodingValue(Reg); RegEnc &= SDWA9EncValues::VOPC_DST_SGPR_MASK; RegEnc |= SDWA9EncValues::VOPC_DST_VCC_MASK; } @@ -490,25 +490,25 @@ SmallVectorImpl &Fixups, const MCSubtargetInfo &STI) const { unsigned Reg = MI.getOperand(OpNo).getReg(); - uint64_t Enc = MRI.getEncodingValue(Reg); + uint64_t Enc = MCRI.getEncodingValue(Reg); // VGPR and AGPR have the same encoding, but SrcA and SrcB operands of mfma // instructions use acc[0:1] modifier bits to distinguish. These bits are // encoded as a virtual 9th bit of the register for these operands. - if (MRI.getRegClass(AMDGPU::AGPR_32RegClassID).contains(Reg) || - MRI.getRegClass(AMDGPU::AReg_64RegClassID).contains(Reg) || - MRI.getRegClass(AMDGPU::AReg_96RegClassID).contains(Reg) || - MRI.getRegClass(AMDGPU::AReg_128RegClassID).contains(Reg) || - MRI.getRegClass(AMDGPU::AReg_160RegClassID).contains(Reg) || - MRI.getRegClass(AMDGPU::AReg_192RegClassID).contains(Reg) || - MRI.getRegClass(AMDGPU::AReg_224RegClassID).contains(Reg) || - MRI.getRegClass(AMDGPU::AReg_256RegClassID).contains(Reg) || - MRI.getRegClass(AMDGPU::AReg_288RegClassID).contains(Reg) || - MRI.getRegClass(AMDGPU::AReg_320RegClassID).contains(Reg) || - MRI.getRegClass(AMDGPU::AReg_352RegClassID).contains(Reg) || - MRI.getRegClass(AMDGPU::AReg_384RegClassID).contains(Reg) || - MRI.getRegClass(AMDGPU::AReg_512RegClassID).contains(Reg) || - MRI.getRegClass(AMDGPU::AGPR_LO16RegClassID).contains(Reg)) + if (MCRI.getRegClass(AMDGPU::AGPR_32RegClassID).contains(Reg) || + MCRI.getRegClass(AMDGPU::AReg_64RegClassID).contains(Reg) || + MCRI.getRegClass(AMDGPU::AReg_96RegClassID).contains(Reg) || + MCRI.getRegClass(AMDGPU::AReg_128RegClassID).contains(Reg) || + MCRI.getRegClass(AMDGPU::AReg_160RegClassID).contains(Reg) || + MCRI.getRegClass(AMDGPU::AReg_192RegClassID).contains(Reg) || + MCRI.getRegClass(AMDGPU::AReg_224RegClassID).contains(Reg) || + MCRI.getRegClass(AMDGPU::AReg_256RegClassID).contains(Reg) || + MCRI.getRegClass(AMDGPU::AReg_288RegClassID).contains(Reg) || + MCRI.getRegClass(AMDGPU::AReg_320RegClassID).contains(Reg) || + MCRI.getRegClass(AMDGPU::AReg_352RegClassID).contains(Reg) || + MCRI.getRegClass(AMDGPU::AReg_384RegClassID).contains(Reg) || + MCRI.getRegClass(AMDGPU::AReg_512RegClassID).contains(Reg) || + MCRI.getRegClass(AMDGPU::AGPR_LO16RegClassID).contains(Reg)) Enc |= 512; Op = Enc; @@ -542,7 +542,7 @@ SmallVectorImpl &Fixups, const MCSubtargetInfo &STI) const { if (MO.isReg()){ - Op = MRI.getEncodingValue(MO.getReg()); + Op = MCRI.getEncodingValue(MO.getReg()); return; } unsigned OpNo = &MO - MI.begin(); diff --git a/llvm/lib/Target/AMDGPU/Utils/AMDGPUBaseInfo.h b/llvm/lib/Target/AMDGPU/Utils/AMDGPUBaseInfo.h --- a/llvm/lib/Target/AMDGPU/Utils/AMDGPUBaseInfo.h +++ b/llvm/lib/Target/AMDGPU/Utils/AMDGPUBaseInfo.h @@ -1159,7 +1159,7 @@ unsigned getRegBitWidth(const MCRegisterClass &RC); /// Get size of register operand -unsigned getRegOperandSize(const MCRegisterInfo *MRI, const MCInstrDesc &Desc, +unsigned getRegOperandSize(const MCRegisterInfo *MCRI, const MCInstrDesc &Desc, unsigned OpNo); LLVM_READNONE diff --git a/llvm/lib/Target/AMDGPU/Utils/AMDGPUBaseInfo.cpp b/llvm/lib/Target/AMDGPU/Utils/AMDGPUBaseInfo.cpp --- a/llvm/lib/Target/AMDGPU/Utils/AMDGPUBaseInfo.cpp +++ b/llvm/lib/Target/AMDGPU/Utils/AMDGPUBaseInfo.cpp @@ -2328,11 +2328,11 @@ return getRegBitWidth(RC.getID()); } -unsigned getRegOperandSize(const MCRegisterInfo *MRI, const MCInstrDesc &Desc, +unsigned getRegOperandSize(const MCRegisterInfo *MCRI, const MCInstrDesc &Desc, unsigned OpNo) { assert(OpNo < Desc.NumOperands); unsigned RCID = Desc.operands()[OpNo].RegClass; - return getRegBitWidth(MRI->getRegClass(RCID)) / 8; + return getRegBitWidth(MCRI->getRegClass(RCID)) / 8; } bool isInlinableLiteral64(int64_t Literal, bool HasInv2Pi) { diff --git a/llvm/lib/Target/ARC/ARCFrameLowering.cpp b/llvm/lib/Target/ARC/ARCFrameLowering.cpp --- a/llvm/lib/Target/ARC/ARCFrameLowering.cpp +++ b/llvm/lib/Target/ARC/ARCFrameLowering.cpp @@ -118,7 +118,7 @@ auto *AFI = MF.getInfo(); MachineModuleInfo &MMI = MF.getMMI(); MCContext &Context = MMI.getContext(); - const MCRegisterInfo *MRI = Context.getRegisterInfo(); + const MCRegisterInfo *MCRI = Context.getRegisterInfo(); const ARCInstrInfo *TII = MF.getSubtarget().getInstrInfo(); MachineBasicBlock::iterator MBBI = MBB.begin(); // Debug location must be unknown since the first debug location is used @@ -204,7 +204,7 @@ int CurOffset = -4; if (hasFP(MF)) { CFIIndex = MF.addFrameInst(MCCFIInstruction::createOffset( - nullptr, MRI->getDwarfRegNum(ARC::FP, true), CurOffset)); + nullptr, MCRI->getDwarfRegNum(ARC::FP, true), CurOffset)); BuildMI(MBB, MBBI, dl, TII->get(TargetOpcode::CFI_INSTRUCTION)) .addCFIIndex(CFIIndex) .setMIFlags(MachineInstr::FrameSetup); @@ -213,7 +213,7 @@ if (MFI.hasCalls()) { CFIIndex = MF.addFrameInst(MCCFIInstruction::createOffset( - nullptr, MRI->getDwarfRegNum(ARC::BLINK, true), CurOffset)); + nullptr, MCRI->getDwarfRegNum(ARC::BLINK, true), CurOffset)); BuildMI(MBB, MBBI, dl, TII->get(TargetOpcode::CFI_INSTRUCTION)) .addCFIIndex(CFIIndex) .setMIFlags(MachineInstr::FrameSetup); @@ -226,7 +226,7 @@ if ((hasFP(MF) && Reg == ARC::FP) || (MFI.hasCalls() && Reg == ARC::BLINK)) continue; CFIIndex = MF.addFrameInst(MCCFIInstruction::createOffset( - nullptr, MRI->getDwarfRegNum(Reg, true), MFI.getObjectOffset(FI))); + nullptr, MCRI->getDwarfRegNum(Reg, true), MFI.getObjectOffset(FI))); BuildMI(MBB, MBBI, dl, TII->get(TargetOpcode::CFI_INSTRUCTION)) .addCFIIndex(CFIIndex) .setMIFlags(MachineInstr::FrameSetup); diff --git a/llvm/lib/Target/ARC/MCTargetDesc/ARCInstPrinter.h b/llvm/lib/Target/ARC/MCTargetDesc/ARCInstPrinter.h --- a/llvm/lib/Target/ARC/MCTargetDesc/ARCInstPrinter.h +++ b/llvm/lib/Target/ARC/MCTargetDesc/ARCInstPrinter.h @@ -22,8 +22,8 @@ class ARCInstPrinter : public MCInstPrinter { public: ARCInstPrinter(const MCAsmInfo &MAI, const MCInstrInfo &MII, - const MCRegisterInfo &MRI) - : MCInstPrinter(MAI, MII, MRI) {} + const MCRegisterInfo &MCRI) + : MCInstPrinter(MAI, MII, MCRI) {} // Autogenerated by tblgen. std::pair getMnemonic(const MCInst *MI) override; diff --git a/llvm/lib/Target/ARC/MCTargetDesc/ARCMCTargetDesc.cpp b/llvm/lib/Target/ARC/MCTargetDesc/ARCMCTargetDesc.cpp --- a/llvm/lib/Target/ARC/MCTargetDesc/ARCMCTargetDesc.cpp +++ b/llvm/lib/Target/ARC/MCTargetDesc/ARCMCTargetDesc.cpp @@ -52,7 +52,7 @@ return createARCMCSubtargetInfoImpl(TT, CPU, /*TuneCPU=*/CPU, FS); } -static MCAsmInfo *createARCMCAsmInfo(const MCRegisterInfo &MRI, +static MCAsmInfo *createARCMCAsmInfo(const MCRegisterInfo &MCRI, const Triple &TT, const MCTargetOptions &Options) { MCAsmInfo *MAI = new ARCMCAsmInfo(TT); @@ -68,8 +68,8 @@ unsigned SyntaxVariant, const MCAsmInfo &MAI, const MCInstrInfo &MII, - const MCRegisterInfo &MRI) { - return new ARCInstPrinter(MAI, MII, MRI); + const MCRegisterInfo &MCRI) { + return new ARCInstPrinter(MAI, MII, MCRI); } ARCTargetStreamer::ARCTargetStreamer(MCStreamer &S) : MCTargetStreamer(S) {} diff --git a/llvm/lib/Target/ARM/ARMBaseInstrInfo.cpp b/llvm/lib/Target/ARM/ARMBaseInstrInfo.cpp --- a/llvm/lib/Target/ARM/ARMBaseInstrInfo.cpp +++ b/llvm/lib/Target/ARM/ARMBaseInstrInfo.cpp @@ -6497,8 +6497,8 @@ // Add a CFI saying that the LR that we want to find is now higher than // before. int LROffset = Auth ? Align - 4 : Align; - const MCRegisterInfo *MRI = Subtarget.getRegisterInfo(); - unsigned DwarfLR = MRI->getDwarfRegNum(ARM::LR, true); + const MCRegisterInfo *MCRI = Subtarget.getRegisterInfo(); + unsigned DwarfLR = MCRI->getDwarfRegNum(ARM::LR, true); int64_t LRPosEntry = MF.addFrameInst( MCCFIInstruction::createOffset(nullptr, DwarfLR, -LROffset)); BuildMI(MBB, It, DebugLoc(), get(ARM::CFI_INSTRUCTION)) @@ -6506,7 +6506,7 @@ .setMIFlags(MachineInstr::FrameSetup); if (Auth) { // Add a CFI for the location of the return adddress PAC. - unsigned DwarfRAC = MRI->getDwarfRegNum(ARM::RA_AUTH_CODE, true); + unsigned DwarfRAC = MCRI->getDwarfRegNum(ARM::RA_AUTH_CODE, true); int64_t RACPosEntry = MF.addFrameInst( MCCFIInstruction::createOffset(nullptr, DwarfRAC, -Align)); BuildMI(MBB, It, DebugLoc(), get(ARM::CFI_INSTRUCTION)) @@ -6519,9 +6519,9 @@ MachineBasicBlock::iterator It, Register Reg) const { MachineFunction &MF = *MBB.getParent(); - const MCRegisterInfo *MRI = Subtarget.getRegisterInfo(); - unsigned DwarfLR = MRI->getDwarfRegNum(ARM::LR, true); - unsigned DwarfReg = MRI->getDwarfRegNum(Reg, true); + const MCRegisterInfo *MCRI = Subtarget.getRegisterInfo(); + unsigned DwarfLR = MCRI->getDwarfRegNum(ARM::LR, true); + unsigned DwarfReg = MCRI->getDwarfRegNum(Reg, true); int64_t LRPosEntry = MF.addFrameInst( MCCFIInstruction::createRegister(nullptr, DwarfLR, DwarfReg)); @@ -6561,8 +6561,8 @@ if (CFI) { // Now stack has moved back up... MachineFunction &MF = *MBB.getParent(); - const MCRegisterInfo *MRI = Subtarget.getRegisterInfo(); - unsigned DwarfLR = MRI->getDwarfRegNum(ARM::LR, true); + const MCRegisterInfo *MCRI = Subtarget.getRegisterInfo(); + unsigned DwarfLR = MCRI->getDwarfRegNum(ARM::LR, true); int64_t StackPosEntry = MF.addFrameInst(MCCFIInstruction::cfiDefCfaOffset(nullptr, 0)); BuildMI(MBB, It, DebugLoc(), get(ARM::CFI_INSTRUCTION)) @@ -6577,7 +6577,7 @@ .setMIFlags(MachineInstr::FrameDestroy); if (Auth) { - unsigned DwarfRAC = MRI->getDwarfRegNum(ARM::RA_AUTH_CODE, true); + unsigned DwarfRAC = MCRI->getDwarfRegNum(ARM::RA_AUTH_CODE, true); int64_t Entry = MF.addFrameInst(MCCFIInstruction::createUndefined(nullptr, DwarfRAC)); BuildMI(MBB, It, DebugLoc(), get(ARM::CFI_INSTRUCTION)) @@ -6593,8 +6593,8 @@ void ARMBaseInstrInfo::emitCFIForLRRestoreFromReg( MachineBasicBlock &MBB, MachineBasicBlock::iterator It) const { MachineFunction &MF = *MBB.getParent(); - const MCRegisterInfo *MRI = Subtarget.getRegisterInfo(); - unsigned DwarfLR = MRI->getDwarfRegNum(ARM::LR, true); + const MCRegisterInfo *MCRI = Subtarget.getRegisterInfo(); + unsigned DwarfLR = MCRI->getDwarfRegNum(ARM::LR, true); int64_t LRPosEntry = MF.addFrameInst(MCCFIInstruction::createRestore(nullptr, DwarfLR)); diff --git a/llvm/lib/Target/ARM/ARMFrameLowering.cpp b/llvm/lib/Target/ARM/ARMFrameLowering.cpp --- a/llvm/lib/Target/ARM/ARMFrameLowering.cpp +++ b/llvm/lib/Target/ARM/ARMFrameLowering.cpp @@ -709,7 +709,7 @@ MachineModuleInfo &MMI = MF.getMMI(); MCContext &Context = MMI.getContext(); const TargetMachine &TM = MF.getTarget(); - const MCRegisterInfo *MRI = Context.getRegisterInfo(); + const MCRegisterInfo *MCRI = Context.getRegisterInfo(); const ARMBaseRegisterInfo *RegInfo = STI.getRegisterInfo(); const ARMBaseInstrInfo &TII = *STI.getInstrInfo(); assert(!AFI->isThumb1OnlyFunction() && @@ -1059,7 +1059,7 @@ if (!NeedsWinCFI) { if (FramePtrOffsetInPush + PushSize != 0) { unsigned CFIIndex = MF.addFrameInst(MCCFIInstruction::cfiDefCfa( - nullptr, MRI->getDwarfRegNum(FramePtr, true), + nullptr, MCRI->getDwarfRegNum(FramePtr, true), FPCXTSaveSize + ArgRegsSaveSize - FramePtrOffsetInPush)); BuildMI(MBB, AfterPush, dl, TII.get(TargetOpcode::CFI_INSTRUCTION)) .addCFIIndex(CFIIndex) @@ -1067,7 +1067,7 @@ } else { unsigned CFIIndex = MF.addFrameInst(MCCFIInstruction::createDefCfaRegister( - nullptr, MRI->getDwarfRegNum(FramePtr, true))); + nullptr, MCRI->getDwarfRegNum(FramePtr, true))); BuildMI(MBB, AfterPush, dl, TII.get(TargetOpcode::CFI_INSTRUCTION)) .addCFIIndex(CFIIndex) .setMIFlags(MachineInstr::FrameSetup); @@ -1115,7 +1115,7 @@ case ARM::R7: case ARM::LR: CFIIndex = MF.addFrameInst(MCCFIInstruction::createOffset( - nullptr, MRI->getDwarfRegNum(Reg, true), MFI.getObjectOffset(FI))); + nullptr, MCRI->getDwarfRegNum(Reg, true), MFI.getObjectOffset(FI))); BuildMI(MBB, Pos, dl, TII.get(TargetOpcode::CFI_INSTRUCTION)) .addCFIIndex(CFIIndex) .setMIFlags(MachineInstr::FrameSetup); @@ -1136,7 +1136,7 @@ case ARM::R11: case ARM::R12: if (STI.splitFramePushPop(MF)) { - unsigned DwarfReg = MRI->getDwarfRegNum( + unsigned DwarfReg = MCRI->getDwarfRegNum( Reg == ARM::R12 ? ARM::RA_AUTH_CODE : Reg, true); unsigned Offset = MFI.getObjectOffset(FI); unsigned CFIIndex = MF.addFrameInst( @@ -1159,7 +1159,7 @@ int FI = Entry.getFrameIdx(); if ((Reg >= ARM::D0 && Reg <= ARM::D31) && (Reg < ARM::D8 || Reg >= ARM::D8 + AFI->getNumAlignedDPRCS2Regs())) { - unsigned DwarfReg = MRI->getDwarfRegNum(Reg, true); + unsigned DwarfReg = MCRI->getDwarfRegNum(Reg, true); unsigned Offset = MFI.getObjectOffset(FI); unsigned CFIIndex = MF.addFrameInst( MCCFIInstruction::createOffset(nullptr, DwarfReg, Offset)); @@ -2924,7 +2924,7 @@ MachineFrameInfo &MFI = MF.getFrameInfo(); MachineModuleInfo &MMI = MF.getMMI(); MCContext &Context = MMI.getContext(); - const MCRegisterInfo *MRI = Context.getRegisterInfo(); + const MCRegisterInfo *MCRI = Context.getRegisterInfo(); const ARMBaseInstrInfo &TII = *static_cast(MF.getSubtarget().getInstrInfo()); ARMFunctionInfo *ARMFI = MF.getInfo(); @@ -3026,11 +3026,11 @@ BuildMI(PrevStackMBB, DL, TII.get(TargetOpcode::CFI_INSTRUCTION)) .addCFIIndex(CFIIndex); CFIIndex = MF.addFrameInst(MCCFIInstruction::createOffset( - nullptr, MRI->getDwarfRegNum(ScratchReg1, true), -4)); + nullptr, MCRI->getDwarfRegNum(ScratchReg1, true), -4)); BuildMI(PrevStackMBB, DL, TII.get(TargetOpcode::CFI_INSTRUCTION)) .addCFIIndex(CFIIndex); CFIIndex = MF.addFrameInst(MCCFIInstruction::createOffset( - nullptr, MRI->getDwarfRegNum(ScratchReg0, true), -8)); + nullptr, MCRI->getDwarfRegNum(ScratchReg0, true), -8)); BuildMI(PrevStackMBB, DL, TII.get(TargetOpcode::CFI_INSTRUCTION)) .addCFIIndex(CFIIndex); } @@ -3240,7 +3240,7 @@ BuildMI(AllocMBB, DL, TII.get(TargetOpcode::CFI_INSTRUCTION)) .addCFIIndex(CFIIndex); CFIIndex = MF.addFrameInst(MCCFIInstruction::createOffset( - nullptr, MRI->getDwarfRegNum(ARM::LR, true), -12)); + nullptr, MCRI->getDwarfRegNum(ARM::LR, true), -12)); BuildMI(AllocMBB, DL, TII.get(TargetOpcode::CFI_INSTRUCTION)) .addCFIIndex(CFIIndex); } @@ -3333,11 +3333,11 @@ // Tell debuggers that r4 and r5 are now the same as they were in the // previous function, that they're the "Same Value". CFIIndex = MF.addFrameInst(MCCFIInstruction::createSameValue( - nullptr, MRI->getDwarfRegNum(ScratchReg0, true))); + nullptr, MCRI->getDwarfRegNum(ScratchReg0, true))); BuildMI(PostStackMBB, DL, TII.get(TargetOpcode::CFI_INSTRUCTION)) .addCFIIndex(CFIIndex); CFIIndex = MF.addFrameInst(MCCFIInstruction::createSameValue( - nullptr, MRI->getDwarfRegNum(ScratchReg1, true))); + nullptr, MCRI->getDwarfRegNum(ScratchReg1, true))); BuildMI(PostStackMBB, DL, TII.get(TargetOpcode::CFI_INSTRUCTION)) .addCFIIndex(CFIIndex); } diff --git a/llvm/lib/Target/ARM/AsmParser/ARMAsmParser.cpp b/llvm/lib/Target/ARM/AsmParser/ARMAsmParser.cpp --- a/llvm/lib/Target/ARM/AsmParser/ARMAsmParser.cpp +++ b/llvm/lib/Target/ARM/AsmParser/ARMAsmParser.cpp @@ -235,7 +235,7 @@ } class ARMAsmParser : public MCTargetAsmParser { - const MCRegisterInfo *MRI; + const MCRegisterInfo *MCRI; UnwindContext UC; ARMMnemonicSets MS; @@ -353,7 +353,7 @@ // Return the low-subreg of a given Q register. unsigned getDRegFromQReg(unsigned QReg) const { - return MRI->getSubReg(QReg, ARM::dsub_0); + return MCRI->getSubReg(QReg, ARM::dsub_0); } // Get the condition code corresponding to the current IT block slot. @@ -682,7 +682,7 @@ MCAsmParserExtension::Initialize(Parser); // Cache the MCRegisterInfo. - MRI = getContext().getRegisterInfo(); + MCRI = getContext().getRegisterInfo(); // Initialize the set of available features. setAvailableFeatures(ComputeAvailableFeatures(STI.getFeatureBits())); @@ -4496,7 +4496,7 @@ // Allow Q regs and just interpret them as the two D sub-registers. if (ARMMCRegisterClasses[ARM::QPRRegClassID].contains(Reg)) { Reg = getDRegFromQReg(Reg); - EReg = MRI->getEncodingValue(Reg); + EReg = MCRI->getEncodingValue(Reg); Registers.emplace_back(EReg, Reg); ++Reg; } @@ -4514,7 +4514,7 @@ return Error(RegLoc, "invalid register in register list"); // Store the register. - EReg = MRI->getEncodingValue(Reg); + EReg = MCRI->getEncodingValue(Reg); Registers.emplace_back(EReg, Reg); // This starts immediately after the first register token in the list, @@ -4543,13 +4543,13 @@ if (!RC->contains(Reg)) return Error(AfterMinusLoc, "invalid register in register list"); // Ranges must go from low to high. - if (MRI->getEncodingValue(Reg) > MRI->getEncodingValue(EndReg)) + if (MCRI->getEncodingValue(Reg) > MCRI->getEncodingValue(EndReg)) return Error(AfterMinusLoc, "bad range in register list"); // Add all the registers in the range to the register list. while (Reg != EndReg) { Reg = getNextRegister(Reg); - EReg = MRI->getEncodingValue(Reg); + EReg = MCRI->getEncodingValue(Reg); if (!insertNoDuplicates(Registers, EReg, Reg)) { Warning(AfterMinusLoc, StringRef("duplicated register (") + ARMInstPrinter::getRegisterName(Reg) + @@ -4585,7 +4585,7 @@ RC == &ARMMCRegisterClasses[ARM::DPRRegClassID] || RC == &ARMMCRegisterClasses[ARM::FPWithVPRRegClassID])) { RC = &ARMMCRegisterClasses[ARM::FPWithVPRRegClassID]; - EReg = MRI->getEncodingValue(Reg); + EReg = MCRI->getEncodingValue(Reg); if (!insertNoDuplicates(Registers, EReg, Reg)) { Warning(RegLoc, "duplicated register (" + RegTok.getString() + ") in register list"); @@ -4602,7 +4602,7 @@ // there's no potential for confusion if you write clrm {r2,r1} // instead of clrm {r1,r2}. if (EnforceOrder && - MRI->getEncodingValue(Reg) < MRI->getEncodingValue(OldReg)) { + MCRI->getEncodingValue(Reg) < MCRI->getEncodingValue(OldReg)) { if (ARMMCRegisterClasses[ARM::GPRRegClassID].contains(Reg)) Warning(RegLoc, "register list not in ascending order"); else if (!ARMMCRegisterClasses[ARM::GPRwithAPSRnospRegClassID].contains(Reg)) @@ -4613,13 +4613,13 @@ RC != &ARMMCRegisterClasses[ARM::GPRwithAPSRnospRegClassID] && Reg != OldReg + 1) return Error(RegLoc, "non-contiguous register range"); - EReg = MRI->getEncodingValue(Reg); + EReg = MCRI->getEncodingValue(Reg); if (!insertNoDuplicates(Registers, EReg, Reg)) { Warning(RegLoc, "duplicated register (" + RegTok.getString() + ") in register list"); } if (isQReg) { - EReg = MRI->getEncodingValue(++Reg); + EReg = MCRI->getEncodingValue(++Reg); Registers.emplace_back(EReg, Reg); } } @@ -4735,13 +4735,13 @@ return Res; switch (LaneKind) { case NoLanes: - Reg = MRI->getMatchingSuperReg(Reg, ARM::dsub_0, - &ARMMCRegisterClasses[ARM::DPairRegClassID]); + Reg = MCRI->getMatchingSuperReg( + Reg, ARM::dsub_0, &ARMMCRegisterClasses[ARM::DPairRegClassID]); Operands.push_back(ARMOperand::CreateVectorList(Reg, 2, false, S, E)); break; case AllLanes: - Reg = MRI->getMatchingSuperReg(Reg, ARM::dsub_0, - &ARMMCRegisterClasses[ARM::DPairRegClassID]); + Reg = MCRI->getMatchingSuperReg( + Reg, ARM::dsub_0, &ARMMCRegisterClasses[ARM::DPairRegClassID]); Operands.push_back(ARMOperand::CreateVectorListAllLanes(Reg, 2, false, S, E)); break; @@ -4933,7 +4933,7 @@ const MCRegisterClass *RC = (Spacing == 1) ? &ARMMCRegisterClasses[ARM::DPairRegClassID] : &ARMMCRegisterClasses[ARM::DPairSpcRegClassID]; - FirstReg = MRI->getMatchingSuperReg(FirstReg, ARM::dsub_0, RC); + FirstReg = MCRI->getMatchingSuperReg(FirstReg, ARM::dsub_0, RC); } auto Create = (LaneKind == NoLanes ? ARMOperand::CreateVectorList : ARMOperand::CreateVectorListAllLanes); @@ -6987,11 +6987,11 @@ if (!Op3.isGPRMem()) return; - const MCRegisterClass &GPR = MRI->getRegClass(ARM::GPRRegClassID); + const MCRegisterClass &GPR = MCRI->getRegClass(ARM::GPRRegClassID); if (!GPR.contains(Op2.getReg())) return; - unsigned RtEncoding = MRI->getEncodingValue(Op2.getReg()); + unsigned RtEncoding = MCRI->getEncodingValue(Op2.getReg()); if (!isThumb() && (RtEncoding & 1)) { // In ARM mode, the registers must be from an aligned pair, this // restriction does not apply in Thumb mode. @@ -7443,14 +7443,14 @@ ARMOperand &Op1 = static_cast(*Operands[Idx]); ARMOperand &Op2 = static_cast(*Operands[Idx + 1]); - const MCRegisterClass &MRC = MRI->getRegClass(ARM::GPRRegClassID); + const MCRegisterClass &MRC = MCRI->getRegClass(ARM::GPRRegClassID); // Adjust only if Op1 and Op2 are GPRs. if (Op1.isReg() && Op2.isReg() && MRC.contains(Op1.getReg()) && MRC.contains(Op2.getReg())) { unsigned Reg1 = Op1.getReg(); unsigned Reg2 = Op2.getReg(); - unsigned Rt = MRI->getEncodingValue(Reg1); - unsigned Rt2 = MRI->getEncodingValue(Reg2); + unsigned Rt = MCRI->getEncodingValue(Reg1); + unsigned Rt2 = MCRI->getEncodingValue(Reg2); // Rt2 must be Rt + 1 and Rt must be even. if (Rt + 1 != Rt2 || (Rt & 1)) { @@ -7458,8 +7458,8 @@ isLoad ? "destination operands must be sequential" : "source operands must be sequential"); } - unsigned NewReg = MRI->getMatchingSuperReg( - Reg1, ARM::gsub_0, &(MRI->getRegClass(ARM::GPRPairRegClassID))); + unsigned NewReg = MCRI->getMatchingSuperReg( + Reg1, ARM::gsub_0, &(MCRI->getRegClass(ARM::GPRPairRegClassID))); Operands[Idx] = ARMOperand::CreateReg(NewReg, Op1.getStartLoc(), Op2.getEndLoc()); Operands.erase(Operands.begin() + Idx + 1); @@ -7570,8 +7570,8 @@ const OperandVector &Operands, bool Load, bool ARMMode, bool Writeback) { unsigned RtIndex = Load || !Writeback ? 0 : 1; - unsigned Rt = MRI->getEncodingValue(Inst.getOperand(RtIndex).getReg()); - unsigned Rt2 = MRI->getEncodingValue(Inst.getOperand(RtIndex + 1).getReg()); + unsigned Rt = MCRI->getEncodingValue(Inst.getOperand(RtIndex).getReg()); + unsigned Rt2 = MCRI->getEncodingValue(Inst.getOperand(RtIndex + 1).getReg()); if (ARMMode) { // Rt can't be R14. @@ -7605,7 +7605,7 @@ } if (Writeback) { - unsigned Rn = MRI->getEncodingValue(Inst.getOperand(3).getReg()); + unsigned Rn = MCRI->getEncodingValue(Inst.getOperand(3).getReg()); if (Rn == Rt || Rn == Rt2) { if (Load) @@ -7795,8 +7795,8 @@ case ARM::STRB_POST_REG: case ARM::t2STRB_POST: { // Rt must be different from Rn. - const unsigned Rt = MRI->getEncodingValue(Inst.getOperand(1).getReg()); - const unsigned Rn = MRI->getEncodingValue(Inst.getOperand(2).getReg()); + const unsigned Rt = MCRI->getEncodingValue(Inst.getOperand(1).getReg()); + const unsigned Rn = MCRI->getEncodingValue(Inst.getOperand(2).getReg()); if (Rt == Rn) return Error(Operands[3]->getStartLoc(), @@ -7808,8 +7808,8 @@ case ARM::t2STR_PRE_imm: case ARM::t2STR_POST_imm: { // Rt must be different from Rn. - const unsigned Rt = MRI->getEncodingValue(Inst.getOperand(0).getReg()); - const unsigned Rn = MRI->getEncodingValue(Inst.getOperand(1).getReg()); + const unsigned Rt = MCRI->getEncodingValue(Inst.getOperand(0).getReg()); + const unsigned Rn = MCRI->getEncodingValue(Inst.getOperand(1).getReg()); if (Rt == Rn) return Error(Operands[3]->getStartLoc(), @@ -7855,8 +7855,8 @@ case ARM::LDRSB_POST: case ARM::t2LDRSB_POST: { // Rt must be different from Rn. - const unsigned Rt = MRI->getEncodingValue(Inst.getOperand(0).getReg()); - const unsigned Rn = MRI->getEncodingValue(Inst.getOperand(2).getReg()); + const unsigned Rt = MCRI->getEncodingValue(Inst.getOperand(0).getReg()); + const unsigned Rn = MCRI->getEncodingValue(Inst.getOperand(2).getReg()); if (Rt == Rn) return Error(Operands[3]->getStartLoc(), @@ -7899,8 +7899,8 @@ break; } - const unsigned Qd = MRI->getEncodingValue(Inst.getOperand(QdIdx).getReg()); - const unsigned Qm = MRI->getEncodingValue(Inst.getOperand(QmIdx).getReg()); + const unsigned Qd = MCRI->getEncodingValue(Inst.getOperand(QdIdx).getReg()); + const unsigned Qm = MCRI->getEncodingValue(Inst.getOperand(QmIdx).getReg()); if (Qd == Qm) { return Error(Operands[3]->getStartLoc(), @@ -8237,8 +8237,8 @@ } case ARM::VMOVRRS: { // Source registers must be sequential. - const unsigned Sm = MRI->getEncodingValue(Inst.getOperand(2).getReg()); - const unsigned Sm1 = MRI->getEncodingValue(Inst.getOperand(3).getReg()); + const unsigned Sm = MCRI->getEncodingValue(Inst.getOperand(2).getReg()); + const unsigned Sm1 = MCRI->getEncodingValue(Inst.getOperand(3).getReg()); if (Sm1 != Sm + 1) return Error(Operands[5]->getStartLoc(), "source operands must be sequential"); @@ -8246,8 +8246,8 @@ } case ARM::VMOVSRR: { // Destination registers must be sequential. - const unsigned Sm = MRI->getEncodingValue(Inst.getOperand(0).getReg()); - const unsigned Sm1 = MRI->getEncodingValue(Inst.getOperand(1).getReg()); + const unsigned Sm = MCRI->getEncodingValue(Inst.getOperand(0).getReg()); + const unsigned Sm1 = MCRI->getEncodingValue(Inst.getOperand(1).getReg()); if (Sm1 != Sm + 1) return Error(Operands[3]->getStartLoc(), "destination operands must be sequential"); @@ -10879,7 +10879,7 @@ // Any arithmetic instruction which writes to the PC also terminates the IT // block. - if (MCID.hasDefOfPhysReg(Inst, ARM::PC, *MRI)) + if (MCID.hasDefOfPhysReg(Inst, ARM::PC, *MCRI)) return true; return false; @@ -12108,7 +12108,7 @@ const SmallVectorImpl &RegList = Op.getRegList(); uint32_t Mask = 0; for (size_t i = 0; i < RegList.size(); ++i) { - unsigned Reg = MRI->getEncodingValue(RegList[i]); + unsigned Reg = MCRI->getEncodingValue(RegList[i]); if (Reg == 15) // pc -> lr Reg = 14; if (Reg == 13) @@ -12128,9 +12128,9 @@ /// ::= .seh_save_sp bool ARMAsmParser::parseDirectiveSEHSaveSP(SMLoc L) { int Reg = tryParseRegister(); - if (Reg == -1 || !MRI->getRegClass(ARM::GPRRegClassID).contains(Reg)) + if (Reg == -1 || !MCRI->getRegClass(ARM::GPRRegClassID).contains(Reg)) return Error(L, "expected GPR"); - unsigned Index = MRI->getEncodingValue(Reg); + unsigned Index = MCRI->getEncodingValue(Reg); if (Index > 14 || Index == 13) return Error(L, "invalid register for .seh_save_sp"); getTargetStreamer().emitARMWinCFISaveSP(Index); @@ -12150,7 +12150,7 @@ const SmallVectorImpl &RegList = Op.getRegList(); uint32_t Mask = 0; for (size_t i = 0; i < RegList.size(); ++i) { - unsigned Reg = MRI->getEncodingValue(RegList[i]); + unsigned Reg = MCRI->getEncodingValue(RegList[i]); assert(Reg < 32U && "Register out of range"); unsigned Bit = (1u << Reg); Mask |= Bit; @@ -12623,7 +12623,7 @@ return Match_rGPR; case MCK_GPRPair: if (Op.isReg() && - MRI->getRegClass(ARM::GPRRegClassID).contains(Op.getReg())) + MCRI->getRegClass(ARM::GPRRegClassID).contains(Op.getReg())) return Match_Success; break; } diff --git a/llvm/lib/Target/ARM/MCTargetDesc/ARMAsmBackend.cpp b/llvm/lib/Target/ARM/MCTargetDesc/ARMAsmBackend.cpp --- a/llvm/lib/Target/ARM/MCTargetDesc/ARMAsmBackend.cpp +++ b/llvm/lib/Target/ARM/MCTargetDesc/ARMAsmBackend.cpp @@ -1129,16 +1129,16 @@ switch (Inst.getOperation()) { case MCCFIInstruction::OpDefCfa: // DW_CFA_def_cfa CFARegisterOffset = Inst.getOffset(); - CFARegister = *MRI.getLLVMRegNum(Inst.getRegister(), true); + CFARegister = *MCRI.getLLVMRegNum(Inst.getRegister(), true); break; case MCCFIInstruction::OpDefCfaOffset: // DW_CFA_def_cfa_offset CFARegisterOffset = Inst.getOffset(); break; case MCCFIInstruction::OpDefCfaRegister: // DW_CFA_def_cfa_register - CFARegister = *MRI.getLLVMRegNum(Inst.getRegister(), true); + CFARegister = *MCRI.getLLVMRegNum(Inst.getRegister(), true); break; case MCCFIInstruction::OpOffset: // DW_CFA_offset - Reg = *MRI.getLLVMRegNum(Inst.getRegister(), true); + Reg = *MCRI.getLLVMRegNum(Inst.getRegister(), true); if (ARMMCRegisterClasses[ARM::GPRRegClassID].contains(Reg)) RegOffsets[Reg] = Inst.getOffset(); else if (ARMMCRegisterClasses[ARM::DPRRegClassID].contains(Reg)) { @@ -1236,7 +1236,7 @@ int RegOffset = Offset->second; if (RegOffset != CurOffset - 4) { DEBUG_WITH_TYPE("compact-unwind", - llvm::dbgs() << MRI.getName(CSReg.Reg) << " saved at " + llvm::dbgs() << MCRI.getName(CSReg.Reg) << " saved at " << RegOffset << " but only supported at " << CurOffset << "\n"); return CU::UNWIND_ARM_MODE_DWARF; @@ -1270,17 +1270,17 @@ auto Offset = RegOffsets.find(FPRCSRegs[Idx]); if (Offset == RegOffsets.end()) { DEBUG_WITH_TYPE("compact-unwind", - llvm::dbgs() << FloatRegCount << " D-regs saved, but " - << MRI.getName(FPRCSRegs[Idx]) - << " not saved\n"); + llvm::dbgs() + << FloatRegCount << " D-regs saved, but " + << MCRI.getName(FPRCSRegs[Idx]) << " not saved\n"); return CU::UNWIND_ARM_MODE_DWARF; } else if (Offset->second != CurOffset - 8) { DEBUG_WITH_TYPE("compact-unwind", - llvm::dbgs() << FloatRegCount << " D-regs saved, but " - << MRI.getName(FPRCSRegs[Idx]) - << " saved at " << Offset->second - << ", expected at " << CurOffset - 8 - << "\n"); + llvm::dbgs() + << FloatRegCount << " D-regs saved, but " + << MCRI.getName(FPRCSRegs[Idx]) << " saved at " + << Offset->second << ", expected at " << CurOffset - 8 + << "\n"); return CU::UNWIND_ARM_MODE_DWARF; } CurOffset -= 8; @@ -1291,7 +1291,7 @@ static MCAsmBackend *createARMAsmBackend(const Target &T, const MCSubtargetInfo &STI, - const MCRegisterInfo &MRI, + const MCRegisterInfo &MCRI, const MCTargetOptions &Options, support::endianness Endian) { const Triple &TheTriple = STI.getTargetTriple(); @@ -1299,7 +1299,7 @@ default: llvm_unreachable("unsupported object format"); case Triple::MachO: - return new ARMAsmBackendDarwin(T, STI, MRI); + return new ARMAsmBackendDarwin(T, STI, MCRI); case Triple::COFF: assert(TheTriple.isOSWindows() && "non-Windows ARM COFF is not supported"); return new ARMAsmBackendWinCOFF(T, STI.getTargetTriple().isThumb()); @@ -1313,14 +1313,14 @@ MCAsmBackend *llvm::createARMLEAsmBackend(const Target &T, const MCSubtargetInfo &STI, - const MCRegisterInfo &MRI, + const MCRegisterInfo &MCRI, const MCTargetOptions &Options) { - return createARMAsmBackend(T, STI, MRI, Options, support::little); + return createARMAsmBackend(T, STI, MCRI, Options, support::little); } MCAsmBackend *llvm::createARMBEAsmBackend(const Target &T, const MCSubtargetInfo &STI, - const MCRegisterInfo &MRI, + const MCRegisterInfo &MCRI, const MCTargetOptions &Options) { - return createARMAsmBackend(T, STI, MRI, Options, support::big); + return createARMAsmBackend(T, STI, MCRI, Options, support::big); } diff --git a/llvm/lib/Target/ARM/MCTargetDesc/ARMAsmBackendDarwin.h b/llvm/lib/Target/ARM/MCTargetDesc/ARMAsmBackendDarwin.h --- a/llvm/lib/Target/ARM/MCTargetDesc/ARMAsmBackendDarwin.h +++ b/llvm/lib/Target/ARM/MCTargetDesc/ARMAsmBackendDarwin.h @@ -15,14 +15,14 @@ namespace llvm { class ARMAsmBackendDarwin : public ARMAsmBackend { - const MCRegisterInfo &MRI; + const MCRegisterInfo &MCRI; Triple TT; public: const MachO::CPUSubTypeARM Subtype; ARMAsmBackendDarwin(const Target &T, const MCSubtargetInfo &STI, - const MCRegisterInfo &MRI) + const MCRegisterInfo &MCRI) : ARMAsmBackend(T, STI.getTargetTriple().isThumb(), support::little), - MRI(MRI), TT(STI.getTargetTriple()), + MCRI(MCRI), TT(STI.getTargetTriple()), Subtype((MachO::CPUSubTypeARM)cantFail( MachO::getCPUSubType(STI.getTargetTriple()))) {} diff --git a/llvm/lib/Target/ARM/MCTargetDesc/ARMELFStreamer.cpp b/llvm/lib/Target/ARM/MCTargetDesc/ARMELFStreamer.cpp --- a/llvm/lib/Target/ARM/MCTargetDesc/ARMELFStreamer.cpp +++ b/llvm/lib/Target/ARM/MCTargetDesc/ARMELFStreamer.cpp @@ -1293,10 +1293,10 @@ void ARMELFStreamer::FlushUnwindOpcodes(bool NoHandlerData) { // Emit the unwind opcode to restore $sp. if (UsedFP) { - const MCRegisterInfo *MRI = getContext().getRegisterInfo(); + const MCRegisterInfo *MCRI = getContext().getRegisterInfo(); int64_t LastRegSaveSPOffset = SPOffset - PendingOffset; UnwindOpAsm.EmitSPOffset(LastRegSaveSPOffset - FPOffset); - UnwindOpAsm.EmitSetSP(MRI->getEncodingValue(FPReg)); + UnwindOpAsm.EmitSetSP(MCRI->getEncodingValue(FPReg)); } else { FlushPendingOffset(); } @@ -1386,8 +1386,8 @@ FPReg = Reg; FPOffset = SPOffset + Offset; - const MCRegisterInfo *MRI = getContext().getRegisterInfo(); - UnwindOpAsm.EmitSetSP(MRI->getEncodingValue(FPReg)); + const MCRegisterInfo *MCRI = getContext().getRegisterInfo(); + UnwindOpAsm.EmitSetSP(MCRI->getEncodingValue(FPReg)); } void ARMELFStreamer::emitPad(int64_t Offset) { @@ -1400,7 +1400,7 @@ } static std::pair -collectHWRegs(const MCRegisterInfo &MRI, unsigned Idx, +collectHWRegs(const MCRegisterInfo &MCRI, unsigned Idx, const SmallVectorImpl &RegList, bool IsVector, uint32_t &Mask_) { uint32_t Mask = 0; @@ -1409,7 +1409,7 @@ unsigned Reg = RegList[Idx - 1]; if (Reg == ARM::RA_AUTH_CODE) break; - Reg = MRI.getEncodingValue(Reg); + Reg = MCRI.getEncodingValue(Reg); assert(Reg < (IsVector ? 32U : 16U) && "Register out of range"); unsigned Bit = (1u << Reg); if ((Mask & Bit) == 0) { @@ -1427,7 +1427,7 @@ bool IsVector) { uint32_t Mask; unsigned Idx, Count; - const MCRegisterInfo &MRI = *getContext().getRegisterInfo(); + const MCRegisterInfo &MCRI = *getContext().getRegisterInfo(); // Collect the registers in the register list. Issue unwinding instructions in // three parts: ordinary hardware registers, return address authentication @@ -1437,7 +1437,7 @@ // value. Idx = RegList.size(); while (Idx > 0) { - std::tie(Idx, Count) = collectHWRegs(MRI, Idx, RegList, IsVector, Mask); + std::tie(Idx, Count) = collectHWRegs(MCRI, Idx, RegList, IsVector, Mask); if (Count) { // Track the change the $sp offset: For the .save directive, the // corresponding push instruction will decrease the $sp by (4 * Count). diff --git a/llvm/lib/Target/ARM/MCTargetDesc/ARMInstPrinter.h b/llvm/lib/Target/ARM/MCTargetDesc/ARMInstPrinter.h --- a/llvm/lib/Target/ARM/MCTargetDesc/ARMInstPrinter.h +++ b/llvm/lib/Target/ARM/MCTargetDesc/ARMInstPrinter.h @@ -21,7 +21,7 @@ class ARMInstPrinter : public MCInstPrinter { public: ARMInstPrinter(const MCAsmInfo &MAI, const MCInstrInfo &MII, - const MCRegisterInfo &MRI); + const MCRegisterInfo &MCRI); bool applyTargetSpecificCLOption(StringRef Opt) override; diff --git a/llvm/lib/Target/ARM/MCTargetDesc/ARMInstPrinter.cpp b/llvm/lib/Target/ARM/MCTargetDesc/ARMInstPrinter.cpp --- a/llvm/lib/Target/ARM/MCTargetDesc/ARMInstPrinter.cpp +++ b/llvm/lib/Target/ARM/MCTargetDesc/ARMInstPrinter.cpp @@ -70,8 +70,8 @@ } ARMInstPrinter::ARMInstPrinter(const MCAsmInfo &MAI, const MCInstrInfo &MII, - const MCRegisterInfo &MRI) - : MCInstPrinter(MAI, MII, MRI) {} + const MCRegisterInfo &MCRI) + : MCInstPrinter(MAI, MII, MCRI) {} bool ARMInstPrinter::applyTargetSpecificCLOption(StringRef Opt) { if (Opt == "reg-names-std") { @@ -260,7 +260,7 @@ case ARM::STREXD: case ARM::LDAEXD: case ARM::STLEXD: { - const MCRegisterClass &MRC = MRI.getRegClass(ARM::GPRRegClassID); + const MCRegisterClass &MRC = MCRI.getRegClass(ARM::GPRRegClassID); bool isStore = Opcode == ARM::STREXD || Opcode == ARM::STLEXD; unsigned Reg = MI->getOperand(isStore ? 1 : 0).getReg(); if (MRC.contains(Reg)) { @@ -270,8 +270,8 @@ if (isStore) NewMI.addOperand(MI->getOperand(0)); - NewReg = MCOperand::createReg(MRI.getMatchingSuperReg( - Reg, ARM::gsub_0, &MRI.getRegClass(ARM::GPRPairRegClassID))); + NewReg = MCOperand::createReg(MCRI.getMatchingSuperReg( + Reg, ARM::gsub_0, &MCRI.getRegClass(ARM::GPRPairRegClassID))); NewMI.addOperand(NewReg); // Copy the rest operands into NewMI. @@ -808,8 +808,8 @@ if (MI->getOpcode() != ARM::t2CLRM) { assert(is_sorted(drop_begin(*MI, OpNum), [&](const MCOperand &LHS, const MCOperand &RHS) { - return MRI.getEncodingValue(LHS.getReg()) < - MRI.getEncodingValue(RHS.getReg()); + return MCRI.getEncodingValue(LHS.getReg()) < + MCRI.getEncodingValue(RHS.getReg()); })); } @@ -826,9 +826,9 @@ const MCSubtargetInfo &STI, raw_ostream &O) { unsigned Reg = MI->getOperand(OpNum).getReg(); - printRegName(O, MRI.getSubReg(Reg, ARM::gsub_0)); + printRegName(O, MCRI.getSubReg(Reg, ARM::gsub_0)); O << ", "; - printRegName(O, MRI.getSubReg(Reg, ARM::gsub_1)); + printRegName(O, MCRI.getSubReg(Reg, ARM::gsub_1)); } void ARMInstPrinter::printSetendOperand(const MCInst *MI, unsigned OpNum, @@ -1433,8 +1433,8 @@ const MCSubtargetInfo &STI, raw_ostream &O) { unsigned Reg = MI->getOperand(OpNum).getReg(); - unsigned Reg0 = MRI.getSubReg(Reg, ARM::dsub_0); - unsigned Reg1 = MRI.getSubReg(Reg, ARM::dsub_1); + unsigned Reg0 = MCRI.getSubReg(Reg, ARM::dsub_0); + unsigned Reg1 = MCRI.getSubReg(Reg, ARM::dsub_1); O << "{"; printRegName(O, Reg0); O << ", "; @@ -1446,8 +1446,8 @@ const MCSubtargetInfo &STI, raw_ostream &O) { unsigned Reg = MI->getOperand(OpNum).getReg(); - unsigned Reg0 = MRI.getSubReg(Reg, ARM::dsub_0); - unsigned Reg1 = MRI.getSubReg(Reg, ARM::dsub_2); + unsigned Reg0 = MCRI.getSubReg(Reg, ARM::dsub_0); + unsigned Reg1 = MCRI.getSubReg(Reg, ARM::dsub_2); O << "{"; printRegName(O, Reg0); O << ", "; @@ -1501,8 +1501,8 @@ const MCSubtargetInfo &STI, raw_ostream &O) { unsigned Reg = MI->getOperand(OpNum).getReg(); - unsigned Reg0 = MRI.getSubReg(Reg, ARM::dsub_0); - unsigned Reg1 = MRI.getSubReg(Reg, ARM::dsub_1); + unsigned Reg0 = MCRI.getSubReg(Reg, ARM::dsub_0); + unsigned Reg1 = MCRI.getSubReg(Reg, ARM::dsub_1); O << "{"; printRegName(O, Reg0); O << "[], "; @@ -1548,8 +1548,8 @@ const MCInst *MI, unsigned OpNum, const MCSubtargetInfo &STI, raw_ostream &O) { unsigned Reg = MI->getOperand(OpNum).getReg(); - unsigned Reg0 = MRI.getSubReg(Reg, ARM::dsub_0); - unsigned Reg1 = MRI.getSubReg(Reg, ARM::dsub_2); + unsigned Reg0 = MCRI.getSubReg(Reg, ARM::dsub_0); + unsigned Reg1 = MCRI.getSubReg(Reg, ARM::dsub_2); O << "{"; printRegName(O, Reg0); O << "[], "; @@ -1630,7 +1630,7 @@ const char *Prefix = "{"; for (unsigned i = 0; i < NumRegs; i++) { O << Prefix; - printRegName(O, MRI.getSubReg(Reg, ARM::qsub_0 + i)); + printRegName(O, MCRI.getSubReg(Reg, ARM::qsub_0 + i)); Prefix = ", "; } O << "}"; diff --git a/llvm/lib/Target/ARM/MCTargetDesc/ARMMCCodeEmitter.cpp b/llvm/lib/Target/ARM/MCTargetDesc/ARMMCCodeEmitter.cpp --- a/llvm/lib/Target/ARM/MCTargetDesc/ARMMCCodeEmitter.cpp +++ b/llvm/lib/Target/ARM/MCTargetDesc/ARMMCCodeEmitter.cpp @@ -1736,14 +1736,14 @@ else Binary |= NumRegs * 2; } else { - const MCRegisterInfo &MRI = *CTX.getRegisterInfo(); + const MCRegisterInfo &MCRI = *CTX.getRegisterInfo(); assert(is_sorted(drop_begin(MI, Op), [&](const MCOperand &LHS, const MCOperand &RHS) { - return MRI.getEncodingValue(LHS.getReg()) < - MRI.getEncodingValue(RHS.getReg()); + return MCRI.getEncodingValue(LHS.getReg()) < + MCRI.getEncodingValue(RHS.getReg()); })); for (unsigned I = Op, E = MI.getNumOperands(); I < E; ++I) { - unsigned RegNo = MRI.getEncodingValue(MI.getOperand(I).getReg()); + unsigned RegNo = MCRI.getEncodingValue(MI.getOperand(I).getReg()); Binary |= 1 << RegNo; } } diff --git a/llvm/lib/Target/ARM/MCTargetDesc/ARMMCTargetDesc.h b/llvm/lib/Target/ARM/MCTargetDesc/ARMMCTargetDesc.h --- a/llvm/lib/Target/ARM/MCTargetDesc/ARMMCTargetDesc.h +++ b/llvm/lib/Target/ARM/MCTargetDesc/ARMMCTargetDesc.h @@ -39,7 +39,7 @@ namespace ARM_MC { std::string ParseARMTriple(const Triple &TT, StringRef CPU); -void initLLVMToCVRegMapping(MCRegisterInfo *MRI); +void initLLVMToCVRegMapping(MCRegisterInfo *MCRI); bool isPredicated(const MCInst &MI, const MCInstrInfo *MCII); bool isCPSRDefined(const MCInst &MI, const MCInstrInfo *MCII); @@ -81,11 +81,11 @@ MCContext &Ctx); MCAsmBackend *createARMLEAsmBackend(const Target &T, const MCSubtargetInfo &STI, - const MCRegisterInfo &MRI, + const MCRegisterInfo &MCRI, const MCTargetOptions &Options); MCAsmBackend *createARMBEAsmBackend(const Target &T, const MCSubtargetInfo &STI, - const MCRegisterInfo &MRI, + const MCRegisterInfo &MCRI, const MCTargetOptions &Options); // Construct a PE/COFF machine code streamer which will generate a PE/COFF diff --git a/llvm/lib/Target/ARM/MCTargetDesc/ARMMCTargetDesc.cpp b/llvm/lib/Target/ARM/MCTargetDesc/ARMMCTargetDesc.cpp --- a/llvm/lib/Target/ARM/MCTargetDesc/ARMMCTargetDesc.cpp +++ b/llvm/lib/Target/ARM/MCTargetDesc/ARMMCTargetDesc.cpp @@ -221,7 +221,7 @@ return X; } -void ARM_MC::initLLVMToCVRegMapping(MCRegisterInfo *MRI) { +void ARM_MC::initLLVMToCVRegMapping(MCRegisterInfo *MCRI) { // Mapping from CodeView to MC register id. static const struct { codeview::RegisterId CVReg; @@ -328,7 +328,7 @@ {codeview::RegisterId::ARM_NQ15, ARM::Q15}, }; for (const auto &I : RegMap) - MRI->mapLLVMRegToCVReg(I.Reg, static_cast(I.CVReg)); + MCRI->mapLLVMRegToCVReg(I.Reg, static_cast(I.CVReg)); } static MCRegisterInfo *createARMMCRegisterInfo(const Triple &Triple) { @@ -338,7 +338,7 @@ return X; } -static MCAsmInfo *createARMMCAsmInfo(const MCRegisterInfo &MRI, +static MCAsmInfo *createARMMCAsmInfo(const MCRegisterInfo &MCRI, const Triple &TheTriple, const MCTargetOptions &Options) { MCAsmInfo *MAI; @@ -351,7 +351,7 @@ else MAI = new ARMELFMCAsmInfo(TheTriple); - unsigned Reg = MRI.getDwarfRegNum(ARM::SP, true); + unsigned Reg = MCRI.getDwarfRegNum(ARM::SP, true); MAI->addInitialFrameState(MCCFIInstruction::cfiDefCfa(nullptr, Reg, 0)); return MAI; @@ -381,9 +381,9 @@ unsigned SyntaxVariant, const MCAsmInfo &MAI, const MCInstrInfo &MII, - const MCRegisterInfo &MRI) { + const MCRegisterInfo &MCRI) { if (SyntaxVariant == 0) - return new ARMInstPrinter(MAI, MII, MRI); + return new ARMInstPrinter(MAI, MII, MCRI); return nullptr; } diff --git a/llvm/lib/Target/ARM/Thumb1FrameLowering.cpp b/llvm/lib/Target/ARM/Thumb1FrameLowering.cpp --- a/llvm/lib/Target/ARM/Thumb1FrameLowering.cpp +++ b/llvm/lib/Target/ARM/Thumb1FrameLowering.cpp @@ -150,7 +150,7 @@ MachineFrameInfo &MFI = MF.getFrameInfo(); ARMFunctionInfo *AFI = MF.getInfo(); MachineModuleInfo &MMI = MF.getMMI(); - const MCRegisterInfo *MRI = MMI.getContext().getRegisterInfo(); + const MCRegisterInfo *MCRI = MMI.getContext().getRegisterInfo(); const ThumbRegisterInfo *RegInfo = static_cast(STI.getRegisterInfo()); const Thumb1InstrInfo &TII = @@ -329,14 +329,15 @@ if(FramePtrOffsetInBlock) { unsigned CFIIndex = MF.addFrameInst(MCCFIInstruction::cfiDefCfa( - nullptr, MRI->getDwarfRegNum(FramePtr, true), (CFAOffset - FramePtrOffsetInBlock))); + nullptr, MCRI->getDwarfRegNum(FramePtr, true), + (CFAOffset - FramePtrOffsetInBlock))); BuildMI(MBB, AfterPush, dl, TII.get(TargetOpcode::CFI_INSTRUCTION)) .addCFIIndex(CFIIndex) .setMIFlags(MachineInstr::FrameSetup); } else { unsigned CFIIndex = MF.addFrameInst(MCCFIInstruction::createDefCfaRegister( - nullptr, MRI->getDwarfRegNum(FramePtr, true))); + nullptr, MCRI->getDwarfRegNum(FramePtr, true))); BuildMI(MBB, AfterPush, dl, TII.get(TargetOpcode::CFI_INSTRUCTION)) .addCFIIndex(CFIIndex) .setMIFlags(MachineInstr::FrameSetup); @@ -379,7 +380,7 @@ case ARM::R7: case ARM::LR: unsigned CFIIndex = MF.addFrameInst(MCCFIInstruction::createOffset( - nullptr, MRI->getDwarfRegNum(Reg, true), MFI.getObjectOffset(FI))); + nullptr, MCRI->getDwarfRegNum(Reg, true), MFI.getObjectOffset(FI))); BuildMI(MBB, Pos, dl, TII.get(TargetOpcode::CFI_INSTRUCTION)) .addCFIIndex(CFIIndex) .setMIFlags(MachineInstr::FrameSetup); @@ -401,7 +402,7 @@ case ARM::R11: case ARM::R12: { unsigned CFIIndex = MF.addFrameInst(MCCFIInstruction::createOffset( - nullptr, MRI->getDwarfRegNum(Reg, true), MFI.getObjectOffset(FI))); + nullptr, MCRI->getDwarfRegNum(Reg, true), MFI.getObjectOffset(FI))); BuildMI(MBB, Pos, dl, TII.get(TargetOpcode::CFI_INSTRUCTION)) .addCFIIndex(CFIIndex) .setMIFlags(MachineInstr::FrameSetup); diff --git a/llvm/lib/Target/AVR/AVRAsmPrinter.cpp b/llvm/lib/Target/AVR/AVRAsmPrinter.cpp --- a/llvm/lib/Target/AVR/AVRAsmPrinter.cpp +++ b/llvm/lib/Target/AVR/AVRAsmPrinter.cpp @@ -45,7 +45,7 @@ class AVRAsmPrinter : public AsmPrinter { public: AVRAsmPrinter(TargetMachine &TM, std::unique_ptr Streamer) - : AsmPrinter(TM, std::move(Streamer)), MRI(*TM.getMCRegisterInfo()) {} + : AsmPrinter(TM, std::move(Streamer)), MCRI(*TM.getMCRegisterInfo()) {} StringRef getPassName() const override { return "AVR Assembly Printer"; } @@ -68,7 +68,7 @@ void emitStartOfAsmFile(Module &M) override; private: - const MCRegisterInfo &MRI; + const MCRegisterInfo &MCRI; bool EmittedStructorSymbolAttrs = false; }; @@ -78,7 +78,7 @@ switch (MO.getType()) { case MachineOperand::MO_Register: - O << AVRInstPrinter::getPrettyRegisterName(MO.getReg(), MRI); + O << AVRInstPrinter::getPrettyRegisterName(MO.getReg(), MCRI); break; case MachineOperand::MO_Immediate: O << MO.getImm(); @@ -137,7 +137,7 @@ : AVR::sub_lo); } - O << AVRInstPrinter::getPrettyRegisterName(Reg, MRI); + O << AVRInstPrinter::getPrettyRegisterName(Reg, MCRI); return false; } } diff --git a/llvm/lib/Target/AVR/AsmParser/AVRAsmParser.cpp b/llvm/lib/Target/AVR/AsmParser/AVRAsmParser.cpp --- a/llvm/lib/Target/AVR/AsmParser/AVRAsmParser.cpp +++ b/llvm/lib/Target/AVR/AsmParser/AVRAsmParser.cpp @@ -41,7 +41,7 @@ class AVRAsmParser : public MCTargetAsmParser { const MCSubtargetInfo &STI; MCAsmParser &Parser; - const MCRegisterInfo *MRI; + const MCRegisterInfo *MCRI; const std::string GENERATE_STUBS = "gs"; enum AVRMatchResultTy { @@ -82,7 +82,7 @@ unsigned toDREG(unsigned Reg, unsigned From = AVR::sub_lo) { MCRegisterClass const *Class = &AVRMCRegisterClasses[AVR::DREGSRegClassID]; - return MRI->getMatchingSuperReg(Reg, From, Class); + return MCRI->getMatchingSuperReg(Reg, From, Class); } bool emit(MCInst &Instruction, SMLoc const &Loc, MCStreamer &Out) const; @@ -97,7 +97,7 @@ const MCInstrInfo &MII, const MCTargetOptions &Options) : MCTargetAsmParser(Options, STI, MII), STI(STI), Parser(Parser) { MCAsmParserExtension::Initialize(Parser); - MRI = getContext().getRegisterInfo(); + MCRI = getContext().getRegisterInfo(); setAvailableFeatures(ComputeAvailableFeatures(STI.getFeatureBits())); } diff --git a/llvm/lib/Target/AVR/MCTargetDesc/AVRAsmBackend.cpp b/llvm/lib/Target/AVR/MCTargetDesc/AVRAsmBackend.cpp --- a/llvm/lib/Target/AVR/MCTargetDesc/AVRAsmBackend.cpp +++ b/llvm/lib/Target/AVR/MCTargetDesc/AVRAsmBackend.cpp @@ -520,7 +520,7 @@ } MCAsmBackend *createAVRAsmBackend(const Target &T, const MCSubtargetInfo &STI, - const MCRegisterInfo &MRI, + const MCRegisterInfo &MCRI, const llvm::MCTargetOptions &TO) { return new AVRAsmBackend(STI.getTargetTriple().getOS()); } diff --git a/llvm/lib/Target/AVR/MCTargetDesc/AVRInstPrinter.h b/llvm/lib/Target/AVR/MCTargetDesc/AVRInstPrinter.h --- a/llvm/lib/Target/AVR/MCTargetDesc/AVRInstPrinter.h +++ b/llvm/lib/Target/AVR/MCTargetDesc/AVRInstPrinter.h @@ -23,11 +23,11 @@ class AVRInstPrinter : public MCInstPrinter { public: AVRInstPrinter(const MCAsmInfo &MAI, const MCInstrInfo &MII, - const MCRegisterInfo &MRI) - : MCInstPrinter(MAI, MII, MRI) {} + const MCRegisterInfo &MCRI) + : MCInstPrinter(MAI, MII, MCRI) {} static const char *getPrettyRegisterName(unsigned RegNo, - MCRegisterInfo const &MRI); + MCRegisterInfo const &MCRI); void printInst(const MCInst *MI, uint64_t Address, StringRef Annot, const MCSubtargetInfo &STI, raw_ostream &O) override; diff --git a/llvm/lib/Target/AVR/MCTargetDesc/AVRInstPrinter.cpp b/llvm/lib/Target/AVR/MCTargetDesc/AVRInstPrinter.cpp --- a/llvm/lib/Target/AVR/MCTargetDesc/AVRInstPrinter.cpp +++ b/llvm/lib/Target/AVR/MCTargetDesc/AVRInstPrinter.cpp @@ -87,11 +87,11 @@ } const char *AVRInstPrinter::getPrettyRegisterName(unsigned RegNum, - MCRegisterInfo const &MRI) { + MCRegisterInfo const &MCRI) { // GCC prints register pairs by just printing the lower register // If the register contains a subregister, print it instead - if (MRI.getNumSubRegIndices() > 0) { - unsigned RegLoNum = MRI.getSubReg(RegNum, AVR::sub_lo); + if (MCRI.getNumSubRegIndices() > 0) { + unsigned RegLoNum = MCRI.getSubReg(RegNum, AVR::sub_lo); RegNum = (RegLoNum != AVR::NoRegister) ? RegLoNum : RegNum; } @@ -128,7 +128,7 @@ if (isPtrReg) { O << getRegisterName(Op.getReg(), AVR::ptr); } else { - O << getPrettyRegisterName(Op.getReg(), MRI); + O << getPrettyRegisterName(Op.getReg(), MCRI); } } else if (Op.isImm()) { O << formatImm(Op.getImm()); diff --git a/llvm/lib/Target/AVR/MCTargetDesc/AVRMCTargetDesc.h b/llvm/lib/Target/AVR/MCTargetDesc/AVRMCTargetDesc.h --- a/llvm/lib/Target/AVR/MCTargetDesc/AVRMCTargetDesc.h +++ b/llvm/lib/Target/AVR/MCTargetDesc/AVRMCTargetDesc.h @@ -37,7 +37,7 @@ /// Creates an assembly backend for AVR. MCAsmBackend *createAVRAsmBackend(const Target &T, const MCSubtargetInfo &STI, - const MCRegisterInfo &MRI, + const MCRegisterInfo &MCRI, const llvm::MCTargetOptions &TO); /// Creates an ELF object writer for AVR. diff --git a/llvm/lib/Target/AVR/MCTargetDesc/AVRMCTargetDesc.cpp b/llvm/lib/Target/AVR/MCTargetDesc/AVRMCTargetDesc.cpp --- a/llvm/lib/Target/AVR/MCTargetDesc/AVRMCTargetDesc.cpp +++ b/llvm/lib/Target/AVR/MCTargetDesc/AVRMCTargetDesc.cpp @@ -61,9 +61,9 @@ unsigned SyntaxVariant, const MCAsmInfo &MAI, const MCInstrInfo &MII, - const MCRegisterInfo &MRI) { + const MCRegisterInfo &MCRI) { if (SyntaxVariant == 0) { - return new AVRInstPrinter(MAI, MII, MRI); + return new AVRInstPrinter(MAI, MII, MCRI); } return nullptr; diff --git a/llvm/lib/Target/BPF/MCTargetDesc/BPFAsmBackend.cpp b/llvm/lib/Target/BPF/MCTargetDesc/BPFAsmBackend.cpp --- a/llvm/lib/Target/BPF/MCTargetDesc/BPFAsmBackend.cpp +++ b/llvm/lib/Target/BPF/MCTargetDesc/BPFAsmBackend.cpp @@ -105,14 +105,14 @@ MCAsmBackend *llvm::createBPFAsmBackend(const Target &T, const MCSubtargetInfo &STI, - const MCRegisterInfo &MRI, + const MCRegisterInfo &MCRI, const MCTargetOptions &) { return new BPFAsmBackend(support::little); } MCAsmBackend *llvm::createBPFbeAsmBackend(const Target &T, const MCSubtargetInfo &STI, - const MCRegisterInfo &MRI, + const MCRegisterInfo &MCRI, const MCTargetOptions &) { return new BPFAsmBackend(support::big); } diff --git a/llvm/lib/Target/BPF/MCTargetDesc/BPFInstPrinter.h b/llvm/lib/Target/BPF/MCTargetDesc/BPFInstPrinter.h --- a/llvm/lib/Target/BPF/MCTargetDesc/BPFInstPrinter.h +++ b/llvm/lib/Target/BPF/MCTargetDesc/BPFInstPrinter.h @@ -19,8 +19,8 @@ class BPFInstPrinter : public MCInstPrinter { public: BPFInstPrinter(const MCAsmInfo &MAI, const MCInstrInfo &MII, - const MCRegisterInfo &MRI) - : MCInstPrinter(MAI, MII, MRI) {} + const MCRegisterInfo &MCRI) + : MCInstPrinter(MAI, MII, MCRI) {} void printInst(const MCInst *MI, uint64_t Address, StringRef Annot, const MCSubtargetInfo &STI, raw_ostream &O) override; diff --git a/llvm/lib/Target/BPF/MCTargetDesc/BPFMCCodeEmitter.cpp b/llvm/lib/Target/BPF/MCTargetDesc/BPFMCCodeEmitter.cpp --- a/llvm/lib/Target/BPF/MCTargetDesc/BPFMCCodeEmitter.cpp +++ b/llvm/lib/Target/BPF/MCTargetDesc/BPFMCCodeEmitter.cpp @@ -31,13 +31,13 @@ namespace { class BPFMCCodeEmitter : public MCCodeEmitter { - const MCRegisterInfo &MRI; + const MCRegisterInfo &MCRI; bool IsLittleEndian; public: BPFMCCodeEmitter(const MCInstrInfo &, const MCRegisterInfo &mri, bool IsLittleEndian) - : MRI(mri), IsLittleEndian(IsLittleEndian) { } + : MCRI(mri), IsLittleEndian(IsLittleEndian) {} BPFMCCodeEmitter(const BPFMCCodeEmitter &) = delete; void operator=(const BPFMCCodeEmitter &) = delete; ~BPFMCCodeEmitter() override = default; @@ -80,7 +80,7 @@ SmallVectorImpl &Fixups, const MCSubtargetInfo &STI) const { if (MO.isReg()) - return MRI.getEncodingValue(MO.getReg()); + return MCRI.getEncodingValue(MO.getReg()); if (MO.isImm()) return static_cast(MO.getImm()); @@ -156,7 +156,7 @@ uint64_t Encoding; const MCOperand Op1 = MI.getOperand(MemOpStartIndex); assert(Op1.isReg() && "First operand is not register."); - Encoding = MRI.getEncodingValue(Op1.getReg()); + Encoding = MCRI.getEncodingValue(Op1.getReg()); Encoding <<= 16; MCOperand Op2 = MI.getOperand(MemOpStartIndex + 1); assert(Op2.isImm() && "Second operand is not immediate."); diff --git a/llvm/lib/Target/BPF/MCTargetDesc/BPFMCTargetDesc.h b/llvm/lib/Target/BPF/MCTargetDesc/BPFMCTargetDesc.h --- a/llvm/lib/Target/BPF/MCTargetDesc/BPFMCTargetDesc.h +++ b/llvm/lib/Target/BPF/MCTargetDesc/BPFMCTargetDesc.h @@ -36,10 +36,10 @@ MCContext &Ctx); MCAsmBackend *createBPFAsmBackend(const Target &T, const MCSubtargetInfo &STI, - const MCRegisterInfo &MRI, + const MCRegisterInfo &MCRI, const MCTargetOptions &Options); MCAsmBackend *createBPFbeAsmBackend(const Target &T, const MCSubtargetInfo &STI, - const MCRegisterInfo &MRI, + const MCRegisterInfo &MCRI, const MCTargetOptions &Options); std::unique_ptr createBPFELFObjectWriter(uint8_t OSABI); diff --git a/llvm/lib/Target/BPF/MCTargetDesc/BPFMCTargetDesc.cpp b/llvm/lib/Target/BPF/MCTargetDesc/BPFMCTargetDesc.cpp --- a/llvm/lib/Target/BPF/MCTargetDesc/BPFMCTargetDesc.cpp +++ b/llvm/lib/Target/BPF/MCTargetDesc/BPFMCTargetDesc.cpp @@ -63,9 +63,9 @@ unsigned SyntaxVariant, const MCAsmInfo &MAI, const MCInstrInfo &MII, - const MCRegisterInfo &MRI) { + const MCRegisterInfo &MCRI) { if (SyntaxVariant == 0) - return new BPFInstPrinter(MAI, MII, MRI); + return new BPFInstPrinter(MAI, MII, MCRI); return nullptr; } diff --git a/llvm/lib/Target/CSKY/AsmParser/CSKYAsmParser.cpp b/llvm/lib/Target/CSKY/AsmParser/CSKYAsmParser.cpp --- a/llvm/lib/Target/CSKY/AsmParser/CSKYAsmParser.cpp +++ b/llvm/lib/Target/CSKY/AsmParser/CSKYAsmParser.cpp @@ -55,7 +55,7 @@ class CSKYAsmParser : public MCTargetAsmParser { - const MCRegisterInfo *MRI; + const MCRegisterInfo *MCRI; unsigned validateTargetOperandClass(MCParsedAsmOperand &Op, unsigned Kind) override; @@ -133,7 +133,7 @@ MCAsmParserExtension::Initialize(Parser); // Cache the MCRegisterInfo. - MRI = getContext().getRegisterInfo(); + MCRI = getContext().getRegisterInfo(); setAvailableFeatures(ComputeAvailableFeatures(STI.getFeatureBits())); getTargetStreamer().emitTargetAttributes(STI); @@ -1735,7 +1735,7 @@ if (CSKYMCRegisterClasses[CSKY::GPRRegClassID].contains(Reg)) { if (Kind == MCK_GPRPair) { - Op.Reg.RegNum = MRI->getEncodingValue(Reg) + CSKY::R0_R1; + Op.Reg.RegNum = MCRI->getEncodingValue(Reg) + CSKY::R0_R1; return Match_Success; } } diff --git a/llvm/lib/Target/CSKY/MCTargetDesc/CSKYAsmBackend.cpp b/llvm/lib/Target/CSKY/MCTargetDesc/CSKYAsmBackend.cpp --- a/llvm/lib/Target/CSKY/MCTargetDesc/CSKYAsmBackend.cpp +++ b/llvm/lib/Target/CSKY/MCTargetDesc/CSKYAsmBackend.cpp @@ -352,7 +352,7 @@ MCAsmBackend *llvm::createCSKYAsmBackend(const Target &T, const MCSubtargetInfo &STI, - const MCRegisterInfo &MRI, + const MCRegisterInfo &MCRI, const MCTargetOptions &Options) { return new CSKYAsmBackend(STI, Options); } diff --git a/llvm/lib/Target/CSKY/MCTargetDesc/CSKYInstPrinter.h b/llvm/lib/Target/CSKY/MCTargetDesc/CSKYInstPrinter.h --- a/llvm/lib/Target/CSKY/MCTargetDesc/CSKYInstPrinter.h +++ b/llvm/lib/Target/CSKY/MCTargetDesc/CSKYInstPrinter.h @@ -24,8 +24,8 @@ public: CSKYInstPrinter(const MCAsmInfo &MAI, const MCInstrInfo &MII, - const MCRegisterInfo &MRI) - : MCInstPrinter(MAI, MII, MRI) {} + const MCRegisterInfo &MCRI) + : MCInstPrinter(MAI, MII, MCRI) {} bool applyTargetSpecificCLOption(StringRef Opt) override; diff --git a/llvm/lib/Target/CSKY/MCTargetDesc/CSKYMCTargetDesc.h b/llvm/lib/Target/CSKY/MCTargetDesc/CSKYMCTargetDesc.h --- a/llvm/lib/Target/CSKY/MCTargetDesc/CSKYMCTargetDesc.h +++ b/llvm/lib/Target/CSKY/MCTargetDesc/CSKYMCTargetDesc.h @@ -31,7 +31,7 @@ std::unique_ptr createCSKYELFObjectWriter(); MCAsmBackend *createCSKYAsmBackend(const Target &T, const MCSubtargetInfo &STI, - const MCRegisterInfo &MRI, + const MCRegisterInfo &MCRI, const MCTargetOptions &Options); MCCodeEmitter *createCSKYMCCodeEmitter(const MCInstrInfo &MCII, MCContext &Ctx); diff --git a/llvm/lib/Target/CSKY/MCTargetDesc/CSKYMCTargetDesc.cpp b/llvm/lib/Target/CSKY/MCTargetDesc/CSKYMCTargetDesc.cpp --- a/llvm/lib/Target/CSKY/MCTargetDesc/CSKYMCTargetDesc.cpp +++ b/llvm/lib/Target/CSKY/MCTargetDesc/CSKYMCTargetDesc.cpp @@ -37,13 +37,13 @@ using namespace llvm; -static MCAsmInfo *createCSKYMCAsmInfo(const MCRegisterInfo &MRI, +static MCAsmInfo *createCSKYMCAsmInfo(const MCRegisterInfo &MCRI, const Triple &TT, const MCTargetOptions &Options) { MCAsmInfo *MAI = new CSKYMCAsmInfo(TT); // Initial state of the frame pointer is SP. - unsigned Reg = MRI.getDwarfRegNum(CSKY::R14, true); + unsigned Reg = MCRI.getDwarfRegNum(CSKY::R14, true); MCCFIInstruction Inst = MCCFIInstruction::cfiDefCfa(nullptr, Reg, 0); MAI->addInitialFrameState(Inst); return MAI; @@ -59,8 +59,8 @@ unsigned SyntaxVariant, const MCAsmInfo &MAI, const MCInstrInfo &MII, - const MCRegisterInfo &MRI) { - return new CSKYInstPrinter(MAI, MII, MRI); + const MCRegisterInfo &MCRI) { + return new CSKYInstPrinter(MAI, MII, MCRI); } static MCRegisterInfo *createCSKYMCRegisterInfo(const Triple &TT) { diff --git a/llvm/lib/Target/DirectX/MCTargetDesc/DirectXMCTargetDesc.cpp b/llvm/lib/Target/DirectX/MCTargetDesc/DirectXMCTargetDesc.cpp --- a/llvm/lib/Target/DirectX/MCTargetDesc/DirectXMCTargetDesc.cpp +++ b/llvm/lib/Target/DirectX/MCTargetDesc/DirectXMCTargetDesc.cpp @@ -47,8 +47,8 @@ class DXILInstPrinter : public MCInstPrinter { public: DXILInstPrinter(const MCAsmInfo &MAI, const MCInstrInfo &MII, - const MCRegisterInfo &MRI) - : MCInstPrinter(MAI, MII, MRI) {} + const MCRegisterInfo &MCRI) + : MCInstPrinter(MAI, MII, MCRI) {} void printInst(const MCInst *MI, uint64_t Address, StringRef Annot, const MCSubtargetInfo &STI, raw_ostream &O) override {} @@ -111,9 +111,9 @@ unsigned SyntaxVariant, const MCAsmInfo &MAI, const MCInstrInfo &MII, - const MCRegisterInfo &MRI) { + const MCRegisterInfo &MCRI) { if (SyntaxVariant == 0) - return new DXILInstPrinter(MAI, MII, MRI); + return new DXILInstPrinter(MAI, MII, MCRI); return nullptr; } @@ -124,7 +124,7 @@ MCAsmBackend *createDXILMCAsmBackend(const Target &T, const MCSubtargetInfo &STI, - const MCRegisterInfo &MRI, + const MCRegisterInfo &MCRI, const MCTargetOptions &Options) { return new DXILAsmBackend(STI); } diff --git a/llvm/lib/Target/Hexagon/MCTargetDesc/HexagonAsmBackend.cpp b/llvm/lib/Target/Hexagon/MCTargetDesc/HexagonAsmBackend.cpp --- a/llvm/lib/Target/Hexagon/MCTargetDesc/HexagonAsmBackend.cpp +++ b/llvm/lib/Target/Hexagon/MCTargetDesc/HexagonAsmBackend.cpp @@ -773,7 +773,7 @@ // MCAsmBackend MCAsmBackend *llvm::createHexagonAsmBackend(Target const &T, const MCSubtargetInfo &STI, - MCRegisterInfo const & /*MRI*/, + MCRegisterInfo const & /*MCRI*/, const MCTargetOptions &Options) { const Triple &TT = STI.getTargetTriple(); uint8_t OSABI = MCELFObjectTargetWriter::getOSABI(TT.getOS()); diff --git a/llvm/lib/Target/Hexagon/MCTargetDesc/HexagonInstPrinter.h b/llvm/lib/Target/Hexagon/MCTargetDesc/HexagonInstPrinter.h --- a/llvm/lib/Target/Hexagon/MCTargetDesc/HexagonInstPrinter.h +++ b/llvm/lib/Target/Hexagon/MCTargetDesc/HexagonInstPrinter.h @@ -25,8 +25,8 @@ class HexagonInstPrinter : public MCInstPrinter { public: explicit HexagonInstPrinter(MCAsmInfo const &MAI, MCInstrInfo const &MII, - MCRegisterInfo const &MRI) - : MCInstPrinter(MAI, MII, MRI), MII(MII) {} + MCRegisterInfo const &MCRI) + : MCInstPrinter(MAI, MII, MCRI), MII(MII) {} void printInst(MCInst const *MI, uint64_t Address, StringRef Annot, const MCSubtargetInfo &STI, raw_ostream &O) override; diff --git a/llvm/lib/Target/Hexagon/MCTargetDesc/HexagonMCInstrInfo.h b/llvm/lib/Target/Hexagon/MCTargetDesc/HexagonMCInstrInfo.h --- a/llvm/lib/Target/Hexagon/MCTargetDesc/HexagonMCInstrInfo.h +++ b/llvm/lib/Target/Hexagon/MCTargetDesc/HexagonMCInstrInfo.h @@ -289,7 +289,7 @@ bool isPredicatedTrue(MCInstrInfo const &MCII, MCInst const &MCI); // Return true if this is a scalar predicate register. -bool isPredReg(MCRegisterInfo const &MRI, unsigned Reg); +bool isPredReg(MCRegisterInfo const &MCRI, unsigned Reg); // Returns true if the Ith operand is a predicate register. bool isPredRegister(MCInstrInfo const &MCII, MCInst const &Inst, unsigned I); diff --git a/llvm/lib/Target/Hexagon/MCTargetDesc/HexagonMCInstrInfo.cpp b/llvm/lib/Target/Hexagon/MCTargetDesc/HexagonMCInstrInfo.cpp --- a/llvm/lib/Target/Hexagon/MCTargetDesc/HexagonMCInstrInfo.cpp +++ b/llvm/lib/Target/Hexagon/MCTargetDesc/HexagonMCInstrInfo.cpp @@ -752,8 +752,8 @@ !((F >> HexagonII::PredicatedFalsePos) & HexagonII::PredicatedFalseMask)); } -bool HexagonMCInstrInfo::isPredReg(MCRegisterInfo const &MRI, unsigned Reg) { - auto &PredRegClass = MRI.getRegClass(Hexagon::PredRegsRegClassID); +bool HexagonMCInstrInfo::isPredReg(MCRegisterInfo const &MCRI, unsigned Reg) { + auto &PredRegClass = MCRI.getRegClass(Hexagon::PredRegsRegClassID); return PredRegClass.contains(Reg); } diff --git a/llvm/lib/Target/Hexagon/MCTargetDesc/HexagonMCTargetDesc.h b/llvm/lib/Target/Hexagon/MCTargetDesc/HexagonMCTargetDesc.h --- a/llvm/lib/Target/Hexagon/MCTargetDesc/HexagonMCTargetDesc.h +++ b/llvm/lib/Target/Hexagon/MCTargetDesc/HexagonMCTargetDesc.h @@ -89,7 +89,7 @@ MCAsmBackend *createHexagonAsmBackend(const Target &T, const MCSubtargetInfo &STI, - const MCRegisterInfo &MRI, + const MCRegisterInfo &MCRI, const MCTargetOptions &Options); std::unique_ptr diff --git a/llvm/lib/Target/Hexagon/MCTargetDesc/HexagonMCTargetDesc.cpp b/llvm/lib/Target/Hexagon/MCTargetDesc/HexagonMCTargetDesc.cpp --- a/llvm/lib/Target/Hexagon/MCTargetDesc/HexagonMCTargetDesc.cpp +++ b/llvm/lib/Target/Hexagon/MCTargetDesc/HexagonMCTargetDesc.cpp @@ -314,14 +314,14 @@ return X; } -static MCAsmInfo *createHexagonMCAsmInfo(const MCRegisterInfo &MRI, +static MCAsmInfo *createHexagonMCAsmInfo(const MCRegisterInfo &MCRI, const Triple &TT, const MCTargetOptions &Options) { MCAsmInfo *MAI = new HexagonMCAsmInfo(TT); // VirtualFP = (R30 + #0). MCCFIInstruction Inst = MCCFIInstruction::cfiDefCfa( - nullptr, MRI.getDwarfRegNum(Hexagon::R30, true), 0); + nullptr, MCRI.getDwarfRegNum(Hexagon::R30, true), 0); MAI->addInitialFrameState(Inst); return MAI; @@ -331,10 +331,9 @@ unsigned SyntaxVariant, const MCAsmInfo &MAI, const MCInstrInfo &MII, - const MCRegisterInfo &MRI) -{ + const MCRegisterInfo &MCRI) { if (SyntaxVariant == 0) - return new HexagonInstPrinter(MAI, MII, MRI); + return new HexagonInstPrinter(MAI, MII, MCRI); else return nullptr; } diff --git a/llvm/lib/Target/Lanai/MCTargetDesc/LanaiAsmBackend.cpp b/llvm/lib/Target/Lanai/MCTargetDesc/LanaiAsmBackend.cpp --- a/llvm/lib/Target/Lanai/MCTargetDesc/LanaiAsmBackend.cpp +++ b/llvm/lib/Target/Lanai/MCTargetDesc/LanaiAsmBackend.cpp @@ -160,7 +160,7 @@ MCAsmBackend *llvm::createLanaiAsmBackend(const Target &T, const MCSubtargetInfo &STI, - const MCRegisterInfo & /*MRI*/, + const MCRegisterInfo & /*MCRI*/, const MCTargetOptions & /*Options*/) { const Triple &TT = STI.getTargetTriple(); if (!TT.isOSBinFormatELF()) diff --git a/llvm/lib/Target/Lanai/MCTargetDesc/LanaiInstPrinter.h b/llvm/lib/Target/Lanai/MCTargetDesc/LanaiInstPrinter.h --- a/llvm/lib/Target/Lanai/MCTargetDesc/LanaiInstPrinter.h +++ b/llvm/lib/Target/Lanai/MCTargetDesc/LanaiInstPrinter.h @@ -21,8 +21,8 @@ class LanaiInstPrinter : public MCInstPrinter { public: LanaiInstPrinter(const MCAsmInfo &MAI, const MCInstrInfo &MII, - const MCRegisterInfo &MRI) - : MCInstPrinter(MAI, MII, MRI) {} + const MCRegisterInfo &MCRI) + : MCInstPrinter(MAI, MII, MCRI) {} void printInst(const MCInst *MI, uint64_t Address, StringRef Annot, const MCSubtargetInfo &STI, raw_ostream &O) override; diff --git a/llvm/lib/Target/Lanai/MCTargetDesc/LanaiMCTargetDesc.h b/llvm/lib/Target/Lanai/MCTargetDesc/LanaiMCTargetDesc.h --- a/llvm/lib/Target/Lanai/MCTargetDesc/LanaiMCTargetDesc.h +++ b/llvm/lib/Target/Lanai/MCTargetDesc/LanaiMCTargetDesc.h @@ -30,7 +30,7 @@ MCContext &Ctx); MCAsmBackend *createLanaiAsmBackend(const Target &T, const MCSubtargetInfo &STI, - const MCRegisterInfo &MRI, + const MCRegisterInfo &MCRI, const MCTargetOptions &Options); std::unique_ptr createLanaiELFObjectWriter(uint8_t OSABI); diff --git a/llvm/lib/Target/Lanai/MCTargetDesc/LanaiMCTargetDesc.cpp b/llvm/lib/Target/Lanai/MCTargetDesc/LanaiMCTargetDesc.cpp --- a/llvm/lib/Target/Lanai/MCTargetDesc/LanaiMCTargetDesc.cpp +++ b/llvm/lib/Target/Lanai/MCTargetDesc/LanaiMCTargetDesc.cpp @@ -76,9 +76,9 @@ unsigned SyntaxVariant, const MCAsmInfo &MAI, const MCInstrInfo &MII, - const MCRegisterInfo &MRI) { + const MCRegisterInfo &MCRI) { if (SyntaxVariant == 0) - return new LanaiInstPrinter(MAI, MII, MRI); + return new LanaiInstPrinter(MAI, MII, MCRI); return nullptr; } diff --git a/llvm/lib/Target/LoongArch/MCTargetDesc/LoongArchAsmBackend.cpp b/llvm/lib/Target/LoongArch/MCTargetDesc/LoongArchAsmBackend.cpp --- a/llvm/lib/Target/LoongArch/MCTargetDesc/LoongArchAsmBackend.cpp +++ b/llvm/lib/Target/LoongArch/MCTargetDesc/LoongArchAsmBackend.cpp @@ -198,7 +198,7 @@ MCAsmBackend *llvm::createLoongArchAsmBackend(const Target &T, const MCSubtargetInfo &STI, - const MCRegisterInfo &MRI, + const MCRegisterInfo &MCRI, const MCTargetOptions &Options) { const Triple &TT = STI.getTargetTriple(); uint8_t OSABI = MCELFObjectTargetWriter::getOSABI(TT.getOS()); diff --git a/llvm/lib/Target/LoongArch/MCTargetDesc/LoongArchInstPrinter.h b/llvm/lib/Target/LoongArch/MCTargetDesc/LoongArchInstPrinter.h --- a/llvm/lib/Target/LoongArch/MCTargetDesc/LoongArchInstPrinter.h +++ b/llvm/lib/Target/LoongArch/MCTargetDesc/LoongArchInstPrinter.h @@ -21,8 +21,8 @@ class LoongArchInstPrinter : public MCInstPrinter { public: LoongArchInstPrinter(const MCAsmInfo &MAI, const MCInstrInfo &MII, - const MCRegisterInfo &MRI) - : MCInstPrinter(MAI, MII, MRI) {} + const MCRegisterInfo &MCRI) + : MCInstPrinter(MAI, MII, MCRI) {} bool applyTargetSpecificCLOption(StringRef Opt) override; diff --git a/llvm/lib/Target/LoongArch/MCTargetDesc/LoongArchMCTargetDesc.h b/llvm/lib/Target/LoongArch/MCTargetDesc/LoongArchMCTargetDesc.h --- a/llvm/lib/Target/LoongArch/MCTargetDesc/LoongArchMCTargetDesc.h +++ b/llvm/lib/Target/LoongArch/MCTargetDesc/LoongArchMCTargetDesc.h @@ -32,7 +32,7 @@ MCAsmBackend *createLoongArchAsmBackend(const Target &T, const MCSubtargetInfo &STI, - const MCRegisterInfo &MRI, + const MCRegisterInfo &MCRI, const MCTargetOptions &Options); std::unique_ptr diff --git a/llvm/lib/Target/LoongArch/MCTargetDesc/LoongArchMCTargetDesc.cpp b/llvm/lib/Target/LoongArch/MCTargetDesc/LoongArchMCTargetDesc.cpp --- a/llvm/lib/Target/LoongArch/MCTargetDesc/LoongArchMCTargetDesc.cpp +++ b/llvm/lib/Target/LoongArch/MCTargetDesc/LoongArchMCTargetDesc.cpp @@ -59,13 +59,13 @@ return createLoongArchMCSubtargetInfoImpl(TT, CPU, /*TuneCPU*/ CPU, FS); } -static MCAsmInfo *createLoongArchMCAsmInfo(const MCRegisterInfo &MRI, +static MCAsmInfo *createLoongArchMCAsmInfo(const MCRegisterInfo &MCRI, const Triple &TT, const MCTargetOptions &Options) { MCAsmInfo *MAI = new LoongArchMCAsmInfo(TT); // Initial state of the frame pointer is sp(r3). - MCRegister SP = MRI.getDwarfRegNum(LoongArch::R3, true); + MCRegister SP = MCRI.getDwarfRegNum(LoongArch::R3, true); MCCFIInstruction Inst = MCCFIInstruction::cfiDefCfa(nullptr, SP, 0); MAI->addInitialFrameState(Inst); @@ -76,8 +76,8 @@ unsigned SyntaxVariant, const MCAsmInfo &MAI, const MCInstrInfo &MII, - const MCRegisterInfo &MRI) { - return new LoongArchInstPrinter(MAI, MII, MRI); + const MCRegisterInfo &MCRI) { + return new LoongArchInstPrinter(MAI, MII, MCRI); } static MCTargetStreamer * diff --git a/llvm/lib/Target/M68k/AsmParser/M68kAsmParser.cpp b/llvm/lib/Target/M68k/AsmParser/M68kAsmParser.cpp --- a/llvm/lib/Target/M68k/AsmParser/M68kAsmParser.cpp +++ b/llvm/lib/Target/M68k/AsmParser/M68kAsmParser.cpp @@ -33,7 +33,7 @@ class M68kAsmParser : public MCTargetAsmParser { const MCSubtargetInfo &STI; MCAsmParser &Parser; - const MCRegisterInfo *MRI; + const MCRegisterInfo *MCRI; #define GET_ASSEMBLER_HEADER #include "M68kGenAsmMatcher.inc" @@ -59,7 +59,7 @@ const MCInstrInfo &MII, const MCTargetOptions &Options) : MCTargetAsmParser(Options, STI, MII), STI(STI), Parser(Parser) { MCAsmParserExtension::Initialize(Parser); - MRI = getContext().getRegisterInfo(); + MCRI = getContext().getRegisterInfo(); setAvailableFeatures(ComputeAvailableFeatures(STI.getFeatureBits())); } diff --git a/llvm/lib/Target/M68k/M68kFrameLowering.cpp b/llvm/lib/Target/M68k/M68kFrameLowering.cpp --- a/llvm/lib/Target/M68k/M68kFrameLowering.cpp +++ b/llvm/lib/Target/M68k/M68kFrameLowering.cpp @@ -453,7 +453,7 @@ MachineFunction &MF = *MBB.getParent(); MachineFrameInfo &MFI = MF.getFrameInfo(); MachineModuleInfo &MMI = MF.getMMI(); - const MCRegisterInfo *MRI = MMI.getContext().getRegisterInfo(); + const MCRegisterInfo *MCRI = MMI.getContext().getRegisterInfo(); // Add callee saved registers to move list. const auto &CSI = MFI.getCalleeSavedInfo(); @@ -465,7 +465,7 @@ int64_t Offset = MFI.getObjectOffset(I.getFrameIdx()); Register Reg = I.getReg(); - unsigned DwarfReg = MRI->getDwarfRegNum(Reg, true); + unsigned DwarfReg = MCRI->getDwarfRegNum(Reg, true); BuildCFI(MBB, MBBI, DL, MCCFIInstruction::createOffset(nullptr, DwarfReg, Offset)); } diff --git a/llvm/lib/Target/M68k/MCTargetDesc/M68kAsmBackend.cpp b/llvm/lib/Target/M68k/MCTargetDesc/M68kAsmBackend.cpp --- a/llvm/lib/Target/M68k/MCTargetDesc/M68kAsmBackend.cpp +++ b/llvm/lib/Target/M68k/MCTargetDesc/M68kAsmBackend.cpp @@ -233,7 +233,7 @@ MCAsmBackend *llvm::createM68kAsmBackend(const Target &T, const MCSubtargetInfo &STI, - const MCRegisterInfo &MRI, + const MCRegisterInfo &MCRI, const MCTargetOptions &Options) { const Triple &TheTriple = STI.getTargetTriple(); uint8_t OSABI = MCELFObjectTargetWriter::getOSABI(TheTriple.getOS()); diff --git a/llvm/lib/Target/M68k/MCTargetDesc/M68kInstPrinter.h b/llvm/lib/Target/M68k/MCTargetDesc/M68kInstPrinter.h --- a/llvm/lib/Target/M68k/MCTargetDesc/M68kInstPrinter.h +++ b/llvm/lib/Target/M68k/MCTargetDesc/M68kInstPrinter.h @@ -23,8 +23,8 @@ class M68kInstPrinter : public MCInstPrinter { public: M68kInstPrinter(const MCAsmInfo &MAI, const MCInstrInfo &MII, - const MCRegisterInfo &MRI) - : MCInstPrinter(MAI, MII, MRI) {} + const MCRegisterInfo &MCRI) + : MCInstPrinter(MAI, MII, MCRI) {} // Autogenerated by tblgen. void printInstruction(const MCInst *MI, uint64_t Address, raw_ostream &O); diff --git a/llvm/lib/Target/M68k/MCTargetDesc/M68kMCTargetDesc.h b/llvm/lib/Target/M68k/MCTargetDesc/M68kMCTargetDesc.h --- a/llvm/lib/Target/M68k/MCTargetDesc/M68kMCTargetDesc.h +++ b/llvm/lib/Target/M68k/MCTargetDesc/M68kMCTargetDesc.h @@ -34,7 +34,7 @@ class raw_pwrite_stream; MCAsmBackend *createM68kAsmBackend(const Target &T, const MCSubtargetInfo &STI, - const MCRegisterInfo &MRI, + const MCRegisterInfo &MCRI, const MCTargetOptions &Options); MCCodeEmitter *createM68kMCCodeEmitter(const MCInstrInfo &MCII, diff --git a/llvm/lib/Target/M68k/MCTargetDesc/M68kMCTargetDesc.cpp b/llvm/lib/Target/M68k/MCTargetDesc/M68kMCTargetDesc.cpp --- a/llvm/lib/Target/M68k/MCTargetDesc/M68kMCTargetDesc.cpp +++ b/llvm/lib/Target/M68k/MCTargetDesc/M68kMCTargetDesc.cpp @@ -70,7 +70,7 @@ return createM68kMCSubtargetInfoImpl(TT, CPU, /*TuneCPU=*/CPU, ArchFS); } -static MCAsmInfo *createM68kMCAsmInfo(const MCRegisterInfo &MRI, +static MCAsmInfo *createM68kMCAsmInfo(const MCRegisterInfo &MCRI, const Triple &TT, const MCTargetOptions &TO) { MCAsmInfo *MAI = new M68kELFMCAsmInfo(TT); @@ -82,12 +82,12 @@ // Initial state of the frame pointer is SP+StackGrowth. // TODO: Add tests for `cfi_*` directives MCCFIInstruction Inst = MCCFIInstruction::cfiDefCfa( - nullptr, MRI.getDwarfRegNum(llvm::M68k::SP, true), -StackGrowth); + nullptr, MCRI.getDwarfRegNum(llvm::M68k::SP, true), -StackGrowth); MAI->addInitialFrameState(Inst); // Add return address to move list Inst = MCCFIInstruction::createOffset( - nullptr, MRI.getDwarfRegNum(M68k::PC, true), StackGrowth); + nullptr, MCRI.getDwarfRegNum(M68k::PC, true), StackGrowth); MAI->addInitialFrameState(Inst); return MAI; @@ -103,8 +103,8 @@ unsigned SyntaxVariant, const MCAsmInfo &MAI, const MCInstrInfo &MII, - const MCRegisterInfo &MRI) { - return new M68kInstPrinter(MAI, MII, MRI); + const MCRegisterInfo &MCRI) { + return new M68kInstPrinter(MAI, MII, MCRI); } extern "C" LLVM_EXTERNAL_VISIBILITY void LLVMInitializeM68kTargetMC() { diff --git a/llvm/lib/Target/MSP430/AsmParser/MSP430AsmParser.cpp b/llvm/lib/Target/MSP430/AsmParser/MSP430AsmParser.cpp --- a/llvm/lib/Target/MSP430/AsmParser/MSP430AsmParser.cpp +++ b/llvm/lib/Target/MSP430/AsmParser/MSP430AsmParser.cpp @@ -38,7 +38,7 @@ class MSP430AsmParser : public MCTargetAsmParser { const MCSubtargetInfo &STI; MCAsmParser &Parser; - const MCRegisterInfo *MRI; + const MCRegisterInfo *MCRI; bool MatchAndEmitInstruction(SMLoc IDLoc, unsigned &Opcode, OperandVector &Operands, MCStreamer &Out, @@ -82,7 +82,7 @@ const MCInstrInfo &MII, const MCTargetOptions &Options) : MCTargetAsmParser(Options, STI, MII), STI(STI), Parser(Parser) { MCAsmParserExtension::Initialize(Parser); - MRI = getContext().getRegisterInfo(); + MCRI = getContext().getRegisterInfo(); setAvailableFeatures(ComputeAvailableFeatures(STI.getFeatureBits())); } diff --git a/llvm/lib/Target/MSP430/MCTargetDesc/MSP430AsmBackend.cpp b/llvm/lib/Target/MSP430/MCTargetDesc/MSP430AsmBackend.cpp --- a/llvm/lib/Target/MSP430/MCTargetDesc/MSP430AsmBackend.cpp +++ b/llvm/lib/Target/MSP430/MCTargetDesc/MSP430AsmBackend.cpp @@ -165,7 +165,7 @@ MCAsmBackend *llvm::createMSP430MCAsmBackend(const Target &T, const MCSubtargetInfo &STI, - const MCRegisterInfo &MRI, + const MCRegisterInfo &MCRI, const MCTargetOptions &Options) { return new MSP430AsmBackend(STI, ELF::ELFOSABI_STANDALONE); } diff --git a/llvm/lib/Target/MSP430/MCTargetDesc/MSP430InstPrinter.h b/llvm/lib/Target/MSP430/MCTargetDesc/MSP430InstPrinter.h --- a/llvm/lib/Target/MSP430/MCTargetDesc/MSP430InstPrinter.h +++ b/llvm/lib/Target/MSP430/MCTargetDesc/MSP430InstPrinter.h @@ -19,8 +19,8 @@ class MSP430InstPrinter : public MCInstPrinter { public: MSP430InstPrinter(const MCAsmInfo &MAI, const MCInstrInfo &MII, - const MCRegisterInfo &MRI) - : MCInstPrinter(MAI, MII, MRI) {} + const MCRegisterInfo &MCRI) + : MCInstPrinter(MAI, MII, MCRI) {} void printInst(const MCInst *MI, uint64_t Address, StringRef Annot, const MCSubtargetInfo &STI, raw_ostream &O) override; diff --git a/llvm/lib/Target/MSP430/MCTargetDesc/MSP430MCTargetDesc.h b/llvm/lib/Target/MSP430/MCTargetDesc/MSP430MCTargetDesc.h --- a/llvm/lib/Target/MSP430/MCTargetDesc/MSP430MCTargetDesc.h +++ b/llvm/lib/Target/MSP430/MCTargetDesc/MSP430MCTargetDesc.h @@ -35,7 +35,7 @@ MCAsmBackend *createMSP430MCAsmBackend(const Target &T, const MCSubtargetInfo &STI, - const MCRegisterInfo &MRI, + const MCRegisterInfo &MCRI, const MCTargetOptions &Options); MCTargetStreamer * diff --git a/llvm/lib/Target/MSP430/MCTargetDesc/MSP430MCTargetDesc.cpp b/llvm/lib/Target/MSP430/MCTargetDesc/MSP430MCTargetDesc.cpp --- a/llvm/lib/Target/MSP430/MCTargetDesc/MSP430MCTargetDesc.cpp +++ b/llvm/lib/Target/MSP430/MCTargetDesc/MSP430MCTargetDesc.cpp @@ -52,9 +52,9 @@ unsigned SyntaxVariant, const MCAsmInfo &MAI, const MCInstrInfo &MII, - const MCRegisterInfo &MRI) { + const MCRegisterInfo &MCRI) { if (SyntaxVariant == 0) - return new MSP430InstPrinter(MAI, MII, MRI); + return new MSP430InstPrinter(MAI, MII, MCRI); return nullptr; } diff --git a/llvm/lib/Target/Mips/MCTargetDesc/MipsAsmBackend.h b/llvm/lib/Target/Mips/MCTargetDesc/MipsAsmBackend.h --- a/llvm/lib/Target/Mips/MCTargetDesc/MipsAsmBackend.h +++ b/llvm/lib/Target/Mips/MCTargetDesc/MipsAsmBackend.h @@ -30,7 +30,7 @@ bool IsN32; public: - MipsAsmBackend(const Target &T, const MCRegisterInfo &MRI, const Triple &TT, + MipsAsmBackend(const Target &T, const MCRegisterInfo &MCRI, const Triple &TT, StringRef CPU, bool N32) : MCAsmBackend(TT.isLittleEndian() ? support::little : support::big), TheTriple(TT), IsN32(N32) {} diff --git a/llvm/lib/Target/Mips/MCTargetDesc/MipsAsmBackend.cpp b/llvm/lib/Target/Mips/MCTargetDesc/MipsAsmBackend.cpp --- a/llvm/lib/Target/Mips/MCTargetDesc/MipsAsmBackend.cpp +++ b/llvm/lib/Target/Mips/MCTargetDesc/MipsAsmBackend.cpp @@ -597,10 +597,10 @@ MCAsmBackend *llvm::createMipsAsmBackend(const Target &T, const MCSubtargetInfo &STI, - const MCRegisterInfo &MRI, + const MCRegisterInfo &MCRI, const MCTargetOptions &Options) { MipsABIInfo ABI = MipsABIInfo::computeTargetABI(STI.getTargetTriple(), STI.getCPU(), Options); - return new MipsAsmBackend(T, MRI, STI.getTargetTriple(), STI.getCPU(), + return new MipsAsmBackend(T, MCRI, STI.getTargetTriple(), STI.getCPU(), ABI.IsN32()); } diff --git a/llvm/lib/Target/Mips/MCTargetDesc/MipsInstPrinter.h b/llvm/lib/Target/Mips/MCTargetDesc/MipsInstPrinter.h --- a/llvm/lib/Target/Mips/MCTargetDesc/MipsInstPrinter.h +++ b/llvm/lib/Target/Mips/MCTargetDesc/MipsInstPrinter.h @@ -75,8 +75,8 @@ class MipsInstPrinter : public MCInstPrinter { public: MipsInstPrinter(const MCAsmInfo &MAI, const MCInstrInfo &MII, - const MCRegisterInfo &MRI) - : MCInstPrinter(MAI, MII, MRI) {} + const MCRegisterInfo &MCRI) + : MCInstPrinter(MAI, MII, MCRI) {} // Autogenerated by tblgen. std::pair getMnemonic(const MCInst *MI) override; diff --git a/llvm/lib/Target/Mips/MCTargetDesc/MipsMCTargetDesc.h b/llvm/lib/Target/Mips/MCTargetDesc/MipsMCTargetDesc.h --- a/llvm/lib/Target/Mips/MCTargetDesc/MipsMCTargetDesc.h +++ b/llvm/lib/Target/Mips/MCTargetDesc/MipsMCTargetDesc.h @@ -36,7 +36,7 @@ MCContext &Ctx); MCAsmBackend *createMipsAsmBackend(const Target &T, const MCSubtargetInfo &STI, - const MCRegisterInfo &MRI, + const MCRegisterInfo &MCRI, const MCTargetOptions &Options); std::unique_ptr diff --git a/llvm/lib/Target/Mips/MCTargetDesc/MipsMCTargetDesc.cpp b/llvm/lib/Target/Mips/MCTargetDesc/MipsMCTargetDesc.cpp --- a/llvm/lib/Target/Mips/MCTargetDesc/MipsMCTargetDesc.cpp +++ b/llvm/lib/Target/Mips/MCTargetDesc/MipsMCTargetDesc.cpp @@ -81,12 +81,12 @@ return createMipsMCSubtargetInfoImpl(TT, CPU, /*TuneCPU*/ CPU, FS); } -static MCAsmInfo *createMipsMCAsmInfo(const MCRegisterInfo &MRI, +static MCAsmInfo *createMipsMCAsmInfo(const MCRegisterInfo &MCRI, const Triple &TT, const MCTargetOptions &Options) { MCAsmInfo *MAI = new MipsMCAsmInfo(TT, Options); - unsigned SP = MRI.getDwarfRegNum(Mips::SP, true); + unsigned SP = MCRI.getDwarfRegNum(Mips::SP, true); MCCFIInstruction Inst = MCCFIInstruction::createDefCfaRegister(nullptr, SP); MAI->addInitialFrameState(Inst); @@ -97,8 +97,8 @@ unsigned SyntaxVariant, const MCAsmInfo &MAI, const MCInstrInfo &MII, - const MCRegisterInfo &MRI) { - return new MipsInstPrinter(MAI, MII, MRI); + const MCRegisterInfo &MCRI) { + return new MipsInstPrinter(MAI, MII, MCRI); } static MCStreamer *createMCStreamer(const Triple &T, MCContext &Context, diff --git a/llvm/lib/Target/Mips/Mips16FrameLowering.cpp b/llvm/lib/Target/Mips/Mips16FrameLowering.cpp --- a/llvm/lib/Target/Mips/Mips16FrameLowering.cpp +++ b/llvm/lib/Target/Mips/Mips16FrameLowering.cpp @@ -56,7 +56,7 @@ if (StackSize == 0 && !MFI.adjustsStack()) return; MachineModuleInfo &MMI = MF.getMMI(); - const MCRegisterInfo *MRI = MMI.getContext().getRegisterInfo(); + const MCRegisterInfo *MCRI = MMI.getContext().getRegisterInfo(); // Adjust stack. TII.makeFrame(Mips::SP, StackSize, MBB, MBBI); @@ -75,7 +75,7 @@ for (const CalleeSavedInfo &I : CSI) { int64_t Offset = MFI.getObjectOffset(I.getFrameIdx()); Register Reg = I.getReg(); - unsigned DReg = MRI->getDwarfRegNum(Reg, true); + unsigned DReg = MCRI->getDwarfRegNum(Reg, true); unsigned CFIIndex = MF.addFrameInst( MCCFIInstruction::createOffset(nullptr, DReg, Offset)); BuildMI(MBB, MBBI, dl, TII.get(TargetOpcode::CFI_INSTRUCTION)) diff --git a/llvm/lib/Target/Mips/MipsSEFrameLowering.cpp b/llvm/lib/Target/Mips/MipsSEFrameLowering.cpp --- a/llvm/lib/Target/Mips/MipsSEFrameLowering.cpp +++ b/llvm/lib/Target/Mips/MipsSEFrameLowering.cpp @@ -428,7 +428,7 @@ if (StackSize == 0 && !MFI.adjustsStack()) return; MachineModuleInfo &MMI = MF.getMMI(); - const MCRegisterInfo *MRI = MMI.getContext().getRegisterInfo(); + const MCRegisterInfo *MCRI = MMI.getContext().getRegisterInfo(); // Adjust stack. TII.adjustStackPtr(SP, -StackSize, MBB, MBBI); @@ -460,9 +460,9 @@ // one for each of the paired single precision registers. if (Mips::AFGR64RegClass.contains(Reg)) { unsigned Reg0 = - MRI->getDwarfRegNum(RegInfo.getSubReg(Reg, Mips::sub_lo), true); + MCRI->getDwarfRegNum(RegInfo.getSubReg(Reg, Mips::sub_lo), true); unsigned Reg1 = - MRI->getDwarfRegNum(RegInfo.getSubReg(Reg, Mips::sub_hi), true); + MCRI->getDwarfRegNum(RegInfo.getSubReg(Reg, Mips::sub_hi), true); if (!STI.isLittle()) std::swap(Reg0, Reg1); @@ -477,8 +477,8 @@ BuildMI(MBB, MBBI, dl, TII.get(TargetOpcode::CFI_INSTRUCTION)) .addCFIIndex(CFIIndex); } else if (Mips::FGR64RegClass.contains(Reg)) { - unsigned Reg0 = MRI->getDwarfRegNum(Reg, true); - unsigned Reg1 = MRI->getDwarfRegNum(Reg, true) + 1; + unsigned Reg0 = MCRI->getDwarfRegNum(Reg, true); + unsigned Reg1 = MCRI->getDwarfRegNum(Reg, true) + 1; if (!STI.isLittle()) std::swap(Reg0, Reg1); @@ -495,7 +495,7 @@ } else { // Reg is either in GPR32 or FGR32. unsigned CFIIndex = MF.addFrameInst(MCCFIInstruction::createOffset( - nullptr, MRI->getDwarfRegNum(Reg, true), Offset)); + nullptr, MCRI->getDwarfRegNum(Reg, true), Offset)); BuildMI(MBB, MBBI, dl, TII.get(TargetOpcode::CFI_INSTRUCTION)) .addCFIIndex(CFIIndex); } @@ -515,7 +515,7 @@ // Emit .cfi_offset directives for eh data registers. for (int I = 0; I < 4; ++I) { int64_t Offset = MFI.getObjectOffset(MipsFI->getEhDataRegFI(I)); - unsigned Reg = MRI->getDwarfRegNum(ABI.GetEhDataReg(I), true); + unsigned Reg = MCRI->getDwarfRegNum(ABI.GetEhDataReg(I), true); unsigned CFIIndex = MF.addFrameInst( MCCFIInstruction::createOffset(nullptr, Reg, Offset)); BuildMI(MBB, MBBI, dl, TII.get(TargetOpcode::CFI_INSTRUCTION)) @@ -531,7 +531,7 @@ // emit ".cfi_def_cfa_register $fp" unsigned CFIIndex = MF.addFrameInst(MCCFIInstruction::createDefCfaRegister( - nullptr, MRI->getDwarfRegNum(FP, true))); + nullptr, MCRI->getDwarfRegNum(FP, true))); BuildMI(MBB, MBBI, dl, TII.get(TargetOpcode::CFI_INSTRUCTION)) .addCFIIndex(CFIIndex); diff --git a/llvm/lib/Target/NVPTX/MCTargetDesc/NVPTXInstPrinter.h b/llvm/lib/Target/NVPTX/MCTargetDesc/NVPTXInstPrinter.h --- a/llvm/lib/Target/NVPTX/MCTargetDesc/NVPTXInstPrinter.h +++ b/llvm/lib/Target/NVPTX/MCTargetDesc/NVPTXInstPrinter.h @@ -22,7 +22,7 @@ class NVPTXInstPrinter : public MCInstPrinter { public: NVPTXInstPrinter(const MCAsmInfo &MAI, const MCInstrInfo &MII, - const MCRegisterInfo &MRI); + const MCRegisterInfo &MCRI); void printRegName(raw_ostream &OS, MCRegister Reg) const override; void printInst(const MCInst *MI, uint64_t Address, StringRef Annot, diff --git a/llvm/lib/Target/NVPTX/MCTargetDesc/NVPTXInstPrinter.cpp b/llvm/lib/Target/NVPTX/MCTargetDesc/NVPTXInstPrinter.cpp --- a/llvm/lib/Target/NVPTX/MCTargetDesc/NVPTXInstPrinter.cpp +++ b/llvm/lib/Target/NVPTX/MCTargetDesc/NVPTXInstPrinter.cpp @@ -28,8 +28,8 @@ #include "NVPTXGenAsmWriter.inc" NVPTXInstPrinter::NVPTXInstPrinter(const MCAsmInfo &MAI, const MCInstrInfo &MII, - const MCRegisterInfo &MRI) - : MCInstPrinter(MAI, MII, MRI) {} + const MCRegisterInfo &MCRI) + : MCInstPrinter(MAI, MII, MCRI) {} void NVPTXInstPrinter::printRegName(raw_ostream &OS, MCRegister Reg) const { // Decode the virtual register diff --git a/llvm/lib/Target/NVPTX/MCTargetDesc/NVPTXMCTargetDesc.cpp b/llvm/lib/Target/NVPTX/MCTargetDesc/NVPTXMCTargetDesc.cpp --- a/llvm/lib/Target/NVPTX/MCTargetDesc/NVPTXMCTargetDesc.cpp +++ b/llvm/lib/Target/NVPTX/MCTargetDesc/NVPTXMCTargetDesc.cpp @@ -54,9 +54,9 @@ unsigned SyntaxVariant, const MCAsmInfo &MAI, const MCInstrInfo &MII, - const MCRegisterInfo &MRI) { + const MCRegisterInfo &MCRI) { if (SyntaxVariant == 0) - return new NVPTXInstPrinter(MAI, MII, MRI); + return new NVPTXInstPrinter(MAI, MII, MCRI); return nullptr; } diff --git a/llvm/lib/Target/PowerPC/MCTargetDesc/PPCAsmBackend.cpp b/llvm/lib/Target/PowerPC/MCTargetDesc/PPCAsmBackend.cpp --- a/llvm/lib/Target/PowerPC/MCTargetDesc/PPCAsmBackend.cpp +++ b/llvm/lib/Target/PowerPC/MCTargetDesc/PPCAsmBackend.cpp @@ -274,7 +274,7 @@ MCAsmBackend *llvm::createPPCAsmBackend(const Target &T, const MCSubtargetInfo &STI, - const MCRegisterInfo &MRI, + const MCRegisterInfo &MCRI, const MCTargetOptions &Options) { const Triple &TT = STI.getTargetTriple(); if (TT.isOSBinFormatXCOFF()) diff --git a/llvm/lib/Target/PowerPC/MCTargetDesc/PPCInstPrinter.h b/llvm/lib/Target/PowerPC/MCTargetDesc/PPCInstPrinter.h --- a/llvm/lib/Target/PowerPC/MCTargetDesc/PPCInstPrinter.h +++ b/llvm/lib/Target/PowerPC/MCTargetDesc/PPCInstPrinter.h @@ -28,8 +28,8 @@ public: PPCInstPrinter(const MCAsmInfo &MAI, const MCInstrInfo &MII, - const MCRegisterInfo &MRI, Triple T) - : MCInstPrinter(MAI, MII, MRI), TT(T) {} + const MCRegisterInfo &MCRI, Triple T) + : MCInstPrinter(MAI, MII, MCRI), TT(T) {} void printRegName(raw_ostream &OS, MCRegister Reg) const override; void printInst(const MCInst *MI, uint64_t Address, StringRef Annot, diff --git a/llvm/lib/Target/PowerPC/MCTargetDesc/PPCInstPrinter.cpp b/llvm/lib/Target/PowerPC/MCTargetDesc/PPCInstPrinter.cpp --- a/llvm/lib/Target/PowerPC/MCTargetDesc/PPCInstPrinter.cpp +++ b/llvm/lib/Target/PowerPC/MCTargetDesc/PPCInstPrinter.cpp @@ -644,7 +644,7 @@ Reg, OpNo); const char *RegName; - RegName = getVerboseConditionRegName(Reg, MRI.getEncodingValue(Reg)); + RegName = getVerboseConditionRegName(Reg, MCRI.getEncodingValue(Reg)); if (RegName == nullptr) RegName = getRegisterName(Reg); if (showRegistersWithPercentPrefix(RegName)) diff --git a/llvm/lib/Target/PowerPC/MCTargetDesc/PPCMCTargetDesc.h b/llvm/lib/Target/PowerPC/MCTargetDesc/PPCMCTargetDesc.h --- a/llvm/lib/Target/PowerPC/MCTargetDesc/PPCMCTargetDesc.h +++ b/llvm/lib/Target/PowerPC/MCTargetDesc/PPCMCTargetDesc.h @@ -37,7 +37,7 @@ MCContext &Ctx); MCAsmBackend *createPPCAsmBackend(const Target &T, const MCSubtargetInfo &STI, - const MCRegisterInfo &MRI, + const MCRegisterInfo &MCRI, const MCTargetOptions &Options); /// Construct an PPC ELF object writer. diff --git a/llvm/lib/Target/PowerPC/MCTargetDesc/PPCMCTargetDesc.cpp b/llvm/lib/Target/PowerPC/MCTargetDesc/PPCMCTargetDesc.cpp --- a/llvm/lib/Target/PowerPC/MCTargetDesc/PPCMCTargetDesc.cpp +++ b/llvm/lib/Target/PowerPC/MCTargetDesc/PPCMCTargetDesc.cpp @@ -94,7 +94,7 @@ return createPPCMCSubtargetInfoImpl(TT, CPU, /*TuneCPU*/ CPU, FullFS); } -static MCAsmInfo *createPPCMCAsmInfo(const MCRegisterInfo &MRI, +static MCAsmInfo *createPPCMCAsmInfo(const MCRegisterInfo &MCRI, const Triple &TheTriple, const MCTargetOptions &Options) { bool isPPC64 = (TheTriple.getArch() == Triple::ppc64 || @@ -109,7 +109,7 @@ // Initial state of the frame pointer is R1. unsigned Reg = isPPC64 ? PPC::X1 : PPC::R1; MCCFIInstruction Inst = - MCCFIInstruction::cfiDefCfa(nullptr, MRI.getDwarfRegNum(Reg, true), 0); + MCCFIInstruction::cfiDefCfa(nullptr, MCRI.getDwarfRegNum(Reg, true), 0); MAI->addInitialFrameState(Inst); return MAI; @@ -370,8 +370,8 @@ unsigned SyntaxVariant, const MCAsmInfo &MAI, const MCInstrInfo &MII, - const MCRegisterInfo &MRI) { - return new PPCInstPrinter(MAI, MII, MRI, T); + const MCRegisterInfo &MCRI) { + return new PPCInstPrinter(MAI, MII, MCRI, T); } namespace { diff --git a/llvm/lib/Target/PowerPC/PPCFrameLowering.cpp b/llvm/lib/Target/PowerPC/PPCFrameLowering.cpp --- a/llvm/lib/Target/PowerPC/PPCFrameLowering.cpp +++ b/llvm/lib/Target/PowerPC/PPCFrameLowering.cpp @@ -611,7 +611,7 @@ const PPCTargetLowering &TLI = *Subtarget.getTargetLowering(); MachineModuleInfo &MMI = MF.getMMI(); - const MCRegisterInfo *MRI = MMI.getContext().getRegisterInfo(); + const MCRegisterInfo *MCRI = MMI.getContext().getRegisterInfo(); DebugLoc dl; // AIX assembler does not support cfi directives. const bool needsCFI = MF.needsFrameMoves() && !Subtarget.isAIXABI(); @@ -1109,7 +1109,7 @@ // Define CFA in terms of BP. Do this in preference to using FP/SP, // because if the stack needed aligning then CFA won't be at a fixed // offset from FP/SP. - unsigned Reg = MRI->getDwarfRegNum(BPReg, true); + unsigned Reg = MCRI->getDwarfRegNum(BPReg, true); CFIIndex = MF.addFrameInst( MCCFIInstruction::createDefCfaRegister(nullptr, Reg)); } else { @@ -1123,7 +1123,7 @@ if (HasFP) { // Describe where FP was saved, at a fixed offset from CFA. - unsigned Reg = MRI->getDwarfRegNum(FPReg, true); + unsigned Reg = MCRI->getDwarfRegNum(FPReg, true); CFIIndex = MF.addFrameInst( MCCFIInstruction::createOffset(nullptr, Reg, FPOffset)); BuildMI(MBB, MBBI, dl, TII.get(TargetOpcode::CFI_INSTRUCTION)) @@ -1132,7 +1132,7 @@ if (FI->usesPICBase()) { // Describe where FP was saved, at a fixed offset from CFA. - unsigned Reg = MRI->getDwarfRegNum(PPC::R30, true); + unsigned Reg = MCRI->getDwarfRegNum(PPC::R30, true); CFIIndex = MF.addFrameInst( MCCFIInstruction::createOffset(nullptr, Reg, PBPOffset)); BuildMI(MBB, MBBI, dl, TII.get(TargetOpcode::CFI_INSTRUCTION)) @@ -1141,7 +1141,7 @@ if (HasBP) { // Describe where BP was saved, at a fixed offset from CFA. - unsigned Reg = MRI->getDwarfRegNum(BPReg, true); + unsigned Reg = MCRI->getDwarfRegNum(BPReg, true); CFIIndex = MF.addFrameInst( MCCFIInstruction::createOffset(nullptr, Reg, BPOffset)); BuildMI(MBB, MBBI, dl, TII.get(TargetOpcode::CFI_INSTRUCTION)) @@ -1150,7 +1150,7 @@ if (MustSaveLR) { // Describe where LR was saved, at a fixed offset from CFA. - unsigned Reg = MRI->getDwarfRegNum(LRReg, true); + unsigned Reg = MCRI->getDwarfRegNum(LRReg, true); CFIIndex = MF.addFrameInst( MCCFIInstruction::createOffset(nullptr, Reg, LROffset)); BuildMI(MBB, MBBI, dl, TII.get(TargetOpcode::CFI_INSTRUCTION)) @@ -1167,7 +1167,7 @@ if (!HasBP && needsCFI) { // Change the definition of CFA from SP+offset to FP+offset, because SP // will change at every alloca. - unsigned Reg = MRI->getDwarfRegNum(FPReg, true); + unsigned Reg = MCRI->getDwarfRegNum(FPReg, true); unsigned CFIIndex = MF.addFrameInst( MCCFIInstruction::createDefCfaRegister(nullptr, Reg)); @@ -1206,7 +1206,7 @@ // actually saved gets its own CFI record. Register CRReg = isELFv2ABI? Reg : PPC::CR2; unsigned CFIIndex = MF.addFrameInst(MCCFIInstruction::createOffset( - nullptr, MRI->getDwarfRegNum(CRReg, true), CRSaveOffset)); + nullptr, MCRI->getDwarfRegNum(CRReg, true), CRSaveOffset)); BuildMI(MBB, MBBI, dl, TII.get(TargetOpcode::CFI_INSTRUCTION)) .addCFIIndex(CFIIndex); continue; @@ -1215,8 +1215,8 @@ if (I.isSpilledToReg()) { unsigned SpilledReg = I.getDstReg(); unsigned CFIRegister = MF.addFrameInst(MCCFIInstruction::createRegister( - nullptr, MRI->getDwarfRegNum(Reg, true), - MRI->getDwarfRegNum(SpilledReg, true))); + nullptr, MCRI->getDwarfRegNum(Reg, true), + MCRI->getDwarfRegNum(SpilledReg, true))); BuildMI(MBB, MBBI, dl, TII.get(TargetOpcode::CFI_INSTRUCTION)) .addCFIIndex(CFIRegister); } else { @@ -1228,7 +1228,7 @@ Offset -= NegFrameSize; unsigned CFIIndex = MF.addFrameInst(MCCFIInstruction::createOffset( - nullptr, MRI->getDwarfRegNum(Reg, true), Offset)); + nullptr, MCRI->getDwarfRegNum(Reg, true), Offset)); BuildMI(MBB, MBBI, dl, TII.get(TargetOpcode::CFI_INSTRUCTION)) .addCFIIndex(CFIIndex); } @@ -1243,7 +1243,7 @@ const PPCInstrInfo &TII = *Subtarget.getInstrInfo(); MachineFrameInfo &MFI = MF.getFrameInfo(); MachineModuleInfo &MMI = MF.getMMI(); - const MCRegisterInfo *MRI = MMI.getContext().getRegisterInfo(); + const MCRegisterInfo *MCRI = MMI.getContext().getRegisterInfo(); // AIX assembler does not support cfi directives. const bool needsCFI = MF.needsFrameMoves() && !Subtarget.isAIXABI(); auto StackAllocMIPos = llvm::find_if(PrologMBB, [](MachineInstr &MI) { @@ -1274,7 +1274,7 @@ // Subroutines to generate .cfi_* directives. auto buildDefCFAReg = [&](MachineBasicBlock &MBB, MachineBasicBlock::iterator MBBI, Register Reg) { - unsigned RegNum = MRI->getDwarfRegNum(Reg, true); + unsigned RegNum = MCRI->getDwarfRegNum(Reg, true); unsigned CFIIndex = MF.addFrameInst( MCCFIInstruction::createDefCfaRegister(nullptr, RegNum)); BuildMI(MBB, MBBI, DL, TII.get(TargetOpcode::CFI_INSTRUCTION)) @@ -1283,7 +1283,7 @@ auto buildDefCFA = [&](MachineBasicBlock &MBB, MachineBasicBlock::iterator MBBI, Register Reg, int Offset) { - unsigned RegNum = MRI->getDwarfRegNum(Reg, true); + unsigned RegNum = MCRI->getDwarfRegNum(Reg, true); unsigned CFIIndex = MBB.getParent()->addFrameInst( MCCFIInstruction::cfiDefCfa(nullptr, RegNum, Offset)); BuildMI(MBB, MBBI, DL, TII.get(TargetOpcode::CFI_INSTRUCTION)) diff --git a/llvm/lib/Target/RISCV/MCTargetDesc/RISCVAsmBackend.cpp b/llvm/lib/Target/RISCV/MCTargetDesc/RISCVAsmBackend.cpp --- a/llvm/lib/Target/RISCV/MCTargetDesc/RISCVAsmBackend.cpp +++ b/llvm/lib/Target/RISCV/MCTargetDesc/RISCVAsmBackend.cpp @@ -630,7 +630,7 @@ MCAsmBackend *llvm::createRISCVAsmBackend(const Target &T, const MCSubtargetInfo &STI, - const MCRegisterInfo &MRI, + const MCRegisterInfo &MCRI, const MCTargetOptions &Options) { const Triple &TT = STI.getTargetTriple(); uint8_t OSABI = MCELFObjectTargetWriter::getOSABI(TT.getOS()); diff --git a/llvm/lib/Target/RISCV/MCTargetDesc/RISCVInstPrinter.h b/llvm/lib/Target/RISCV/MCTargetDesc/RISCVInstPrinter.h --- a/llvm/lib/Target/RISCV/MCTargetDesc/RISCVInstPrinter.h +++ b/llvm/lib/Target/RISCV/MCTargetDesc/RISCVInstPrinter.h @@ -21,8 +21,8 @@ class RISCVInstPrinter : public MCInstPrinter { public: RISCVInstPrinter(const MCAsmInfo &MAI, const MCInstrInfo &MII, - const MCRegisterInfo &MRI) - : MCInstPrinter(MAI, MII, MRI) {} + const MCRegisterInfo &MCRI) + : MCInstPrinter(MAI, MII, MCRI) {} bool applyTargetSpecificCLOption(StringRef Opt) override; diff --git a/llvm/lib/Target/RISCV/MCTargetDesc/RISCVMCTargetDesc.h b/llvm/lib/Target/RISCV/MCTargetDesc/RISCVMCTargetDesc.h --- a/llvm/lib/Target/RISCV/MCTargetDesc/RISCVMCTargetDesc.h +++ b/llvm/lib/Target/RISCV/MCTargetDesc/RISCVMCTargetDesc.h @@ -32,7 +32,7 @@ MCContext &Ctx); MCAsmBackend *createRISCVAsmBackend(const Target &T, const MCSubtargetInfo &STI, - const MCRegisterInfo &MRI, + const MCRegisterInfo &MCRI, const MCTargetOptions &Options); std::unique_ptr createRISCVELFObjectWriter(uint8_t OSABI, diff --git a/llvm/lib/Target/RISCV/MCTargetDesc/RISCVMCTargetDesc.cpp b/llvm/lib/Target/RISCV/MCTargetDesc/RISCVMCTargetDesc.cpp --- a/llvm/lib/Target/RISCV/MCTargetDesc/RISCVMCTargetDesc.cpp +++ b/llvm/lib/Target/RISCV/MCTargetDesc/RISCVMCTargetDesc.cpp @@ -56,12 +56,12 @@ return X; } -static MCAsmInfo *createRISCVMCAsmInfo(const MCRegisterInfo &MRI, +static MCAsmInfo *createRISCVMCAsmInfo(const MCRegisterInfo &MCRI, const Triple &TT, const MCTargetOptions &Options) { MCAsmInfo *MAI = new RISCVMCAsmInfo(TT); - MCRegister SP = MRI.getDwarfRegNum(RISCV::X2, true); + MCRegister SP = MCRI.getDwarfRegNum(RISCV::X2, true); MCCFIInstruction Inst = MCCFIInstruction::cfiDefCfa(nullptr, SP, 0); MAI->addInitialFrameState(Inst); @@ -88,8 +88,8 @@ unsigned SyntaxVariant, const MCAsmInfo &MAI, const MCInstrInfo &MII, - const MCRegisterInfo &MRI) { - return new RISCVInstPrinter(MAI, MII, MRI); + const MCRegisterInfo &MCRI) { + return new RISCVInstPrinter(MAI, MII, MCRI); } static MCTargetStreamer * diff --git a/llvm/lib/Target/SPIRV/MCTargetDesc/SPIRVAsmBackend.cpp b/llvm/lib/Target/SPIRV/MCTargetDesc/SPIRVAsmBackend.cpp --- a/llvm/lib/Target/SPIRV/MCTargetDesc/SPIRVAsmBackend.cpp +++ b/llvm/lib/Target/SPIRV/MCTargetDesc/SPIRVAsmBackend.cpp @@ -57,7 +57,7 @@ MCAsmBackend *llvm::createSPIRVAsmBackend(const Target &T, const MCSubtargetInfo &STI, - const MCRegisterInfo &MRI, + const MCRegisterInfo &MCRI, const MCTargetOptions &) { return new SPIRVAsmBackend(support::little); } diff --git a/llvm/lib/Target/SPIRV/MCTargetDesc/SPIRVMCTargetDesc.h b/llvm/lib/Target/SPIRV/MCTargetDesc/SPIRVMCTargetDesc.h --- a/llvm/lib/Target/SPIRV/MCTargetDesc/SPIRVMCTargetDesc.h +++ b/llvm/lib/Target/SPIRV/MCTargetDesc/SPIRVMCTargetDesc.h @@ -31,7 +31,7 @@ MCContext &Ctx); MCAsmBackend *createSPIRVAsmBackend(const Target &T, const MCSubtargetInfo &STI, - const MCRegisterInfo &MRI, + const MCRegisterInfo &MCRI, const MCTargetOptions &Options); std::unique_ptr createSPIRVObjectTargetWriter(); diff --git a/llvm/lib/Target/SPIRV/MCTargetDesc/SPIRVMCTargetDesc.cpp b/llvm/lib/Target/SPIRV/MCTargetDesc/SPIRVMCTargetDesc.cpp --- a/llvm/lib/Target/SPIRV/MCTargetDesc/SPIRVMCTargetDesc.cpp +++ b/llvm/lib/Target/SPIRV/MCTargetDesc/SPIRVMCTargetDesc.cpp @@ -68,9 +68,9 @@ unsigned SyntaxVariant, const MCAsmInfo &MAI, const MCInstrInfo &MII, - const MCRegisterInfo &MRI) { + const MCRegisterInfo &MCRI) { assert(SyntaxVariant == 0); - return new SPIRVInstPrinter(MAI, MII, MRI); + return new SPIRVInstPrinter(MAI, MII, MCRI); } namespace { diff --git a/llvm/lib/Target/Sparc/MCTargetDesc/SparcAsmBackend.cpp b/llvm/lib/Target/Sparc/MCTargetDesc/SparcAsmBackend.cpp --- a/llvm/lib/Target/Sparc/MCTargetDesc/SparcAsmBackend.cpp +++ b/llvm/lib/Target/Sparc/MCTargetDesc/SparcAsmBackend.cpp @@ -370,7 +370,7 @@ MCAsmBackend *llvm::createSparcAsmBackend(const Target &T, const MCSubtargetInfo &STI, - const MCRegisterInfo &MRI, + const MCRegisterInfo &MCRI, const MCTargetOptions &Options) { return new ELFSparcAsmBackend(T, STI.getTargetTriple().getOS()); } diff --git a/llvm/lib/Target/Sparc/MCTargetDesc/SparcInstPrinter.h b/llvm/lib/Target/Sparc/MCTargetDesc/SparcInstPrinter.h --- a/llvm/lib/Target/Sparc/MCTargetDesc/SparcInstPrinter.h +++ b/llvm/lib/Target/Sparc/MCTargetDesc/SparcInstPrinter.h @@ -20,8 +20,8 @@ class SparcInstPrinter : public MCInstPrinter { public: SparcInstPrinter(const MCAsmInfo &MAI, const MCInstrInfo &MII, - const MCRegisterInfo &MRI) - : MCInstPrinter(MAI, MII, MRI) {} + const MCRegisterInfo &MCRI) + : MCInstPrinter(MAI, MII, MCRI) {} void printRegName(raw_ostream &OS, MCRegister Reg) const override; void printInst(const MCInst *MI, uint64_t Address, StringRef Annot, diff --git a/llvm/lib/Target/Sparc/MCTargetDesc/SparcMCTargetDesc.h b/llvm/lib/Target/Sparc/MCTargetDesc/SparcMCTargetDesc.h --- a/llvm/lib/Target/Sparc/MCTargetDesc/SparcMCTargetDesc.h +++ b/llvm/lib/Target/Sparc/MCTargetDesc/SparcMCTargetDesc.h @@ -31,7 +31,7 @@ MCCodeEmitter *createSparcMCCodeEmitter(const MCInstrInfo &MCII, MCContext &Ctx); MCAsmBackend *createSparcAsmBackend(const Target &T, const MCSubtargetInfo &STI, - const MCRegisterInfo &MRI, + const MCRegisterInfo &MCRI, const MCTargetOptions &Options); std::unique_ptr createSparcELFObjectWriter(bool Is64Bit, uint8_t OSABI); diff --git a/llvm/lib/Target/Sparc/MCTargetDesc/SparcMCTargetDesc.cpp b/llvm/lib/Target/Sparc/MCTargetDesc/SparcMCTargetDesc.cpp --- a/llvm/lib/Target/Sparc/MCTargetDesc/SparcMCTargetDesc.cpp +++ b/llvm/lib/Target/Sparc/MCTargetDesc/SparcMCTargetDesc.cpp @@ -33,21 +33,21 @@ #define GET_REGINFO_MC_DESC #include "SparcGenRegisterInfo.inc" -static MCAsmInfo *createSparcMCAsmInfo(const MCRegisterInfo &MRI, +static MCAsmInfo *createSparcMCAsmInfo(const MCRegisterInfo &MCRI, const Triple &TT, const MCTargetOptions &Options) { MCAsmInfo *MAI = new SparcELFMCAsmInfo(TT); - unsigned Reg = MRI.getDwarfRegNum(SP::O6, true); + unsigned Reg = MCRI.getDwarfRegNum(SP::O6, true); MCCFIInstruction Inst = MCCFIInstruction::cfiDefCfa(nullptr, Reg, 0); MAI->addInitialFrameState(Inst); return MAI; } -static MCAsmInfo *createSparcV9MCAsmInfo(const MCRegisterInfo &MRI, +static MCAsmInfo *createSparcV9MCAsmInfo(const MCRegisterInfo &MCRI, const Triple &TT, const MCTargetOptions &Options) { MCAsmInfo *MAI = new SparcELFMCAsmInfo(TT); - unsigned Reg = MRI.getDwarfRegNum(SP::O6, true); + unsigned Reg = MCRI.getDwarfRegNum(SP::O6, true); MCCFIInstruction Inst = MCCFIInstruction::cfiDefCfa(nullptr, Reg, 2047); MAI->addInitialFrameState(Inst); return MAI; @@ -92,8 +92,8 @@ unsigned SyntaxVariant, const MCAsmInfo &MAI, const MCInstrInfo &MII, - const MCRegisterInfo &MRI) { - return new SparcInstPrinter(MAI, MII, MRI); + const MCRegisterInfo &MCRI) { + return new SparcInstPrinter(MAI, MII, MCRI); } extern "C" LLVM_EXTERNAL_VISIBILITY void LLVMInitializeSparcTargetMC() { diff --git a/llvm/lib/Target/SystemZ/MCTargetDesc/SystemZInstPrinter.h b/llvm/lib/Target/SystemZ/MCTargetDesc/SystemZInstPrinter.h --- a/llvm/lib/Target/SystemZ/MCTargetDesc/SystemZInstPrinter.h +++ b/llvm/lib/Target/SystemZ/MCTargetDesc/SystemZInstPrinter.h @@ -24,8 +24,8 @@ class SystemZInstPrinter : public MCInstPrinter { public: SystemZInstPrinter(const MCAsmInfo &MAI, const MCInstrInfo &MII, - const MCRegisterInfo &MRI) - : MCInstPrinter(MAI, MII, MRI) {} + const MCRegisterInfo &MCRI) + : MCInstPrinter(MAI, MII, MCRI) {} // Automatically generated by tblgen. std::pair getMnemonic(const MCInst *MI) override; diff --git a/llvm/lib/Target/SystemZ/MCTargetDesc/SystemZMCAsmBackend.cpp b/llvm/lib/Target/SystemZ/MCTargetDesc/SystemZMCAsmBackend.cpp --- a/llvm/lib/Target/SystemZ/MCTargetDesc/SystemZMCAsmBackend.cpp +++ b/llvm/lib/Target/SystemZ/MCTargetDesc/SystemZMCAsmBackend.cpp @@ -194,7 +194,7 @@ MCAsmBackend *llvm::createSystemZMCAsmBackend(const Target &T, const MCSubtargetInfo &STI, - const MCRegisterInfo &MRI, + const MCRegisterInfo &MCRI, const MCTargetOptions &Options) { uint8_t OSABI = MCELFObjectTargetWriter::getOSABI(STI.getTargetTriple().getOS()); diff --git a/llvm/lib/Target/SystemZ/MCTargetDesc/SystemZMCTargetDesc.h b/llvm/lib/Target/SystemZ/MCTargetDesc/SystemZMCTargetDesc.h --- a/llvm/lib/Target/SystemZ/MCTargetDesc/SystemZMCTargetDesc.h +++ b/llvm/lib/Target/SystemZ/MCTargetDesc/SystemZMCTargetDesc.h @@ -82,7 +82,7 @@ MCAsmBackend *createSystemZMCAsmBackend(const Target &T, const MCSubtargetInfo &STI, - const MCRegisterInfo &MRI, + const MCRegisterInfo &MCRI, const MCTargetOptions &Options); std::unique_ptr createSystemZObjectWriter(uint8_t OSABI); diff --git a/llvm/lib/Target/SystemZ/MCTargetDesc/SystemZMCTargetDesc.cpp b/llvm/lib/Target/SystemZ/MCTargetDesc/SystemZMCTargetDesc.cpp --- a/llvm/lib/Target/SystemZ/MCTargetDesc/SystemZMCTargetDesc.cpp +++ b/llvm/lib/Target/SystemZ/MCTargetDesc/SystemZMCTargetDesc.cpp @@ -150,7 +150,7 @@ return Map[Reg]; } -static MCAsmInfo *createSystemZMCAsmInfo(const MCRegisterInfo &MRI, +static MCAsmInfo *createSystemZMCAsmInfo(const MCRegisterInfo &MCRI, const Triple &TT, const MCTargetOptions &Options) { if (TT.isOSzOS()) @@ -158,7 +158,7 @@ MCAsmInfo *MAI = new SystemZMCAsmInfoELF(TT); MCCFIInstruction Inst = MCCFIInstruction::cfiDefCfa( - nullptr, MRI.getDwarfRegNum(SystemZ::R15D, true), + nullptr, MCRI.getDwarfRegNum(SystemZ::R15D, true), SystemZMC::ELFCFAOffsetFromInitialSP); MAI->addInitialFrameState(Inst); return MAI; @@ -185,8 +185,8 @@ unsigned SyntaxVariant, const MCAsmInfo &MAI, const MCInstrInfo &MII, - const MCRegisterInfo &MRI) { - return new SystemZInstPrinter(MAI, MII, MRI); + const MCRegisterInfo &MCRI) { + return new SystemZInstPrinter(MAI, MII, MCRI); } void SystemZTargetStreamer::emitConstantPools() { diff --git a/llvm/lib/Target/SystemZ/SystemZAsmPrinter.cpp b/llvm/lib/Target/SystemZ/SystemZAsmPrinter.cpp --- a/llvm/lib/Target/SystemZ/SystemZAsmPrinter.cpp +++ b/llvm/lib/Target/SystemZ/SystemZAsmPrinter.cpp @@ -837,14 +837,14 @@ bool SystemZAsmPrinter::PrintAsmOperand(const MachineInstr *MI, unsigned OpNo, const char *ExtraCode, raw_ostream &OS) { - const MCRegisterInfo &MRI = *TM.getMCRegisterInfo(); + const MCRegisterInfo &MCRI = *TM.getMCRegisterInfo(); const MachineOperand &MO = MI->getOperand(OpNo); MCOperand MCOp; if (ExtraCode) { if (ExtraCode[0] == 'N' && !ExtraCode[1] && MO.isReg() && SystemZ::GR128BitRegClass.contains(MO.getReg())) - MCOp = - MCOperand::createReg(MRI.getSubReg(MO.getReg(), SystemZ::subreg_l64)); + MCOp = MCOperand::createReg( + MCRI.getSubReg(MO.getReg(), SystemZ::subreg_l64)); else return AsmPrinter::PrintAsmOperand(MI, OpNo, ExtraCode, OS); } else { diff --git a/llvm/lib/Target/SystemZ/SystemZFrameLowering.cpp b/llvm/lib/Target/SystemZ/SystemZFrameLowering.cpp --- a/llvm/lib/Target/SystemZ/SystemZFrameLowering.cpp +++ b/llvm/lib/Target/SystemZ/SystemZFrameLowering.cpp @@ -527,8 +527,8 @@ const SystemZInstrInfo *ZII) { MachineFunction &MF = *MBB.getParent(); MachineModuleInfo &MMI = MF.getMMI(); - const MCRegisterInfo *MRI = MMI.getContext().getRegisterInfo(); - unsigned RegNum = MRI->getDwarfRegNum(Reg, true); + const MCRegisterInfo *MCRI = MMI.getContext().getRegisterInfo(); + unsigned RegNum = MCRI->getDwarfRegNum(Reg, true); unsigned CFIIndex = MF.addFrameInst( MCCFIInstruction::createDefCfaRegister(nullptr, RegNum)); BuildMI(MBB, MBBI, DL, ZII->get(TargetOpcode::CFI_INSTRUCTION)) @@ -545,7 +545,7 @@ SystemZMachineFunctionInfo *ZFI = MF.getInfo(); MachineBasicBlock::iterator MBBI = MBB.begin(); MachineModuleInfo &MMI = MF.getMMI(); - const MCRegisterInfo *MRI = MMI.getContext().getRegisterInfo(); + const MCRegisterInfo *MCRI = MMI.getContext().getRegisterInfo(); const std::vector &CSI = MFFrame.getCalleeSavedInfo(); bool HasFP = hasFP(MF); @@ -587,7 +587,7 @@ int FI = Save.getFrameIdx(); int64_t Offset = MFFrame.getObjectOffset(FI); unsigned CFIIndex = MF.addFrameInst(MCCFIInstruction::createOffset( - nullptr, MRI->getDwarfRegNum(Reg, true), Offset)); + nullptr, MCRI->getDwarfRegNum(Reg, true), Offset)); BuildMI(MBB, MBBI, DL, ZII->get(TargetOpcode::CFI_INSTRUCTION)) .addCFIIndex(CFIIndex); } @@ -680,7 +680,7 @@ continue; // Add CFI for the this save. - unsigned DwarfReg = MRI->getDwarfRegNum(Reg, true); + unsigned DwarfReg = MCRI->getDwarfRegNum(Reg, true); Register IgnoredFrameReg; int64_t Offset = getFrameIndexReference(MF, Save.getFrameIdx(), IgnoredFrameReg) diff --git a/llvm/lib/Target/TargetMachine.cpp b/llvm/lib/Target/TargetMachine.cpp --- a/llvm/lib/Target/TargetMachine.cpp +++ b/llvm/lib/Target/TargetMachine.cpp @@ -33,7 +33,7 @@ const TargetOptions &Options) : TheTarget(T), DL(DataLayoutString), TargetTriple(TT), TargetCPU(std::string(CPU)), TargetFS(std::string(FS)), AsmInfo(nullptr), - MRI(nullptr), MII(nullptr), STI(nullptr), RequireStructuredCFG(false), + MCRI(nullptr), MII(nullptr), STI(nullptr), RequireStructuredCFG(false), O0WantsFastISel(false), DefaultOptions(Options), Options(Options) {} TargetMachine::~TargetMachine() = default; diff --git a/llvm/lib/Target/VE/MCTargetDesc/VEAsmBackend.cpp b/llvm/lib/Target/VE/MCTargetDesc/VEAsmBackend.cpp --- a/llvm/lib/Target/VE/MCTargetDesc/VEAsmBackend.cpp +++ b/llvm/lib/Target/VE/MCTargetDesc/VEAsmBackend.cpp @@ -222,7 +222,7 @@ MCAsmBackend *llvm::createVEAsmBackend(const Target &T, const MCSubtargetInfo &STI, - const MCRegisterInfo &MRI, + const MCRegisterInfo &MCRI, const MCTargetOptions &Options) { return new ELFVEAsmBackend(T, STI.getTargetTriple().getOS()); } diff --git a/llvm/lib/Target/VE/MCTargetDesc/VEInstPrinter.h b/llvm/lib/Target/VE/MCTargetDesc/VEInstPrinter.h --- a/llvm/lib/Target/VE/MCTargetDesc/VEInstPrinter.h +++ b/llvm/lib/Target/VE/MCTargetDesc/VEInstPrinter.h @@ -21,8 +21,8 @@ class VEInstPrinter : public MCInstPrinter { public: VEInstPrinter(const MCAsmInfo &MAI, const MCInstrInfo &MII, - const MCRegisterInfo &MRI) - : MCInstPrinter(MAI, MII, MRI) {} + const MCRegisterInfo &MCRI) + : MCInstPrinter(MAI, MII, MCRI) {} void printRegName(raw_ostream &OS, MCRegister Reg) const override; void printInst(const MCInst *MI, uint64_t Address, StringRef Annot, diff --git a/llvm/lib/Target/VE/MCTargetDesc/VEInstPrinter.cpp b/llvm/lib/Target/VE/MCTargetDesc/VEInstPrinter.cpp --- a/llvm/lib/Target/VE/MCTargetDesc/VEInstPrinter.cpp +++ b/llvm/lib/Target/VE/MCTargetDesc/VEInstPrinter.cpp @@ -31,7 +31,7 @@ // Generic registers have identical register name among register classes. unsigned AltIdx = VE::AsmName; // Misc registers have each own name, so no use alt-names. - if (MRI.getRegClass(VE::MISCRegClassID).contains(Reg)) + if (MCRI.getRegClass(VE::MISCRegClassID).contains(Reg)) AltIdx = VE::NoRegAltName; OS << '%' << getRegisterName(Reg, AltIdx); } diff --git a/llvm/lib/Target/VE/MCTargetDesc/VEMCTargetDesc.h b/llvm/lib/Target/VE/MCTargetDesc/VEMCTargetDesc.h --- a/llvm/lib/Target/VE/MCTargetDesc/VEMCTargetDesc.h +++ b/llvm/lib/Target/VE/MCTargetDesc/VEMCTargetDesc.h @@ -30,7 +30,7 @@ MCCodeEmitter *createVEMCCodeEmitter(const MCInstrInfo &MCII, MCContext &Ctx); MCAsmBackend *createVEAsmBackend(const Target &T, const MCSubtargetInfo &STI, - const MCRegisterInfo &MRI, + const MCRegisterInfo &MCRI, const MCTargetOptions &Options); std::unique_ptr createVEELFObjectWriter(uint8_t OSABI); } // namespace llvm diff --git a/llvm/lib/Target/VE/MCTargetDesc/VEMCTargetDesc.cpp b/llvm/lib/Target/VE/MCTargetDesc/VEMCTargetDesc.cpp --- a/llvm/lib/Target/VE/MCTargetDesc/VEMCTargetDesc.cpp +++ b/llvm/lib/Target/VE/MCTargetDesc/VEMCTargetDesc.cpp @@ -33,10 +33,11 @@ #define GET_REGINFO_MC_DESC #include "VEGenRegisterInfo.inc" -static MCAsmInfo *createVEMCAsmInfo(const MCRegisterInfo &MRI, const Triple &TT, +static MCAsmInfo *createVEMCAsmInfo(const MCRegisterInfo &MCRI, + const Triple &TT, const MCTargetOptions &Options) { MCAsmInfo *MAI = new VEELFMCAsmInfo(TT); - unsigned Reg = MRI.getDwarfRegNum(VE::SX11, true); + unsigned Reg = MCRI.getDwarfRegNum(VE::SX11, true); MCCFIInstruction Inst = MCCFIInstruction::cfiDefCfa(nullptr, Reg, 0); MAI->addInitialFrameState(Inst); return MAI; @@ -77,8 +78,8 @@ unsigned SyntaxVariant, const MCAsmInfo &MAI, const MCInstrInfo &MII, - const MCRegisterInfo &MRI) { - return new VEInstPrinter(MAI, MII, MRI); + const MCRegisterInfo &MCRI) { + return new VEInstPrinter(MAI, MII, MCRI); } extern "C" LLVM_EXTERNAL_VISIBILITY void LLVMInitializeVETargetMC() { diff --git a/llvm/lib/Target/WebAssembly/MCTargetDesc/WebAssemblyInstPrinter.h b/llvm/lib/Target/WebAssembly/MCTargetDesc/WebAssemblyInstPrinter.h --- a/llvm/lib/Target/WebAssembly/MCTargetDesc/WebAssemblyInstPrinter.h +++ b/llvm/lib/Target/WebAssembly/MCTargetDesc/WebAssemblyInstPrinter.h @@ -33,7 +33,7 @@ public: WebAssemblyInstPrinter(const MCAsmInfo &MAI, const MCInstrInfo &MII, - const MCRegisterInfo &MRI); + const MCRegisterInfo &MCRI); void printRegName(raw_ostream &OS, MCRegister Reg) const override; void printInst(const MCInst *MI, uint64_t Address, StringRef Annot, diff --git a/llvm/lib/Target/WebAssembly/MCTargetDesc/WebAssemblyInstPrinter.cpp b/llvm/lib/Target/WebAssembly/MCTargetDesc/WebAssemblyInstPrinter.cpp --- a/llvm/lib/Target/WebAssembly/MCTargetDesc/WebAssemblyInstPrinter.cpp +++ b/llvm/lib/Target/WebAssembly/MCTargetDesc/WebAssemblyInstPrinter.cpp @@ -35,8 +35,8 @@ WebAssemblyInstPrinter::WebAssemblyInstPrinter(const MCAsmInfo &MAI, const MCInstrInfo &MII, - const MCRegisterInfo &MRI) - : MCInstPrinter(MAI, MII, MRI) {} + const MCRegisterInfo &MCRI) + : MCInstPrinter(MAI, MII, MCRI) {} void WebAssemblyInstPrinter::printRegName(raw_ostream &OS, MCRegister Reg) const { diff --git a/llvm/lib/Target/WebAssembly/MCTargetDesc/WebAssemblyMCTargetDesc.cpp b/llvm/lib/Target/WebAssembly/MCTargetDesc/WebAssemblyMCTargetDesc.cpp --- a/llvm/lib/Target/WebAssembly/MCTargetDesc/WebAssemblyMCTargetDesc.cpp +++ b/llvm/lib/Target/WebAssembly/MCTargetDesc/WebAssemblyMCTargetDesc.cpp @@ -35,7 +35,7 @@ #define GET_REGINFO_MC_DESC #include "WebAssemblyGenRegisterInfo.inc" -static MCAsmInfo *createMCAsmInfo(const MCRegisterInfo & /*MRI*/, +static MCAsmInfo *createMCAsmInfo(const MCRegisterInfo & /*MCRI*/, const Triple &TT, const MCTargetOptions &Options) { return new WebAssemblyMCAsmInfo(TT, Options); @@ -57,9 +57,9 @@ unsigned SyntaxVariant, const MCAsmInfo &MAI, const MCInstrInfo &MII, - const MCRegisterInfo &MRI) { + const MCRegisterInfo &MCRI) { assert(SyntaxVariant == 0 && "WebAssembly only has one syntax variant"); - return new WebAssemblyInstPrinter(MAI, MII, MRI); + return new WebAssemblyInstPrinter(MAI, MII, MCRI); } static MCCodeEmitter *createCodeEmitter(const MCInstrInfo &MCII, @@ -69,7 +69,7 @@ static MCAsmBackend *createAsmBackend(const Target & /*T*/, const MCSubtargetInfo &STI, - const MCRegisterInfo & /*MRI*/, + const MCRegisterInfo & /*MCRI*/, const MCTargetOptions & /*Options*/) { return createWebAssemblyAsmBackend(STI.getTargetTriple()); } diff --git a/llvm/lib/Target/X86/AsmParser/X86AsmParser.cpp b/llvm/lib/Target/X86/AsmParser/X86AsmParser.cpp --- a/llvm/lib/Target/X86/AsmParser/X86AsmParser.cpp +++ b/llvm/lib/Target/X86/AsmParser/X86AsmParser.cpp @@ -3632,7 +3632,7 @@ } bool X86AsmParser::processInstruction(MCInst &Inst, const OperandVector &Ops) { - const MCRegisterInfo *MRI = getContext().getRegisterInfo(); + const MCRegisterInfo *MCRI = getContext().getRegisterInfo(); switch (Inst.getOpcode()) { default: return false; @@ -3672,8 +3672,8 @@ // We can get a smaller encoding by using VEX.R instead of VEX.B if one of // the registers is extended, but other isn't. if (ForcedVEXEncoding == VEXEncoding_VEX3 || - MRI->getEncodingValue(Inst.getOperand(0).getReg()) >= 8 || - MRI->getEncodingValue(Inst.getOperand(1).getReg()) < 8) + MCRI->getEncodingValue(Inst.getOperand(0).getReg()) >= 8 || + MCRI->getEncodingValue(Inst.getOperand(1).getReg()) < 8) return false; unsigned NewOpc; @@ -3701,8 +3701,8 @@ // We can get a smaller encoding by using VEX.R instead of VEX.B if one of // the registers is extended, but other isn't. if (ForcedVEXEncoding == VEXEncoding_VEX3 || - MRI->getEncodingValue(Inst.getOperand(0).getReg()) >= 8 || - MRI->getEncodingValue(Inst.getOperand(2).getReg()) < 8) + MCRI->getEncodingValue(Inst.getOperand(0).getReg()) >= 8 || + MCRI->getEncodingValue(Inst.getOperand(2).getReg()) < 8) return false; unsigned NewOpc; @@ -3835,7 +3835,7 @@ bool X86AsmParser::validateInstruction(MCInst &Inst, const OperandVector &Ops) { using namespace X86; - const MCRegisterInfo *MRI = getContext().getRegisterInfo(); + const MCRegisterInfo *MCRI = getContext().getRegisterInfo(); unsigned Opcode = Inst.getOpcode(); uint64_t TSFlags = MII.get(Opcode).TSFlags; if (isVFCMADDCPH(Opcode) || isVFCMADDCSH(Opcode) || isVFMADDCPH(Opcode) || @@ -3863,7 +3863,7 @@ isVP4DPWSSDS(Opcode) || isVP4DPWSSD(Opcode)) { unsigned Src2 = Inst.getOperand(Inst.getNumOperands() - X86::AddrNumOperands - 1).getReg(); - unsigned Src2Enc = MRI->getEncodingValue(Src2); + unsigned Src2Enc = MCRI->getEncodingValue(Src2); if (Src2Enc % 4 != 0) { StringRef RegName = X86IntelInstPrinter::getRegisterName(Src2); unsigned GroupStart = (Src2Enc / 4) * 4; @@ -3880,16 +3880,16 @@ isVPGATHERQD(Opcode) || isVPGATHERQQ(Opcode)) { bool HasEVEX = (TSFlags & X86II::EncodingMask) == X86II::EVEX; if (HasEVEX) { - unsigned Dest = MRI->getEncodingValue(Inst.getOperand(0).getReg()); - unsigned Index = MRI->getEncodingValue( + unsigned Dest = MCRI->getEncodingValue(Inst.getOperand(0).getReg()); + unsigned Index = MCRI->getEncodingValue( Inst.getOperand(4 + X86::AddrIndexReg).getReg()); if (Dest == Index) return Warning(Ops[0]->getStartLoc(), "index and destination registers " "should be distinct"); } else { - unsigned Dest = MRI->getEncodingValue(Inst.getOperand(0).getReg()); - unsigned Mask = MRI->getEncodingValue(Inst.getOperand(1).getReg()); - unsigned Index = MRI->getEncodingValue( + unsigned Dest = MCRI->getEncodingValue(Inst.getOperand(0).getReg()); + unsigned Mask = MCRI->getEncodingValue(Inst.getOperand(1).getReg()); + unsigned Index = MCRI->getEncodingValue( Inst.getOperand(3 + X86::AddrIndexReg).getReg()); if (Dest == Mask || Dest == Index || Mask == Index) return Warning(Ops[0]->getStartLoc(), "mask, index, and destination " @@ -4845,7 +4845,7 @@ bool X86AsmParser::parseSEHRegisterNumber(unsigned RegClassID, MCRegister &RegNo) { SMLoc startLoc = getLexer().getLoc(); - const MCRegisterInfo *MRI = getContext().getRegisterInfo(); + const MCRegisterInfo *MCRI = getContext().getRegisterInfo(); // Try parsing the argument as a register first. if (getLexer().getTok().isNot(AsmToken::Integer)) { @@ -4868,7 +4868,7 @@ // from the encoding back to the LLVM register number. RegNo = 0; for (MCPhysReg Reg : X86MCRegisterClasses[RegClassID]) { - if (MRI->getEncodingValue(Reg) == EncodedReg) { + if (MCRI->getEncodingValue(Reg) == EncodedReg) { RegNo = Reg; break; } diff --git a/llvm/lib/Target/X86/MCTargetDesc/X86ATTInstPrinter.h b/llvm/lib/Target/X86/MCTargetDesc/X86ATTInstPrinter.h --- a/llvm/lib/Target/X86/MCTargetDesc/X86ATTInstPrinter.h +++ b/llvm/lib/Target/X86/MCTargetDesc/X86ATTInstPrinter.h @@ -20,8 +20,8 @@ class X86ATTInstPrinter final : public X86InstPrinterCommon { public: X86ATTInstPrinter(const MCAsmInfo &MAI, const MCInstrInfo &MII, - const MCRegisterInfo &MRI) - : X86InstPrinterCommon(MAI, MII, MRI), HasCustomInstComment(false) {} + const MCRegisterInfo &MCRI) + : X86InstPrinterCommon(MAI, MII, MCRI), HasCustomInstComment(false) {} void printRegName(raw_ostream &OS, MCRegister Reg) const override; void printInst(const MCInst *MI, uint64_t Address, StringRef Annot, diff --git a/llvm/lib/Target/X86/MCTargetDesc/X86AsmBackend.cpp b/llvm/lib/Target/X86/MCTargetDesc/X86AsmBackend.cpp --- a/llvm/lib/Target/X86/MCTargetDesc/X86AsmBackend.cpp +++ b/llvm/lib/Target/X86/MCTargetDesc/X86AsmBackend.cpp @@ -1186,7 +1186,7 @@ } // namespace CU class DarwinX86AsmBackend : public X86AsmBackend { - const MCRegisterInfo &MRI; + const MCRegisterInfo &MCRI; /// Number of registers that can be saved in a compact unwind encoding. enum { CU_NUM_SAVED_REGS = 6 }; @@ -1333,9 +1333,9 @@ } public: - DarwinX86AsmBackend(const Target &T, const MCRegisterInfo &MRI, + DarwinX86AsmBackend(const Target &T, const MCRegisterInfo &MCRI, const MCSubtargetInfo &STI) - : X86AsmBackend(T, STI), MRI(MRI), TT(STI.getTargetTriple()), + : X86AsmBackend(T, STI), MCRI(MCRI), TT(STI.getTargetTriple()), Is64Bit(TT.isArch64Bit()) { memset(SavedRegs, 0, sizeof(SavedRegs)); OffsetSize = Is64Bit ? 8 : 4; @@ -1388,7 +1388,7 @@ // If the frame pointer is other than esp/rsp, we do not have a way to // generate a compact unwinding representation, so bail out. - if (*MRI.getLLVMRegNum(Inst.getRegister(), true) != + if (*MCRI.getLLVMRegNum(Inst.getRegister(), true) != (Is64Bit ? X86::RBP : X86::EBP)) return CU::UNWIND_MODE_DWARF; @@ -1436,7 +1436,7 @@ // unwind encoding. return CU::UNWIND_MODE_DWARF; - unsigned Reg = *MRI.getLLVMRegNum(Inst.getRegister(), true); + unsigned Reg = *MCRI.getLLVMRegNum(Inst.getRegister(), true); SavedRegs[SavedRegIdx++] = Reg; StackAdjust += OffsetSize; MinAbsOffset = std::min(MinAbsOffset, abs(Inst.getOffset())); @@ -1513,11 +1513,11 @@ MCAsmBackend *llvm::createX86_32AsmBackend(const Target &T, const MCSubtargetInfo &STI, - const MCRegisterInfo &MRI, + const MCRegisterInfo &MCRI, const MCTargetOptions &Options) { const Triple &TheTriple = STI.getTargetTriple(); if (TheTriple.isOSBinFormatMachO()) - return new DarwinX86AsmBackend(T, MRI, STI); + return new DarwinX86AsmBackend(T, MCRI, STI); if (TheTriple.isOSWindows() && TheTriple.isOSBinFormatCOFF()) return new WindowsX86AsmBackend(T, false, STI); @@ -1532,11 +1532,11 @@ MCAsmBackend *llvm::createX86_64AsmBackend(const Target &T, const MCSubtargetInfo &STI, - const MCRegisterInfo &MRI, + const MCRegisterInfo &MCRI, const MCTargetOptions &Options) { const Triple &TheTriple = STI.getTargetTriple(); if (TheTriple.isOSBinFormatMachO()) - return new DarwinX86AsmBackend(T, MRI, STI); + return new DarwinX86AsmBackend(T, MCRI, STI); if (TheTriple.isOSWindows() && TheTriple.isOSBinFormatCOFF()) return new WindowsX86AsmBackend(T, true, STI); diff --git a/llvm/lib/Target/X86/MCTargetDesc/X86IntelInstPrinter.h b/llvm/lib/Target/X86/MCTargetDesc/X86IntelInstPrinter.h --- a/llvm/lib/Target/X86/MCTargetDesc/X86IntelInstPrinter.h +++ b/llvm/lib/Target/X86/MCTargetDesc/X86IntelInstPrinter.h @@ -21,8 +21,8 @@ class X86IntelInstPrinter final : public X86InstPrinterCommon { public: X86IntelInstPrinter(const MCAsmInfo &MAI, const MCInstrInfo &MII, - const MCRegisterInfo &MRI) - : X86InstPrinterCommon(MAI, MII, MRI) {} + const MCRegisterInfo &MCRI) + : X86InstPrinterCommon(MAI, MII, MCRI) {} void printRegName(raw_ostream &OS, MCRegister Reg) const override; void printInst(const MCInst *MI, uint64_t Address, StringRef Annot, diff --git a/llvm/lib/Target/X86/MCTargetDesc/X86MCTargetDesc.h b/llvm/lib/Target/X86/MCTargetDesc/X86MCTargetDesc.h --- a/llvm/lib/Target/X86/MCTargetDesc/X86MCTargetDesc.h +++ b/llvm/lib/Target/X86/MCTargetDesc/X86MCTargetDesc.h @@ -57,8 +57,7 @@ unsigned getDwarfRegFlavour(const Triple &TT, bool isEH); -void initLLVMToSEHAndCVRegMapping(MCRegisterInfo *MRI); - +void initLLVMToSEHAndCVRegMapping(MCRegisterInfo *MCRI); /// Returns true if this instruction has a LOCK prefix. bool hasLockPrefix(const MCInst &MI); @@ -96,11 +95,11 @@ MCAsmBackend *createX86_32AsmBackend(const Target &T, const MCSubtargetInfo &STI, - const MCRegisterInfo &MRI, + const MCRegisterInfo &MCRI, const MCTargetOptions &Options); MCAsmBackend *createX86_64AsmBackend(const Target &T, const MCSubtargetInfo &STI, - const MCRegisterInfo &MRI, + const MCRegisterInfo &MCRI, const MCTargetOptions &Options); /// Implements X86-only directives for assembly emission. diff --git a/llvm/lib/Target/X86/MCTargetDesc/X86MCTargetDesc.cpp b/llvm/lib/Target/X86/MCTargetDesc/X86MCTargetDesc.cpp --- a/llvm/lib/Target/X86/MCTargetDesc/X86MCTargetDesc.cpp +++ b/llvm/lib/Target/X86/MCTargetDesc/X86MCTargetDesc.cpp @@ -165,11 +165,11 @@ return !is16BitMemOperand(MI, MemoryOperand, STI); } -void X86_MC::initLLVMToSEHAndCVRegMapping(MCRegisterInfo *MRI) { +void X86_MC::initLLVMToSEHAndCVRegMapping(MCRegisterInfo *MCRI) { // FIXME: TableGen these. for (unsigned Reg = X86::NoRegister + 1; Reg < X86::NUM_TARGET_REGS; ++Reg) { - unsigned SEH = MRI->getEncodingValue(Reg); - MRI->mapLLVMRegToSEHReg(Reg, SEH); + unsigned SEH = MCRI->getEncodingValue(Reg); + MCRI->mapLLVMRegToSEHReg(Reg, SEH); } // Mapping from CodeView to MC register id. @@ -384,7 +384,7 @@ }; for (const auto &I : RegMap) - MRI->mapLLVMRegToCVReg(I.Reg, static_cast(I.CVReg)); + MCRI->mapLLVMRegToCVReg(I.Reg, static_cast(I.CVReg)); } MCSubtargetInfo *X86_MC::createX86MCSubtargetInfo(const Triple &TT, @@ -418,7 +418,7 @@ return X; } -static MCAsmInfo *createX86MCAsmInfo(const MCRegisterInfo &MRI, +static MCAsmInfo *createX86MCAsmInfo(const MCRegisterInfo &MCRI, const Triple &TheTriple, const MCTargetOptions &Options) { bool is64Bit = TheTriple.getArch() == Triple::x86_64; @@ -453,13 +453,13 @@ // Initial state of the frame pointer is esp+stackGrowth. unsigned StackPtr = is64Bit ? X86::RSP : X86::ESP; MCCFIInstruction Inst = MCCFIInstruction::cfiDefCfa( - nullptr, MRI.getDwarfRegNum(StackPtr, true), -stackGrowth); + nullptr, MCRI.getDwarfRegNum(StackPtr, true), -stackGrowth); MAI->addInitialFrameState(Inst); // Add return address to move list unsigned InstPtr = is64Bit ? X86::RIP : X86::EIP; MCCFIInstruction Inst2 = MCCFIInstruction::createOffset( - nullptr, MRI.getDwarfRegNum(InstPtr, true), stackGrowth); + nullptr, MCRI.getDwarfRegNum(InstPtr, true), stackGrowth); MAI->addInitialFrameState(Inst2); return MAI; @@ -469,11 +469,11 @@ unsigned SyntaxVariant, const MCAsmInfo &MAI, const MCInstrInfo &MII, - const MCRegisterInfo &MRI) { + const MCRegisterInfo &MCRI) { if (SyntaxVariant == 0) - return new X86ATTInstPrinter(MAI, MII, MRI); + return new X86ATTInstPrinter(MAI, MII, MCRI); if (SyntaxVariant == 1) - return new X86IntelInstPrinter(MAI, MII, MRI); + return new X86IntelInstPrinter(MAI, MII, MCRI); return nullptr; } @@ -497,7 +497,7 @@ #define GET_STIPREDICATE_DECLS_FOR_MC_ANALYSIS #include "X86GenSubtargetInfo.inc" - bool clearsSuperRegisters(const MCRegisterInfo &MRI, const MCInst &Inst, + bool clearsSuperRegisters(const MCRegisterInfo &MCRI, const MCInst &Inst, APInt &Mask) const override; std::vector> findPltEntries(uint64_t PltSectionVA, ArrayRef PltContents, @@ -517,7 +517,7 @@ #define GET_STIPREDICATE_DEFS_FOR_MC_ANALYSIS #include "X86GenSubtargetInfo.inc" -bool X86MCInstrAnalysis::clearsSuperRegisters(const MCRegisterInfo &MRI, +bool X86MCInstrAnalysis::clearsSuperRegisters(const MCRegisterInfo &MCRI, const MCInst &Inst, APInt &Mask) const { const MCInstrDesc &Desc = Info->get(Inst.getOpcode()); @@ -530,9 +530,9 @@ bool HasEVEX = (Desc.TSFlags & X86II::EncodingMask) == X86II::EVEX; bool HasXOP = (Desc.TSFlags & X86II::EncodingMask) == X86II::XOP; - const MCRegisterClass &GR32RC = MRI.getRegClass(X86::GR32RegClassID); - const MCRegisterClass &VR128XRC = MRI.getRegClass(X86::VR128XRegClassID); - const MCRegisterClass &VR256XRC = MRI.getRegClass(X86::VR256XRegClassID); + const MCRegisterClass &GR32RC = MCRI.getRegClass(X86::GR32RegClassID); + const MCRegisterClass &VR128XRC = MCRI.getRegClass(X86::VR128XRegClassID); + const MCRegisterClass &VR256XRC = MCRI.getRegClass(X86::VR256XRegClassID); auto ClearsSuperReg = [=](unsigned RegID) { // On X86-64, a general purpose integer register is viewed as a 64-bit diff --git a/llvm/lib/Target/X86/MCTargetDesc/X86WinCOFFTargetStreamer.cpp b/llvm/lib/Target/X86/MCTargetDesc/X86WinCOFFTargetStreamer.cpp --- a/llvm/lib/Target/X86/MCTargetDesc/X86WinCOFFTargetStreamer.cpp +++ b/llvm/lib/Target/X86/MCTargetDesc/X86WinCOFFTargetStreamer.cpp @@ -288,23 +288,41 @@ }; } // end namespace -static Printable printFPOReg(const MCRegisterInfo *MRI, unsigned LLVMReg) { - return Printable([MRI, LLVMReg](raw_ostream &OS) { +static Printable printFPOReg(const MCRegisterInfo *MCRI, unsigned LLVMReg) { + return Printable([MCRI, LLVMReg](raw_ostream &OS) { switch (LLVMReg) { // MSVC only seems to emit symbolic register names for EIP, EBP, and ESP, // but the format seems to support more than that, so we emit them. - case X86::EAX: OS << "$eax"; break; - case X86::EBX: OS << "$ebx"; break; - case X86::ECX: OS << "$ecx"; break; - case X86::EDX: OS << "$edx"; break; - case X86::EDI: OS << "$edi"; break; - case X86::ESI: OS << "$esi"; break; - case X86::ESP: OS << "$esp"; break; - case X86::EBP: OS << "$ebp"; break; - case X86::EIP: OS << "$eip"; break; + case X86::EAX: + OS << "$eax"; + break; + case X86::EBX: + OS << "$ebx"; + break; + case X86::ECX: + OS << "$ecx"; + break; + case X86::EDX: + OS << "$edx"; + break; + case X86::EDI: + OS << "$edi"; + break; + case X86::ESI: + OS << "$esi"; + break; + case X86::ESP: + OS << "$esp"; + break; + case X86::EBP: + OS << "$ebp"; + break; + case X86::EIP: + OS << "$eip"; + break; // Otherwise, get the codeview register number and print $N. default: - OS << '$' << MRI->getCodeViewRegNum(LLVMReg); + OS << '$' << MCRI->getCodeViewRegNum(LLVMReg); break; } }); @@ -318,14 +336,14 @@ // Compute the new FrameFunc string. FrameFunc.clear(); raw_svector_ostream FuncOS(FrameFunc); - const MCRegisterInfo *MRI = OS.getContext().getRegisterInfo(); + const MCRegisterInfo *MCRI = OS.getContext().getRegisterInfo(); assert((StackAlign == 0 || FrameReg != 0) && "cannot align stack without frame reg"); StringRef CFAVar = StackAlign == 0 ? "$T0" : "$T1"; if (FrameReg) { // CFA is FrameReg + FrameRegOff. - FuncOS << CFAVar << ' ' << printFPOReg(MRI, FrameReg) << ' ' << FrameRegOff + FuncOS << CFAVar << ' ' << printFPOReg(MCRI, FrameReg) << ' ' << FrameRegOff << " + = "; // Assign $T0, the VFRAME register, the value of ESP after it is aligned. @@ -350,7 +368,7 @@ // Each saved register is stored at an unchanging negative CFA offset. for (RegSaveOffset RO : RegSaveOffsets) - FuncOS << printFPOReg(MRI, RO.Reg) << ' ' << CFAVar << ' ' << RO.Offset + FuncOS << printFPOReg(MCRI, RO.Reg) << ' ' << CFAVar << ' ' << RO.Offset << " - ^ = "; // Add it to the CV string table. diff --git a/llvm/lib/Target/X86/X86FrameLowering.cpp b/llvm/lib/Target/X86/X86FrameLowering.cpp --- a/llvm/lib/Target/X86/X86FrameLowering.cpp +++ b/llvm/lib/Target/X86/X86FrameLowering.cpp @@ -456,12 +456,12 @@ return; } const MachineModuleInfo &MMI = MF.getMMI(); - const MCRegisterInfo *MRI = MMI.getContext().getRegisterInfo(); + const MCRegisterInfo *MCRI = MMI.getContext().getRegisterInfo(); const Register FramePtr = TRI->getFrameRegister(MF); const Register MachineFramePtr = STI.isTarget64BitILP32() ? Register(getX86SubSuperRegister(FramePtr, 64)) : FramePtr; - unsigned DwarfReg = MRI->getDwarfRegNum(MachineFramePtr, true); + unsigned DwarfReg = MCRI->getDwarfRegNum(MachineFramePtr, true); // Offset = space for return address + size of the frame pointer itself. unsigned Offset = (Is64Bit ? 8 : 4) + (Uses64BitFramePtr ? 8 : 4); BuildCFI(MBB, MBBI, DebugLoc{}, @@ -475,7 +475,7 @@ MachineFunction &MF = *MBB.getParent(); MachineFrameInfo &MFI = MF.getFrameInfo(); MachineModuleInfo &MMI = MF.getMMI(); - const MCRegisterInfo *MRI = MMI.getContext().getRegisterInfo(); + const MCRegisterInfo *MCRI = MMI.getContext().getRegisterInfo(); // Add callee saved registers to move list. const std::vector &CSI = MFI.getCalleeSavedInfo(); @@ -484,7 +484,7 @@ for (const CalleeSavedInfo &I : CSI) { int64_t Offset = MFI.getObjectOffset(I.getFrameIdx()); Register Reg = I.getReg(); - unsigned DwarfReg = MRI->getDwarfRegNum(Reg, true); + unsigned DwarfReg = MCRI->getDwarfRegNum(Reg, true); if (IsPrologue) { BuildCFI(MBB, MBBI, DL, diff --git a/llvm/lib/Target/XCore/MCTargetDesc/XCoreInstPrinter.h b/llvm/lib/Target/XCore/MCTargetDesc/XCoreInstPrinter.h --- a/llvm/lib/Target/XCore/MCTargetDesc/XCoreInstPrinter.h +++ b/llvm/lib/Target/XCore/MCTargetDesc/XCoreInstPrinter.h @@ -23,8 +23,8 @@ class XCoreInstPrinter : public MCInstPrinter { public: XCoreInstPrinter(const MCAsmInfo &MAI, const MCInstrInfo &MII, - const MCRegisterInfo &MRI) - : MCInstPrinter(MAI, MII, MRI) {} + const MCRegisterInfo &MCRI) + : MCInstPrinter(MAI, MII, MCRI) {} // Autogenerated by tblgen. std::pair getMnemonic(const MCInst *MI) override; diff --git a/llvm/lib/Target/XCore/MCTargetDesc/XCoreMCTargetDesc.cpp b/llvm/lib/Target/XCore/MCTargetDesc/XCoreMCTargetDesc.cpp --- a/llvm/lib/Target/XCore/MCTargetDesc/XCoreMCTargetDesc.cpp +++ b/llvm/lib/Target/XCore/MCTargetDesc/XCoreMCTargetDesc.cpp @@ -55,7 +55,7 @@ return createXCoreMCSubtargetInfoImpl(TT, CPU, /*TuneCPU*/ CPU, FS); } -static MCAsmInfo *createXCoreMCAsmInfo(const MCRegisterInfo &MRI, +static MCAsmInfo *createXCoreMCAsmInfo(const MCRegisterInfo &MCRI, const Triple &TT, const MCTargetOptions &Options) { MCAsmInfo *MAI = new XCoreMCAsmInfo(TT); @@ -71,8 +71,8 @@ unsigned SyntaxVariant, const MCAsmInfo &MAI, const MCInstrInfo &MII, - const MCRegisterInfo &MRI) { - return new XCoreInstPrinter(MAI, MII, MRI); + const MCRegisterInfo &MCRI) { + return new XCoreInstPrinter(MAI, MII, MCRI); } XCoreTargetStreamer::XCoreTargetStreamer(MCStreamer &S) : MCTargetStreamer(S) {} diff --git a/llvm/lib/Target/XCore/XCoreFrameLowering.cpp b/llvm/lib/Target/XCore/XCoreFrameLowering.cpp --- a/llvm/lib/Target/XCore/XCoreFrameLowering.cpp +++ b/llvm/lib/Target/XCore/XCoreFrameLowering.cpp @@ -226,7 +226,7 @@ MachineBasicBlock::iterator MBBI = MBB.begin(); MachineFrameInfo &MFI = MF.getFrameInfo(); MachineModuleInfo *MMI = &MF.getMMI(); - const MCRegisterInfo *MRI = MMI->getContext().getRegisterInfo(); + const MCRegisterInfo *MCRI = MMI->getContext().getRegisterInfo(); const XCoreInstrInfo &TII = *MF.getSubtarget().getInstrInfo(); XCoreFunctionInfo *XFI = MF.getInfo(); // Debug location must be unknown since the first debug location is used @@ -267,7 +267,7 @@ true); if (emitFrameMoves) { EmitDefCfaOffset(MBB, MBBI, dl, TII, Adjusted*4); - unsigned DRegNum = MRI->getDwarfRegNum(XCore::LR, true); + unsigned DRegNum = MCRI->getDwarfRegNum(XCore::LR, true); EmitCfiOffset(MBB, MBBI, dl, TII, DRegNum, 0); } } @@ -292,7 +292,7 @@ .addMemOperand(getFrameIndexMMO(MBB, SpillList[i].FI, MachineMemOperand::MOStore)); if (emitFrameMoves) { - unsigned DRegNum = MRI->getDwarfRegNum(SpillList[i].Reg, true); + unsigned DRegNum = MCRI->getDwarfRegNum(SpillList[i].Reg, true); EmitCfiOffset(MBB, MBBI, dl, TII, DRegNum, SpillList[i].Offset); } } @@ -307,7 +307,7 @@ BuildMI(MBB, MBBI, dl, TII.get(XCore::LDAWSP_ru6), FramePtr).addImm(0); if (emitFrameMoves) EmitDefCfaRegister(MBB, MBBI, dl, TII, MF, - MRI->getDwarfRegNum(FramePtr, true)); + MCRI->getDwarfRegNum(FramePtr, true)); } if (emitFrameMoves) { @@ -317,7 +317,7 @@ ++Pos; const CalleeSavedInfo &CSI = SpillLabel.second; int Offset = MFI.getObjectOffset(CSI.getFrameIdx()); - unsigned DRegNum = MRI->getDwarfRegNum(CSI.getReg(), true); + unsigned DRegNum = MCRI->getDwarfRegNum(CSI.getReg(), true); EmitCfiOffset(MBB, Pos, dl, TII, DRegNum, Offset); } if (XFI->hasEHSpillSlot()) { @@ -331,10 +331,10 @@ MF.getSubtarget().getTargetLowering()); assert(SpillList.size()==2 && "Unexpected SpillList size"); EmitCfiOffset(MBB, MBBI, dl, TII, - MRI->getDwarfRegNum(SpillList[0].Reg, true), + MCRI->getDwarfRegNum(SpillList[0].Reg, true), SpillList[0].Offset); EmitCfiOffset(MBB, MBBI, dl, TII, - MRI->getDwarfRegNum(SpillList[1].Reg, true), + MCRI->getDwarfRegNum(SpillList[1].Reg, true), SpillList[1].Offset); } } diff --git a/llvm/lib/Target/Xtensa/MCTargetDesc/XtensaAsmBackend.cpp b/llvm/lib/Target/Xtensa/MCTargetDesc/XtensaAsmBackend.cpp --- a/llvm/lib/Target/Xtensa/MCTargetDesc/XtensaAsmBackend.cpp +++ b/llvm/lib/Target/Xtensa/MCTargetDesc/XtensaAsmBackend.cpp @@ -216,7 +216,7 @@ MCAsmBackend *llvm::createXtensaMCAsmBackend(const Target &T, const MCSubtargetInfo &STI, - const MCRegisterInfo &MRI, + const MCRegisterInfo &MCRI, const MCTargetOptions &Options) { uint8_t OSABI = MCELFObjectTargetWriter::getOSABI(STI.getTargetTriple().getOS()); diff --git a/llvm/lib/Target/Xtensa/MCTargetDesc/XtensaInstPrinter.h b/llvm/lib/Target/Xtensa/MCTargetDesc/XtensaInstPrinter.h --- a/llvm/lib/Target/Xtensa/MCTargetDesc/XtensaInstPrinter.h +++ b/llvm/lib/Target/Xtensa/MCTargetDesc/XtensaInstPrinter.h @@ -24,8 +24,8 @@ class XtensaInstPrinter : public MCInstPrinter { public: XtensaInstPrinter(const MCAsmInfo &MAI, const MCInstrInfo &MII, - const MCRegisterInfo &MRI) - : MCInstPrinter(MAI, MII, MRI) {} + const MCRegisterInfo &MCRI) + : MCInstPrinter(MAI, MII, MCRI) {} // Automatically generated by tblgen. std::pair getMnemonic(const MCInst *MI) override; diff --git a/llvm/lib/Target/Xtensa/MCTargetDesc/XtensaMCTargetDesc.h b/llvm/lib/Target/Xtensa/MCTargetDesc/XtensaMCTargetDesc.h --- a/llvm/lib/Target/Xtensa/MCTargetDesc/XtensaMCTargetDesc.h +++ b/llvm/lib/Target/Xtensa/MCTargetDesc/XtensaMCTargetDesc.h @@ -39,7 +39,7 @@ MCAsmBackend *createXtensaMCAsmBackend(const Target &T, const MCSubtargetInfo &STI, - const MCRegisterInfo &MRI, + const MCRegisterInfo &MCRI, const MCTargetOptions &Options); std::unique_ptr createXtensaObjectWriter(uint8_t OSABI, bool IsLittleEndian); diff --git a/llvm/lib/Target/Xtensa/MCTargetDesc/XtensaMCTargetDesc.cpp b/llvm/lib/Target/Xtensa/MCTargetDesc/XtensaMCTargetDesc.cpp --- a/llvm/lib/Target/Xtensa/MCTargetDesc/XtensaMCTargetDesc.cpp +++ b/llvm/lib/Target/Xtensa/MCTargetDesc/XtensaMCTargetDesc.cpp @@ -31,7 +31,7 @@ using namespace llvm; -static MCAsmInfo *createXtensaMCAsmInfo(const MCRegisterInfo &MRI, +static MCAsmInfo *createXtensaMCAsmInfo(const MCRegisterInfo &MCRI, const Triple &TT, const MCTargetOptions &Options) { MCAsmInfo *MAI = new XtensaMCAsmInfo(TT); @@ -48,8 +48,8 @@ unsigned SyntaxVariant, const MCAsmInfo &MAI, const MCInstrInfo &MII, - const MCRegisterInfo &MRI) { - return new XtensaInstPrinter(MAI, MII, MRI); + const MCRegisterInfo &MCRI) { + return new XtensaInstPrinter(MAI, MII, MCRI); } static MCRegisterInfo *createXtensaMCRegisterInfo(const Triple &TT) { diff --git a/llvm/tools/llvm-dwp/llvm-dwp.cpp b/llvm/tools/llvm-dwp/llvm-dwp.cpp --- a/llvm/tools/llvm-dwp/llvm-dwp.cpp +++ b/llvm/tools/llvm-dwp/llvm-dwp.cpp @@ -152,13 +152,13 @@ std::string TripleName = ErrOrTriple->getTriple(); // Create all the MC Objects. - std::unique_ptr MRI(TheTarget->createMCRegInfo(TripleName)); - if (!MRI) + std::unique_ptr MCRI(TheTarget->createMCRegInfo(TripleName)); + if (!MCRI) return error(Twine("no register info for target ") + TripleName, Context); MCTargetOptions MCOptions = llvm::mc::InitMCTargetOptionsFromFlags(); std::unique_ptr MAI( - TheTarget->createMCAsmInfo(*MRI, TripleName, MCOptions)); + TheTarget->createMCAsmInfo(*MCRI, TripleName, MCOptions)); if (!MAI) return error("no asm info for target " + TripleName, Context); @@ -167,13 +167,13 @@ if (!MSTI) return error("no subtarget info for target " + TripleName, Context); - MCContext MC(*ErrOrTriple, MAI.get(), MRI.get(), MSTI.get()); + MCContext MC(*ErrOrTriple, MAI.get(), MCRI.get(), MSTI.get()); std::unique_ptr MOFI( TheTarget->createMCObjectFileInfo(MC, /*PIC=*/false)); MC.setObjectFileInfo(MOFI.get()); MCTargetOptions Options; - auto MAB = TheTarget->createMCAsmBackend(*MSTI, *MRI, Options); + auto MAB = TheTarget->createMCAsmBackend(*MSTI, *MCRI, Options); if (!MAB) return error("no asm backend for target " + TripleName, Context); diff --git a/llvm/tools/llvm-jitlink/llvm-jitlink.cpp b/llvm/tools/llvm-jitlink/llvm-jitlink.cpp --- a/llvm/tools/llvm-jitlink/llvm-jitlink.cpp +++ b/llvm/tools/llvm-jitlink/llvm-jitlink.cpp @@ -300,13 +300,14 @@ namespace llvm { -static raw_ostream & -operator<<(raw_ostream &OS, const Session::MemoryRegionInfo &MRI) { +static raw_ostream &operator<<(raw_ostream &OS, + const Session::MemoryRegionInfo &MCRI) { return OS << "target addr = " - << format("0x%016" PRIx64, MRI.getTargetAddress()) - << ", content: " << (const void *)MRI.getContent().data() << " -- " - << (const void *)(MRI.getContent().data() + MRI.getContent().size()) - << " (" << MRI.getContent().size() << " bytes)"; + << format("0x%016" PRIx64, MCRI.getTargetAddress()) + << ", content: " << (const void *)MCRI.getContent().data() << " -- " + << (const void *)(MCRI.getContent().data() + + MCRI.getContent().size()) + << " (" << MCRI.getContent().size() << " bytes)"; } static raw_ostream & @@ -1790,7 +1791,7 @@ struct TargetInfo { const Target *TheTarget; std::unique_ptr STI; - std::unique_ptr MRI; + std::unique_ptr MCRI; std::unique_ptr MAI; std::unique_ptr Ctx; std::unique_ptr Disassembler; @@ -1816,8 +1817,8 @@ make_error("Unable to create subtarget for " + TripleName, inconvertibleErrorCode())); - std::unique_ptr MRI(TheTarget->createMCRegInfo(TripleName)); - if (!MRI) + std::unique_ptr MCRI(TheTarget->createMCRegInfo(TripleName)); + if (!MCRI) ExitOnErr(make_error("Unable to create target register info " "for " + TripleName, @@ -1825,14 +1826,14 @@ MCTargetOptions MCOptions; std::unique_ptr MAI( - TheTarget->createMCAsmInfo(*MRI, TripleName, MCOptions)); + TheTarget->createMCAsmInfo(*MCRI, TripleName, MCOptions)); if (!MAI) ExitOnErr(make_error("Unable to create target asm info " + TripleName, inconvertibleErrorCode())); auto Ctx = std::make_unique(Triple(TripleName), MAI.get(), - MRI.get(), STI.get()); + MCRI.get(), STI.get()); std::unique_ptr Disassembler( TheTarget->createMCDisassembler(*STI, *Ctx)); @@ -1855,12 +1856,12 @@ inconvertibleErrorCode())); std::unique_ptr InstPrinter( - TheTarget->createMCInstPrinter(Triple(TripleName), 0, *MAI, *MII, *MRI)); + TheTarget->createMCInstPrinter(Triple(TripleName), 0, *MAI, *MII, *MCRI)); if (!InstPrinter) ExitOnErr(make_error( "Unable to create instruction printer for" + TripleName, inconvertibleErrorCode())); - return {TheTarget, std::move(STI), std::move(MRI), + return {TheTarget, std::move(STI), std::move(MCRI), std::move(MAI), std::move(Ctx), std::move(Disassembler), std::move(MII), std::move(MIA), std::move(InstPrinter)}; } diff --git a/llvm/tools/llvm-mc-assemble-fuzzer/llvm-mc-assemble-fuzzer.cpp b/llvm/tools/llvm-mc-assemble-fuzzer/llvm-mc-assemble-fuzzer.cpp --- a/llvm/tools/llvm-mc-assemble-fuzzer/llvm-mc-assemble-fuzzer.cpp +++ b/llvm/tools/llvm-mc-assemble-fuzzer/llvm-mc-assemble-fuzzer.cpp @@ -158,15 +158,15 @@ abort(); } - std::unique_ptr MRI(TheTarget->createMCRegInfo(TripleName)); - if (!MRI) { + std::unique_ptr MCRI(TheTarget->createMCRegInfo(TripleName)); + if (!MCRI) { errs() << "Unable to create target register info!"; abort(); } MCTargetOptions MCOptions = mc::InitMCTargetOptionsFromFlags(); std::unique_ptr MAI( - TheTarget->createMCAsmInfo(*MRI, TripleName, MCOptions)); + TheTarget->createMCAsmInfo(*MCRI, TripleName, MCOptions)); if (!MAI) { errs() << "Unable to create target asm info!"; abort(); @@ -175,15 +175,15 @@ std::unique_ptr STI( TheTarget->createMCSubtargetInfo(TripleName, MCPU, FeaturesStr)); - MCContext Ctx(TheTriple, MAI.get(), MRI.get(), STI.get(), &SrcMgr); + MCContext Ctx(TheTriple, MAI.get(), MCRI.get(), STI.get(), &SrcMgr); std::unique_ptr MOFI( TheTarget->createMCObjectFileInfo(Ctx, /*PIC=*/false)); Ctx.setObjectFileInfo(MOFI.get()); const unsigned OutputAsmVariant = 0; std::unique_ptr MCII(TheTarget->createMCInstrInfo()); - MCInstPrinter *IP = TheTarget->createMCInstPrinter(Triple(TripleName), OutputAsmVariant, - *MAI, *MCII, *MRI); + MCInstPrinter *IP = TheTarget->createMCInstPrinter( + Triple(TripleName), OutputAsmVariant, *MAI, *MCII, *MCRI); if (!IP) { errs() << "error: unable to create instruction printer for target triple '" @@ -230,7 +230,7 @@ } MCCodeEmitter *CE = TheTarget->createMCCodeEmitter(*MCII, Ctx); - MCAsmBackend *MAB = TheTarget->createMCAsmBackend(*STI, *MRI, MCOptions); + MCAsmBackend *MAB = TheTarget->createMCAsmBackend(*STI, *MCRI, MCOptions); Str.reset(TheTarget->createMCObjectStreamer( TheTriple, Ctx, std::unique_ptr(MAB), MAB->createObjectWriter(*OS), std::unique_ptr(CE), *STI, diff --git a/llvm/tools/llvm-mc/Disassembler.cpp b/llvm/tools/llvm-mc/Disassembler.cpp --- a/llvm/tools/llvm-mc/Disassembler.cpp +++ b/llvm/tools/llvm-mc/Disassembler.cpp @@ -135,14 +135,14 @@ MCContext &Ctx, raw_ostream &Out, const MCTargetOptions &MCOptions) { - std::unique_ptr MRI(T.createMCRegInfo(Triple)); - if (!MRI) { + std::unique_ptr MCRI(T.createMCRegInfo(Triple)); + if (!MCRI) { errs() << "error: no register info for target " << Triple << "\n"; return -1; } std::unique_ptr MAI( - T.createMCAsmInfo(*MRI, Triple, MCOptions)); + T.createMCAsmInfo(*MCRI, Triple, MCOptions)); if (!MAI) { errs() << "error: no assembly info for target " << Triple << "\n"; return -1; diff --git a/llvm/tools/llvm-mc/llvm-mc.cpp b/llvm/tools/llvm-mc/llvm-mc.cpp --- a/llvm/tools/llvm-mc/llvm-mc.cpp +++ b/llvm/tools/llvm-mc/llvm-mc.cpp @@ -391,11 +391,11 @@ // it later. SrcMgr.setIncludeDirs(IncludeDirs); - std::unique_ptr MRI(TheTarget->createMCRegInfo(TripleName)); - assert(MRI && "Unable to create target register info!"); + std::unique_ptr MCRI(TheTarget->createMCRegInfo(TripleName)); + assert(MCRI && "Unable to create target register info!"); std::unique_ptr MAI( - TheTarget->createMCAsmInfo(*MRI, TripleName, MCOptions)); + TheTarget->createMCAsmInfo(*MCRI, TripleName, MCOptions)); assert(MAI && "Unable to create target asm info!"); MAI->setRelaxELFRelocations(RelaxELFRel); @@ -425,7 +425,7 @@ // FIXME: This is not pretty. MCContext has a ptr to MCObjectFileInfo and // MCObjectFileInfo needs a MCContext reference in order to initialize itself. - MCContext Ctx(TheTriple, MAI.get(), MRI.get(), STI.get(), &SrcMgr, + MCContext Ctx(TheTriple, MAI.get(), MCRI.get(), STI.get(), &SrcMgr, &MCOptions); std::unique_ptr MOFI( TheTarget->createMCObjectFileInfo(Ctx, PIC, LargeCodeModel)); @@ -517,7 +517,7 @@ MCInstPrinter *IP = nullptr; if (FileType == OFT_AssemblyFile) { IP = TheTarget->createMCInstPrinter(Triple(TripleName), OutputAsmVariant, - *MAI, *MCII, *MRI); + *MAI, *MCII, *MCRI); if (!IP) { WithColor::error() @@ -542,7 +542,7 @@ CE.reset(TheTarget->createMCCodeEmitter(*MCII, Ctx)); std::unique_ptr MAB( - TheTarget->createMCAsmBackend(*STI, *MRI, MCOptions)); + TheTarget->createMCAsmBackend(*STI, *MCRI, MCOptions)); auto FOut = std::make_unique(*OS); Str.reset( TheTarget->createAsmStreamer(Ctx, std::move(FOut), /*asmverbose*/ true, @@ -560,7 +560,7 @@ } MCCodeEmitter *CE = TheTarget->createMCCodeEmitter(*MCII, Ctx); - MCAsmBackend *MAB = TheTarget->createMCAsmBackend(*STI, *MRI, MCOptions); + MCAsmBackend *MAB = TheTarget->createMCAsmBackend(*STI, *MCRI, MCOptions); Str.reset(TheTarget->createMCObjectStreamer( TheTriple, Ctx, std::unique_ptr(MAB), DwoOut ? MAB->createDwoObjectWriter(*OS, DwoOut->os()) diff --git a/llvm/tools/llvm-mca/llvm-mca.cpp b/llvm/tools/llvm-mca/llvm-mca.cpp --- a/llvm/tools/llvm-mca/llvm-mca.cpp +++ b/llvm/tools/llvm-mca/llvm-mca.cpp @@ -388,12 +388,12 @@ bool IsOutOfOrder = STI->getSchedModel().isOutOfOrder(); processViewOptions(IsOutOfOrder); - std::unique_ptr MRI(TheTarget->createMCRegInfo(TripleName)); - assert(MRI && "Unable to create target register info!"); + std::unique_ptr MCRI(TheTarget->createMCRegInfo(TripleName)); + assert(MCRI && "Unable to create target register info!"); MCTargetOptions MCOptions = mc::InitMCTargetOptionsFromFlags(); std::unique_ptr MAI( - TheTarget->createMCAsmInfo(*MRI, TripleName, MCOptions)); + TheTarget->createMCAsmInfo(*MCRI, TripleName, MCOptions)); assert(MAI && "Unable to create target asm info!"); SourceMgr SrcMgr; @@ -401,7 +401,7 @@ // Tell SrcMgr about this buffer, which is what the parser will pick up. SrcMgr.AddNewSourceBuffer(std::move(*BufferPtr), SMLoc()); - MCContext Ctx(TheTriple, MAI.get(), MRI.get(), STI.get(), &SrcMgr); + MCContext Ctx(TheTriple, MAI.get(), MCRI.get(), STI.get(), &SrcMgr); std::unique_ptr MOFI( TheTarget->createMCObjectFileInfo(Ctx, /*PIC=*/false)); Ctx.setObjectFileInfo(MOFI.get()); @@ -423,7 +423,7 @@ unsigned IPtempOutputAsmVariant = OutputAsmVariant == -1 ? 0 : OutputAsmVariant; std::unique_ptr IPtemp(TheTarget->createMCInstPrinter( - Triple(TripleName), IPtempOutputAsmVariant, *MAI, *MCII, *MRI)); + Triple(TripleName), IPtempOutputAsmVariant, *MAI, *MCII, *MCRI)); if (!IPtemp) { WithColor::error() << "unable to create instruction printer for target triple '" @@ -502,7 +502,7 @@ if (OutputAsmVariant >= 0) AssemblerDialect = static_cast(OutputAsmVariant); std::unique_ptr IP(TheTarget->createMCInstPrinter( - Triple(TripleName), AssemblerDialect, *MAI, *MCII, *MRI)); + Triple(TripleName), AssemblerDialect, *MAI, *MCII, *MCRI)); if (!IP) { WithColor::error() << "unable to create instruction printer for target triple '" @@ -534,10 +534,10 @@ } // Create an instruction builder. - mca::InstrBuilder IB(*STI, *MCII, *MRI, MCIA.get(), *IM); + mca::InstrBuilder IB(*STI, *MCII, *MCRI, MCIA.get(), *IM); // Create a context to control ownership of the pipeline hardware. - mca::Context MCA(*MRI, *STI); + mca::Context MCA(*MCRI, *STI); mca::PipelineOptions PO(MicroOpQueue, DecoderThroughput, DispatchWidth, RegisterFileSize, LoadQueueSize, StoreQueueSize, @@ -551,7 +551,7 @@ assert(MCE && "Unable to create code emitter!"); std::unique_ptr MAB(TheTarget->createMCAsmBackend( - *STI, *MRI, mc::InitMCTargetOptionsFromFlags())); + *STI, *MCRI, mc::InitMCTargetOptionsFromFlags())); assert(MAB && "Unable to create asm backend!"); json::Object JSONOutput; diff --git a/llvm/tools/llvm-ml/Disassembler.cpp b/llvm/tools/llvm-ml/Disassembler.cpp --- a/llvm/tools/llvm-ml/Disassembler.cpp +++ b/llvm/tools/llvm-ml/Disassembler.cpp @@ -127,22 +127,22 @@ MCSubtargetInfo &STI, MCStreamer &Streamer, MemoryBuffer &Buffer, SourceMgr &SM, raw_ostream &Out) { - std::unique_ptr MRI(T.createMCRegInfo(TripleName)); - if (!MRI) { + std::unique_ptr MCRI(T.createMCRegInfo(TripleName)); + if (!MCRI) { errs() << "error: no register info for target " << TripleName << "\n"; return -1; } MCTargetOptions MCOptions; std::unique_ptr MAI( - T.createMCAsmInfo(*MRI, TripleName, MCOptions)); + T.createMCAsmInfo(*MCRI, TripleName, MCOptions)); if (!MAI) { errs() << "error: no assembly info for target " << TripleName << "\n"; return -1; } // Set up the MCContext for creating symbols and MCExpr's. - MCContext Ctx(Triple(TripleName), MAI.get(), MRI.get(), &STI); + MCContext Ctx(Triple(TripleName), MAI.get(), MCRI.get(), &STI); std::unique_ptr DisAsm( T.createMCDisassembler(STI, Ctx)); diff --git a/llvm/tools/llvm-ml/llvm-ml.cpp b/llvm/tools/llvm-ml/llvm-ml.cpp --- a/llvm/tools/llvm-ml/llvm-ml.cpp +++ b/llvm/tools/llvm-ml/llvm-ml.cpp @@ -319,11 +319,11 @@ } SrcMgr.setIncludeDirs(IncludeDirs); - std::unique_ptr MRI(TheTarget->createMCRegInfo(TripleName)); - assert(MRI && "Unable to create target register info!"); + std::unique_ptr MCRI(TheTarget->createMCRegInfo(TripleName)); + assert(MCRI && "Unable to create target register info!"); std::unique_ptr MAI( - TheTarget->createMCAsmInfo(*MRI, TripleName, MCOptions)); + TheTarget->createMCAsmInfo(*MCRI, TripleName, MCOptions)); assert(MAI && "Unable to create target asm info!"); MAI->setPreserveAsmComments(InputArgs.hasArg(OPT_preserve_comments)); @@ -334,7 +334,7 @@ // FIXME: This is not pretty. MCContext has a ptr to MCObjectFileInfo and // MCObjectFileInfo needs a MCContext reference in order to initialize itself. - MCContext Ctx(TheTriple, MAI.get(), MRI.get(), STI.get(), &SrcMgr); + MCContext Ctx(TheTriple, MAI.get(), MCRI.get(), STI.get(), &SrcMgr); std::unique_ptr MOFI(TheTarget->createMCObjectFileInfo( Ctx, /*PIC=*/false, /*LargeCodeModel=*/true)); Ctx.setObjectFileInfo(MOFI.get()); @@ -375,7 +375,7 @@ const unsigned OutputAsmVariant = OutputATTAsm ? 0U // ATT dialect : 1U; // Intel dialect IP = TheTarget->createMCInstPrinter(TheTriple, OutputAsmVariant, *MAI, - *MCII, *MRI); + *MCII, *MCRI); if (!IP) { WithColor::error() @@ -394,7 +394,7 @@ CE.reset(TheTarget->createMCCodeEmitter(*MCII, Ctx)); std::unique_ptr MAB( - TheTarget->createMCAsmBackend(*STI, *MRI, MCOptions)); + TheTarget->createMCAsmBackend(*STI, *MCRI, MCOptions)); auto FOut = std::make_unique(*OS); Str.reset(TheTarget->createAsmStreamer( Ctx, std::move(FOut), /*asmverbose*/ true, @@ -410,7 +410,7 @@ } MCCodeEmitter *CE = TheTarget->createMCCodeEmitter(*MCII, Ctx); - MCAsmBackend *MAB = TheTarget->createMCAsmBackend(*STI, *MRI, MCOptions); + MCAsmBackend *MAB = TheTarget->createMCAsmBackend(*STI, *MCRI, MCOptions); Str.reset(TheTarget->createMCObjectStreamer( TheTriple, Ctx, std::unique_ptr(MAB), MAB->createObjectWriter(*OS), std::unique_ptr(CE), *STI, diff --git a/llvm/tools/llvm-objdump/MachODump.cpp b/llvm/tools/llvm-objdump/MachODump.cpp --- a/llvm/tools/llvm-objdump/MachODump.cpp +++ b/llvm/tools/llvm-objdump/MachODump.cpp @@ -7578,16 +7578,16 @@ MCTargetOptions MCOptions; // Set up disassembler. - std::unique_ptr MRI( + std::unique_ptr MCRI( TheTarget->createMCRegInfo(TripleName)); - CHECK_TARGET_INFO_CREATION(MRI); + CHECK_TARGET_INFO_CREATION(MCRI); std::unique_ptr AsmInfo( - TheTarget->createMCAsmInfo(*MRI, TripleName, MCOptions)); + TheTarget->createMCAsmInfo(*MCRI, TripleName, MCOptions)); CHECK_TARGET_INFO_CREATION(AsmInfo); std::unique_ptr STI( TheTarget->createMCSubtargetInfo(TripleName, MachOMCPU, FeaturesStr)); CHECK_TARGET_INFO_CREATION(STI); - MCContext Ctx(Triple(TripleName), AsmInfo.get(), MRI.get(), STI.get()); + MCContext Ctx(Triple(TripleName), AsmInfo.get(), MCRI.get(), STI.get()); std::unique_ptr DisAsm( TheTarget->createMCDisassembler(*STI, Ctx)); CHECK_TARGET_INFO_CREATION(DisAsm); @@ -7603,7 +7603,7 @@ } int AsmPrinterVariant = AsmInfo->getAssemblerDialect(); std::unique_ptr IP(TheTarget->createMCInstPrinter( - Triple(TripleName), AsmPrinterVariant, *AsmInfo, *InstrInfo, *MRI)); + Triple(TripleName), AsmPrinterVariant, *AsmInfo, *InstrInfo, *MCRI)); CHECK_TARGET_INFO_CREATION(IP); // Set the display preference for hex vs. decimal immediates. IP->setPrintImmHex(PrintImmHex); @@ -7618,7 +7618,7 @@ // IP->setCommentStream(CommentStream); // Set up separate thumb disassembler if needed. - std::unique_ptr ThumbMRI; + std::unique_ptr ThumbMCRI; std::unique_ptr ThumbAsmInfo; std::unique_ptr ThumbSTI; std::unique_ptr ThumbDisAsm; @@ -7628,17 +7628,17 @@ struct DisassembleInfo ThumbSymbolizerInfo(nullptr, nullptr, nullptr, false); std::unique_ptr ThumbRelInfo; if (ThumbTarget) { - ThumbMRI.reset(ThumbTarget->createMCRegInfo(ThumbTripleName)); - CHECK_THUMB_TARGET_INFO_CREATION(ThumbMRI); + ThumbMCRI.reset(ThumbTarget->createMCRegInfo(ThumbTripleName)); + CHECK_THUMB_TARGET_INFO_CREATION(ThumbMCRI); ThumbAsmInfo.reset( - ThumbTarget->createMCAsmInfo(*ThumbMRI, ThumbTripleName, MCOptions)); + ThumbTarget->createMCAsmInfo(*ThumbMCRI, ThumbTripleName, MCOptions)); CHECK_THUMB_TARGET_INFO_CREATION(ThumbAsmInfo); ThumbSTI.reset( ThumbTarget->createMCSubtargetInfo(ThumbTripleName, MachOMCPU, FeaturesStr)); CHECK_THUMB_TARGET_INFO_CREATION(ThumbSTI); ThumbCtx.reset(new MCContext(Triple(ThumbTripleName), ThumbAsmInfo.get(), - ThumbMRI.get(), ThumbSTI.get())); + ThumbMCRI.get(), ThumbSTI.get())); ThumbDisAsm.reset(ThumbTarget->createMCDisassembler(*ThumbSTI, *ThumbCtx)); CHECK_THUMB_TARGET_INFO_CREATION(ThumbDisAsm); MCContext *PtrThumbCtx = ThumbCtx.get(); @@ -7653,7 +7653,7 @@ int ThumbAsmPrinterVariant = ThumbAsmInfo->getAssemblerDialect(); ThumbIP.reset(ThumbTarget->createMCInstPrinter( Triple(ThumbTripleName), ThumbAsmPrinterVariant, *ThumbAsmInfo, - *ThumbInstrInfo, *ThumbMRI)); + *ThumbInstrInfo, *ThumbMCRI)); CHECK_THUMB_TARGET_INFO_CREATION(ThumbIP); // Set the display preference for hex vs. decimal immediates. ThumbIP->setPrintImmHex(PrintImmHex); diff --git a/llvm/tools/llvm-objdump/SourcePrinter.h b/llvm/tools/llvm-objdump/SourcePrinter.h --- a/llvm/tools/llvm-objdump/SourcePrinter.h +++ b/llvm/tools/llvm-objdump/SourcePrinter.h @@ -36,7 +36,7 @@ bool liveAtAddress(object::SectionedAddress Addr); - void print(raw_ostream &OS, const MCRegisterInfo &MRI) const; + void print(raw_ostream &OS, const MCRegisterInfo &MCRI) const; }; /// Helper class for printing source variable locations alongside disassembly. @@ -60,7 +60,7 @@ // The columns we are currently drawing. IndexedMap ActiveCols; - const MCRegisterInfo &MRI; + const MCRegisterInfo &MCRI; const MCSubtargetInfo &STI; void addVariable(DWARFDie FuncDie, DWARFDie VarDie); @@ -81,8 +81,8 @@ unsigned findFreeColumn(); public: - LiveVariablePrinter(const MCRegisterInfo &MRI, const MCSubtargetInfo &STI) - : ActiveCols(Column()), MRI(MRI), STI(STI) {} + LiveVariablePrinter(const MCRegisterInfo &MCRI, const MCSubtargetInfo &STI) + : ActiveCols(Column()), MCRI(MCRI), STI(STI) {} void dump() const; diff --git a/llvm/tools/llvm-objdump/SourcePrinter.cpp b/llvm/tools/llvm-objdump/SourcePrinter.cpp --- a/llvm/tools/llvm-objdump/SourcePrinter.cpp +++ b/llvm/tools/llvm-objdump/SourcePrinter.cpp @@ -38,15 +38,15 @@ LocExpr.Range->HighPC > Addr.Address; } -void LiveVariable::print(raw_ostream &OS, const MCRegisterInfo &MRI) const { +void LiveVariable::print(raw_ostream &OS, const MCRegisterInfo &MCRI) const { DataExtractor Data({LocExpr.Expr.data(), LocExpr.Expr.size()}, Unit->getContext().isLittleEndian(), 0); DWARFExpression Expression(Data, Unit->getAddressByteSize()); - auto GetRegName = [&MRI, &OS](uint64_t DwarfRegNum, bool IsEH) -> StringRef { + auto GetRegName = [&MCRI, &OS](uint64_t DwarfRegNum, bool IsEH) -> StringRef { if (std::optional LLVMRegNum = - MRI.getLLVMRegNum(DwarfRegNum, IsEH)) - if (const char *RegName = MRI.getName(*LLVMRegNum)) + MCRI.getLLVMRegNum(DwarfRegNum, IsEH)) + if (const char *RegName = MCRI.getName(*LLVMRegNum)) return StringRef(RegName); OS << ""; return {}; @@ -136,7 +136,7 @@ void LiveVariablePrinter::dump() const { for (const LiveVariable &LV : LiveVariables) { dbgs() << LV.VarName << " @ " << LV.LocExpr.Range << ": "; - LV.print(dbgs(), MRI); + LV.print(dbgs(), MCRI); dbgs() << "\n"; } } @@ -293,7 +293,7 @@ OS << " = "; { WithColor ExprColor(OS, raw_ostream::CYAN); - LiveVariables[ActiveCols[ColIdx].VarIdx].print(OS, MRI); + LiveVariables[ActiveCols[ColIdx].VarIdx].print(OS, MCRI); } // If there are any columns to the right of the expression we just diff --git a/llvm/tools/llvm-objdump/llvm-objdump.cpp b/llvm/tools/llvm-objdump/llvm-objdump.cpp --- a/llvm/tools/llvm-objdump/llvm-objdump.cpp +++ b/llvm/tools/llvm-objdump/llvm-objdump.cpp @@ -2020,16 +2020,16 @@ Features.AddFeature("+all"); } - std::unique_ptr MRI( + std::unique_ptr MCRI( TheTarget->createMCRegInfo(TripleName)); - if (!MRI) + if (!MCRI) reportError(Obj->getFileName(), "no register info for target " + TripleName); // Set up disassembler. MCTargetOptions MCOptions; std::unique_ptr AsmInfo( - TheTarget->createMCAsmInfo(*MRI, TripleName, MCOptions)); + TheTarget->createMCAsmInfo(*MCRI, TripleName, MCOptions)); if (!AsmInfo) reportError(Obj->getFileName(), "no assembly info for target " + TripleName); @@ -2069,7 +2069,7 @@ if (!MII) reportError(Obj->getFileName(), "no instruction info for target " + TripleName); - MCContext Ctx(Triple(TripleName), AsmInfo.get(), MRI.get(), STI.get()); + MCContext Ctx(Triple(TripleName), AsmInfo.get(), MCRI.get(), STI.get()); // FIXME: for now initialize MCObjectFileInfo with default values std::unique_ptr MOFI( TheTarget->createMCObjectFileInfo(Ctx, /*PIC=*/false)); @@ -2101,7 +2101,7 @@ int AsmPrinterVariant = AsmInfo->getAssemblerDialect(); std::unique_ptr IP(TheTarget->createMCInstPrinter( - Triple(TripleName), AsmPrinterVariant, *AsmInfo, *MII, *MRI)); + Triple(TripleName), AsmPrinterVariant, *AsmInfo, *MII, *MCRI)); if (!IP) reportError(Obj->getFileName(), "no instruction printer for target " + TripleName); diff --git a/llvm/tools/llvm-profgen/ProfiledBinary.h b/llvm/tools/llvm-profgen/ProfiledBinary.h --- a/llvm/tools/llvm-profgen/ProfiledBinary.h +++ b/llvm/tools/llvm-profgen/ProfiledBinary.h @@ -202,7 +202,7 @@ std::vector TextSegmentOffsets; // Mutiple MC component info - std::unique_ptr MRI; + std::unique_ptr MCRI; std::unique_ptr AsmInfo; std::unique_ptr STI; std::unique_ptr MII; diff --git a/llvm/tools/llvm-profgen/ProfiledBinary.cpp b/llvm/tools/llvm-profgen/ProfiledBinary.cpp --- a/llvm/tools/llvm-profgen/ProfiledBinary.cpp +++ b/llvm/tools/llvm-profgen/ProfiledBinary.cpp @@ -602,12 +602,12 @@ std::string TripleName = TheTriple.getTriple(); StringRef FileName = Obj->getFileName(); - MRI.reset(TheTarget->createMCRegInfo(TripleName)); - if (!MRI) + MCRI.reset(TheTarget->createMCRegInfo(TripleName)); + if (!MCRI) exitWithError("no register info for target " + TripleName, FileName); MCTargetOptions MCOptions; - AsmInfo.reset(TheTarget->createMCAsmInfo(*MRI, TripleName, MCOptions)); + AsmInfo.reset(TheTarget->createMCAsmInfo(*MCRI, TripleName, MCOptions)); if (!AsmInfo) exitWithError("no assembly info for target " + TripleName, FileName); @@ -623,7 +623,7 @@ if (!MII) exitWithError("no instruction info for target " + TripleName, FileName); - MCContext Ctx(Triple(TripleName), AsmInfo.get(), MRI.get(), STI.get()); + MCContext Ctx(Triple(TripleName), AsmInfo.get(), MCRI.get(), STI.get()); std::unique_ptr MOFI( TheTarget->createMCObjectFileInfo(Ctx, /*PIC=*/false)); Ctx.setObjectFileInfo(MOFI.get()); @@ -635,7 +635,7 @@ int AsmPrinterVariant = AsmInfo->getAssemblerDialect(); IPrinter.reset(TheTarget->createMCInstPrinter( - Triple(TripleName), AsmPrinterVariant, *AsmInfo, *MII, *MRI)); + Triple(TripleName), AsmPrinterVariant, *AsmInfo, *MII, *MCRI)); IPrinter->setPrintBranchImmAsAddress(true); } diff --git a/llvm/tools/llvm-rtdyld/llvm-rtdyld.cpp b/llvm/tools/llvm-rtdyld/llvm-rtdyld.cpp --- a/llvm/tools/llvm-rtdyld/llvm-rtdyld.cpp +++ b/llvm/tools/llvm-rtdyld/llvm-rtdyld.cpp @@ -797,17 +797,17 @@ if (!STI) ErrorAndExit("Unable to create subtarget info!"); - std::unique_ptr MRI(TheTarget->createMCRegInfo(TripleName)); - if (!MRI) + std::unique_ptr MCRI(TheTarget->createMCRegInfo(TripleName)); + if (!MCRI) ErrorAndExit("Unable to create target register info!"); MCTargetOptions MCOptions; std::unique_ptr MAI( - TheTarget->createMCAsmInfo(*MRI, TripleName, MCOptions)); + TheTarget->createMCAsmInfo(*MCRI, TripleName, MCOptions)); if (!MAI) ErrorAndExit("Unable to create target asm info!"); - MCContext Ctx(Triple(TripleName), MAI.get(), MRI.get(), STI.get()); + MCContext Ctx(Triple(TripleName), MAI.get(), MCRI.get(), STI.get()); std::unique_ptr Disassembler( TheTarget->createMCDisassembler(*STI, Ctx)); @@ -819,7 +819,7 @@ ErrorAndExit("Unable to create target instruction info!"); std::unique_ptr InstPrinter( - TheTarget->createMCInstPrinter(Triple(TripleName), 0, *MAI, *MII, *MRI)); + TheTarget->createMCInstPrinter(Triple(TripleName), 0, *MAI, *MII, *MCRI)); // Load any dylibs requested on the command line. loadDylibs(); diff --git a/llvm/tools/sancov/sancov.cpp b/llvm/tools/sancov/sancov.cpp --- a/llvm/tools/sancov/sancov.cpp +++ b/llvm/tools/sancov/sancov.cpp @@ -729,16 +729,16 @@ TheTarget->createMCSubtargetInfo(TripleName, "", "")); failIfEmpty(STI, "no subtarget info for target " + TripleName); - std::unique_ptr MRI( + std::unique_ptr MCRI( TheTarget->createMCRegInfo(TripleName)); - failIfEmpty(MRI, "no register info for target " + TripleName); + failIfEmpty(MCRI, "no register info for target " + TripleName); MCTargetOptions MCOptions; std::unique_ptr AsmInfo( - TheTarget->createMCAsmInfo(*MRI, TripleName, MCOptions)); + TheTarget->createMCAsmInfo(*MCRI, TripleName, MCOptions)); failIfEmpty(AsmInfo, "no asm info for target " + TripleName); - MCContext Ctx(TheTriple, AsmInfo.get(), MRI.get(), STI.get()); + MCContext Ctx(TheTriple, AsmInfo.get(), MCRI.get(), STI.get()); std::unique_ptr DisAsm( TheTarget->createMCDisassembler(*STI, Ctx)); failIfEmpty(DisAsm, "no disassembler info for target " + TripleName); diff --git a/llvm/unittests/DebugInfo/DWARF/DWARFExpressionCompactPrinterTest.cpp b/llvm/unittests/DebugInfo/DWARF/DWARFExpressionCompactPrinterTest.cpp --- a/llvm/unittests/DebugInfo/DWARF/DWARFExpressionCompactPrinterTest.cpp +++ b/llvm/unittests/DebugInfo/DWARF/DWARFExpressionCompactPrinterTest.cpp @@ -25,7 +25,7 @@ namespace { class DWARFExpressionCompactPrinterTest : public ::testing::Test { public: - std::unique_ptr MRI; + std::unique_ptr MCRI; DWARFExpressionCompactPrinterTest() { InitializeAllTargets(); @@ -41,7 +41,7 @@ if (!TheTarget) return; - MRI.reset(TheTarget->createMCRegInfo(TripleName)); + MCRI.reset(TheTarget->createMCRegInfo(TripleName)); } void TestExprPrinter(ArrayRef ExprData, StringRef Expected); @@ -51,7 +51,7 @@ void DWARFExpressionCompactPrinterTest::TestExprPrinter( ArrayRef ExprData, StringRef Expected) { // If we didn't build ARM, do not run the test. - if (!MRI) + if (!MCRI) GTEST_SKIP(); // Print the expression, passing in the subprogram DIE, and check that the @@ -63,8 +63,8 @@ auto GetRegName = [&](uint64_t DwarfRegNum, bool IsEH) -> StringRef { if (std::optional LLVMRegNum = - this->MRI->getLLVMRegNum(DwarfRegNum, IsEH)) - if (const char *RegName = this->MRI->getName(*LLVMRegNum)) + this->MCRI->getLLVMRegNum(DwarfRegNum, IsEH)) + if (const char *RegName = this->MCRI->getName(*LLVMRegNum)) return llvm::StringRef(RegName); OS << ""; return {}; diff --git a/llvm/unittests/DebugInfo/DWARF/DWARFExpressionCopyBytesTest.cpp b/llvm/unittests/DebugInfo/DWARF/DWARFExpressionCopyBytesTest.cpp --- a/llvm/unittests/DebugInfo/DWARF/DWARFExpressionCopyBytesTest.cpp +++ b/llvm/unittests/DebugInfo/DWARF/DWARFExpressionCopyBytesTest.cpp @@ -46,7 +46,7 @@ class DWARFExpressionCopyBytesTest : public ::testing::Test { public: const char *TripleName = "x86_64-pc-linux"; - std::unique_ptr MRI; + std::unique_ptr MCRI; std::unique_ptr MAI; std::unique_ptr STI; const Target *TheTarget; @@ -61,8 +61,8 @@ if (!TheTarget) return; - MRI.reset(TheTarget->createMCRegInfo(TripleName)); - MAI.reset(TheTarget->createMCAsmInfo(*MRI, TripleName, MCTargetOptions())); + MCRI.reset(TheTarget->createMCRegInfo(TripleName)); + MAI.reset(TheTarget->createMCAsmInfo(*MCRI, TripleName, MCTargetOptions())); STI.reset(TheTarget->createMCSubtargetInfo(TripleName, "", "")); } @@ -99,7 +99,7 @@ DWARFExpressionCopyBytesTest::createStreamer(raw_pwrite_stream &OS) { StreamerContext Res; Res.Ctx = - std::make_unique(Triple(TripleName), MAI.get(), MRI.get(), + std::make_unique(Triple(TripleName), MAI.get(), MCRI.get(), /*MSTI=*/nullptr); Res.MOFI.reset(TheTarget->createMCObjectFileInfo(*Res.Ctx.get(), /*PIC=*/false)); @@ -108,7 +108,7 @@ Res.MII.reset(TheTarget->createMCInstrInfo()); MCCodeEmitter *MCE = TheTarget->createMCCodeEmitter(*Res.MII, *Res.Ctx); MCAsmBackend *MAB = - TheTarget->createMCAsmBackend(*STI, *MRI, MCTargetOptions()); + TheTarget->createMCAsmBackend(*STI, *MCRI, MCTargetOptions()); std::unique_ptr OW = MAB->createObjectWriter(OS); Res.Streamer.reset(TheTarget->createMCObjectStreamer( Triple(TripleName), *Res.Ctx, std::unique_ptr(MAB), @@ -188,7 +188,7 @@ void DWARFExpressionCopyBytesTest::testExpr(ArrayRef ExprData) { // If we didn't build x86, do not run the test. - if (!MRI) + if (!MCRI) GTEST_SKIP(); DataExtractor DE(ExprData, true, 8); diff --git a/llvm/unittests/DebugInfo/DWARF/DwarfGenerator.h b/llvm/unittests/DebugInfo/DWARF/DwarfGenerator.h --- a/llvm/unittests/DebugInfo/DWARF/DwarfGenerator.h +++ b/llvm/unittests/DebugInfo/DWARF/DwarfGenerator.h @@ -241,7 +241,7 @@ /// calling Generator::addCompileUnit(), and then getting the dwarfgen::DIE from /// the returned compile unit and adding attributes and children to each DIE. class Generator { - std::unique_ptr MRI; + std::unique_ptr MCRI; std::unique_ptr MAI; std::unique_ptr MC; MCAsmBackend *MAB; // Owned by MCStreamer diff --git a/llvm/unittests/DebugInfo/DWARF/DwarfGenerator.cpp b/llvm/unittests/DebugInfo/DWARF/DwarfGenerator.cpp --- a/llvm/unittests/DebugInfo/DWARF/DwarfGenerator.cpp +++ b/llvm/unittests/DebugInfo/DWARF/DwarfGenerator.cpp @@ -425,14 +425,14 @@ TripleName = TheTriple.getTriple(); // Create all the MC Objects. - MRI.reset(TheTarget->createMCRegInfo(TripleName)); - if (!MRI) + MCRI.reset(TheTarget->createMCRegInfo(TripleName)); + if (!MCRI) return make_error(Twine("no register info for target ") + TripleName, inconvertibleErrorCode()); MCTargetOptions MCOptions = mc::InitMCTargetOptionsFromFlags(); - MAI.reset(TheTarget->createMCAsmInfo(*MRI, TripleName, MCOptions)); + MAI.reset(TheTarget->createMCAsmInfo(*MCRI, TripleName, MCOptions)); if (!MAI) return make_error("no asm info for target " + TripleName, inconvertibleErrorCode()); @@ -442,7 +442,7 @@ return make_error("no subtarget info for target " + TripleName, inconvertibleErrorCode()); - MAB = TheTarget->createMCAsmBackend(*MSTI, *MRI, MCOptions); + MAB = TheTarget->createMCAsmBackend(*MSTI, *MCRI, MCOptions); if (!MAB) return make_error("no asm backend for target " + TripleName, inconvertibleErrorCode()); @@ -459,7 +459,7 @@ return make_error("no target machine for target " + TripleName, inconvertibleErrorCode()); - MC.reset(new MCContext(TheTriple, MAI.get(), MRI.get(), MSTI.get())); + MC.reset(new MCContext(TheTriple, MAI.get(), MCRI.get(), MSTI.get())); TLOF = TM->getObjFileLowering(); TLOF->Initialize(*MC, *TM); MC->setObjectFileInfo(TLOF); diff --git a/llvm/unittests/MC/AMDGPU/DwarfRegMappings.cpp b/llvm/unittests/MC/AMDGPU/DwarfRegMappings.cpp --- a/llvm/unittests/MC/AMDGPU/DwarfRegMappings.cpp +++ b/llvm/unittests/MC/AMDGPU/DwarfRegMappings.cpp @@ -47,14 +47,14 @@ {"amdgcn-amd-", "amdgcn-amd-amdhsa", "amdgcn-amd-amdpal"}) { auto TM = createTargetMachine(Triple, "gfx1010", "+wavefrontsize64"); if (TM && TM->getMCRegisterInfo()) { - auto MRI = TM->getMCRegisterInfo(); + auto MCRI = TM->getMCRegisterInfo(); // Wave64 Dwarf register mapping test numbers // PC_64 => 16, EXEC_MASK_64 => 17, S0 => 32, S63 => 95, // S64 => 1088, S105 => 1129, V0 => 2560, V255 => 2815, // A0 => 3072, A255 => 3327 for (int llvmReg : {16, 17, 32, 95, 1088, 1129, 2560, 2815, 3072, 3327}) { - MCRegister PCReg(*MRI->getLLVMRegNum(llvmReg, false)); - EXPECT_EQ(llvmReg, MRI->getDwarfRegNum(PCReg, false)); + MCRegister PCReg(*MCRI->getLLVMRegNum(llvmReg, false)); + EXPECT_EQ(llvmReg, MCRI->getDwarfRegNum(PCReg, false)); } } } @@ -65,14 +65,14 @@ {"amdgcn-amd-", "amdgcn-amd-amdhsa", "amdgcn-amd-amdpal"}) { auto TM = createTargetMachine(Triple, "gfx1010", "+wavefrontsize32"); if (TM && TM->getMCRegisterInfo()) { - auto MRI = TM->getMCRegisterInfo(); + auto MCRI = TM->getMCRegisterInfo(); // Wave32 Dwarf register mapping test numbers // PC_64 => 16, EXEC_MASK_32 => 1, S0 => 32, S63 => 95, // S64 => 1088, S105 => 1129, V0 => 1536, V255 => 1791, // A0 => 2048, A255 => 2303 for (int llvmReg : {16, 1, 32, 95, 1088, 1129, 1536, 1791, 2048, 2303}) { - MCRegister PCReg(*MRI->getLLVMRegNum(llvmReg, false)); - EXPECT_EQ(llvmReg, MRI->getDwarfRegNum(PCReg, false)); + MCRegister PCReg(*MCRI->getLLVMRegNum(llvmReg, false)); + EXPECT_EQ(llvmReg, MCRI->getDwarfRegNum(PCReg, false)); } } } diff --git a/llvm/unittests/MC/DwarfLineTableHeaders.cpp b/llvm/unittests/MC/DwarfLineTableHeaders.cpp --- a/llvm/unittests/MC/DwarfLineTableHeaders.cpp +++ b/llvm/unittests/MC/DwarfLineTableHeaders.cpp @@ -37,7 +37,7 @@ class DwarfLineTableHeaders : public ::testing::Test { public: const char *TripleName = "x86_64-pc-linux"; - std::unique_ptr MRI; + std::unique_ptr MCRI; std::unique_ptr MAI; std::unique_ptr STI; const Target *TheTarget; @@ -60,9 +60,9 @@ if (!TheTarget) return; - MRI.reset(TheTarget->createMCRegInfo(TripleName)); + MCRI.reset(TheTarget->createMCRegInfo(TripleName)); MCTargetOptions MCOptions; - MAI.reset(TheTarget->createMCAsmInfo(*MRI, TripleName, MCOptions)); + MAI.reset(TheTarget->createMCAsmInfo(*MCRI, TripleName, MCOptions)); STI.reset(TheTarget->createMCSubtargetInfo(TripleName, "", "")); } @@ -70,7 +70,7 @@ StreamerContext createStreamer(raw_pwrite_stream &OS) { StreamerContext Res; Res.Ctx = - std::make_unique(Triple(TripleName), MAI.get(), MRI.get(), + std::make_unique(Triple(TripleName), MAI.get(), MCRI.get(), /*MSTI=*/nullptr); Res.MOFI.reset(TheTarget->createMCObjectFileInfo(*Res.Ctx.get(), /*PIC=*/false)); @@ -79,7 +79,7 @@ Res.MII.reset(TheTarget->createMCInstrInfo()); MCCodeEmitter *MCE = TheTarget->createMCCodeEmitter(*Res.MII, *Res.Ctx); MCAsmBackend *MAB = - TheTarget->createMCAsmBackend(*STI, *MRI, MCTargetOptions()); + TheTarget->createMCAsmBackend(*STI, *MCRI, MCTargetOptions()); std::unique_ptr OW = MAB->createObjectWriter(OS); Res.Streamer.reset(TheTarget->createMCObjectStreamer( Triple(TripleName), *Res.Ctx, std::unique_ptr(MAB), @@ -199,7 +199,7 @@ } // namespace TEST_F(DwarfLineTableHeaders, TestDWARF4HeaderEmission) { - if (!MRI) + if (!MCRI) return; SmallString<0> EmittedBinContents; @@ -223,7 +223,7 @@ } TEST_F(DwarfLineTableHeaders, TestDWARF5HeaderEmission) { - if (!MRI) + if (!MCRI) return; SmallString<0> EmittedBinContents; diff --git a/llvm/unittests/MC/DwarfLineTables.cpp b/llvm/unittests/MC/DwarfLineTables.cpp --- a/llvm/unittests/MC/DwarfLineTables.cpp +++ b/llvm/unittests/MC/DwarfLineTables.cpp @@ -22,7 +22,7 @@ namespace { struct Context { const char *TripleName = "x86_64-pc-linux"; - std::unique_ptr MRI; + std::unique_ptr MCRI; std::unique_ptr MAI; std::unique_ptr Ctx; @@ -37,10 +37,10 @@ if (!TheTarget) return; - MRI.reset(TheTarget->createMCRegInfo(TripleName)); + MCRI.reset(TheTarget->createMCRegInfo(TripleName)); MCTargetOptions MCOptions; - MAI.reset(TheTarget->createMCAsmInfo(*MRI, TripleName, MCOptions)); - Ctx = std::make_unique(Triple(TripleName), MAI.get(), MRI.get(), + MAI.reset(TheTarget->createMCAsmInfo(*MCRI, TripleName, MCOptions)); + Ctx = std::make_unique(Triple(TripleName), MAI.get(), MCRI.get(), /*MSTI=*/nullptr); } diff --git a/llvm/unittests/MC/MCInstPrinter.cpp b/llvm/unittests/MC/MCInstPrinter.cpp --- a/llvm/unittests/MC/MCInstPrinter.cpp +++ b/llvm/unittests/MC/MCInstPrinter.cpp @@ -22,7 +22,7 @@ namespace { class MCInstPrinterTest : public ::testing::Test { public: - std::unique_ptr MRI; + std::unique_ptr MCRI; std::unique_ptr MAI; std::unique_ptr MII; std::unique_ptr Printer; @@ -41,12 +41,12 @@ if (!TheTarget) return; - MRI.reset(TheTarget->createMCRegInfo(TripleName)); + MCRI.reset(TheTarget->createMCRegInfo(TripleName)); MCTargetOptions MCOptions; - MAI.reset(TheTarget->createMCAsmInfo(*MRI, TripleName, MCOptions)); + MAI.reset(TheTarget->createMCAsmInfo(*MCRI, TripleName, MCOptions)); MII.reset(TheTarget->createMCInstrInfo()); Printer.reset(TheTarget->createMCInstPrinter( - Triple(TripleName), MAI->getAssemblerDialect(), *MAI, *MII, *MRI)); + Triple(TripleName), MAI->getAssemblerDialect(), *MAI, *MII, *MCRI)); } template std::string formatHex(T i) { diff --git a/llvm/unittests/MC/SystemZ/SystemZAsmLexerTest.cpp b/llvm/unittests/MC/SystemZ/SystemZAsmLexerTest.cpp --- a/llvm/unittests/MC/SystemZ/SystemZAsmLexerTest.cpp +++ b/llvm/unittests/MC/SystemZ/SystemZAsmLexerTest.cpp @@ -35,7 +35,7 @@ LLVMInitializeSystemZAsmParser(); } - std::unique_ptr MRI; + std::unique_ptr MCRI; std::unique_ptr MAI; std::unique_ptr MII; std::unique_ptr MOFI; @@ -64,8 +64,8 @@ TheTarget = TargetRegistry::lookupTarget(TripleName, Error); EXPECT_NE(TheTarget, nullptr); - MRI.reset(TheTarget->createMCRegInfo(TripleName)); - EXPECT_NE(MRI, nullptr); + MCRI.reset(TheTarget->createMCRegInfo(TripleName)); + EXPECT_NE(MCRI, nullptr); MII.reset(TheTarget->createMCInstrInfo()); EXPECT_NE(MII, nullptr); @@ -73,7 +73,7 @@ STI.reset(TheTarget->createMCSubtargetInfo(TripleName, "z10", "")); EXPECT_NE(STI, nullptr); - MAI.reset(TheTarget->createMCAsmInfo(*MRI, TripleName, MCOptions)); + MAI.reset(TheTarget->createMCAsmInfo(*MCRI, TripleName, MCOptions)); EXPECT_NE(MAI, nullptr); } @@ -82,7 +82,7 @@ SrcMgr.AddNewSourceBuffer(std::move(Buffer), SMLoc()); EXPECT_EQ(Buffer, nullptr); - Ctx.reset(new MCContext(Triple, MAI.get(), MRI.get(), STI.get(), &SrcMgr, + Ctx.reset(new MCContext(Triple, MAI.get(), MCRI.get(), STI.get(), &SrcMgr, &MCOptions)); MOFI.reset(TheTarget->createMCObjectFileInfo(*Ctx, /*PIC=*/false, /*LargeCodeModel=*/false)); diff --git a/llvm/unittests/MC/X86/X86MCDisassemblerTest.cpp b/llvm/unittests/MC/X86/X86MCDisassemblerTest.cpp --- a/llvm/unittests/MC/X86/X86MCDisassemblerTest.cpp +++ b/llvm/unittests/MC/X86/X86MCDisassemblerTest.cpp @@ -24,7 +24,7 @@ struct Context { const char *TripleName = "x86_64-unknown-elf"; - std::unique_ptr MRI; + std::unique_ptr MCRI; std::unique_ptr MAI; std::unique_ptr Ctx; std::unique_ptr STI; @@ -41,10 +41,10 @@ if (!TheTarget) return; - MRI.reset(TheTarget->createMCRegInfo(TripleName)); - MAI.reset(TheTarget->createMCAsmInfo(*MRI, TripleName, MCTargetOptions())); + MCRI.reset(TheTarget->createMCRegInfo(TripleName)); + MAI.reset(TheTarget->createMCAsmInfo(*MCRI, TripleName, MCTargetOptions())); STI.reset(TheTarget->createMCSubtargetInfo(TripleName, "", "")); - Ctx = std::make_unique(Triple(TripleName), MAI.get(), MRI.get(), + Ctx = std::make_unique(Triple(TripleName), MAI.get(), MCRI.get(), STI.get()); DisAsm.reset(TheTarget->createMCDisassembler(*STI, *Ctx)); diff --git a/llvm/unittests/Target/AArch64/AArch64InstPrinterTest.cpp b/llvm/unittests/Target/AArch64/AArch64InstPrinterTest.cpp --- a/llvm/unittests/Target/AArch64/AArch64InstPrinterTest.cpp +++ b/llvm/unittests/Target/AArch64/AArch64InstPrinterTest.cpp @@ -24,8 +24,8 @@ class AArch64InstPrinterTest : public AArch64InstPrinter { public: AArch64InstPrinterTest(const MCAsmInfo &MAI, const MCInstrInfo &MII, - const MCRegisterInfo &MRI) - : AArch64InstPrinter(MAI, MII, MRI) {} + const MCRegisterInfo &MCRI) + : AArch64InstPrinter(MAI, MII, MCRI) {} void printAlignedLabel(const MCInst *MI, uint64_t Address, unsigned OpNum, const MCSubtargetInfo &STI, raw_ostream &O) { AArch64InstPrinter::printAlignedLabel(MI, Address, OpNum, STI, O); @@ -35,19 +35,19 @@ static std::string AArch64InstPrinterTestPrintAlignedLabel(uint64_t value) { MCAsmInfo MAI; MCInstrInfo MII; - MCRegisterInfo MRI; + MCRegisterInfo MCRI; MCSubtargetInfo STI(Triple(""), "", "", "", ArrayRef((SubtargetFeatureKV *)NULL, (size_t)0), ArrayRef((SubtargetSubTypeKV *)NULL, (size_t)0), NULL, NULL, NULL, NULL, NULL, NULL); - MCContext Ctx(Triple(""), &MAI, &MRI, &STI); + MCContext Ctx(Triple(""), &MAI, &MCRI, &STI); MCInst MI; MI.addOperand(MCOperand::createExpr(MCConstantExpr::create(value, Ctx))); std::string str; raw_string_ostream O(str); - AArch64InstPrinterTest(MAI, MII, MRI).printAlignedLabel(&MI, 0, 0, STI, O); + AArch64InstPrinterTest(MAI, MII, MCRI).printAlignedLabel(&MI, 0, 0, STI, O); return str; } diff --git a/llvm/unittests/tools/llvm-mca/MCATestBase.h b/llvm/unittests/tools/llvm-mca/MCATestBase.h --- a/llvm/unittests/tools/llvm-mca/MCATestBase.h +++ b/llvm/unittests/tools/llvm-mca/MCATestBase.h @@ -58,7 +58,7 @@ // MC components. std::unique_ptr STI; - std::unique_ptr MRI; + std::unique_ptr MCRI; std::unique_ptr MAI; std::unique_ptr MOFI; std::unique_ptr Ctx; diff --git a/llvm/unittests/tools/llvm-mca/MCATestBase.cpp b/llvm/unittests/tools/llvm-mca/MCATestBase.cpp --- a/llvm/unittests/tools/llvm-mca/MCATestBase.cpp +++ b/llvm/unittests/tools/llvm-mca/MCATestBase.cpp @@ -37,14 +37,15 @@ ASSERT_TRUE(STI); ASSERT_TRUE(STI->isCPUStringValid(CPUName)); - MRI.reset(TheTarget->createMCRegInfo(TripleName)); - ASSERT_TRUE(MRI); + MCRI.reset(TheTarget->createMCRegInfo(TripleName)); + ASSERT_TRUE(MCRI); auto MCOptions = getMCTargetOptions(); - MAI.reset(TheTarget->createMCAsmInfo(*MRI, TripleName, MCOptions)); + MAI.reset(TheTarget->createMCAsmInfo(*MCRI, TripleName, MCOptions)); ASSERT_TRUE(MAI); - Ctx = std::make_unique(TheTriple, MAI.get(), MRI.get(), STI.get()); + Ctx = + std::make_unique(TheTriple, MAI.get(), MCRI.get(), STI.get()); MOFI.reset(TheTarget->createMCObjectFileInfo(*Ctx, /*PIC=*/false)); Ctx->setObjectFileInfo(MOFI.get()); @@ -55,18 +56,18 @@ ASSERT_TRUE(MCIA); IP.reset(TheTarget->createMCInstPrinter(TheTriple, /*AssemblerDialect=*/0, - *MAI, *MCII, *MRI)); + *MAI, *MCII, *MCRI)); ASSERT_TRUE(IP); } Error MCATestBase::runBaselineMCA(json::Object &Result, ArrayRef Insts, ArrayRef Views, const mca::PipelineOptions *PO) { - mca::Context MCA(*MRI, *STI); + mca::Context MCA(*MCRI, *STI); // Default InstrumentManager auto IM = std::make_unique(*STI, *MCII); - mca::InstrBuilder IB(*STI, *MCII, *MRI, MCIA.get(), *IM); + mca::InstrBuilder IB(*STI, *MCII, *MCRI, MCIA.get(), *IM); const SmallVector Instruments; SmallVector> LoweredInsts; diff --git a/llvm/unittests/tools/llvm-mca/X86/TestIncrementalMCA.cpp b/llvm/unittests/tools/llvm-mca/X86/TestIncrementalMCA.cpp --- a/llvm/unittests/tools/llvm-mca/X86/TestIncrementalMCA.cpp +++ b/llvm/unittests/tools/llvm-mca/X86/TestIncrementalMCA.cpp @@ -14,7 +14,7 @@ using namespace mca; TEST_F(X86TestBase, TestResumablePipeline) { - mca::Context MCA(*MRI, *STI); + mca::Context MCA(*MCRI, *STI); mca::IncrementalSourceMgr ISM; // Empty CustomBehaviour. @@ -33,7 +33,7 @@ P->addEventListener(SV.get()); auto IM = std::make_unique(*STI, *MCII); - mca::InstrBuilder IB(*STI, *MCII, *MRI, MCIA.get(), *IM); + mca::InstrBuilder IB(*STI, *MCII, *MCRI, MCIA.get(), *IM); const SmallVector Instruments; // Tile size = 7 @@ -82,7 +82,7 @@ } TEST_F(X86TestBase, TestInstructionRecycling) { - mca::Context MCA(*MRI, *STI); + mca::Context MCA(*MCRI, *STI); std::unordered_map> RecycledInsts; @@ -124,7 +124,7 @@ // Default InstrumentManager auto IM = std::make_unique(*STI, *MCII); - mca::InstrBuilder IB(*STI, *MCII, *MRI, MCIA.get(), *IM); + mca::InstrBuilder IB(*STI, *MCII, *MCRI, MCIA.get(), *IM); IB.setInstRecycleCallback(GetRecycledInst); const SmallVector Instruments;