diff --git a/llvm/include/llvm/TargetParser/RISCVTargetParser.h b/llvm/include/llvm/TargetParser/RISCVTargetParser.h --- a/llvm/include/llvm/TargetParser/RISCVTargetParser.h +++ b/llvm/include/llvm/TargetParser/RISCVTargetParser.h @@ -24,17 +24,11 @@ static constexpr unsigned RVVBitsPerBlock = 64; enum CPUKind : unsigned { -#define PROC(ENUM, NAME, FEATURES, DEFAULT_MARCH) CK_##ENUM, +#define PROC(ENUM, NAME, DEFAULT_MARCH) CK_##ENUM, #define TUNE_PROC(ENUM, NAME) CK_##ENUM, #include "llvm/TargetParser/RISCVTargetParserDef.inc" }; -enum FeatureKind : unsigned { - FK_INVALID = 0, - FK_NONE = 1, - FK_64BIT = 1 << 2, -}; - bool checkCPUKind(CPUKind Kind, bool IsRV64); bool checkTuneCPUKind(CPUKind Kind, bool IsRV64); CPUKind parseCPUKind(StringRef CPU); diff --git a/llvm/lib/TargetParser/RISCVTargetParser.cpp b/llvm/lib/TargetParser/RISCVTargetParser.cpp --- a/llvm/lib/TargetParser/RISCVTargetParser.cpp +++ b/llvm/lib/TargetParser/RISCVTargetParser.cpp @@ -21,14 +21,14 @@ struct CPUInfo { StringLiteral Name; CPUKind Kind; - unsigned Features; StringLiteral DefaultMarch; - bool is64Bit() const { return (Features & FK_64BIT); } + bool isInvalid() const { return DefaultMarch.empty(); } + bool is64Bit() const { return DefaultMarch.starts_with("rv64"); } }; constexpr CPUInfo RISCVCPUInfo[] = { -#define PROC(ENUM, NAME, FEATURES, DEFAULT_MARCH) \ - {NAME, CK_##ENUM, FEATURES, DEFAULT_MARCH}, +#define PROC(ENUM, NAME, DEFAULT_MARCH) \ + {NAME, CK_##ENUM, DEFAULT_MARCH}, #include "llvm/TargetParser/RISCVTargetParserDef.inc" }; @@ -50,14 +50,14 @@ CPUKind parseCPUKind(StringRef CPU) { return llvm::StringSwitch(CPU) -#define PROC(ENUM, NAME, FEATURES, DEFAULT_MARCH) .Case(NAME, CK_##ENUM) +#define PROC(ENUM, NAME, DEFAULT_MARCH) .Case(NAME, CK_##ENUM) #include "llvm/TargetParser/RISCVTargetParserDef.inc" .Default(CK_INVALID); } CPUKind parseTuneCPUKind(StringRef TuneCPU, bool IsRV64) { return llvm::StringSwitch(TuneCPU) -#define PROC(ENUM, NAME, FEATURES, DEFAULT_MARCH) .Case(NAME, CK_##ENUM) +#define PROC(ENUM, NAME, DEFAULT_MARCH) .Case(NAME, CK_##ENUM) #define TUNE_PROC(ENUM, NAME) .Case(NAME, CK_##ENUM) #include "llvm/TargetParser/RISCVTargetParserDef.inc" .Default(CK_INVALID); @@ -87,12 +87,12 @@ // Get all features except standard extension feature bool getCPUFeaturesExceptStdExt(CPUKind Kind, std::vector &Features) { - unsigned CPUFeatures = RISCVCPUInfo[static_cast(Kind)].Features; + const CPUInfo &Info = RISCVCPUInfo[static_cast(Kind)]; - if (CPUFeatures == FK_INVALID) + if (Info.isInvalid()) return false; - if (CPUFeatures & FK_64BIT) + if (Info.is64Bit()) Features.push_back("+64bit"); else Features.push_back("-64bit"); diff --git a/llvm/utils/TableGen/RISCVTargetDefEmitter.cpp b/llvm/utils/TableGen/RISCVTargetDefEmitter.cpp --- a/llvm/utils/TableGen/RISCVTargetDefEmitter.cpp +++ b/llvm/utils/TableGen/RISCVTargetDefEmitter.cpp @@ -54,16 +54,12 @@ return (*ISAInfo)->toString(); } -static std::string getEnumFeatures(int XLen) { - return XLen == 64 ? "FK_64BIT" : "FK_NONE"; -} - void llvm::EmitRISCVTargetDef(const RecordKeeper &RK, raw_ostream &OS) { OS << "#ifndef PROC\n" - << "#define PROC(ENUM, NAME, FEATURES, DEFAULT_MARCH)\n" + << "#define PROC(ENUM, NAME, DEFAULT_MARCH)\n" << "#endif\n\n"; - OS << "PROC(INVALID, {\"invalid\"}, FK_INVALID, {\"\"})\n"; + OS << "PROC(INVALID, {\"invalid\"}, {\"\"})\n"; // Iterate on all definition records. for (const Record *Rec : RK.getAllDerivedDefinitions("RISCVProcessorModel")) { int XLen = getXLen(*Rec); @@ -74,8 +70,7 @@ MArch = getMArch(XLen, *Rec); OS << "PROC(" << Rec->getName() << ", " - << "{\"" << Rec->getValueAsString("Name") << "\"}," - << getEnumFeatures(XLen) << ", " + << "{\"" << Rec->getValueAsString("Name") << "\"}, " << "{\"" << MArch << "\"})\n"; } OS << "\n#undef PROC\n";