diff --git a/mlir/include/mlir/Dialect/Arith/IR/ArithOps.td b/mlir/include/mlir/Dialect/Arith/IR/ArithOps.td
--- a/mlir/include/mlir/Dialect/Arith/IR/ArithOps.td
+++ b/mlir/include/mlir/Dialect/Arith/IR/ArithOps.td
@@ -102,7 +102,7 @@
 // excluding indices: signless integers, vectors or tensors thereof.
 def SignlessFixedWidthIntegerLike : TypeConstraint<Or<[
         AnySignlessInteger.predicate,
-        VectorOf<[AnySignlessInteger]>.predicate,
+        VectorOfAnyRankOf<[AnySignlessInteger]>.predicate,
         TensorOf<[AnySignlessInteger]>.predicate]>,
     "signless-fixed-width-integer-like">;
 
diff --git a/mlir/test/Conversion/ArithToLLVM/arith-to-llvm.mlir b/mlir/test/Conversion/ArithToLLVM/arith-to-llvm.mlir
--- a/mlir/test/Conversion/ArithToLLVM/arith-to-llvm.mlir
+++ b/mlir/test/Conversion/ArithToLLVM/arith-to-llvm.mlir
@@ -297,6 +297,18 @@
   return
 }
 
+// CHECK-LABEL: @integer_cast_0d_vector
+func.func @integer_cast_0d_vector(%arg0 : vector<i3>) {
+// CHECK: %[[ARG0:.*]] = builtin.unrealized_conversion_cast
+// CHECK-NEXT: = llvm.sext %[[ARG0]] : vector<1xi3> to vector<1xi6>
+  %0 = arith.extsi %arg0 : vector<i3> to vector<i6>
+// CHECK-NEXT: = llvm.zext %[[ARG0]] : vector<1xi3> to vector<1xi6>
+  %1 = arith.extui %arg0 : vector<i3> to vector<i6>
+// CHECK-NEXT: = llvm.trunc %[[ARG0]] : vector<1xi3> to vector<1xi2>
+  %2 = arith.trunci %arg0 : vector<i3> to vector<i2>
+  return
+}
+
 // CHECK-LABEL: func @fcmp(%arg0: f32, %arg1: f32) {
 func.func @fcmp(f32, f32) -> () {
 ^bb0(%arg0: f32, %arg1: f32):