diff --git a/llvm/lib/Target/RISCV/RISCVAsmPrinter.cpp b/llvm/lib/Target/RISCV/RISCVAsmPrinter.cpp
--- a/llvm/lib/Target/RISCV/RISCVAsmPrinter.cpp
+++ b/llvm/lib/Target/RISCV/RISCVAsmPrinter.cpp
@@ -443,10 +443,10 @@
                                                                             8),
         MCSTI);
     if (Reg != RISCV::X10)
-      OutStreamer->emitInstruction(MCInstBuilder(RISCV::OR)
+      OutStreamer->emitInstruction(MCInstBuilder(RISCV::ADDI)
                                        .addReg(RISCV::X10)
-                                       .addReg(RISCV::X0)
-                                       .addReg(Reg),
+                                       .addReg(Reg)
+                                       .addImm(0),
                                    MCSTI);
     OutStreamer->emitInstruction(
         MCInstBuilder(RISCV::ADDI)