diff --git a/llvm/lib/Target/RISCV/RISCVISelLowering.cpp b/llvm/lib/Target/RISCV/RISCVISelLowering.cpp --- a/llvm/lib/Target/RISCV/RISCVISelLowering.cpp +++ b/llvm/lib/Target/RISCV/RISCVISelLowering.cpp @@ -5922,19 +5922,19 @@ llvm_unreachable("Unhandled reduction"); case ISD::VECREDUCE_AND: case ISD::VP_REDUCE_AND: { - // vcpop ~x == 0 + // vfirst ~x < 0 SDValue TrueMask = DAG.getNode(RISCVISD::VMSET_VL, DL, ContainerVT, VL); Vec = DAG.getNode(RISCVISD::VMXOR_VL, DL, ContainerVT, Vec, TrueMask, VL); - Vec = DAG.getNode(RISCVISD::VCPOP_VL, DL, XLenVT, Vec, Mask, VL); - CC = ISD::SETEQ; + Vec = DAG.getNode(RISCVISD::VFIRST_VL, DL, XLenVT, Vec, Mask, VL); + CC = ISD::SETLT; BaseOpc = ISD::AND; break; } case ISD::VECREDUCE_OR: case ISD::VP_REDUCE_OR: - // vcpop x != 0 - Vec = DAG.getNode(RISCVISD::VCPOP_VL, DL, XLenVT, Vec, Mask, VL); - CC = ISD::SETNE; + // vfirst x >= 0 + Vec = DAG.getNode(RISCVISD::VFIRST_VL, DL, XLenVT, Vec, Mask, VL); + CC = ISD::SETGE; BaseOpc = ISD::OR; break; case ISD::VECREDUCE_XOR: @@ -5958,8 +5958,8 @@ // Note that we must return the start value when no elements are operated // upon. The vcpop instructions we've emitted in each case above will return // 0 for an inactive vector, and so we've already received the neutral value: - // AND gives us (0 == 0) -> 1 and OR/XOR give us (0 != 0) -> 0. Therefore we - // can simply include the start value. + // AND gives us (-1 < 0) -> 1, OR gives us (-1 >= 0) ->0, and XOR give us + // (0 != 0) -> 0. Therefore we can simply include the start value. return DAG.getNode(BaseOpc, DL, XLenVT, SetCC, Op.getOperand(0)); } diff --git a/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-reduction-mask-vp.ll b/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-reduction-mask-vp.ll --- a/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-reduction-mask-vp.ll +++ b/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-reduction-mask-vp.ll @@ -12,8 +12,8 @@ ; CHECK-NEXT: vsetvli zero, a1, e8, mf8, ta, ma ; CHECK-NEXT: vmnot.m v9, v0 ; CHECK-NEXT: vmv1r.v v0, v8 -; CHECK-NEXT: vcpop.m a1, v9, v0.t -; CHECK-NEXT: seqz a1, a1 +; CHECK-NEXT: vfirst.m a1, v9, v0.t +; CHECK-NEXT: slti a1, a1, 0 ; CHECK-NEXT: and a0, a1, a0 ; CHECK-NEXT: neg a0, a0 ; CHECK-NEXT: ret @@ -29,8 +29,9 @@ ; RV32-NEXT: vmv1r.v v9, v0 ; RV32-NEXT: vsetvli zero, a1, e8, mf8, ta, ma ; RV32-NEXT: vmv1r.v v0, v8 -; RV32-NEXT: vcpop.m a1, v9, v0.t -; RV32-NEXT: snez a1, a1 +; RV32-NEXT: vfirst.m a1, v9, v0.t +; RV32-NEXT: slti a1, a1, 0 +; RV32-NEXT: not a1, a1 ; RV32-NEXT: or a0, a1, a0 ; RV32-NEXT: slli a0, a0, 31 ; RV32-NEXT: srai a0, a0, 31 @@ -41,8 +42,9 @@ ; RV64-NEXT: vmv1r.v v9, v0 ; RV64-NEXT: vsetvli zero, a1, e8, mf8, ta, ma ; RV64-NEXT: vmv1r.v v0, v8 -; RV64-NEXT: vcpop.m a1, v9, v0.t -; RV64-NEXT: snez a1, a1 +; RV64-NEXT: vfirst.m a1, v9, v0.t +; RV64-NEXT: slti a1, a1, 0 +; RV64-NEXT: not a1, a1 ; RV64-NEXT: or a0, a1, a0 ; RV64-NEXT: slli a0, a0, 63 ; RV64-NEXT: srai a0, a0, 63 @@ -87,8 +89,8 @@ ; CHECK-NEXT: vsetvli zero, a1, e8, mf8, ta, ma ; CHECK-NEXT: vmnot.m v9, v0 ; CHECK-NEXT: vmv1r.v v0, v8 -; CHECK-NEXT: vcpop.m a1, v9, v0.t -; CHECK-NEXT: seqz a1, a1 +; CHECK-NEXT: vfirst.m a1, v9, v0.t +; CHECK-NEXT: slti a1, a1, 0 ; CHECK-NEXT: and a0, a1, a0 ; CHECK-NEXT: neg a0, a0 ; CHECK-NEXT: ret @@ -104,8 +106,9 @@ ; RV32-NEXT: vmv1r.v v9, v0 ; RV32-NEXT: vsetvli zero, a1, e8, mf8, ta, ma ; RV32-NEXT: vmv1r.v v0, v8 -; RV32-NEXT: vcpop.m a1, v9, v0.t -; RV32-NEXT: snez a1, a1 +; RV32-NEXT: vfirst.m a1, v9, v0.t +; RV32-NEXT: slti a1, a1, 0 +; RV32-NEXT: not a1, a1 ; RV32-NEXT: or a0, a1, a0 ; RV32-NEXT: slli a0, a0, 31 ; RV32-NEXT: srai a0, a0, 31 @@ -116,8 +119,9 @@ ; RV64-NEXT: vmv1r.v v9, v0 ; RV64-NEXT: vsetvli zero, a1, e8, mf8, ta, ma ; RV64-NEXT: vmv1r.v v0, v8 -; RV64-NEXT: vcpop.m a1, v9, v0.t -; RV64-NEXT: snez a1, a1 +; RV64-NEXT: vfirst.m a1, v9, v0.t +; RV64-NEXT: slti a1, a1, 0 +; RV64-NEXT: not a1, a1 ; RV64-NEXT: or a0, a1, a0 ; RV64-NEXT: slli a0, a0, 63 ; RV64-NEXT: srai a0, a0, 63 @@ -162,8 +166,8 @@ ; CHECK-NEXT: vsetvli zero, a1, e8, mf4, ta, ma ; CHECK-NEXT: vmnot.m v9, v0 ; CHECK-NEXT: vmv1r.v v0, v8 -; CHECK-NEXT: vcpop.m a1, v9, v0.t -; CHECK-NEXT: seqz a1, a1 +; CHECK-NEXT: vfirst.m a1, v9, v0.t +; CHECK-NEXT: slti a1, a1, 0 ; CHECK-NEXT: and a0, a1, a0 ; CHECK-NEXT: neg a0, a0 ; CHECK-NEXT: ret @@ -179,8 +183,9 @@ ; RV32-NEXT: vmv1r.v v9, v0 ; RV32-NEXT: vsetvli zero, a1, e8, mf4, ta, ma ; RV32-NEXT: vmv1r.v v0, v8 -; RV32-NEXT: vcpop.m a1, v9, v0.t -; RV32-NEXT: snez a1, a1 +; RV32-NEXT: vfirst.m a1, v9, v0.t +; RV32-NEXT: slti a1, a1, 0 +; RV32-NEXT: not a1, a1 ; RV32-NEXT: or a0, a1, a0 ; RV32-NEXT: slli a0, a0, 31 ; RV32-NEXT: srai a0, a0, 31 @@ -191,8 +196,9 @@ ; RV64-NEXT: vmv1r.v v9, v0 ; RV64-NEXT: vsetvli zero, a1, e8, mf4, ta, ma ; RV64-NEXT: vmv1r.v v0, v8 -; RV64-NEXT: vcpop.m a1, v9, v0.t -; RV64-NEXT: snez a1, a1 +; RV64-NEXT: vfirst.m a1, v9, v0.t +; RV64-NEXT: slti a1, a1, 0 +; RV64-NEXT: not a1, a1 ; RV64-NEXT: or a0, a1, a0 ; RV64-NEXT: slli a0, a0, 63 ; RV64-NEXT: srai a0, a0, 63 @@ -237,8 +243,8 @@ ; CHECK-NEXT: vsetvli zero, a1, e8, mf2, ta, ma ; CHECK-NEXT: vmnot.m v9, v0 ; CHECK-NEXT: vmv1r.v v0, v8 -; CHECK-NEXT: vcpop.m a1, v9, v0.t -; CHECK-NEXT: seqz a1, a1 +; CHECK-NEXT: vfirst.m a1, v9, v0.t +; CHECK-NEXT: slti a1, a1, 0 ; CHECK-NEXT: and a0, a1, a0 ; CHECK-NEXT: neg a0, a0 ; CHECK-NEXT: ret @@ -254,8 +260,9 @@ ; RV32-NEXT: vmv1r.v v9, v0 ; RV32-NEXT: vsetvli zero, a1, e8, mf2, ta, ma ; RV32-NEXT: vmv1r.v v0, v8 -; RV32-NEXT: vcpop.m a1, v9, v0.t -; RV32-NEXT: snez a1, a1 +; RV32-NEXT: vfirst.m a1, v9, v0.t +; RV32-NEXT: slti a1, a1, 0 +; RV32-NEXT: not a1, a1 ; RV32-NEXT: or a0, a1, a0 ; RV32-NEXT: slli a0, a0, 31 ; RV32-NEXT: srai a0, a0, 31 @@ -266,8 +273,9 @@ ; RV64-NEXT: vmv1r.v v9, v0 ; RV64-NEXT: vsetvli zero, a1, e8, mf2, ta, ma ; RV64-NEXT: vmv1r.v v0, v8 -; RV64-NEXT: vcpop.m a1, v9, v0.t -; RV64-NEXT: snez a1, a1 +; RV64-NEXT: vfirst.m a1, v9, v0.t +; RV64-NEXT: slti a1, a1, 0 +; RV64-NEXT: not a1, a1 ; RV64-NEXT: or a0, a1, a0 ; RV64-NEXT: slli a0, a0, 63 ; RV64-NEXT: srai a0, a0, 63 @@ -312,8 +320,8 @@ ; CHECK-NEXT: vsetvli zero, a1, e8, m1, ta, ma ; CHECK-NEXT: vmnot.m v9, v0 ; CHECK-NEXT: vmv1r.v v0, v8 -; CHECK-NEXT: vcpop.m a1, v9, v0.t -; CHECK-NEXT: seqz a1, a1 +; CHECK-NEXT: vfirst.m a1, v9, v0.t +; CHECK-NEXT: slti a1, a1, 0 ; CHECK-NEXT: and a0, a1, a0 ; CHECK-NEXT: neg a0, a0 ; CHECK-NEXT: ret @@ -329,8 +337,8 @@ ; CHECK-NEXT: vsetvli zero, a1, e8, m1, ta, ma ; CHECK-NEXT: vmnot.m v9, v0 ; CHECK-NEXT: vmv1r.v v0, v8 -; CHECK-NEXT: vcpop.m a1, v9, v0.t -; CHECK-NEXT: seqz a1, a1 +; CHECK-NEXT: vfirst.m a1, v9, v0.t +; CHECK-NEXT: slti a1, a1, 0 ; CHECK-NEXT: and a0, a1, a0 ; CHECK-NEXT: neg a0, a0 ; CHECK-NEXT: ret @@ -352,8 +360,8 @@ ; CHECK-NEXT: vsetvli zero, a2, e8, m8, ta, ma ; CHECK-NEXT: vmnot.m v11, v0 ; CHECK-NEXT: vmv1r.v v0, v9 -; CHECK-NEXT: vcpop.m a2, v11, v0.t -; CHECK-NEXT: seqz a2, a2 +; CHECK-NEXT: vfirst.m a2, v11, v0.t +; CHECK-NEXT: slti a2, a2, 0 ; CHECK-NEXT: addi a3, a1, -128 ; CHECK-NEXT: sltu a1, a1, a3 ; CHECK-NEXT: addi a1, a1, -1 @@ -361,8 +369,8 @@ ; CHECK-NEXT: vsetvli zero, a1, e8, m8, ta, ma ; CHECK-NEXT: vmnot.m v8, v8 ; CHECK-NEXT: vmv1r.v v0, v10 -; CHECK-NEXT: vcpop.m a1, v8, v0.t -; CHECK-NEXT: seqz a1, a1 +; CHECK-NEXT: vfirst.m a1, v8, v0.t +; CHECK-NEXT: slti a1, a1, 0 ; CHECK-NEXT: and a0, a1, a0 ; CHECK-NEXT: and a0, a0, a2 ; CHECK-NEXT: neg a0, a0 @@ -379,8 +387,9 @@ ; RV32-NEXT: vmv1r.v v9, v0 ; RV32-NEXT: vsetvli zero, a1, e8, m1, ta, ma ; RV32-NEXT: vmv1r.v v0, v8 -; RV32-NEXT: vcpop.m a1, v9, v0.t -; RV32-NEXT: snez a1, a1 +; RV32-NEXT: vfirst.m a1, v9, v0.t +; RV32-NEXT: slti a1, a1, 0 +; RV32-NEXT: not a1, a1 ; RV32-NEXT: or a0, a1, a0 ; RV32-NEXT: slli a0, a0, 31 ; RV32-NEXT: srai a0, a0, 31 @@ -391,8 +400,9 @@ ; RV64-NEXT: vmv1r.v v9, v0 ; RV64-NEXT: vsetvli zero, a1, e8, m1, ta, ma ; RV64-NEXT: vmv1r.v v0, v8 -; RV64-NEXT: vcpop.m a1, v9, v0.t -; RV64-NEXT: snez a1, a1 +; RV64-NEXT: vfirst.m a1, v9, v0.t +; RV64-NEXT: slti a1, a1, 0 +; RV64-NEXT: not a1, a1 ; RV64-NEXT: or a0, a1, a0 ; RV64-NEXT: slli a0, a0, 63 ; RV64-NEXT: srai a0, a0, 63 @@ -577,8 +587,8 @@ ; CHECK-NEXT: vsetvli zero, a1, e8, mf8, ta, ma ; CHECK-NEXT: vmnot.m v9, v0 ; CHECK-NEXT: vmv1r.v v0, v8 -; CHECK-NEXT: vcpop.m a1, v9, v0.t -; CHECK-NEXT: seqz a1, a1 +; CHECK-NEXT: vfirst.m a1, v9, v0.t +; CHECK-NEXT: slti a1, a1, 0 ; CHECK-NEXT: and a0, a1, a0 ; CHECK-NEXT: neg a0, a0 ; CHECK-NEXT: ret @@ -594,8 +604,8 @@ ; CHECK-NEXT: vsetvli zero, a1, e8, mf8, ta, ma ; CHECK-NEXT: vmnot.m v9, v0 ; CHECK-NEXT: vmv1r.v v0, v8 -; CHECK-NEXT: vcpop.m a1, v9, v0.t -; CHECK-NEXT: seqz a1, a1 +; CHECK-NEXT: vfirst.m a1, v9, v0.t +; CHECK-NEXT: slti a1, a1, 0 ; CHECK-NEXT: and a0, a1, a0 ; CHECK-NEXT: neg a0, a0 ; CHECK-NEXT: ret @@ -611,8 +621,8 @@ ; CHECK-NEXT: vsetvli zero, a1, e8, mf4, ta, ma ; CHECK-NEXT: vmnot.m v9, v0 ; CHECK-NEXT: vmv1r.v v0, v8 -; CHECK-NEXT: vcpop.m a1, v9, v0.t -; CHECK-NEXT: seqz a1, a1 +; CHECK-NEXT: vfirst.m a1, v9, v0.t +; CHECK-NEXT: slti a1, a1, 0 ; CHECK-NEXT: and a0, a1, a0 ; CHECK-NEXT: neg a0, a0 ; CHECK-NEXT: ret @@ -628,8 +638,8 @@ ; CHECK-NEXT: vsetvli zero, a1, e8, mf2, ta, ma ; CHECK-NEXT: vmnot.m v9, v0 ; CHECK-NEXT: vmv1r.v v0, v8 -; CHECK-NEXT: vcpop.m a1, v9, v0.t -; CHECK-NEXT: seqz a1, a1 +; CHECK-NEXT: vfirst.m a1, v9, v0.t +; CHECK-NEXT: slti a1, a1, 0 ; CHECK-NEXT: and a0, a1, a0 ; CHECK-NEXT: neg a0, a0 ; CHECK-NEXT: ret @@ -645,8 +655,8 @@ ; CHECK-NEXT: vsetvli zero, a1, e8, m1, ta, ma ; CHECK-NEXT: vmnot.m v9, v0 ; CHECK-NEXT: vmv1r.v v0, v8 -; CHECK-NEXT: vcpop.m a1, v9, v0.t -; CHECK-NEXT: seqz a1, a1 +; CHECK-NEXT: vfirst.m a1, v9, v0.t +; CHECK-NEXT: slti a1, a1, 0 ; CHECK-NEXT: and a0, a1, a0 ; CHECK-NEXT: neg a0, a0 ; CHECK-NEXT: ret @@ -662,8 +672,8 @@ ; CHECK-NEXT: vsetvli zero, a1, e8, m2, ta, ma ; CHECK-NEXT: vmnot.m v9, v0 ; CHECK-NEXT: vmv1r.v v0, v8 -; CHECK-NEXT: vcpop.m a1, v9, v0.t -; CHECK-NEXT: seqz a1, a1 +; CHECK-NEXT: vfirst.m a1, v9, v0.t +; CHECK-NEXT: slti a1, a1, 0 ; CHECK-NEXT: and a0, a1, a0 ; CHECK-NEXT: neg a0, a0 ; CHECK-NEXT: ret @@ -679,8 +689,8 @@ ; CHECK-NEXT: vsetvli zero, a1, e8, m4, ta, ma ; CHECK-NEXT: vmnot.m v9, v0 ; CHECK-NEXT: vmv1r.v v0, v8 -; CHECK-NEXT: vcpop.m a1, v9, v0.t -; CHECK-NEXT: seqz a1, a1 +; CHECK-NEXT: vfirst.m a1, v9, v0.t +; CHECK-NEXT: slti a1, a1, 0 ; CHECK-NEXT: and a0, a1, a0 ; CHECK-NEXT: neg a0, a0 ; CHECK-NEXT: ret @@ -696,8 +706,9 @@ ; RV32-NEXT: vmv1r.v v9, v0 ; RV32-NEXT: vsetvli zero, a1, e8, mf8, ta, ma ; RV32-NEXT: vmv1r.v v0, v8 -; RV32-NEXT: vcpop.m a1, v9, v0.t -; RV32-NEXT: snez a1, a1 +; RV32-NEXT: vfirst.m a1, v9, v0.t +; RV32-NEXT: slti a1, a1, 0 +; RV32-NEXT: not a1, a1 ; RV32-NEXT: or a0, a1, a0 ; RV32-NEXT: slli a0, a0, 31 ; RV32-NEXT: srai a0, a0, 31 @@ -708,8 +719,9 @@ ; RV64-NEXT: vmv1r.v v9, v0 ; RV64-NEXT: vsetvli zero, a1, e8, mf8, ta, ma ; RV64-NEXT: vmv1r.v v0, v8 -; RV64-NEXT: vcpop.m a1, v9, v0.t -; RV64-NEXT: snez a1, a1 +; RV64-NEXT: vfirst.m a1, v9, v0.t +; RV64-NEXT: slti a1, a1, 0 +; RV64-NEXT: not a1, a1 ; RV64-NEXT: or a0, a1, a0 ; RV64-NEXT: slli a0, a0, 63 ; RV64-NEXT: srai a0, a0, 63 @@ -726,8 +738,9 @@ ; RV32-NEXT: vmv1r.v v9, v0 ; RV32-NEXT: vsetvli zero, a1, e8, mf8, ta, ma ; RV32-NEXT: vmv1r.v v0, v8 -; RV32-NEXT: vcpop.m a1, v9, v0.t -; RV32-NEXT: snez a1, a1 +; RV32-NEXT: vfirst.m a1, v9, v0.t +; RV32-NEXT: slti a1, a1, 0 +; RV32-NEXT: not a1, a1 ; RV32-NEXT: or a0, a1, a0 ; RV32-NEXT: slli a0, a0, 31 ; RV32-NEXT: srai a0, a0, 31 @@ -738,8 +751,9 @@ ; RV64-NEXT: vmv1r.v v9, v0 ; RV64-NEXT: vsetvli zero, a1, e8, mf8, ta, ma ; RV64-NEXT: vmv1r.v v0, v8 -; RV64-NEXT: vcpop.m a1, v9, v0.t -; RV64-NEXT: snez a1, a1 +; RV64-NEXT: vfirst.m a1, v9, v0.t +; RV64-NEXT: slti a1, a1, 0 +; RV64-NEXT: not a1, a1 ; RV64-NEXT: or a0, a1, a0 ; RV64-NEXT: slli a0, a0, 63 ; RV64-NEXT: srai a0, a0, 63 @@ -756,8 +770,9 @@ ; RV32-NEXT: vmv1r.v v9, v0 ; RV32-NEXT: vsetvli zero, a1, e8, mf4, ta, ma ; RV32-NEXT: vmv1r.v v0, v8 -; RV32-NEXT: vcpop.m a1, v9, v0.t -; RV32-NEXT: snez a1, a1 +; RV32-NEXT: vfirst.m a1, v9, v0.t +; RV32-NEXT: slti a1, a1, 0 +; RV32-NEXT: not a1, a1 ; RV32-NEXT: or a0, a1, a0 ; RV32-NEXT: slli a0, a0, 31 ; RV32-NEXT: srai a0, a0, 31 @@ -768,8 +783,9 @@ ; RV64-NEXT: vmv1r.v v9, v0 ; RV64-NEXT: vsetvli zero, a1, e8, mf4, ta, ma ; RV64-NEXT: vmv1r.v v0, v8 -; RV64-NEXT: vcpop.m a1, v9, v0.t -; RV64-NEXT: snez a1, a1 +; RV64-NEXT: vfirst.m a1, v9, v0.t +; RV64-NEXT: slti a1, a1, 0 +; RV64-NEXT: not a1, a1 ; RV64-NEXT: or a0, a1, a0 ; RV64-NEXT: slli a0, a0, 63 ; RV64-NEXT: srai a0, a0, 63 @@ -786,8 +802,9 @@ ; RV32-NEXT: vmv1r.v v9, v0 ; RV32-NEXT: vsetvli zero, a1, e8, mf2, ta, ma ; RV32-NEXT: vmv1r.v v0, v8 -; RV32-NEXT: vcpop.m a1, v9, v0.t -; RV32-NEXT: snez a1, a1 +; RV32-NEXT: vfirst.m a1, v9, v0.t +; RV32-NEXT: slti a1, a1, 0 +; RV32-NEXT: not a1, a1 ; RV32-NEXT: or a0, a1, a0 ; RV32-NEXT: slli a0, a0, 31 ; RV32-NEXT: srai a0, a0, 31 @@ -798,8 +815,9 @@ ; RV64-NEXT: vmv1r.v v9, v0 ; RV64-NEXT: vsetvli zero, a1, e8, mf2, ta, ma ; RV64-NEXT: vmv1r.v v0, v8 -; RV64-NEXT: vcpop.m a1, v9, v0.t -; RV64-NEXT: snez a1, a1 +; RV64-NEXT: vfirst.m a1, v9, v0.t +; RV64-NEXT: slti a1, a1, 0 +; RV64-NEXT: not a1, a1 ; RV64-NEXT: or a0, a1, a0 ; RV64-NEXT: slli a0, a0, 63 ; RV64-NEXT: srai a0, a0, 63 @@ -816,8 +834,9 @@ ; RV32-NEXT: vmv1r.v v9, v0 ; RV32-NEXT: vsetvli zero, a1, e8, m1, ta, ma ; RV32-NEXT: vmv1r.v v0, v8 -; RV32-NEXT: vcpop.m a1, v9, v0.t -; RV32-NEXT: snez a1, a1 +; RV32-NEXT: vfirst.m a1, v9, v0.t +; RV32-NEXT: slti a1, a1, 0 +; RV32-NEXT: not a1, a1 ; RV32-NEXT: or a0, a1, a0 ; RV32-NEXT: slli a0, a0, 31 ; RV32-NEXT: srai a0, a0, 31 @@ -828,8 +847,9 @@ ; RV64-NEXT: vmv1r.v v9, v0 ; RV64-NEXT: vsetvli zero, a1, e8, m1, ta, ma ; RV64-NEXT: vmv1r.v v0, v8 -; RV64-NEXT: vcpop.m a1, v9, v0.t -; RV64-NEXT: snez a1, a1 +; RV64-NEXT: vfirst.m a1, v9, v0.t +; RV64-NEXT: slti a1, a1, 0 +; RV64-NEXT: not a1, a1 ; RV64-NEXT: or a0, a1, a0 ; RV64-NEXT: slli a0, a0, 63 ; RV64-NEXT: srai a0, a0, 63 @@ -846,8 +866,9 @@ ; RV32-NEXT: vmv1r.v v9, v0 ; RV32-NEXT: vsetvli zero, a1, e8, m2, ta, ma ; RV32-NEXT: vmv1r.v v0, v8 -; RV32-NEXT: vcpop.m a1, v9, v0.t -; RV32-NEXT: snez a1, a1 +; RV32-NEXT: vfirst.m a1, v9, v0.t +; RV32-NEXT: slti a1, a1, 0 +; RV32-NEXT: not a1, a1 ; RV32-NEXT: or a0, a1, a0 ; RV32-NEXT: slli a0, a0, 31 ; RV32-NEXT: srai a0, a0, 31 @@ -858,8 +879,9 @@ ; RV64-NEXT: vmv1r.v v9, v0 ; RV64-NEXT: vsetvli zero, a1, e8, m2, ta, ma ; RV64-NEXT: vmv1r.v v0, v8 -; RV64-NEXT: vcpop.m a1, v9, v0.t -; RV64-NEXT: snez a1, a1 +; RV64-NEXT: vfirst.m a1, v9, v0.t +; RV64-NEXT: slti a1, a1, 0 +; RV64-NEXT: not a1, a1 ; RV64-NEXT: or a0, a1, a0 ; RV64-NEXT: slli a0, a0, 63 ; RV64-NEXT: srai a0, a0, 63 @@ -876,8 +898,9 @@ ; RV32-NEXT: vmv1r.v v9, v0 ; RV32-NEXT: vsetvli zero, a1, e8, m4, ta, ma ; RV32-NEXT: vmv1r.v v0, v8 -; RV32-NEXT: vcpop.m a1, v9, v0.t -; RV32-NEXT: snez a1, a1 +; RV32-NEXT: vfirst.m a1, v9, v0.t +; RV32-NEXT: slti a1, a1, 0 +; RV32-NEXT: not a1, a1 ; RV32-NEXT: or a0, a1, a0 ; RV32-NEXT: slli a0, a0, 31 ; RV32-NEXT: srai a0, a0, 31 @@ -888,8 +911,9 @@ ; RV64-NEXT: vmv1r.v v9, v0 ; RV64-NEXT: vsetvli zero, a1, e8, m4, ta, ma ; RV64-NEXT: vmv1r.v v0, v8 -; RV64-NEXT: vcpop.m a1, v9, v0.t -; RV64-NEXT: snez a1, a1 +; RV64-NEXT: vfirst.m a1, v9, v0.t +; RV64-NEXT: slti a1, a1, 0 +; RV64-NEXT: not a1, a1 ; RV64-NEXT: or a0, a1, a0 ; RV64-NEXT: slli a0, a0, 63 ; RV64-NEXT: srai a0, a0, 63 @@ -906,8 +930,9 @@ ; RV32-NEXT: vmv1r.v v9, v0 ; RV32-NEXT: vsetvli zero, a1, e8, mf8, ta, ma ; RV32-NEXT: vmv1r.v v0, v8 -; RV32-NEXT: vcpop.m a1, v9, v0.t -; RV32-NEXT: snez a1, a1 +; RV32-NEXT: vfirst.m a1, v9, v0.t +; RV32-NEXT: slti a1, a1, 0 +; RV32-NEXT: not a1, a1 ; RV32-NEXT: or a0, a1, a0 ; RV32-NEXT: slli a0, a0, 31 ; RV32-NEXT: srai a0, a0, 31 @@ -918,8 +943,9 @@ ; RV64-NEXT: vmv1r.v v9, v0 ; RV64-NEXT: vsetvli zero, a1, e8, mf8, ta, ma ; RV64-NEXT: vmv1r.v v0, v8 -; RV64-NEXT: vcpop.m a1, v9, v0.t -; RV64-NEXT: snez a1, a1 +; RV64-NEXT: vfirst.m a1, v9, v0.t +; RV64-NEXT: slti a1, a1, 0 +; RV64-NEXT: not a1, a1 ; RV64-NEXT: or a0, a1, a0 ; RV64-NEXT: slli a0, a0, 63 ; RV64-NEXT: srai a0, a0, 63 @@ -936,8 +962,9 @@ ; RV32-NEXT: vmv1r.v v9, v0 ; RV32-NEXT: vsetvli zero, a1, e8, mf8, ta, ma ; RV32-NEXT: vmv1r.v v0, v8 -; RV32-NEXT: vcpop.m a1, v9, v0.t -; RV32-NEXT: snez a1, a1 +; RV32-NEXT: vfirst.m a1, v9, v0.t +; RV32-NEXT: slti a1, a1, 0 +; RV32-NEXT: not a1, a1 ; RV32-NEXT: or a0, a1, a0 ; RV32-NEXT: slli a0, a0, 31 ; RV32-NEXT: srai a0, a0, 31 @@ -948,8 +975,9 @@ ; RV64-NEXT: vmv1r.v v9, v0 ; RV64-NEXT: vsetvli zero, a1, e8, mf8, ta, ma ; RV64-NEXT: vmv1r.v v0, v8 -; RV64-NEXT: vcpop.m a1, v9, v0.t -; RV64-NEXT: snez a1, a1 +; RV64-NEXT: vfirst.m a1, v9, v0.t +; RV64-NEXT: slti a1, a1, 0 +; RV64-NEXT: not a1, a1 ; RV64-NEXT: or a0, a1, a0 ; RV64-NEXT: slli a0, a0, 63 ; RV64-NEXT: srai a0, a0, 63 @@ -966,8 +994,9 @@ ; RV32-NEXT: vmv1r.v v9, v0 ; RV32-NEXT: vsetvli zero, a1, e8, mf4, ta, ma ; RV32-NEXT: vmv1r.v v0, v8 -; RV32-NEXT: vcpop.m a1, v9, v0.t -; RV32-NEXT: snez a1, a1 +; RV32-NEXT: vfirst.m a1, v9, v0.t +; RV32-NEXT: slti a1, a1, 0 +; RV32-NEXT: not a1, a1 ; RV32-NEXT: or a0, a1, a0 ; RV32-NEXT: slli a0, a0, 31 ; RV32-NEXT: srai a0, a0, 31 @@ -978,8 +1007,9 @@ ; RV64-NEXT: vmv1r.v v9, v0 ; RV64-NEXT: vsetvli zero, a1, e8, mf4, ta, ma ; RV64-NEXT: vmv1r.v v0, v8 -; RV64-NEXT: vcpop.m a1, v9, v0.t -; RV64-NEXT: snez a1, a1 +; RV64-NEXT: vfirst.m a1, v9, v0.t +; RV64-NEXT: slti a1, a1, 0 +; RV64-NEXT: not a1, a1 ; RV64-NEXT: or a0, a1, a0 ; RV64-NEXT: slli a0, a0, 63 ; RV64-NEXT: srai a0, a0, 63 @@ -996,8 +1026,9 @@ ; RV32-NEXT: vmv1r.v v9, v0 ; RV32-NEXT: vsetvli zero, a1, e8, mf2, ta, ma ; RV32-NEXT: vmv1r.v v0, v8 -; RV32-NEXT: vcpop.m a1, v9, v0.t -; RV32-NEXT: snez a1, a1 +; RV32-NEXT: vfirst.m a1, v9, v0.t +; RV32-NEXT: slti a1, a1, 0 +; RV32-NEXT: not a1, a1 ; RV32-NEXT: or a0, a1, a0 ; RV32-NEXT: slli a0, a0, 31 ; RV32-NEXT: srai a0, a0, 31 @@ -1008,8 +1039,9 @@ ; RV64-NEXT: vmv1r.v v9, v0 ; RV64-NEXT: vsetvli zero, a1, e8, mf2, ta, ma ; RV64-NEXT: vmv1r.v v0, v8 -; RV64-NEXT: vcpop.m a1, v9, v0.t -; RV64-NEXT: snez a1, a1 +; RV64-NEXT: vfirst.m a1, v9, v0.t +; RV64-NEXT: slti a1, a1, 0 +; RV64-NEXT: not a1, a1 ; RV64-NEXT: or a0, a1, a0 ; RV64-NEXT: slli a0, a0, 63 ; RV64-NEXT: srai a0, a0, 63 @@ -1026,8 +1058,9 @@ ; RV32-NEXT: vmv1r.v v9, v0 ; RV32-NEXT: vsetvli zero, a1, e8, m1, ta, ma ; RV32-NEXT: vmv1r.v v0, v8 -; RV32-NEXT: vcpop.m a1, v9, v0.t -; RV32-NEXT: snez a1, a1 +; RV32-NEXT: vfirst.m a1, v9, v0.t +; RV32-NEXT: slti a1, a1, 0 +; RV32-NEXT: not a1, a1 ; RV32-NEXT: or a0, a1, a0 ; RV32-NEXT: slli a0, a0, 31 ; RV32-NEXT: srai a0, a0, 31 @@ -1038,8 +1071,9 @@ ; RV64-NEXT: vmv1r.v v9, v0 ; RV64-NEXT: vsetvli zero, a1, e8, m1, ta, ma ; RV64-NEXT: vmv1r.v v0, v8 -; RV64-NEXT: vcpop.m a1, v9, v0.t -; RV64-NEXT: snez a1, a1 +; RV64-NEXT: vfirst.m a1, v9, v0.t +; RV64-NEXT: slti a1, a1, 0 +; RV64-NEXT: not a1, a1 ; RV64-NEXT: or a0, a1, a0 ; RV64-NEXT: slli a0, a0, 63 ; RV64-NEXT: srai a0, a0, 63 @@ -1056,8 +1090,9 @@ ; RV32-NEXT: vmv1r.v v9, v0 ; RV32-NEXT: vsetvli zero, a1, e8, m2, ta, ma ; RV32-NEXT: vmv1r.v v0, v8 -; RV32-NEXT: vcpop.m a1, v9, v0.t -; RV32-NEXT: snez a1, a1 +; RV32-NEXT: vfirst.m a1, v9, v0.t +; RV32-NEXT: slti a1, a1, 0 +; RV32-NEXT: not a1, a1 ; RV32-NEXT: or a0, a1, a0 ; RV32-NEXT: slli a0, a0, 31 ; RV32-NEXT: srai a0, a0, 31 @@ -1068,8 +1103,9 @@ ; RV64-NEXT: vmv1r.v v9, v0 ; RV64-NEXT: vsetvli zero, a1, e8, m2, ta, ma ; RV64-NEXT: vmv1r.v v0, v8 -; RV64-NEXT: vcpop.m a1, v9, v0.t -; RV64-NEXT: snez a1, a1 +; RV64-NEXT: vfirst.m a1, v9, v0.t +; RV64-NEXT: slti a1, a1, 0 +; RV64-NEXT: not a1, a1 ; RV64-NEXT: or a0, a1, a0 ; RV64-NEXT: slli a0, a0, 63 ; RV64-NEXT: srai a0, a0, 63 @@ -1086,8 +1122,9 @@ ; RV32-NEXT: vmv1r.v v9, v0 ; RV32-NEXT: vsetvli zero, a1, e8, m4, ta, ma ; RV32-NEXT: vmv1r.v v0, v8 -; RV32-NEXT: vcpop.m a1, v9, v0.t -; RV32-NEXT: snez a1, a1 +; RV32-NEXT: vfirst.m a1, v9, v0.t +; RV32-NEXT: slti a1, a1, 0 +; RV32-NEXT: not a1, a1 ; RV32-NEXT: or a0, a1, a0 ; RV32-NEXT: slli a0, a0, 31 ; RV32-NEXT: srai a0, a0, 31 @@ -1098,8 +1135,9 @@ ; RV64-NEXT: vmv1r.v v9, v0 ; RV64-NEXT: vsetvli zero, a1, e8, m4, ta, ma ; RV64-NEXT: vmv1r.v v0, v8 -; RV64-NEXT: vcpop.m a1, v9, v0.t -; RV64-NEXT: snez a1, a1 +; RV64-NEXT: vfirst.m a1, v9, v0.t +; RV64-NEXT: slti a1, a1, 0 +; RV64-NEXT: not a1, a1 ; RV64-NEXT: or a0, a1, a0 ; RV64-NEXT: slli a0, a0, 63 ; RV64-NEXT: srai a0, a0, 63 @@ -1116,8 +1154,8 @@ ; CHECK-NEXT: vsetvli zero, a1, e8, mf8, ta, ma ; CHECK-NEXT: vmnot.m v9, v0 ; CHECK-NEXT: vmv1r.v v0, v8 -; CHECK-NEXT: vcpop.m a1, v9, v0.t -; CHECK-NEXT: seqz a1, a1 +; CHECK-NEXT: vfirst.m a1, v9, v0.t +; CHECK-NEXT: slti a1, a1, 0 ; CHECK-NEXT: and a0, a1, a0 ; CHECK-NEXT: neg a0, a0 ; CHECK-NEXT: ret @@ -1133,8 +1171,8 @@ ; CHECK-NEXT: vsetvli zero, a1, e8, mf8, ta, ma ; CHECK-NEXT: vmnot.m v9, v0 ; CHECK-NEXT: vmv1r.v v0, v8 -; CHECK-NEXT: vcpop.m a1, v9, v0.t -; CHECK-NEXT: seqz a1, a1 +; CHECK-NEXT: vfirst.m a1, v9, v0.t +; CHECK-NEXT: slti a1, a1, 0 ; CHECK-NEXT: and a0, a1, a0 ; CHECK-NEXT: neg a0, a0 ; CHECK-NEXT: ret @@ -1150,8 +1188,8 @@ ; CHECK-NEXT: vsetvli zero, a1, e8, mf4, ta, ma ; CHECK-NEXT: vmnot.m v9, v0 ; CHECK-NEXT: vmv1r.v v0, v8 -; CHECK-NEXT: vcpop.m a1, v9, v0.t -; CHECK-NEXT: seqz a1, a1 +; CHECK-NEXT: vfirst.m a1, v9, v0.t +; CHECK-NEXT: slti a1, a1, 0 ; CHECK-NEXT: and a0, a1, a0 ; CHECK-NEXT: neg a0, a0 ; CHECK-NEXT: ret @@ -1167,8 +1205,8 @@ ; CHECK-NEXT: vsetvli zero, a1, e8, mf2, ta, ma ; CHECK-NEXT: vmnot.m v9, v0 ; CHECK-NEXT: vmv1r.v v0, v8 -; CHECK-NEXT: vcpop.m a1, v9, v0.t -; CHECK-NEXT: seqz a1, a1 +; CHECK-NEXT: vfirst.m a1, v9, v0.t +; CHECK-NEXT: slti a1, a1, 0 ; CHECK-NEXT: and a0, a1, a0 ; CHECK-NEXT: neg a0, a0 ; CHECK-NEXT: ret @@ -1184,8 +1222,8 @@ ; CHECK-NEXT: vsetvli zero, a1, e8, m1, ta, ma ; CHECK-NEXT: vmnot.m v9, v0 ; CHECK-NEXT: vmv1r.v v0, v8 -; CHECK-NEXT: vcpop.m a1, v9, v0.t -; CHECK-NEXT: seqz a1, a1 +; CHECK-NEXT: vfirst.m a1, v9, v0.t +; CHECK-NEXT: slti a1, a1, 0 ; CHECK-NEXT: and a0, a1, a0 ; CHECK-NEXT: neg a0, a0 ; CHECK-NEXT: ret @@ -1201,8 +1239,8 @@ ; CHECK-NEXT: vsetvli zero, a1, e8, m2, ta, ma ; CHECK-NEXT: vmnot.m v9, v0 ; CHECK-NEXT: vmv1r.v v0, v8 -; CHECK-NEXT: vcpop.m a1, v9, v0.t -; CHECK-NEXT: seqz a1, a1 +; CHECK-NEXT: vfirst.m a1, v9, v0.t +; CHECK-NEXT: slti a1, a1, 0 ; CHECK-NEXT: and a0, a1, a0 ; CHECK-NEXT: neg a0, a0 ; CHECK-NEXT: ret @@ -1218,8 +1256,8 @@ ; CHECK-NEXT: vsetvli zero, a1, e8, m4, ta, ma ; CHECK-NEXT: vmnot.m v9, v0 ; CHECK-NEXT: vmv1r.v v0, v8 -; CHECK-NEXT: vcpop.m a1, v9, v0.t -; CHECK-NEXT: seqz a1, a1 +; CHECK-NEXT: vfirst.m a1, v9, v0.t +; CHECK-NEXT: slti a1, a1, 0 ; CHECK-NEXT: and a0, a1, a0 ; CHECK-NEXT: neg a0, a0 ; CHECK-NEXT: ret @@ -1235,8 +1273,8 @@ ; CHECK-NEXT: vsetvli zero, a1, e8, mf8, ta, ma ; CHECK-NEXT: vmnot.m v9, v0 ; CHECK-NEXT: vmv1r.v v0, v8 -; CHECK-NEXT: vcpop.m a1, v9, v0.t -; CHECK-NEXT: seqz a1, a1 +; CHECK-NEXT: vfirst.m a1, v9, v0.t +; CHECK-NEXT: slti a1, a1, 0 ; CHECK-NEXT: and a0, a1, a0 ; CHECK-NEXT: ret %r = call i1 @llvm.vp.reduce.mul.v1i1(i1 %s, <1 x i1> %v, <1 x i1> %m, i32 %evl) @@ -1251,8 +1289,8 @@ ; CHECK-NEXT: vsetvli zero, a1, e8, mf8, ta, ma ; CHECK-NEXT: vmnot.m v9, v0 ; CHECK-NEXT: vmv1r.v v0, v8 -; CHECK-NEXT: vcpop.m a1, v9, v0.t -; CHECK-NEXT: seqz a1, a1 +; CHECK-NEXT: vfirst.m a1, v9, v0.t +; CHECK-NEXT: slti a1, a1, 0 ; CHECK-NEXT: and a0, a1, a0 ; CHECK-NEXT: neg a0, a0 ; CHECK-NEXT: ret @@ -1268,8 +1306,8 @@ ; CHECK-NEXT: vsetvli zero, a1, e8, mf4, ta, ma ; CHECK-NEXT: vmnot.m v9, v0 ; CHECK-NEXT: vmv1r.v v0, v8 -; CHECK-NEXT: vcpop.m a1, v9, v0.t -; CHECK-NEXT: seqz a1, a1 +; CHECK-NEXT: vfirst.m a1, v9, v0.t +; CHECK-NEXT: slti a1, a1, 0 ; CHECK-NEXT: and a0, a1, a0 ; CHECK-NEXT: neg a0, a0 ; CHECK-NEXT: ret @@ -1285,8 +1323,8 @@ ; CHECK-NEXT: vsetvli zero, a1, e8, mf2, ta, ma ; CHECK-NEXT: vmnot.m v9, v0 ; CHECK-NEXT: vmv1r.v v0, v8 -; CHECK-NEXT: vcpop.m a1, v9, v0.t -; CHECK-NEXT: seqz a1, a1 +; CHECK-NEXT: vfirst.m a1, v9, v0.t +; CHECK-NEXT: slti a1, a1, 0 ; CHECK-NEXT: and a0, a1, a0 ; CHECK-NEXT: neg a0, a0 ; CHECK-NEXT: ret @@ -1302,8 +1340,8 @@ ; CHECK-NEXT: vsetvli zero, a1, e8, m1, ta, ma ; CHECK-NEXT: vmnot.m v9, v0 ; CHECK-NEXT: vmv1r.v v0, v8 -; CHECK-NEXT: vcpop.m a1, v9, v0.t -; CHECK-NEXT: seqz a1, a1 +; CHECK-NEXT: vfirst.m a1, v9, v0.t +; CHECK-NEXT: slti a1, a1, 0 ; CHECK-NEXT: and a0, a1, a0 ; CHECK-NEXT: neg a0, a0 ; CHECK-NEXT: ret @@ -1319,8 +1357,8 @@ ; CHECK-NEXT: vsetvli zero, a1, e8, m2, ta, ma ; CHECK-NEXT: vmnot.m v9, v0 ; CHECK-NEXT: vmv1r.v v0, v8 -; CHECK-NEXT: vcpop.m a1, v9, v0.t -; CHECK-NEXT: seqz a1, a1 +; CHECK-NEXT: vfirst.m a1, v9, v0.t +; CHECK-NEXT: slti a1, a1, 0 ; CHECK-NEXT: and a0, a1, a0 ; CHECK-NEXT: neg a0, a0 ; CHECK-NEXT: ret @@ -1336,8 +1374,8 @@ ; CHECK-NEXT: vsetvli zero, a1, e8, m4, ta, ma ; CHECK-NEXT: vmnot.m v9, v0 ; CHECK-NEXT: vmv1r.v v0, v8 -; CHECK-NEXT: vcpop.m a1, v9, v0.t -; CHECK-NEXT: seqz a1, a1 +; CHECK-NEXT: vfirst.m a1, v9, v0.t +; CHECK-NEXT: slti a1, a1, 0 ; CHECK-NEXT: and a0, a1, a0 ; CHECK-NEXT: neg a0, a0 ; CHECK-NEXT: ret diff --git a/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vreductions-mask.ll b/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vreductions-mask.ll --- a/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vreductions-mask.ll +++ b/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vreductions-mask.ll @@ -108,8 +108,8 @@ ; CHECK-LABEL: vreduce_or_v2i1: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetivli zero, 2, e8, mf8, ta, ma -; CHECK-NEXT: vcpop.m a0, v0 -; CHECK-NEXT: seqz a0, a0 +; CHECK-NEXT: vfirst.m a0, v0 +; CHECK-NEXT: slti a0, a0, 0 ; CHECK-NEXT: addi a0, a0, -1 ; CHECK-NEXT: ret %red = call i1 @llvm.vector.reduce.or.v2i1(<2 x i1> %v) @@ -161,9 +161,9 @@ ; CHECK: # %bb.0: ; CHECK-NEXT: vsetivli zero, 2, e8, mf8, ta, ma ; CHECK-NEXT: vmnot.m v8, v0 -; CHECK-NEXT: vcpop.m a0, v8 -; CHECK-NEXT: snez a0, a0 -; CHECK-NEXT: addi a0, a0, -1 +; CHECK-NEXT: vfirst.m a0, v8 +; CHECK-NEXT: slti a0, a0, 0 +; CHECK-NEXT: neg a0, a0 ; CHECK-NEXT: ret %red = call i1 @llvm.vector.reduce.and.v2i1(<2 x i1> %v) ret i1 %red @@ -175,8 +175,8 @@ ; CHECK-LABEL: vreduce_umax_v2i1: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetivli zero, 2, e8, mf8, ta, ma -; CHECK-NEXT: vcpop.m a0, v0 -; CHECK-NEXT: seqz a0, a0 +; CHECK-NEXT: vfirst.m a0, v0 +; CHECK-NEXT: slti a0, a0, 0 ; CHECK-NEXT: addi a0, a0, -1 ; CHECK-NEXT: ret %red = call i1 @llvm.vector.reduce.umax.v2i1(<2 x i1> %v) @@ -190,9 +190,9 @@ ; CHECK: # %bb.0: ; CHECK-NEXT: vsetivli zero, 2, e8, mf8, ta, ma ; CHECK-NEXT: vmnot.m v8, v0 -; CHECK-NEXT: vcpop.m a0, v8 -; CHECK-NEXT: snez a0, a0 -; CHECK-NEXT: addi a0, a0, -1 +; CHECK-NEXT: vfirst.m a0, v8 +; CHECK-NEXT: slti a0, a0, 0 +; CHECK-NEXT: neg a0, a0 ; CHECK-NEXT: ret %red = call i1 @llvm.vector.reduce.smax.v2i1(<2 x i1> %v) ret i1 %red @@ -205,9 +205,9 @@ ; CHECK: # %bb.0: ; CHECK-NEXT: vsetivli zero, 2, e8, mf8, ta, ma ; CHECK-NEXT: vmnot.m v8, v0 -; CHECK-NEXT: vcpop.m a0, v8 -; CHECK-NEXT: snez a0, a0 -; CHECK-NEXT: addi a0, a0, -1 +; CHECK-NEXT: vfirst.m a0, v8 +; CHECK-NEXT: slti a0, a0, 0 +; CHECK-NEXT: neg a0, a0 ; CHECK-NEXT: ret %red = call i1 @llvm.vector.reduce.umin.v2i1(<2 x i1> %v) ret i1 %red @@ -219,8 +219,8 @@ ; CHECK-LABEL: vreduce_smin_v2i1: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetivli zero, 2, e8, mf8, ta, ma -; CHECK-NEXT: vcpop.m a0, v0 -; CHECK-NEXT: seqz a0, a0 +; CHECK-NEXT: vfirst.m a0, v0 +; CHECK-NEXT: slti a0, a0, 0 ; CHECK-NEXT: addi a0, a0, -1 ; CHECK-NEXT: ret %red = call i1 @llvm.vector.reduce.smin.v2i1(<2 x i1> %v) @@ -233,8 +233,8 @@ ; CHECK-LABEL: vreduce_or_v4i1: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetivli zero, 4, e8, mf4, ta, ma -; CHECK-NEXT: vcpop.m a0, v0 -; CHECK-NEXT: seqz a0, a0 +; CHECK-NEXT: vfirst.m a0, v0 +; CHECK-NEXT: slti a0, a0, 0 ; CHECK-NEXT: addi a0, a0, -1 ; CHECK-NEXT: ret %red = call i1 @llvm.vector.reduce.or.v4i1(<4 x i1> %v) @@ -286,9 +286,9 @@ ; CHECK: # %bb.0: ; CHECK-NEXT: vsetivli zero, 4, e8, mf4, ta, ma ; CHECK-NEXT: vmnot.m v8, v0 -; CHECK-NEXT: vcpop.m a0, v8 -; CHECK-NEXT: snez a0, a0 -; CHECK-NEXT: addi a0, a0, -1 +; CHECK-NEXT: vfirst.m a0, v8 +; CHECK-NEXT: slti a0, a0, 0 +; CHECK-NEXT: neg a0, a0 ; CHECK-NEXT: ret %red = call i1 @llvm.vector.reduce.and.v4i1(<4 x i1> %v) ret i1 %red @@ -300,8 +300,8 @@ ; CHECK-LABEL: vreduce_umax_v4i1: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetivli zero, 4, e8, mf4, ta, ma -; CHECK-NEXT: vcpop.m a0, v0 -; CHECK-NEXT: seqz a0, a0 +; CHECK-NEXT: vfirst.m a0, v0 +; CHECK-NEXT: slti a0, a0, 0 ; CHECK-NEXT: addi a0, a0, -1 ; CHECK-NEXT: ret %red = call i1 @llvm.vector.reduce.umax.v4i1(<4 x i1> %v) @@ -315,9 +315,9 @@ ; CHECK: # %bb.0: ; CHECK-NEXT: vsetivli zero, 4, e8, mf4, ta, ma ; CHECK-NEXT: vmnot.m v8, v0 -; CHECK-NEXT: vcpop.m a0, v8 -; CHECK-NEXT: snez a0, a0 -; CHECK-NEXT: addi a0, a0, -1 +; CHECK-NEXT: vfirst.m a0, v8 +; CHECK-NEXT: slti a0, a0, 0 +; CHECK-NEXT: neg a0, a0 ; CHECK-NEXT: ret %red = call i1 @llvm.vector.reduce.smax.v4i1(<4 x i1> %v) ret i1 %red @@ -330,9 +330,9 @@ ; CHECK: # %bb.0: ; CHECK-NEXT: vsetivli zero, 4, e8, mf4, ta, ma ; CHECK-NEXT: vmnot.m v8, v0 -; CHECK-NEXT: vcpop.m a0, v8 -; CHECK-NEXT: snez a0, a0 -; CHECK-NEXT: addi a0, a0, -1 +; CHECK-NEXT: vfirst.m a0, v8 +; CHECK-NEXT: slti a0, a0, 0 +; CHECK-NEXT: neg a0, a0 ; CHECK-NEXT: ret %red = call i1 @llvm.vector.reduce.umin.v4i1(<4 x i1> %v) ret i1 %red @@ -344,8 +344,8 @@ ; CHECK-LABEL: vreduce_smin_v4i1: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetivli zero, 4, e8, mf4, ta, ma -; CHECK-NEXT: vcpop.m a0, v0 -; CHECK-NEXT: seqz a0, a0 +; CHECK-NEXT: vfirst.m a0, v0 +; CHECK-NEXT: slti a0, a0, 0 ; CHECK-NEXT: addi a0, a0, -1 ; CHECK-NEXT: ret %red = call i1 @llvm.vector.reduce.smin.v4i1(<4 x i1> %v) @@ -358,8 +358,8 @@ ; CHECK-LABEL: vreduce_or_v8i1: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetivli zero, 8, e8, mf2, ta, ma -; CHECK-NEXT: vcpop.m a0, v0 -; CHECK-NEXT: seqz a0, a0 +; CHECK-NEXT: vfirst.m a0, v0 +; CHECK-NEXT: slti a0, a0, 0 ; CHECK-NEXT: addi a0, a0, -1 ; CHECK-NEXT: ret %red = call i1 @llvm.vector.reduce.or.v8i1(<8 x i1> %v) @@ -411,9 +411,9 @@ ; CHECK: # %bb.0: ; CHECK-NEXT: vsetivli zero, 8, e8, mf2, ta, ma ; CHECK-NEXT: vmnot.m v8, v0 -; CHECK-NEXT: vcpop.m a0, v8 -; CHECK-NEXT: snez a0, a0 -; CHECK-NEXT: addi a0, a0, -1 +; CHECK-NEXT: vfirst.m a0, v8 +; CHECK-NEXT: slti a0, a0, 0 +; CHECK-NEXT: neg a0, a0 ; CHECK-NEXT: ret %red = call i1 @llvm.vector.reduce.and.v8i1(<8 x i1> %v) ret i1 %red @@ -425,8 +425,8 @@ ; CHECK-LABEL: vreduce_umax_v8i1: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetivli zero, 8, e8, mf2, ta, ma -; CHECK-NEXT: vcpop.m a0, v0 -; CHECK-NEXT: seqz a0, a0 +; CHECK-NEXT: vfirst.m a0, v0 +; CHECK-NEXT: slti a0, a0, 0 ; CHECK-NEXT: addi a0, a0, -1 ; CHECK-NEXT: ret %red = call i1 @llvm.vector.reduce.umax.v8i1(<8 x i1> %v) @@ -440,9 +440,9 @@ ; CHECK: # %bb.0: ; CHECK-NEXT: vsetivli zero, 8, e8, mf2, ta, ma ; CHECK-NEXT: vmnot.m v8, v0 -; CHECK-NEXT: vcpop.m a0, v8 -; CHECK-NEXT: snez a0, a0 -; CHECK-NEXT: addi a0, a0, -1 +; CHECK-NEXT: vfirst.m a0, v8 +; CHECK-NEXT: slti a0, a0, 0 +; CHECK-NEXT: neg a0, a0 ; CHECK-NEXT: ret %red = call i1 @llvm.vector.reduce.smax.v8i1(<8 x i1> %v) ret i1 %red @@ -455,9 +455,9 @@ ; CHECK: # %bb.0: ; CHECK-NEXT: vsetivli zero, 8, e8, mf2, ta, ma ; CHECK-NEXT: vmnot.m v8, v0 -; CHECK-NEXT: vcpop.m a0, v8 -; CHECK-NEXT: snez a0, a0 -; CHECK-NEXT: addi a0, a0, -1 +; CHECK-NEXT: vfirst.m a0, v8 +; CHECK-NEXT: slti a0, a0, 0 +; CHECK-NEXT: neg a0, a0 ; CHECK-NEXT: ret %red = call i1 @llvm.vector.reduce.umin.v8i1(<8 x i1> %v) ret i1 %red @@ -469,8 +469,8 @@ ; CHECK-LABEL: vreduce_smin_v8i1: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetivli zero, 8, e8, mf2, ta, ma -; CHECK-NEXT: vcpop.m a0, v0 -; CHECK-NEXT: seqz a0, a0 +; CHECK-NEXT: vfirst.m a0, v0 +; CHECK-NEXT: slti a0, a0, 0 ; CHECK-NEXT: addi a0, a0, -1 ; CHECK-NEXT: ret %red = call i1 @llvm.vector.reduce.smin.v8i1(<8 x i1> %v) @@ -483,8 +483,8 @@ ; CHECK-LABEL: vreduce_or_v16i1: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetivli zero, 16, e8, m1, ta, ma -; CHECK-NEXT: vcpop.m a0, v0 -; CHECK-NEXT: seqz a0, a0 +; CHECK-NEXT: vfirst.m a0, v0 +; CHECK-NEXT: slti a0, a0, 0 ; CHECK-NEXT: addi a0, a0, -1 ; CHECK-NEXT: ret %red = call i1 @llvm.vector.reduce.or.v16i1(<16 x i1> %v) @@ -536,9 +536,9 @@ ; CHECK: # %bb.0: ; CHECK-NEXT: vsetivli zero, 16, e8, m1, ta, ma ; CHECK-NEXT: vmnot.m v8, v0 -; CHECK-NEXT: vcpop.m a0, v8 -; CHECK-NEXT: snez a0, a0 -; CHECK-NEXT: addi a0, a0, -1 +; CHECK-NEXT: vfirst.m a0, v8 +; CHECK-NEXT: slti a0, a0, 0 +; CHECK-NEXT: neg a0, a0 ; CHECK-NEXT: ret %red = call i1 @llvm.vector.reduce.and.v16i1(<16 x i1> %v) ret i1 %red @@ -550,8 +550,8 @@ ; CHECK-LABEL: vreduce_umax_v16i1: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetivli zero, 16, e8, m1, ta, ma -; CHECK-NEXT: vcpop.m a0, v0 -; CHECK-NEXT: seqz a0, a0 +; CHECK-NEXT: vfirst.m a0, v0 +; CHECK-NEXT: slti a0, a0, 0 ; CHECK-NEXT: addi a0, a0, -1 ; CHECK-NEXT: ret %red = call i1 @llvm.vector.reduce.umax.v16i1(<16 x i1> %v) @@ -565,9 +565,9 @@ ; CHECK: # %bb.0: ; CHECK-NEXT: vsetivli zero, 16, e8, m1, ta, ma ; CHECK-NEXT: vmnot.m v8, v0 -; CHECK-NEXT: vcpop.m a0, v8 -; CHECK-NEXT: snez a0, a0 -; CHECK-NEXT: addi a0, a0, -1 +; CHECK-NEXT: vfirst.m a0, v8 +; CHECK-NEXT: slti a0, a0, 0 +; CHECK-NEXT: neg a0, a0 ; CHECK-NEXT: ret %red = call i1 @llvm.vector.reduce.smax.v16i1(<16 x i1> %v) ret i1 %red @@ -580,9 +580,9 @@ ; CHECK: # %bb.0: ; CHECK-NEXT: vsetivli zero, 16, e8, m1, ta, ma ; CHECK-NEXT: vmnot.m v8, v0 -; CHECK-NEXT: vcpop.m a0, v8 -; CHECK-NEXT: snez a0, a0 -; CHECK-NEXT: addi a0, a0, -1 +; CHECK-NEXT: vfirst.m a0, v8 +; CHECK-NEXT: slti a0, a0, 0 +; CHECK-NEXT: neg a0, a0 ; CHECK-NEXT: ret %red = call i1 @llvm.vector.reduce.umin.v16i1(<16 x i1> %v) ret i1 %red @@ -594,8 +594,8 @@ ; CHECK-LABEL: vreduce_smin_v16i1: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetivli zero, 16, e8, m1, ta, ma -; CHECK-NEXT: vcpop.m a0, v0 -; CHECK-NEXT: seqz a0, a0 +; CHECK-NEXT: vfirst.m a0, v0 +; CHECK-NEXT: slti a0, a0, 0 ; CHECK-NEXT: addi a0, a0, -1 ; CHECK-NEXT: ret %red = call i1 @llvm.vector.reduce.smin.v16i1(<16 x i1> %v) @@ -609,8 +609,8 @@ ; LMULMAX1: # %bb.0: ; LMULMAX1-NEXT: vsetivli zero, 16, e8, m1, ta, ma ; LMULMAX1-NEXT: vmor.mm v8, v0, v8 -; LMULMAX1-NEXT: vcpop.m a0, v8 -; LMULMAX1-NEXT: seqz a0, a0 +; LMULMAX1-NEXT: vfirst.m a0, v8 +; LMULMAX1-NEXT: slti a0, a0, 0 ; LMULMAX1-NEXT: addi a0, a0, -1 ; LMULMAX1-NEXT: ret ; @@ -618,8 +618,8 @@ ; LMULMAX8: # %bb.0: ; LMULMAX8-NEXT: li a0, 32 ; LMULMAX8-NEXT: vsetvli zero, a0, e8, m2, ta, ma -; LMULMAX8-NEXT: vcpop.m a0, v0 -; LMULMAX8-NEXT: seqz a0, a0 +; LMULMAX8-NEXT: vfirst.m a0, v0 +; LMULMAX8-NEXT: slti a0, a0, 0 ; LMULMAX8-NEXT: addi a0, a0, -1 ; LMULMAX8-NEXT: ret %red = call i1 @llvm.vector.reduce.or.v32i1(<32 x i1> %v) @@ -675,9 +675,9 @@ ; LMULMAX1: # %bb.0: ; LMULMAX1-NEXT: vsetivli zero, 16, e8, m1, ta, ma ; LMULMAX1-NEXT: vmnand.mm v8, v0, v8 -; LMULMAX1-NEXT: vcpop.m a0, v8 -; LMULMAX1-NEXT: snez a0, a0 -; LMULMAX1-NEXT: addi a0, a0, -1 +; LMULMAX1-NEXT: vfirst.m a0, v8 +; LMULMAX1-NEXT: slti a0, a0, 0 +; LMULMAX1-NEXT: neg a0, a0 ; LMULMAX1-NEXT: ret ; ; LMULMAX8-LABEL: vreduce_and_v32i1: @@ -685,9 +685,9 @@ ; LMULMAX8-NEXT: li a0, 32 ; LMULMAX8-NEXT: vsetvli zero, a0, e8, m2, ta, ma ; LMULMAX8-NEXT: vmnot.m v8, v0 -; LMULMAX8-NEXT: vcpop.m a0, v8 -; LMULMAX8-NEXT: snez a0, a0 -; LMULMAX8-NEXT: addi a0, a0, -1 +; LMULMAX8-NEXT: vfirst.m a0, v8 +; LMULMAX8-NEXT: slti a0, a0, 0 +; LMULMAX8-NEXT: neg a0, a0 ; LMULMAX8-NEXT: ret %red = call i1 @llvm.vector.reduce.and.v32i1(<32 x i1> %v) ret i1 %red @@ -700,8 +700,8 @@ ; LMULMAX1: # %bb.0: ; LMULMAX1-NEXT: vsetivli zero, 16, e8, m1, ta, ma ; LMULMAX1-NEXT: vmor.mm v8, v0, v8 -; LMULMAX1-NEXT: vcpop.m a0, v8 -; LMULMAX1-NEXT: seqz a0, a0 +; LMULMAX1-NEXT: vfirst.m a0, v8 +; LMULMAX1-NEXT: slti a0, a0, 0 ; LMULMAX1-NEXT: addi a0, a0, -1 ; LMULMAX1-NEXT: ret ; @@ -709,8 +709,8 @@ ; LMULMAX8: # %bb.0: ; LMULMAX8-NEXT: li a0, 32 ; LMULMAX8-NEXT: vsetvli zero, a0, e8, m2, ta, ma -; LMULMAX8-NEXT: vcpop.m a0, v0 -; LMULMAX8-NEXT: seqz a0, a0 +; LMULMAX8-NEXT: vfirst.m a0, v0 +; LMULMAX8-NEXT: slti a0, a0, 0 ; LMULMAX8-NEXT: addi a0, a0, -1 ; LMULMAX8-NEXT: ret %red = call i1 @llvm.vector.reduce.umax.v32i1(<32 x i1> %v) @@ -724,9 +724,9 @@ ; LMULMAX1: # %bb.0: ; LMULMAX1-NEXT: vsetivli zero, 16, e8, m1, ta, ma ; LMULMAX1-NEXT: vmnand.mm v8, v0, v8 -; LMULMAX1-NEXT: vcpop.m a0, v8 -; LMULMAX1-NEXT: snez a0, a0 -; LMULMAX1-NEXT: addi a0, a0, -1 +; LMULMAX1-NEXT: vfirst.m a0, v8 +; LMULMAX1-NEXT: slti a0, a0, 0 +; LMULMAX1-NEXT: neg a0, a0 ; LMULMAX1-NEXT: ret ; ; LMULMAX8-LABEL: vreduce_smax_v32i1: @@ -734,9 +734,9 @@ ; LMULMAX8-NEXT: li a0, 32 ; LMULMAX8-NEXT: vsetvli zero, a0, e8, m2, ta, ma ; LMULMAX8-NEXT: vmnot.m v8, v0 -; LMULMAX8-NEXT: vcpop.m a0, v8 -; LMULMAX8-NEXT: snez a0, a0 -; LMULMAX8-NEXT: addi a0, a0, -1 +; LMULMAX8-NEXT: vfirst.m a0, v8 +; LMULMAX8-NEXT: slti a0, a0, 0 +; LMULMAX8-NEXT: neg a0, a0 ; LMULMAX8-NEXT: ret %red = call i1 @llvm.vector.reduce.smax.v32i1(<32 x i1> %v) ret i1 %red @@ -749,9 +749,9 @@ ; LMULMAX1: # %bb.0: ; LMULMAX1-NEXT: vsetivli zero, 16, e8, m1, ta, ma ; LMULMAX1-NEXT: vmnand.mm v8, v0, v8 -; LMULMAX1-NEXT: vcpop.m a0, v8 -; LMULMAX1-NEXT: snez a0, a0 -; LMULMAX1-NEXT: addi a0, a0, -1 +; LMULMAX1-NEXT: vfirst.m a0, v8 +; LMULMAX1-NEXT: slti a0, a0, 0 +; LMULMAX1-NEXT: neg a0, a0 ; LMULMAX1-NEXT: ret ; ; LMULMAX8-LABEL: vreduce_umin_v32i1: @@ -759,9 +759,9 @@ ; LMULMAX8-NEXT: li a0, 32 ; LMULMAX8-NEXT: vsetvli zero, a0, e8, m2, ta, ma ; LMULMAX8-NEXT: vmnot.m v8, v0 -; LMULMAX8-NEXT: vcpop.m a0, v8 -; LMULMAX8-NEXT: snez a0, a0 -; LMULMAX8-NEXT: addi a0, a0, -1 +; LMULMAX8-NEXT: vfirst.m a0, v8 +; LMULMAX8-NEXT: slti a0, a0, 0 +; LMULMAX8-NEXT: neg a0, a0 ; LMULMAX8-NEXT: ret %red = call i1 @llvm.vector.reduce.umin.v32i1(<32 x i1> %v) ret i1 %red @@ -774,8 +774,8 @@ ; LMULMAX1: # %bb.0: ; LMULMAX1-NEXT: vsetivli zero, 16, e8, m1, ta, ma ; LMULMAX1-NEXT: vmor.mm v8, v0, v8 -; LMULMAX1-NEXT: vcpop.m a0, v8 -; LMULMAX1-NEXT: seqz a0, a0 +; LMULMAX1-NEXT: vfirst.m a0, v8 +; LMULMAX1-NEXT: slti a0, a0, 0 ; LMULMAX1-NEXT: addi a0, a0, -1 ; LMULMAX1-NEXT: ret ; @@ -783,8 +783,8 @@ ; LMULMAX8: # %bb.0: ; LMULMAX8-NEXT: li a0, 32 ; LMULMAX8-NEXT: vsetvli zero, a0, e8, m2, ta, ma -; LMULMAX8-NEXT: vcpop.m a0, v0 -; LMULMAX8-NEXT: seqz a0, a0 +; LMULMAX8-NEXT: vfirst.m a0, v0 +; LMULMAX8-NEXT: slti a0, a0, 0 ; LMULMAX8-NEXT: addi a0, a0, -1 ; LMULMAX8-NEXT: ret %red = call i1 @llvm.vector.reduce.smin.v32i1(<32 x i1> %v) @@ -800,8 +800,8 @@ ; LMULMAX1-NEXT: vmor.mm v8, v8, v10 ; LMULMAX1-NEXT: vmor.mm v9, v0, v9 ; LMULMAX1-NEXT: vmor.mm v8, v9, v8 -; LMULMAX1-NEXT: vcpop.m a0, v8 -; LMULMAX1-NEXT: seqz a0, a0 +; LMULMAX1-NEXT: vfirst.m a0, v8 +; LMULMAX1-NEXT: slti a0, a0, 0 ; LMULMAX1-NEXT: addi a0, a0, -1 ; LMULMAX1-NEXT: ret ; @@ -809,8 +809,8 @@ ; LMULMAX8: # %bb.0: ; LMULMAX8-NEXT: li a0, 64 ; LMULMAX8-NEXT: vsetvli zero, a0, e8, m4, ta, ma -; LMULMAX8-NEXT: vcpop.m a0, v0 -; LMULMAX8-NEXT: seqz a0, a0 +; LMULMAX8-NEXT: vfirst.m a0, v0 +; LMULMAX8-NEXT: slti a0, a0, 0 ; LMULMAX8-NEXT: addi a0, a0, -1 ; LMULMAX8-NEXT: ret %red = call i1 @llvm.vector.reduce.or.v64i1(<64 x i1> %v) @@ -872,9 +872,9 @@ ; LMULMAX1-NEXT: vmand.mm v8, v8, v10 ; LMULMAX1-NEXT: vmand.mm v9, v0, v9 ; LMULMAX1-NEXT: vmnand.mm v8, v9, v8 -; LMULMAX1-NEXT: vcpop.m a0, v8 -; LMULMAX1-NEXT: snez a0, a0 -; LMULMAX1-NEXT: addi a0, a0, -1 +; LMULMAX1-NEXT: vfirst.m a0, v8 +; LMULMAX1-NEXT: slti a0, a0, 0 +; LMULMAX1-NEXT: neg a0, a0 ; LMULMAX1-NEXT: ret ; ; LMULMAX8-LABEL: vreduce_and_v64i1: @@ -882,9 +882,9 @@ ; LMULMAX8-NEXT: li a0, 64 ; LMULMAX8-NEXT: vsetvli zero, a0, e8, m4, ta, ma ; LMULMAX8-NEXT: vmnot.m v8, v0 -; LMULMAX8-NEXT: vcpop.m a0, v8 -; LMULMAX8-NEXT: snez a0, a0 -; LMULMAX8-NEXT: addi a0, a0, -1 +; LMULMAX8-NEXT: vfirst.m a0, v8 +; LMULMAX8-NEXT: slti a0, a0, 0 +; LMULMAX8-NEXT: neg a0, a0 ; LMULMAX8-NEXT: ret %red = call i1 @llvm.vector.reduce.and.v64i1(<64 x i1> %v) ret i1 %red @@ -899,8 +899,8 @@ ; LMULMAX1-NEXT: vmor.mm v8, v8, v10 ; LMULMAX1-NEXT: vmor.mm v9, v0, v9 ; LMULMAX1-NEXT: vmor.mm v8, v9, v8 -; LMULMAX1-NEXT: vcpop.m a0, v8 -; LMULMAX1-NEXT: seqz a0, a0 +; LMULMAX1-NEXT: vfirst.m a0, v8 +; LMULMAX1-NEXT: slti a0, a0, 0 ; LMULMAX1-NEXT: addi a0, a0, -1 ; LMULMAX1-NEXT: ret ; @@ -908,8 +908,8 @@ ; LMULMAX8: # %bb.0: ; LMULMAX8-NEXT: li a0, 64 ; LMULMAX8-NEXT: vsetvli zero, a0, e8, m4, ta, ma -; LMULMAX8-NEXT: vcpop.m a0, v0 -; LMULMAX8-NEXT: seqz a0, a0 +; LMULMAX8-NEXT: vfirst.m a0, v0 +; LMULMAX8-NEXT: slti a0, a0, 0 ; LMULMAX8-NEXT: addi a0, a0, -1 ; LMULMAX8-NEXT: ret %red = call i1 @llvm.vector.reduce.umax.v64i1(<64 x i1> %v) @@ -925,9 +925,9 @@ ; LMULMAX1-NEXT: vmand.mm v8, v8, v10 ; LMULMAX1-NEXT: vmand.mm v9, v0, v9 ; LMULMAX1-NEXT: vmnand.mm v8, v9, v8 -; LMULMAX1-NEXT: vcpop.m a0, v8 -; LMULMAX1-NEXT: snez a0, a0 -; LMULMAX1-NEXT: addi a0, a0, -1 +; LMULMAX1-NEXT: vfirst.m a0, v8 +; LMULMAX1-NEXT: slti a0, a0, 0 +; LMULMAX1-NEXT: neg a0, a0 ; LMULMAX1-NEXT: ret ; ; LMULMAX8-LABEL: vreduce_smax_v64i1: @@ -935,9 +935,9 @@ ; LMULMAX8-NEXT: li a0, 64 ; LMULMAX8-NEXT: vsetvli zero, a0, e8, m4, ta, ma ; LMULMAX8-NEXT: vmnot.m v8, v0 -; LMULMAX8-NEXT: vcpop.m a0, v8 -; LMULMAX8-NEXT: snez a0, a0 -; LMULMAX8-NEXT: addi a0, a0, -1 +; LMULMAX8-NEXT: vfirst.m a0, v8 +; LMULMAX8-NEXT: slti a0, a0, 0 +; LMULMAX8-NEXT: neg a0, a0 ; LMULMAX8-NEXT: ret %red = call i1 @llvm.vector.reduce.smax.v64i1(<64 x i1> %v) ret i1 %red @@ -952,9 +952,9 @@ ; LMULMAX1-NEXT: vmand.mm v8, v8, v10 ; LMULMAX1-NEXT: vmand.mm v9, v0, v9 ; LMULMAX1-NEXT: vmnand.mm v8, v9, v8 -; LMULMAX1-NEXT: vcpop.m a0, v8 -; LMULMAX1-NEXT: snez a0, a0 -; LMULMAX1-NEXT: addi a0, a0, -1 +; LMULMAX1-NEXT: vfirst.m a0, v8 +; LMULMAX1-NEXT: slti a0, a0, 0 +; LMULMAX1-NEXT: neg a0, a0 ; LMULMAX1-NEXT: ret ; ; LMULMAX8-LABEL: vreduce_umin_v64i1: @@ -962,9 +962,9 @@ ; LMULMAX8-NEXT: li a0, 64 ; LMULMAX8-NEXT: vsetvli zero, a0, e8, m4, ta, ma ; LMULMAX8-NEXT: vmnot.m v8, v0 -; LMULMAX8-NEXT: vcpop.m a0, v8 -; LMULMAX8-NEXT: snez a0, a0 -; LMULMAX8-NEXT: addi a0, a0, -1 +; LMULMAX8-NEXT: vfirst.m a0, v8 +; LMULMAX8-NEXT: slti a0, a0, 0 +; LMULMAX8-NEXT: neg a0, a0 ; LMULMAX8-NEXT: ret %red = call i1 @llvm.vector.reduce.umin.v64i1(<64 x i1> %v) ret i1 %red @@ -979,8 +979,8 @@ ; LMULMAX1-NEXT: vmor.mm v8, v8, v10 ; LMULMAX1-NEXT: vmor.mm v9, v0, v9 ; LMULMAX1-NEXT: vmor.mm v8, v9, v8 -; LMULMAX1-NEXT: vcpop.m a0, v8 -; LMULMAX1-NEXT: seqz a0, a0 +; LMULMAX1-NEXT: vfirst.m a0, v8 +; LMULMAX1-NEXT: slti a0, a0, 0 ; LMULMAX1-NEXT: addi a0, a0, -1 ; LMULMAX1-NEXT: ret ; @@ -988,8 +988,8 @@ ; LMULMAX8: # %bb.0: ; LMULMAX8-NEXT: li a0, 64 ; LMULMAX8-NEXT: vsetvli zero, a0, e8, m4, ta, ma -; LMULMAX8-NEXT: vcpop.m a0, v0 -; LMULMAX8-NEXT: seqz a0, a0 +; LMULMAX8-NEXT: vfirst.m a0, v0 +; LMULMAX8-NEXT: slti a0, a0, 0 ; LMULMAX8-NEXT: addi a0, a0, -1 ; LMULMAX8-NEXT: ret %red = call i1 @llvm.vector.reduce.smin.v64i1(<64 x i1> %v) diff --git a/llvm/test/CodeGen/RISCV/rvv/vreductions-mask-vp.ll b/llvm/test/CodeGen/RISCV/rvv/vreductions-mask-vp.ll --- a/llvm/test/CodeGen/RISCV/rvv/vreductions-mask-vp.ll +++ b/llvm/test/CodeGen/RISCV/rvv/vreductions-mask-vp.ll @@ -10,8 +10,8 @@ ; CHECK-NEXT: vsetvli zero, a1, e8, mf8, ta, ma ; CHECK-NEXT: vmnot.m v9, v0 ; CHECK-NEXT: vmv1r.v v0, v8 -; CHECK-NEXT: vcpop.m a1, v9, v0.t -; CHECK-NEXT: seqz a1, a1 +; CHECK-NEXT: vfirst.m a1, v9, v0.t +; CHECK-NEXT: slti a1, a1, 0 ; CHECK-NEXT: and a0, a1, a0 ; CHECK-NEXT: neg a0, a0 ; CHECK-NEXT: ret @@ -27,8 +27,9 @@ ; RV32-NEXT: vmv1r.v v9, v0 ; RV32-NEXT: vsetvli zero, a1, e8, mf8, ta, ma ; RV32-NEXT: vmv1r.v v0, v8 -; RV32-NEXT: vcpop.m a1, v9, v0.t -; RV32-NEXT: snez a1, a1 +; RV32-NEXT: vfirst.m a1, v9, v0.t +; RV32-NEXT: slti a1, a1, 0 +; RV32-NEXT: not a1, a1 ; RV32-NEXT: or a0, a1, a0 ; RV32-NEXT: slli a0, a0, 31 ; RV32-NEXT: srai a0, a0, 31 @@ -39,8 +40,9 @@ ; RV64-NEXT: vmv1r.v v9, v0 ; RV64-NEXT: vsetvli zero, a1, e8, mf8, ta, ma ; RV64-NEXT: vmv1r.v v0, v8 -; RV64-NEXT: vcpop.m a1, v9, v0.t -; RV64-NEXT: snez a1, a1 +; RV64-NEXT: vfirst.m a1, v9, v0.t +; RV64-NEXT: slti a1, a1, 0 +; RV64-NEXT: not a1, a1 ; RV64-NEXT: or a0, a1, a0 ; RV64-NEXT: slli a0, a0, 63 ; RV64-NEXT: srai a0, a0, 63 @@ -85,8 +87,8 @@ ; CHECK-NEXT: vsetvli zero, a1, e8, mf4, ta, ma ; CHECK-NEXT: vmnot.m v9, v0 ; CHECK-NEXT: vmv1r.v v0, v8 -; CHECK-NEXT: vcpop.m a1, v9, v0.t -; CHECK-NEXT: seqz a1, a1 +; CHECK-NEXT: vfirst.m a1, v9, v0.t +; CHECK-NEXT: slti a1, a1, 0 ; CHECK-NEXT: and a0, a1, a0 ; CHECK-NEXT: neg a0, a0 ; CHECK-NEXT: ret @@ -102,8 +104,9 @@ ; RV32-NEXT: vmv1r.v v9, v0 ; RV32-NEXT: vsetvli zero, a1, e8, mf4, ta, ma ; RV32-NEXT: vmv1r.v v0, v8 -; RV32-NEXT: vcpop.m a1, v9, v0.t -; RV32-NEXT: snez a1, a1 +; RV32-NEXT: vfirst.m a1, v9, v0.t +; RV32-NEXT: slti a1, a1, 0 +; RV32-NEXT: not a1, a1 ; RV32-NEXT: or a0, a1, a0 ; RV32-NEXT: slli a0, a0, 31 ; RV32-NEXT: srai a0, a0, 31 @@ -114,8 +117,9 @@ ; RV64-NEXT: vmv1r.v v9, v0 ; RV64-NEXT: vsetvli zero, a1, e8, mf4, ta, ma ; RV64-NEXT: vmv1r.v v0, v8 -; RV64-NEXT: vcpop.m a1, v9, v0.t -; RV64-NEXT: snez a1, a1 +; RV64-NEXT: vfirst.m a1, v9, v0.t +; RV64-NEXT: slti a1, a1, 0 +; RV64-NEXT: not a1, a1 ; RV64-NEXT: or a0, a1, a0 ; RV64-NEXT: slli a0, a0, 63 ; RV64-NEXT: srai a0, a0, 63 @@ -160,8 +164,8 @@ ; CHECK-NEXT: vsetvli zero, a1, e8, mf2, ta, ma ; CHECK-NEXT: vmnot.m v9, v0 ; CHECK-NEXT: vmv1r.v v0, v8 -; CHECK-NEXT: vcpop.m a1, v9, v0.t -; CHECK-NEXT: seqz a1, a1 +; CHECK-NEXT: vfirst.m a1, v9, v0.t +; CHECK-NEXT: slti a1, a1, 0 ; CHECK-NEXT: and a0, a1, a0 ; CHECK-NEXT: neg a0, a0 ; CHECK-NEXT: ret @@ -177,8 +181,9 @@ ; RV32-NEXT: vmv1r.v v9, v0 ; RV32-NEXT: vsetvli zero, a1, e8, mf2, ta, ma ; RV32-NEXT: vmv1r.v v0, v8 -; RV32-NEXT: vcpop.m a1, v9, v0.t -; RV32-NEXT: snez a1, a1 +; RV32-NEXT: vfirst.m a1, v9, v0.t +; RV32-NEXT: slti a1, a1, 0 +; RV32-NEXT: not a1, a1 ; RV32-NEXT: or a0, a1, a0 ; RV32-NEXT: slli a0, a0, 31 ; RV32-NEXT: srai a0, a0, 31 @@ -189,8 +194,9 @@ ; RV64-NEXT: vmv1r.v v9, v0 ; RV64-NEXT: vsetvli zero, a1, e8, mf2, ta, ma ; RV64-NEXT: vmv1r.v v0, v8 -; RV64-NEXT: vcpop.m a1, v9, v0.t -; RV64-NEXT: snez a1, a1 +; RV64-NEXT: vfirst.m a1, v9, v0.t +; RV64-NEXT: slti a1, a1, 0 +; RV64-NEXT: not a1, a1 ; RV64-NEXT: or a0, a1, a0 ; RV64-NEXT: slli a0, a0, 63 ; RV64-NEXT: srai a0, a0, 63 @@ -235,8 +241,8 @@ ; CHECK-NEXT: vsetvli zero, a1, e8, m1, ta, ma ; CHECK-NEXT: vmnot.m v9, v0 ; CHECK-NEXT: vmv1r.v v0, v8 -; CHECK-NEXT: vcpop.m a1, v9, v0.t -; CHECK-NEXT: seqz a1, a1 +; CHECK-NEXT: vfirst.m a1, v9, v0.t +; CHECK-NEXT: slti a1, a1, 0 ; CHECK-NEXT: and a0, a1, a0 ; CHECK-NEXT: neg a0, a0 ; CHECK-NEXT: ret @@ -252,8 +258,9 @@ ; RV32-NEXT: vmv1r.v v9, v0 ; RV32-NEXT: vsetvli zero, a1, e8, m1, ta, ma ; RV32-NEXT: vmv1r.v v0, v8 -; RV32-NEXT: vcpop.m a1, v9, v0.t -; RV32-NEXT: snez a1, a1 +; RV32-NEXT: vfirst.m a1, v9, v0.t +; RV32-NEXT: slti a1, a1, 0 +; RV32-NEXT: not a1, a1 ; RV32-NEXT: or a0, a1, a0 ; RV32-NEXT: slli a0, a0, 31 ; RV32-NEXT: srai a0, a0, 31 @@ -264,8 +271,9 @@ ; RV64-NEXT: vmv1r.v v9, v0 ; RV64-NEXT: vsetvli zero, a1, e8, m1, ta, ma ; RV64-NEXT: vmv1r.v v0, v8 -; RV64-NEXT: vcpop.m a1, v9, v0.t -; RV64-NEXT: snez a1, a1 +; RV64-NEXT: vfirst.m a1, v9, v0.t +; RV64-NEXT: slti a1, a1, 0 +; RV64-NEXT: not a1, a1 ; RV64-NEXT: or a0, a1, a0 ; RV64-NEXT: slli a0, a0, 63 ; RV64-NEXT: srai a0, a0, 63 @@ -310,8 +318,8 @@ ; CHECK-NEXT: vsetvli zero, a1, e8, m2, ta, ma ; CHECK-NEXT: vmnot.m v9, v0 ; CHECK-NEXT: vmv1r.v v0, v8 -; CHECK-NEXT: vcpop.m a1, v9, v0.t -; CHECK-NEXT: seqz a1, a1 +; CHECK-NEXT: vfirst.m a1, v9, v0.t +; CHECK-NEXT: slti a1, a1, 0 ; CHECK-NEXT: and a0, a1, a0 ; CHECK-NEXT: neg a0, a0 ; CHECK-NEXT: ret @@ -327,8 +335,9 @@ ; RV32-NEXT: vmv1r.v v9, v0 ; RV32-NEXT: vsetvli zero, a1, e8, m2, ta, ma ; RV32-NEXT: vmv1r.v v0, v8 -; RV32-NEXT: vcpop.m a1, v9, v0.t -; RV32-NEXT: snez a1, a1 +; RV32-NEXT: vfirst.m a1, v9, v0.t +; RV32-NEXT: slti a1, a1, 0 +; RV32-NEXT: not a1, a1 ; RV32-NEXT: or a0, a1, a0 ; RV32-NEXT: slli a0, a0, 31 ; RV32-NEXT: srai a0, a0, 31 @@ -339,8 +348,9 @@ ; RV64-NEXT: vmv1r.v v9, v0 ; RV64-NEXT: vsetvli zero, a1, e8, m2, ta, ma ; RV64-NEXT: vmv1r.v v0, v8 -; RV64-NEXT: vcpop.m a1, v9, v0.t -; RV64-NEXT: snez a1, a1 +; RV64-NEXT: vfirst.m a1, v9, v0.t +; RV64-NEXT: slti a1, a1, 0 +; RV64-NEXT: not a1, a1 ; RV64-NEXT: or a0, a1, a0 ; RV64-NEXT: slli a0, a0, 63 ; RV64-NEXT: srai a0, a0, 63 @@ -385,8 +395,8 @@ ; CHECK-NEXT: vsetvli zero, a1, e8, m4, ta, ma ; CHECK-NEXT: vmnot.m v9, v0 ; CHECK-NEXT: vmv1r.v v0, v8 -; CHECK-NEXT: vcpop.m a1, v9, v0.t -; CHECK-NEXT: seqz a1, a1 +; CHECK-NEXT: vfirst.m a1, v9, v0.t +; CHECK-NEXT: slti a1, a1, 0 ; CHECK-NEXT: and a0, a1, a0 ; CHECK-NEXT: neg a0, a0 ; CHECK-NEXT: ret @@ -402,8 +412,9 @@ ; RV32-NEXT: vmv1r.v v9, v0 ; RV32-NEXT: vsetvli zero, a1, e8, m4, ta, ma ; RV32-NEXT: vmv1r.v v0, v8 -; RV32-NEXT: vcpop.m a1, v9, v0.t -; RV32-NEXT: snez a1, a1 +; RV32-NEXT: vfirst.m a1, v9, v0.t +; RV32-NEXT: slti a1, a1, 0 +; RV32-NEXT: not a1, a1 ; RV32-NEXT: or a0, a1, a0 ; RV32-NEXT: slli a0, a0, 31 ; RV32-NEXT: srai a0, a0, 31 @@ -414,8 +425,9 @@ ; RV64-NEXT: vmv1r.v v9, v0 ; RV64-NEXT: vsetvli zero, a1, e8, m4, ta, ma ; RV64-NEXT: vmv1r.v v0, v8 -; RV64-NEXT: vcpop.m a1, v9, v0.t -; RV64-NEXT: snez a1, a1 +; RV64-NEXT: vfirst.m a1, v9, v0.t +; RV64-NEXT: slti a1, a1, 0 +; RV64-NEXT: not a1, a1 ; RV64-NEXT: or a0, a1, a0 ; RV64-NEXT: slli a0, a0, 63 ; RV64-NEXT: srai a0, a0, 63 @@ -460,8 +472,9 @@ ; RV32-NEXT: vmv1r.v v9, v0 ; RV32-NEXT: vsetvli zero, a1, e8, m8, ta, ma ; RV32-NEXT: vmv1r.v v0, v8 -; RV32-NEXT: vcpop.m a1, v9, v0.t -; RV32-NEXT: snez a1, a1 +; RV32-NEXT: vfirst.m a1, v9, v0.t +; RV32-NEXT: slti a1, a1, 0 +; RV32-NEXT: not a1, a1 ; RV32-NEXT: or a0, a1, a0 ; RV32-NEXT: slli a0, a0, 31 ; RV32-NEXT: srai a0, a0, 31 @@ -472,8 +485,9 @@ ; RV64-NEXT: vmv1r.v v9, v0 ; RV64-NEXT: vsetvli zero, a1, e8, m8, ta, ma ; RV64-NEXT: vmv1r.v v0, v8 -; RV64-NEXT: vcpop.m a1, v9, v0.t -; RV64-NEXT: snez a1, a1 +; RV64-NEXT: vfirst.m a1, v9, v0.t +; RV64-NEXT: slti a1, a1, 0 +; RV64-NEXT: not a1, a1 ; RV64-NEXT: or a0, a1, a0 ; RV64-NEXT: slli a0, a0, 63 ; RV64-NEXT: srai a0, a0, 63 @@ -490,8 +504,8 @@ ; CHECK-NEXT: vsetvli zero, a1, e8, m8, ta, ma ; CHECK-NEXT: vmnot.m v9, v0 ; CHECK-NEXT: vmv1r.v v0, v8 -; CHECK-NEXT: vcpop.m a1, v9, v0.t -; CHECK-NEXT: seqz a1, a1 +; CHECK-NEXT: vfirst.m a1, v9, v0.t +; CHECK-NEXT: slti a1, a1, 0 ; CHECK-NEXT: and a0, a1, a0 ; CHECK-NEXT: neg a0, a0 ; CHECK-NEXT: ret @@ -507,8 +521,9 @@ ; RV32-NEXT: vmv1r.v v9, v0 ; RV32-NEXT: vsetvli zero, a1, e8, m8, ta, ma ; RV32-NEXT: vmv1r.v v0, v8 -; RV32-NEXT: vcpop.m a1, v9, v0.t -; RV32-NEXT: snez a1, a1 +; RV32-NEXT: vfirst.m a1, v9, v0.t +; RV32-NEXT: slti a1, a1, 0 +; RV32-NEXT: not a1, a1 ; RV32-NEXT: or a0, a1, a0 ; RV32-NEXT: slli a0, a0, 31 ; RV32-NEXT: srai a0, a0, 31 @@ -519,8 +534,9 @@ ; RV64-NEXT: vmv1r.v v9, v0 ; RV64-NEXT: vsetvli zero, a1, e8, m8, ta, ma ; RV64-NEXT: vmv1r.v v0, v8 -; RV64-NEXT: vcpop.m a1, v9, v0.t -; RV64-NEXT: snez a1, a1 +; RV64-NEXT: vfirst.m a1, v9, v0.t +; RV64-NEXT: slti a1, a1, 0 +; RV64-NEXT: not a1, a1 ; RV64-NEXT: or a0, a1, a0 ; RV64-NEXT: slli a0, a0, 63 ; RV64-NEXT: srai a0, a0, 63 @@ -571,16 +587,18 @@ ; RV32-NEXT: and a3, a4, a3 ; RV32-NEXT: vsetvli zero, a3, e8, m8, ta, ma ; RV32-NEXT: vmv1r.v v0, v10 -; RV32-NEXT: vcpop.m a3, v8, v0.t -; RV32-NEXT: snez a3, a3 +; RV32-NEXT: vfirst.m a3, v8, v0.t +; RV32-NEXT: slti a3, a3, 0 +; RV32-NEXT: not a3, a3 ; RV32-NEXT: bltu a1, a2, .LBB22_2 ; RV32-NEXT: # %bb.1: ; RV32-NEXT: mv a1, a2 ; RV32-NEXT: .LBB22_2: ; RV32-NEXT: vsetvli zero, a1, e8, m8, ta, ma ; RV32-NEXT: vmv1r.v v0, v9 -; RV32-NEXT: vcpop.m a1, v11, v0.t -; RV32-NEXT: snez a1, a1 +; RV32-NEXT: vfirst.m a1, v11, v0.t +; RV32-NEXT: slti a1, a1, 0 +; RV32-NEXT: not a1, a1 ; RV32-NEXT: or a0, a3, a0 ; RV32-NEXT: or a0, a0, a1 ; RV32-NEXT: slli a0, a0, 31 @@ -598,16 +616,18 @@ ; RV64-NEXT: and a3, a4, a3 ; RV64-NEXT: vsetvli zero, a3, e8, m8, ta, ma ; RV64-NEXT: vmv1r.v v0, v10 -; RV64-NEXT: vcpop.m a3, v8, v0.t -; RV64-NEXT: snez a3, a3 +; RV64-NEXT: vfirst.m a3, v8, v0.t +; RV64-NEXT: slti a3, a3, 0 +; RV64-NEXT: not a3, a3 ; RV64-NEXT: bltu a1, a2, .LBB22_2 ; RV64-NEXT: # %bb.1: ; RV64-NEXT: mv a1, a2 ; RV64-NEXT: .LBB22_2: ; RV64-NEXT: vsetvli zero, a1, e8, m8, ta, ma ; RV64-NEXT: vmv1r.v v0, v9 -; RV64-NEXT: vcpop.m a1, v11, v0.t -; RV64-NEXT: snez a1, a1 +; RV64-NEXT: vfirst.m a1, v11, v0.t +; RV64-NEXT: slti a1, a1, 0 +; RV64-NEXT: not a1, a1 ; RV64-NEXT: or a0, a3, a0 ; RV64-NEXT: or a0, a0, a1 ; RV64-NEXT: slli a0, a0, 63 @@ -822,8 +842,8 @@ ; CHECK-NEXT: vsetvli zero, a1, e8, mf8, ta, ma ; CHECK-NEXT: vmnot.m v9, v0 ; CHECK-NEXT: vmv1r.v v0, v8 -; CHECK-NEXT: vcpop.m a1, v9, v0.t -; CHECK-NEXT: seqz a1, a1 +; CHECK-NEXT: vfirst.m a1, v9, v0.t +; CHECK-NEXT: slti a1, a1, 0 ; CHECK-NEXT: and a0, a1, a0 ; CHECK-NEXT: neg a0, a0 ; CHECK-NEXT: ret @@ -839,8 +859,8 @@ ; CHECK-NEXT: vsetvli zero, a1, e8, mf4, ta, ma ; CHECK-NEXT: vmnot.m v9, v0 ; CHECK-NEXT: vmv1r.v v0, v8 -; CHECK-NEXT: vcpop.m a1, v9, v0.t -; CHECK-NEXT: seqz a1, a1 +; CHECK-NEXT: vfirst.m a1, v9, v0.t +; CHECK-NEXT: slti a1, a1, 0 ; CHECK-NEXT: and a0, a1, a0 ; CHECK-NEXT: neg a0, a0 ; CHECK-NEXT: ret @@ -856,8 +876,8 @@ ; CHECK-NEXT: vsetvli zero, a1, e8, mf2, ta, ma ; CHECK-NEXT: vmnot.m v9, v0 ; CHECK-NEXT: vmv1r.v v0, v8 -; CHECK-NEXT: vcpop.m a1, v9, v0.t -; CHECK-NEXT: seqz a1, a1 +; CHECK-NEXT: vfirst.m a1, v9, v0.t +; CHECK-NEXT: slti a1, a1, 0 ; CHECK-NEXT: and a0, a1, a0 ; CHECK-NEXT: neg a0, a0 ; CHECK-NEXT: ret @@ -873,8 +893,8 @@ ; CHECK-NEXT: vsetvli zero, a1, e8, m1, ta, ma ; CHECK-NEXT: vmnot.m v9, v0 ; CHECK-NEXT: vmv1r.v v0, v8 -; CHECK-NEXT: vcpop.m a1, v9, v0.t -; CHECK-NEXT: seqz a1, a1 +; CHECK-NEXT: vfirst.m a1, v9, v0.t +; CHECK-NEXT: slti a1, a1, 0 ; CHECK-NEXT: and a0, a1, a0 ; CHECK-NEXT: neg a0, a0 ; CHECK-NEXT: ret @@ -890,8 +910,8 @@ ; CHECK-NEXT: vsetvli zero, a1, e8, m2, ta, ma ; CHECK-NEXT: vmnot.m v9, v0 ; CHECK-NEXT: vmv1r.v v0, v8 -; CHECK-NEXT: vcpop.m a1, v9, v0.t -; CHECK-NEXT: seqz a1, a1 +; CHECK-NEXT: vfirst.m a1, v9, v0.t +; CHECK-NEXT: slti a1, a1, 0 ; CHECK-NEXT: and a0, a1, a0 ; CHECK-NEXT: neg a0, a0 ; CHECK-NEXT: ret @@ -907,8 +927,8 @@ ; CHECK-NEXT: vsetvli zero, a1, e8, m4, ta, ma ; CHECK-NEXT: vmnot.m v9, v0 ; CHECK-NEXT: vmv1r.v v0, v8 -; CHECK-NEXT: vcpop.m a1, v9, v0.t -; CHECK-NEXT: seqz a1, a1 +; CHECK-NEXT: vfirst.m a1, v9, v0.t +; CHECK-NEXT: slti a1, a1, 0 ; CHECK-NEXT: and a0, a1, a0 ; CHECK-NEXT: neg a0, a0 ; CHECK-NEXT: ret @@ -924,8 +944,8 @@ ; CHECK-NEXT: vsetvli zero, a1, e8, m8, ta, ma ; CHECK-NEXT: vmnot.m v9, v0 ; CHECK-NEXT: vmv1r.v v0, v8 -; CHECK-NEXT: vcpop.m a1, v9, v0.t -; CHECK-NEXT: seqz a1, a1 +; CHECK-NEXT: vfirst.m a1, v9, v0.t +; CHECK-NEXT: slti a1, a1, 0 ; CHECK-NEXT: and a0, a1, a0 ; CHECK-NEXT: neg a0, a0 ; CHECK-NEXT: ret @@ -941,8 +961,9 @@ ; RV32-NEXT: vmv1r.v v9, v0 ; RV32-NEXT: vsetvli zero, a1, e8, mf8, ta, ma ; RV32-NEXT: vmv1r.v v0, v8 -; RV32-NEXT: vcpop.m a1, v9, v0.t -; RV32-NEXT: snez a1, a1 +; RV32-NEXT: vfirst.m a1, v9, v0.t +; RV32-NEXT: slti a1, a1, 0 +; RV32-NEXT: not a1, a1 ; RV32-NEXT: or a0, a1, a0 ; RV32-NEXT: slli a0, a0, 31 ; RV32-NEXT: srai a0, a0, 31 @@ -953,8 +974,9 @@ ; RV64-NEXT: vmv1r.v v9, v0 ; RV64-NEXT: vsetvli zero, a1, e8, mf8, ta, ma ; RV64-NEXT: vmv1r.v v0, v8 -; RV64-NEXT: vcpop.m a1, v9, v0.t -; RV64-NEXT: snez a1, a1 +; RV64-NEXT: vfirst.m a1, v9, v0.t +; RV64-NEXT: slti a1, a1, 0 +; RV64-NEXT: not a1, a1 ; RV64-NEXT: or a0, a1, a0 ; RV64-NEXT: slli a0, a0, 63 ; RV64-NEXT: srai a0, a0, 63 @@ -971,8 +993,9 @@ ; RV32-NEXT: vmv1r.v v9, v0 ; RV32-NEXT: vsetvli zero, a1, e8, mf4, ta, ma ; RV32-NEXT: vmv1r.v v0, v8 -; RV32-NEXT: vcpop.m a1, v9, v0.t -; RV32-NEXT: snez a1, a1 +; RV32-NEXT: vfirst.m a1, v9, v0.t +; RV32-NEXT: slti a1, a1, 0 +; RV32-NEXT: not a1, a1 ; RV32-NEXT: or a0, a1, a0 ; RV32-NEXT: slli a0, a0, 31 ; RV32-NEXT: srai a0, a0, 31 @@ -983,8 +1006,9 @@ ; RV64-NEXT: vmv1r.v v9, v0 ; RV64-NEXT: vsetvli zero, a1, e8, mf4, ta, ma ; RV64-NEXT: vmv1r.v v0, v8 -; RV64-NEXT: vcpop.m a1, v9, v0.t -; RV64-NEXT: snez a1, a1 +; RV64-NEXT: vfirst.m a1, v9, v0.t +; RV64-NEXT: slti a1, a1, 0 +; RV64-NEXT: not a1, a1 ; RV64-NEXT: or a0, a1, a0 ; RV64-NEXT: slli a0, a0, 63 ; RV64-NEXT: srai a0, a0, 63 @@ -1001,8 +1025,9 @@ ; RV32-NEXT: vmv1r.v v9, v0 ; RV32-NEXT: vsetvli zero, a1, e8, mf2, ta, ma ; RV32-NEXT: vmv1r.v v0, v8 -; RV32-NEXT: vcpop.m a1, v9, v0.t -; RV32-NEXT: snez a1, a1 +; RV32-NEXT: vfirst.m a1, v9, v0.t +; RV32-NEXT: slti a1, a1, 0 +; RV32-NEXT: not a1, a1 ; RV32-NEXT: or a0, a1, a0 ; RV32-NEXT: slli a0, a0, 31 ; RV32-NEXT: srai a0, a0, 31 @@ -1013,8 +1038,9 @@ ; RV64-NEXT: vmv1r.v v9, v0 ; RV64-NEXT: vsetvli zero, a1, e8, mf2, ta, ma ; RV64-NEXT: vmv1r.v v0, v8 -; RV64-NEXT: vcpop.m a1, v9, v0.t -; RV64-NEXT: snez a1, a1 +; RV64-NEXT: vfirst.m a1, v9, v0.t +; RV64-NEXT: slti a1, a1, 0 +; RV64-NEXT: not a1, a1 ; RV64-NEXT: or a0, a1, a0 ; RV64-NEXT: slli a0, a0, 63 ; RV64-NEXT: srai a0, a0, 63 @@ -1031,8 +1057,9 @@ ; RV32-NEXT: vmv1r.v v9, v0 ; RV32-NEXT: vsetvli zero, a1, e8, m1, ta, ma ; RV32-NEXT: vmv1r.v v0, v8 -; RV32-NEXT: vcpop.m a1, v9, v0.t -; RV32-NEXT: snez a1, a1 +; RV32-NEXT: vfirst.m a1, v9, v0.t +; RV32-NEXT: slti a1, a1, 0 +; RV32-NEXT: not a1, a1 ; RV32-NEXT: or a0, a1, a0 ; RV32-NEXT: slli a0, a0, 31 ; RV32-NEXT: srai a0, a0, 31 @@ -1043,8 +1070,9 @@ ; RV64-NEXT: vmv1r.v v9, v0 ; RV64-NEXT: vsetvli zero, a1, e8, m1, ta, ma ; RV64-NEXT: vmv1r.v v0, v8 -; RV64-NEXT: vcpop.m a1, v9, v0.t -; RV64-NEXT: snez a1, a1 +; RV64-NEXT: vfirst.m a1, v9, v0.t +; RV64-NEXT: slti a1, a1, 0 +; RV64-NEXT: not a1, a1 ; RV64-NEXT: or a0, a1, a0 ; RV64-NEXT: slli a0, a0, 63 ; RV64-NEXT: srai a0, a0, 63 @@ -1061,8 +1089,9 @@ ; RV32-NEXT: vmv1r.v v9, v0 ; RV32-NEXT: vsetvli zero, a1, e8, m2, ta, ma ; RV32-NEXT: vmv1r.v v0, v8 -; RV32-NEXT: vcpop.m a1, v9, v0.t -; RV32-NEXT: snez a1, a1 +; RV32-NEXT: vfirst.m a1, v9, v0.t +; RV32-NEXT: slti a1, a1, 0 +; RV32-NEXT: not a1, a1 ; RV32-NEXT: or a0, a1, a0 ; RV32-NEXT: slli a0, a0, 31 ; RV32-NEXT: srai a0, a0, 31 @@ -1073,8 +1102,9 @@ ; RV64-NEXT: vmv1r.v v9, v0 ; RV64-NEXT: vsetvli zero, a1, e8, m2, ta, ma ; RV64-NEXT: vmv1r.v v0, v8 -; RV64-NEXT: vcpop.m a1, v9, v0.t -; RV64-NEXT: snez a1, a1 +; RV64-NEXT: vfirst.m a1, v9, v0.t +; RV64-NEXT: slti a1, a1, 0 +; RV64-NEXT: not a1, a1 ; RV64-NEXT: or a0, a1, a0 ; RV64-NEXT: slli a0, a0, 63 ; RV64-NEXT: srai a0, a0, 63 @@ -1091,8 +1121,9 @@ ; RV32-NEXT: vmv1r.v v9, v0 ; RV32-NEXT: vsetvli zero, a1, e8, m4, ta, ma ; RV32-NEXT: vmv1r.v v0, v8 -; RV32-NEXT: vcpop.m a1, v9, v0.t -; RV32-NEXT: snez a1, a1 +; RV32-NEXT: vfirst.m a1, v9, v0.t +; RV32-NEXT: slti a1, a1, 0 +; RV32-NEXT: not a1, a1 ; RV32-NEXT: or a0, a1, a0 ; RV32-NEXT: slli a0, a0, 31 ; RV32-NEXT: srai a0, a0, 31 @@ -1103,8 +1134,9 @@ ; RV64-NEXT: vmv1r.v v9, v0 ; RV64-NEXT: vsetvli zero, a1, e8, m4, ta, ma ; RV64-NEXT: vmv1r.v v0, v8 -; RV64-NEXT: vcpop.m a1, v9, v0.t -; RV64-NEXT: snez a1, a1 +; RV64-NEXT: vfirst.m a1, v9, v0.t +; RV64-NEXT: slti a1, a1, 0 +; RV64-NEXT: not a1, a1 ; RV64-NEXT: or a0, a1, a0 ; RV64-NEXT: slli a0, a0, 63 ; RV64-NEXT: srai a0, a0, 63 @@ -1121,8 +1153,9 @@ ; RV32-NEXT: vmv1r.v v9, v0 ; RV32-NEXT: vsetvli zero, a1, e8, m8, ta, ma ; RV32-NEXT: vmv1r.v v0, v8 -; RV32-NEXT: vcpop.m a1, v9, v0.t -; RV32-NEXT: snez a1, a1 +; RV32-NEXT: vfirst.m a1, v9, v0.t +; RV32-NEXT: slti a1, a1, 0 +; RV32-NEXT: not a1, a1 ; RV32-NEXT: or a0, a1, a0 ; RV32-NEXT: slli a0, a0, 31 ; RV32-NEXT: srai a0, a0, 31 @@ -1133,8 +1166,9 @@ ; RV64-NEXT: vmv1r.v v9, v0 ; RV64-NEXT: vsetvli zero, a1, e8, m8, ta, ma ; RV64-NEXT: vmv1r.v v0, v8 -; RV64-NEXT: vcpop.m a1, v9, v0.t -; RV64-NEXT: snez a1, a1 +; RV64-NEXT: vfirst.m a1, v9, v0.t +; RV64-NEXT: slti a1, a1, 0 +; RV64-NEXT: not a1, a1 ; RV64-NEXT: or a0, a1, a0 ; RV64-NEXT: slli a0, a0, 63 ; RV64-NEXT: srai a0, a0, 63 @@ -1151,8 +1185,9 @@ ; RV32-NEXT: vmv1r.v v9, v0 ; RV32-NEXT: vsetvli zero, a1, e8, mf8, ta, ma ; RV32-NEXT: vmv1r.v v0, v8 -; RV32-NEXT: vcpop.m a1, v9, v0.t -; RV32-NEXT: snez a1, a1 +; RV32-NEXT: vfirst.m a1, v9, v0.t +; RV32-NEXT: slti a1, a1, 0 +; RV32-NEXT: not a1, a1 ; RV32-NEXT: or a0, a1, a0 ; RV32-NEXT: slli a0, a0, 31 ; RV32-NEXT: srai a0, a0, 31 @@ -1163,8 +1198,9 @@ ; RV64-NEXT: vmv1r.v v9, v0 ; RV64-NEXT: vsetvli zero, a1, e8, mf8, ta, ma ; RV64-NEXT: vmv1r.v v0, v8 -; RV64-NEXT: vcpop.m a1, v9, v0.t -; RV64-NEXT: snez a1, a1 +; RV64-NEXT: vfirst.m a1, v9, v0.t +; RV64-NEXT: slti a1, a1, 0 +; RV64-NEXT: not a1, a1 ; RV64-NEXT: or a0, a1, a0 ; RV64-NEXT: slli a0, a0, 63 ; RV64-NEXT: srai a0, a0, 63 @@ -1181,8 +1217,9 @@ ; RV32-NEXT: vmv1r.v v9, v0 ; RV32-NEXT: vsetvli zero, a1, e8, mf4, ta, ma ; RV32-NEXT: vmv1r.v v0, v8 -; RV32-NEXT: vcpop.m a1, v9, v0.t -; RV32-NEXT: snez a1, a1 +; RV32-NEXT: vfirst.m a1, v9, v0.t +; RV32-NEXT: slti a1, a1, 0 +; RV32-NEXT: not a1, a1 ; RV32-NEXT: or a0, a1, a0 ; RV32-NEXT: slli a0, a0, 31 ; RV32-NEXT: srai a0, a0, 31 @@ -1193,8 +1230,9 @@ ; RV64-NEXT: vmv1r.v v9, v0 ; RV64-NEXT: vsetvli zero, a1, e8, mf4, ta, ma ; RV64-NEXT: vmv1r.v v0, v8 -; RV64-NEXT: vcpop.m a1, v9, v0.t -; RV64-NEXT: snez a1, a1 +; RV64-NEXT: vfirst.m a1, v9, v0.t +; RV64-NEXT: slti a1, a1, 0 +; RV64-NEXT: not a1, a1 ; RV64-NEXT: or a0, a1, a0 ; RV64-NEXT: slli a0, a0, 63 ; RV64-NEXT: srai a0, a0, 63 @@ -1211,8 +1249,9 @@ ; RV32-NEXT: vmv1r.v v9, v0 ; RV32-NEXT: vsetvli zero, a1, e8, mf2, ta, ma ; RV32-NEXT: vmv1r.v v0, v8 -; RV32-NEXT: vcpop.m a1, v9, v0.t -; RV32-NEXT: snez a1, a1 +; RV32-NEXT: vfirst.m a1, v9, v0.t +; RV32-NEXT: slti a1, a1, 0 +; RV32-NEXT: not a1, a1 ; RV32-NEXT: or a0, a1, a0 ; RV32-NEXT: slli a0, a0, 31 ; RV32-NEXT: srai a0, a0, 31 @@ -1223,8 +1262,9 @@ ; RV64-NEXT: vmv1r.v v9, v0 ; RV64-NEXT: vsetvli zero, a1, e8, mf2, ta, ma ; RV64-NEXT: vmv1r.v v0, v8 -; RV64-NEXT: vcpop.m a1, v9, v0.t -; RV64-NEXT: snez a1, a1 +; RV64-NEXT: vfirst.m a1, v9, v0.t +; RV64-NEXT: slti a1, a1, 0 +; RV64-NEXT: not a1, a1 ; RV64-NEXT: or a0, a1, a0 ; RV64-NEXT: slli a0, a0, 63 ; RV64-NEXT: srai a0, a0, 63 @@ -1241,8 +1281,9 @@ ; RV32-NEXT: vmv1r.v v9, v0 ; RV32-NEXT: vsetvli zero, a1, e8, m1, ta, ma ; RV32-NEXT: vmv1r.v v0, v8 -; RV32-NEXT: vcpop.m a1, v9, v0.t -; RV32-NEXT: snez a1, a1 +; RV32-NEXT: vfirst.m a1, v9, v0.t +; RV32-NEXT: slti a1, a1, 0 +; RV32-NEXT: not a1, a1 ; RV32-NEXT: or a0, a1, a0 ; RV32-NEXT: slli a0, a0, 31 ; RV32-NEXT: srai a0, a0, 31 @@ -1253,8 +1294,9 @@ ; RV64-NEXT: vmv1r.v v9, v0 ; RV64-NEXT: vsetvli zero, a1, e8, m1, ta, ma ; RV64-NEXT: vmv1r.v v0, v8 -; RV64-NEXT: vcpop.m a1, v9, v0.t -; RV64-NEXT: snez a1, a1 +; RV64-NEXT: vfirst.m a1, v9, v0.t +; RV64-NEXT: slti a1, a1, 0 +; RV64-NEXT: not a1, a1 ; RV64-NEXT: or a0, a1, a0 ; RV64-NEXT: slli a0, a0, 63 ; RV64-NEXT: srai a0, a0, 63 @@ -1271,8 +1313,9 @@ ; RV32-NEXT: vmv1r.v v9, v0 ; RV32-NEXT: vsetvli zero, a1, e8, m2, ta, ma ; RV32-NEXT: vmv1r.v v0, v8 -; RV32-NEXT: vcpop.m a1, v9, v0.t -; RV32-NEXT: snez a1, a1 +; RV32-NEXT: vfirst.m a1, v9, v0.t +; RV32-NEXT: slti a1, a1, 0 +; RV32-NEXT: not a1, a1 ; RV32-NEXT: or a0, a1, a0 ; RV32-NEXT: slli a0, a0, 31 ; RV32-NEXT: srai a0, a0, 31 @@ -1283,8 +1326,9 @@ ; RV64-NEXT: vmv1r.v v9, v0 ; RV64-NEXT: vsetvli zero, a1, e8, m2, ta, ma ; RV64-NEXT: vmv1r.v v0, v8 -; RV64-NEXT: vcpop.m a1, v9, v0.t -; RV64-NEXT: snez a1, a1 +; RV64-NEXT: vfirst.m a1, v9, v0.t +; RV64-NEXT: slti a1, a1, 0 +; RV64-NEXT: not a1, a1 ; RV64-NEXT: or a0, a1, a0 ; RV64-NEXT: slli a0, a0, 63 ; RV64-NEXT: srai a0, a0, 63 @@ -1301,8 +1345,9 @@ ; RV32-NEXT: vmv1r.v v9, v0 ; RV32-NEXT: vsetvli zero, a1, e8, m4, ta, ma ; RV32-NEXT: vmv1r.v v0, v8 -; RV32-NEXT: vcpop.m a1, v9, v0.t -; RV32-NEXT: snez a1, a1 +; RV32-NEXT: vfirst.m a1, v9, v0.t +; RV32-NEXT: slti a1, a1, 0 +; RV32-NEXT: not a1, a1 ; RV32-NEXT: or a0, a1, a0 ; RV32-NEXT: slli a0, a0, 31 ; RV32-NEXT: srai a0, a0, 31 @@ -1313,8 +1358,9 @@ ; RV64-NEXT: vmv1r.v v9, v0 ; RV64-NEXT: vsetvli zero, a1, e8, m4, ta, ma ; RV64-NEXT: vmv1r.v v0, v8 -; RV64-NEXT: vcpop.m a1, v9, v0.t -; RV64-NEXT: snez a1, a1 +; RV64-NEXT: vfirst.m a1, v9, v0.t +; RV64-NEXT: slti a1, a1, 0 +; RV64-NEXT: not a1, a1 ; RV64-NEXT: or a0, a1, a0 ; RV64-NEXT: slli a0, a0, 63 ; RV64-NEXT: srai a0, a0, 63 @@ -1331,8 +1377,9 @@ ; RV32-NEXT: vmv1r.v v9, v0 ; RV32-NEXT: vsetvli zero, a1, e8, m8, ta, ma ; RV32-NEXT: vmv1r.v v0, v8 -; RV32-NEXT: vcpop.m a1, v9, v0.t -; RV32-NEXT: snez a1, a1 +; RV32-NEXT: vfirst.m a1, v9, v0.t +; RV32-NEXT: slti a1, a1, 0 +; RV32-NEXT: not a1, a1 ; RV32-NEXT: or a0, a1, a0 ; RV32-NEXT: slli a0, a0, 31 ; RV32-NEXT: srai a0, a0, 31 @@ -1343,8 +1390,9 @@ ; RV64-NEXT: vmv1r.v v9, v0 ; RV64-NEXT: vsetvli zero, a1, e8, m8, ta, ma ; RV64-NEXT: vmv1r.v v0, v8 -; RV64-NEXT: vcpop.m a1, v9, v0.t -; RV64-NEXT: snez a1, a1 +; RV64-NEXT: vfirst.m a1, v9, v0.t +; RV64-NEXT: slti a1, a1, 0 +; RV64-NEXT: not a1, a1 ; RV64-NEXT: or a0, a1, a0 ; RV64-NEXT: slli a0, a0, 63 ; RV64-NEXT: srai a0, a0, 63 @@ -1361,8 +1409,8 @@ ; CHECK-NEXT: vsetvli zero, a1, e8, mf8, ta, ma ; CHECK-NEXT: vmnot.m v9, v0 ; CHECK-NEXT: vmv1r.v v0, v8 -; CHECK-NEXT: vcpop.m a1, v9, v0.t -; CHECK-NEXT: seqz a1, a1 +; CHECK-NEXT: vfirst.m a1, v9, v0.t +; CHECK-NEXT: slti a1, a1, 0 ; CHECK-NEXT: and a0, a1, a0 ; CHECK-NEXT: neg a0, a0 ; CHECK-NEXT: ret @@ -1378,8 +1426,8 @@ ; CHECK-NEXT: vsetvli zero, a1, e8, mf4, ta, ma ; CHECK-NEXT: vmnot.m v9, v0 ; CHECK-NEXT: vmv1r.v v0, v8 -; CHECK-NEXT: vcpop.m a1, v9, v0.t -; CHECK-NEXT: seqz a1, a1 +; CHECK-NEXT: vfirst.m a1, v9, v0.t +; CHECK-NEXT: slti a1, a1, 0 ; CHECK-NEXT: and a0, a1, a0 ; CHECK-NEXT: neg a0, a0 ; CHECK-NEXT: ret @@ -1395,8 +1443,8 @@ ; CHECK-NEXT: vsetvli zero, a1, e8, mf2, ta, ma ; CHECK-NEXT: vmnot.m v9, v0 ; CHECK-NEXT: vmv1r.v v0, v8 -; CHECK-NEXT: vcpop.m a1, v9, v0.t -; CHECK-NEXT: seqz a1, a1 +; CHECK-NEXT: vfirst.m a1, v9, v0.t +; CHECK-NEXT: slti a1, a1, 0 ; CHECK-NEXT: and a0, a1, a0 ; CHECK-NEXT: neg a0, a0 ; CHECK-NEXT: ret @@ -1412,8 +1460,8 @@ ; CHECK-NEXT: vsetvli zero, a1, e8, m1, ta, ma ; CHECK-NEXT: vmnot.m v9, v0 ; CHECK-NEXT: vmv1r.v v0, v8 -; CHECK-NEXT: vcpop.m a1, v9, v0.t -; CHECK-NEXT: seqz a1, a1 +; CHECK-NEXT: vfirst.m a1, v9, v0.t +; CHECK-NEXT: slti a1, a1, 0 ; CHECK-NEXT: and a0, a1, a0 ; CHECK-NEXT: neg a0, a0 ; CHECK-NEXT: ret @@ -1429,8 +1477,8 @@ ; CHECK-NEXT: vsetvli zero, a1, e8, m2, ta, ma ; CHECK-NEXT: vmnot.m v9, v0 ; CHECK-NEXT: vmv1r.v v0, v8 -; CHECK-NEXT: vcpop.m a1, v9, v0.t -; CHECK-NEXT: seqz a1, a1 +; CHECK-NEXT: vfirst.m a1, v9, v0.t +; CHECK-NEXT: slti a1, a1, 0 ; CHECK-NEXT: and a0, a1, a0 ; CHECK-NEXT: neg a0, a0 ; CHECK-NEXT: ret @@ -1446,8 +1494,8 @@ ; CHECK-NEXT: vsetvli zero, a1, e8, m4, ta, ma ; CHECK-NEXT: vmnot.m v9, v0 ; CHECK-NEXT: vmv1r.v v0, v8 -; CHECK-NEXT: vcpop.m a1, v9, v0.t -; CHECK-NEXT: seqz a1, a1 +; CHECK-NEXT: vfirst.m a1, v9, v0.t +; CHECK-NEXT: slti a1, a1, 0 ; CHECK-NEXT: and a0, a1, a0 ; CHECK-NEXT: neg a0, a0 ; CHECK-NEXT: ret @@ -1463,8 +1511,8 @@ ; CHECK-NEXT: vsetvli zero, a1, e8, m8, ta, ma ; CHECK-NEXT: vmnot.m v9, v0 ; CHECK-NEXT: vmv1r.v v0, v8 -; CHECK-NEXT: vcpop.m a1, v9, v0.t -; CHECK-NEXT: seqz a1, a1 +; CHECK-NEXT: vfirst.m a1, v9, v0.t +; CHECK-NEXT: slti a1, a1, 0 ; CHECK-NEXT: and a0, a1, a0 ; CHECK-NEXT: neg a0, a0 ; CHECK-NEXT: ret @@ -1480,8 +1528,8 @@ ; CHECK-NEXT: vsetvli zero, a1, e8, mf8, ta, ma ; CHECK-NEXT: vmnot.m v9, v0 ; CHECK-NEXT: vmv1r.v v0, v8 -; CHECK-NEXT: vcpop.m a1, v9, v0.t -; CHECK-NEXT: seqz a1, a1 +; CHECK-NEXT: vfirst.m a1, v9, v0.t +; CHECK-NEXT: slti a1, a1, 0 ; CHECK-NEXT: and a0, a1, a0 ; CHECK-NEXT: neg a0, a0 ; CHECK-NEXT: ret @@ -1497,8 +1545,8 @@ ; CHECK-NEXT: vsetvli zero, a1, e8, mf4, ta, ma ; CHECK-NEXT: vmnot.m v9, v0 ; CHECK-NEXT: vmv1r.v v0, v8 -; CHECK-NEXT: vcpop.m a1, v9, v0.t -; CHECK-NEXT: seqz a1, a1 +; CHECK-NEXT: vfirst.m a1, v9, v0.t +; CHECK-NEXT: slti a1, a1, 0 ; CHECK-NEXT: and a0, a1, a0 ; CHECK-NEXT: neg a0, a0 ; CHECK-NEXT: ret @@ -1514,8 +1562,8 @@ ; CHECK-NEXT: vsetvli zero, a1, e8, mf2, ta, ma ; CHECK-NEXT: vmnot.m v9, v0 ; CHECK-NEXT: vmv1r.v v0, v8 -; CHECK-NEXT: vcpop.m a1, v9, v0.t -; CHECK-NEXT: seqz a1, a1 +; CHECK-NEXT: vfirst.m a1, v9, v0.t +; CHECK-NEXT: slti a1, a1, 0 ; CHECK-NEXT: and a0, a1, a0 ; CHECK-NEXT: neg a0, a0 ; CHECK-NEXT: ret @@ -1531,8 +1579,8 @@ ; CHECK-NEXT: vsetvli zero, a1, e8, m1, ta, ma ; CHECK-NEXT: vmnot.m v9, v0 ; CHECK-NEXT: vmv1r.v v0, v8 -; CHECK-NEXT: vcpop.m a1, v9, v0.t -; CHECK-NEXT: seqz a1, a1 +; CHECK-NEXT: vfirst.m a1, v9, v0.t +; CHECK-NEXT: slti a1, a1, 0 ; CHECK-NEXT: and a0, a1, a0 ; CHECK-NEXT: neg a0, a0 ; CHECK-NEXT: ret @@ -1548,8 +1596,8 @@ ; CHECK-NEXT: vsetvli zero, a1, e8, m2, ta, ma ; CHECK-NEXT: vmnot.m v9, v0 ; CHECK-NEXT: vmv1r.v v0, v8 -; CHECK-NEXT: vcpop.m a1, v9, v0.t -; CHECK-NEXT: seqz a1, a1 +; CHECK-NEXT: vfirst.m a1, v9, v0.t +; CHECK-NEXT: slti a1, a1, 0 ; CHECK-NEXT: and a0, a1, a0 ; CHECK-NEXT: neg a0, a0 ; CHECK-NEXT: ret @@ -1565,8 +1613,8 @@ ; CHECK-NEXT: vsetvli zero, a1, e8, m4, ta, ma ; CHECK-NEXT: vmnot.m v9, v0 ; CHECK-NEXT: vmv1r.v v0, v8 -; CHECK-NEXT: vcpop.m a1, v9, v0.t -; CHECK-NEXT: seqz a1, a1 +; CHECK-NEXT: vfirst.m a1, v9, v0.t +; CHECK-NEXT: slti a1, a1, 0 ; CHECK-NEXT: and a0, a1, a0 ; CHECK-NEXT: neg a0, a0 ; CHECK-NEXT: ret @@ -1582,8 +1630,8 @@ ; CHECK-NEXT: vsetvli zero, a1, e8, m8, ta, ma ; CHECK-NEXT: vmnot.m v9, v0 ; CHECK-NEXT: vmv1r.v v0, v8 -; CHECK-NEXT: vcpop.m a1, v9, v0.t -; CHECK-NEXT: seqz a1, a1 +; CHECK-NEXT: vfirst.m a1, v9, v0.t +; CHECK-NEXT: slti a1, a1, 0 ; CHECK-NEXT: and a0, a1, a0 ; CHECK-NEXT: neg a0, a0 ; CHECK-NEXT: ret diff --git a/llvm/test/CodeGen/RISCV/rvv/vreductions-mask.ll b/llvm/test/CodeGen/RISCV/rvv/vreductions-mask.ll --- a/llvm/test/CodeGen/RISCV/rvv/vreductions-mask.ll +++ b/llvm/test/CodeGen/RISCV/rvv/vreductions-mask.ll @@ -8,8 +8,8 @@ ; CHECK-LABEL: vreduce_or_nxv1i1: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a0, zero, e8, mf8, ta, ma -; CHECK-NEXT: vcpop.m a0, v0 -; CHECK-NEXT: seqz a0, a0 +; CHECK-NEXT: vfirst.m a0, v0 +; CHECK-NEXT: slti a0, a0, 0 ; CHECK-NEXT: addi a0, a0, -1 ; CHECK-NEXT: ret %red = call i1 @llvm.vector.reduce.or.nxv1i1( %v) @@ -30,9 +30,9 @@ ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a0, zero, e8, mf8, ta, ma ; CHECK-NEXT: vmnot.m v8, v0 -; CHECK-NEXT: vcpop.m a0, v8 -; CHECK-NEXT: snez a0, a0 -; CHECK-NEXT: addi a0, a0, -1 +; CHECK-NEXT: vfirst.m a0, v8 +; CHECK-NEXT: slti a0, a0, 0 +; CHECK-NEXT: neg a0, a0 ; CHECK-NEXT: ret %red = call i1 @llvm.vector.reduce.and.nxv1i1( %v) ret i1 %red @@ -44,8 +44,8 @@ ; CHECK-LABEL: vreduce_umax_nxv1i1: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a0, zero, e8, mf8, ta, ma -; CHECK-NEXT: vcpop.m a0, v0 -; CHECK-NEXT: seqz a0, a0 +; CHECK-NEXT: vfirst.m a0, v0 +; CHECK-NEXT: slti a0, a0, 0 ; CHECK-NEXT: addi a0, a0, -1 ; CHECK-NEXT: ret %red = call i1 @llvm.vector.reduce.umax.nxv1i1( %v) @@ -59,9 +59,9 @@ ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a0, zero, e8, mf8, ta, ma ; CHECK-NEXT: vmnot.m v8, v0 -; CHECK-NEXT: vcpop.m a0, v8 -; CHECK-NEXT: snez a0, a0 -; CHECK-NEXT: addi a0, a0, -1 +; CHECK-NEXT: vfirst.m a0, v8 +; CHECK-NEXT: slti a0, a0, 0 +; CHECK-NEXT: neg a0, a0 ; CHECK-NEXT: ret %red = call i1 @llvm.vector.reduce.smax.nxv1i1( %v) ret i1 %red @@ -74,9 +74,9 @@ ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a0, zero, e8, mf8, ta, ma ; CHECK-NEXT: vmnot.m v8, v0 -; CHECK-NEXT: vcpop.m a0, v8 -; CHECK-NEXT: snez a0, a0 -; CHECK-NEXT: addi a0, a0, -1 +; CHECK-NEXT: vfirst.m a0, v8 +; CHECK-NEXT: slti a0, a0, 0 +; CHECK-NEXT: neg a0, a0 ; CHECK-NEXT: ret %red = call i1 @llvm.vector.reduce.umin.nxv1i1( %v) ret i1 %red @@ -88,8 +88,8 @@ ; CHECK-LABEL: vreduce_smin_nxv1i1: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a0, zero, e8, mf8, ta, ma -; CHECK-NEXT: vcpop.m a0, v0 -; CHECK-NEXT: seqz a0, a0 +; CHECK-NEXT: vfirst.m a0, v0 +; CHECK-NEXT: slti a0, a0, 0 ; CHECK-NEXT: addi a0, a0, -1 ; CHECK-NEXT: ret %red = call i1 @llvm.vector.reduce.smin.nxv1i1( %v) @@ -102,8 +102,8 @@ ; CHECK-LABEL: vreduce_or_nxv2i1: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a0, zero, e8, mf4, ta, ma -; CHECK-NEXT: vcpop.m a0, v0 -; CHECK-NEXT: seqz a0, a0 +; CHECK-NEXT: vfirst.m a0, v0 +; CHECK-NEXT: slti a0, a0, 0 ; CHECK-NEXT: addi a0, a0, -1 ; CHECK-NEXT: ret %red = call i1 @llvm.vector.reduce.or.nxv2i1( %v) @@ -124,9 +124,9 @@ ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a0, zero, e8, mf4, ta, ma ; CHECK-NEXT: vmnot.m v8, v0 -; CHECK-NEXT: vcpop.m a0, v8 -; CHECK-NEXT: snez a0, a0 -; CHECK-NEXT: addi a0, a0, -1 +; CHECK-NEXT: vfirst.m a0, v8 +; CHECK-NEXT: slti a0, a0, 0 +; CHECK-NEXT: neg a0, a0 ; CHECK-NEXT: ret %red = call i1 @llvm.vector.reduce.and.nxv2i1( %v) ret i1 %red @@ -138,8 +138,8 @@ ; CHECK-LABEL: vreduce_umax_nxv2i1: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a0, zero, e8, mf4, ta, ma -; CHECK-NEXT: vcpop.m a0, v0 -; CHECK-NEXT: seqz a0, a0 +; CHECK-NEXT: vfirst.m a0, v0 +; CHECK-NEXT: slti a0, a0, 0 ; CHECK-NEXT: addi a0, a0, -1 ; CHECK-NEXT: ret %red = call i1 @llvm.vector.reduce.umax.nxv2i1( %v) @@ -153,9 +153,9 @@ ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a0, zero, e8, mf4, ta, ma ; CHECK-NEXT: vmnot.m v8, v0 -; CHECK-NEXT: vcpop.m a0, v8 -; CHECK-NEXT: snez a0, a0 -; CHECK-NEXT: addi a0, a0, -1 +; CHECK-NEXT: vfirst.m a0, v8 +; CHECK-NEXT: slti a0, a0, 0 +; CHECK-NEXT: neg a0, a0 ; CHECK-NEXT: ret %red = call i1 @llvm.vector.reduce.smax.nxv2i1( %v) ret i1 %red @@ -168,9 +168,9 @@ ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a0, zero, e8, mf4, ta, ma ; CHECK-NEXT: vmnot.m v8, v0 -; CHECK-NEXT: vcpop.m a0, v8 -; CHECK-NEXT: snez a0, a0 -; CHECK-NEXT: addi a0, a0, -1 +; CHECK-NEXT: vfirst.m a0, v8 +; CHECK-NEXT: slti a0, a0, 0 +; CHECK-NEXT: neg a0, a0 ; CHECK-NEXT: ret %red = call i1 @llvm.vector.reduce.umin.nxv2i1( %v) ret i1 %red @@ -182,8 +182,8 @@ ; CHECK-LABEL: vreduce_smin_nxv2i1: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a0, zero, e8, mf4, ta, ma -; CHECK-NEXT: vcpop.m a0, v0 -; CHECK-NEXT: seqz a0, a0 +; CHECK-NEXT: vfirst.m a0, v0 +; CHECK-NEXT: slti a0, a0, 0 ; CHECK-NEXT: addi a0, a0, -1 ; CHECK-NEXT: ret %red = call i1 @llvm.vector.reduce.smin.nxv2i1( %v) @@ -196,8 +196,8 @@ ; CHECK-LABEL: vreduce_or_nxv4i1: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a0, zero, e8, mf2, ta, ma -; CHECK-NEXT: vcpop.m a0, v0 -; CHECK-NEXT: seqz a0, a0 +; CHECK-NEXT: vfirst.m a0, v0 +; CHECK-NEXT: slti a0, a0, 0 ; CHECK-NEXT: addi a0, a0, -1 ; CHECK-NEXT: ret %red = call i1 @llvm.vector.reduce.or.nxv4i1( %v) @@ -218,9 +218,9 @@ ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a0, zero, e8, mf2, ta, ma ; CHECK-NEXT: vmnot.m v8, v0 -; CHECK-NEXT: vcpop.m a0, v8 -; CHECK-NEXT: snez a0, a0 -; CHECK-NEXT: addi a0, a0, -1 +; CHECK-NEXT: vfirst.m a0, v8 +; CHECK-NEXT: slti a0, a0, 0 +; CHECK-NEXT: neg a0, a0 ; CHECK-NEXT: ret %red = call i1 @llvm.vector.reduce.and.nxv4i1( %v) ret i1 %red @@ -232,8 +232,8 @@ ; CHECK-LABEL: vreduce_umax_nxv4i1: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a0, zero, e8, mf2, ta, ma -; CHECK-NEXT: vcpop.m a0, v0 -; CHECK-NEXT: seqz a0, a0 +; CHECK-NEXT: vfirst.m a0, v0 +; CHECK-NEXT: slti a0, a0, 0 ; CHECK-NEXT: addi a0, a0, -1 ; CHECK-NEXT: ret %red = call i1 @llvm.vector.reduce.umax.nxv4i1( %v) @@ -247,9 +247,9 @@ ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a0, zero, e8, mf2, ta, ma ; CHECK-NEXT: vmnot.m v8, v0 -; CHECK-NEXT: vcpop.m a0, v8 -; CHECK-NEXT: snez a0, a0 -; CHECK-NEXT: addi a0, a0, -1 +; CHECK-NEXT: vfirst.m a0, v8 +; CHECK-NEXT: slti a0, a0, 0 +; CHECK-NEXT: neg a0, a0 ; CHECK-NEXT: ret %red = call i1 @llvm.vector.reduce.smax.nxv4i1( %v) ret i1 %red @@ -262,9 +262,9 @@ ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a0, zero, e8, mf2, ta, ma ; CHECK-NEXT: vmnot.m v8, v0 -; CHECK-NEXT: vcpop.m a0, v8 -; CHECK-NEXT: snez a0, a0 -; CHECK-NEXT: addi a0, a0, -1 +; CHECK-NEXT: vfirst.m a0, v8 +; CHECK-NEXT: slti a0, a0, 0 +; CHECK-NEXT: neg a0, a0 ; CHECK-NEXT: ret %red = call i1 @llvm.vector.reduce.umin.nxv4i1( %v) ret i1 %red @@ -276,8 +276,8 @@ ; CHECK-LABEL: vreduce_smin_nxv4i1: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a0, zero, e8, mf2, ta, ma -; CHECK-NEXT: vcpop.m a0, v0 -; CHECK-NEXT: seqz a0, a0 +; CHECK-NEXT: vfirst.m a0, v0 +; CHECK-NEXT: slti a0, a0, 0 ; CHECK-NEXT: addi a0, a0, -1 ; CHECK-NEXT: ret %red = call i1 @llvm.vector.reduce.smin.nxv4i1( %v) @@ -290,8 +290,8 @@ ; CHECK-LABEL: vreduce_or_nxv8i1: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a0, zero, e8, m1, ta, ma -; CHECK-NEXT: vcpop.m a0, v0 -; CHECK-NEXT: seqz a0, a0 +; CHECK-NEXT: vfirst.m a0, v0 +; CHECK-NEXT: slti a0, a0, 0 ; CHECK-NEXT: addi a0, a0, -1 ; CHECK-NEXT: ret %red = call i1 @llvm.vector.reduce.or.nxv8i1( %v) @@ -312,9 +312,9 @@ ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a0, zero, e8, m1, ta, ma ; CHECK-NEXT: vmnot.m v8, v0 -; CHECK-NEXT: vcpop.m a0, v8 -; CHECK-NEXT: snez a0, a0 -; CHECK-NEXT: addi a0, a0, -1 +; CHECK-NEXT: vfirst.m a0, v8 +; CHECK-NEXT: slti a0, a0, 0 +; CHECK-NEXT: neg a0, a0 ; CHECK-NEXT: ret %red = call i1 @llvm.vector.reduce.and.nxv8i1( %v) ret i1 %red @@ -326,8 +326,8 @@ ; CHECK-LABEL: vreduce_umax_nxv8i1: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a0, zero, e8, m1, ta, ma -; CHECK-NEXT: vcpop.m a0, v0 -; CHECK-NEXT: seqz a0, a0 +; CHECK-NEXT: vfirst.m a0, v0 +; CHECK-NEXT: slti a0, a0, 0 ; CHECK-NEXT: addi a0, a0, -1 ; CHECK-NEXT: ret %red = call i1 @llvm.vector.reduce.umax.nxv8i1( %v) @@ -341,9 +341,9 @@ ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a0, zero, e8, m1, ta, ma ; CHECK-NEXT: vmnot.m v8, v0 -; CHECK-NEXT: vcpop.m a0, v8 -; CHECK-NEXT: snez a0, a0 -; CHECK-NEXT: addi a0, a0, -1 +; CHECK-NEXT: vfirst.m a0, v8 +; CHECK-NEXT: slti a0, a0, 0 +; CHECK-NEXT: neg a0, a0 ; CHECK-NEXT: ret %red = call i1 @llvm.vector.reduce.smax.nxv8i1( %v) ret i1 %red @@ -356,9 +356,9 @@ ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a0, zero, e8, m1, ta, ma ; CHECK-NEXT: vmnot.m v8, v0 -; CHECK-NEXT: vcpop.m a0, v8 -; CHECK-NEXT: snez a0, a0 -; CHECK-NEXT: addi a0, a0, -1 +; CHECK-NEXT: vfirst.m a0, v8 +; CHECK-NEXT: slti a0, a0, 0 +; CHECK-NEXT: neg a0, a0 ; CHECK-NEXT: ret %red = call i1 @llvm.vector.reduce.umin.nxv8i1( %v) ret i1 %red @@ -370,8 +370,8 @@ ; CHECK-LABEL: vreduce_smin_nxv8i1: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a0, zero, e8, m1, ta, ma -; CHECK-NEXT: vcpop.m a0, v0 -; CHECK-NEXT: seqz a0, a0 +; CHECK-NEXT: vfirst.m a0, v0 +; CHECK-NEXT: slti a0, a0, 0 ; CHECK-NEXT: addi a0, a0, -1 ; CHECK-NEXT: ret %red = call i1 @llvm.vector.reduce.smin.nxv8i1( %v) @@ -384,8 +384,8 @@ ; CHECK-LABEL: vreduce_or_nxv16i1: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a0, zero, e8, m2, ta, ma -; CHECK-NEXT: vcpop.m a0, v0 -; CHECK-NEXT: seqz a0, a0 +; CHECK-NEXT: vfirst.m a0, v0 +; CHECK-NEXT: slti a0, a0, 0 ; CHECK-NEXT: addi a0, a0, -1 ; CHECK-NEXT: ret %red = call i1 @llvm.vector.reduce.or.nxv16i1( %v) @@ -406,9 +406,9 @@ ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a0, zero, e8, m2, ta, ma ; CHECK-NEXT: vmnot.m v8, v0 -; CHECK-NEXT: vcpop.m a0, v8 -; CHECK-NEXT: snez a0, a0 -; CHECK-NEXT: addi a0, a0, -1 +; CHECK-NEXT: vfirst.m a0, v8 +; CHECK-NEXT: slti a0, a0, 0 +; CHECK-NEXT: neg a0, a0 ; CHECK-NEXT: ret %red = call i1 @llvm.vector.reduce.and.nxv16i1( %v) ret i1 %red @@ -420,8 +420,8 @@ ; CHECK-LABEL: vreduce_umax_nxv16i1: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a0, zero, e8, m2, ta, ma -; CHECK-NEXT: vcpop.m a0, v0 -; CHECK-NEXT: seqz a0, a0 +; CHECK-NEXT: vfirst.m a0, v0 +; CHECK-NEXT: slti a0, a0, 0 ; CHECK-NEXT: addi a0, a0, -1 ; CHECK-NEXT: ret %red = call i1 @llvm.vector.reduce.umax.nxv16i1( %v) @@ -435,9 +435,9 @@ ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a0, zero, e8, m2, ta, ma ; CHECK-NEXT: vmnot.m v8, v0 -; CHECK-NEXT: vcpop.m a0, v8 -; CHECK-NEXT: snez a0, a0 -; CHECK-NEXT: addi a0, a0, -1 +; CHECK-NEXT: vfirst.m a0, v8 +; CHECK-NEXT: slti a0, a0, 0 +; CHECK-NEXT: neg a0, a0 ; CHECK-NEXT: ret %red = call i1 @llvm.vector.reduce.smax.nxv16i1( %v) ret i1 %red @@ -450,9 +450,9 @@ ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a0, zero, e8, m2, ta, ma ; CHECK-NEXT: vmnot.m v8, v0 -; CHECK-NEXT: vcpop.m a0, v8 -; CHECK-NEXT: snez a0, a0 -; CHECK-NEXT: addi a0, a0, -1 +; CHECK-NEXT: vfirst.m a0, v8 +; CHECK-NEXT: slti a0, a0, 0 +; CHECK-NEXT: neg a0, a0 ; CHECK-NEXT: ret %red = call i1 @llvm.vector.reduce.umin.nxv16i1( %v) ret i1 %red @@ -464,8 +464,8 @@ ; CHECK-LABEL: vreduce_smin_nxv16i1: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a0, zero, e8, m2, ta, ma -; CHECK-NEXT: vcpop.m a0, v0 -; CHECK-NEXT: seqz a0, a0 +; CHECK-NEXT: vfirst.m a0, v0 +; CHECK-NEXT: slti a0, a0, 0 ; CHECK-NEXT: addi a0, a0, -1 ; CHECK-NEXT: ret %red = call i1 @llvm.vector.reduce.smin.nxv16i1( %v) @@ -478,8 +478,8 @@ ; CHECK-LABEL: vreduce_or_nxv32i1: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a0, zero, e8, m4, ta, ma -; CHECK-NEXT: vcpop.m a0, v0 -; CHECK-NEXT: seqz a0, a0 +; CHECK-NEXT: vfirst.m a0, v0 +; CHECK-NEXT: slti a0, a0, 0 ; CHECK-NEXT: addi a0, a0, -1 ; CHECK-NEXT: ret %red = call i1 @llvm.vector.reduce.or.nxv32i1( %v) @@ -500,9 +500,9 @@ ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a0, zero, e8, m4, ta, ma ; CHECK-NEXT: vmnot.m v8, v0 -; CHECK-NEXT: vcpop.m a0, v8 -; CHECK-NEXT: snez a0, a0 -; CHECK-NEXT: addi a0, a0, -1 +; CHECK-NEXT: vfirst.m a0, v8 +; CHECK-NEXT: slti a0, a0, 0 +; CHECK-NEXT: neg a0, a0 ; CHECK-NEXT: ret %red = call i1 @llvm.vector.reduce.and.nxv32i1( %v) ret i1 %red @@ -514,8 +514,8 @@ ; CHECK-LABEL: vreduce_umax_nxv32i1: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a0, zero, e8, m4, ta, ma -; CHECK-NEXT: vcpop.m a0, v0 -; CHECK-NEXT: seqz a0, a0 +; CHECK-NEXT: vfirst.m a0, v0 +; CHECK-NEXT: slti a0, a0, 0 ; CHECK-NEXT: addi a0, a0, -1 ; CHECK-NEXT: ret %red = call i1 @llvm.vector.reduce.umax.nxv32i1( %v) @@ -529,9 +529,9 @@ ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a0, zero, e8, m4, ta, ma ; CHECK-NEXT: vmnot.m v8, v0 -; CHECK-NEXT: vcpop.m a0, v8 -; CHECK-NEXT: snez a0, a0 -; CHECK-NEXT: addi a0, a0, -1 +; CHECK-NEXT: vfirst.m a0, v8 +; CHECK-NEXT: slti a0, a0, 0 +; CHECK-NEXT: neg a0, a0 ; CHECK-NEXT: ret %red = call i1 @llvm.vector.reduce.smax.nxv32i1( %v) ret i1 %red @@ -544,9 +544,9 @@ ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a0, zero, e8, m4, ta, ma ; CHECK-NEXT: vmnot.m v8, v0 -; CHECK-NEXT: vcpop.m a0, v8 -; CHECK-NEXT: snez a0, a0 -; CHECK-NEXT: addi a0, a0, -1 +; CHECK-NEXT: vfirst.m a0, v8 +; CHECK-NEXT: slti a0, a0, 0 +; CHECK-NEXT: neg a0, a0 ; CHECK-NEXT: ret %red = call i1 @llvm.vector.reduce.umin.nxv32i1( %v) ret i1 %red @@ -558,8 +558,8 @@ ; CHECK-LABEL: vreduce_smin_nxv32i1: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a0, zero, e8, m4, ta, ma -; CHECK-NEXT: vcpop.m a0, v0 -; CHECK-NEXT: seqz a0, a0 +; CHECK-NEXT: vfirst.m a0, v0 +; CHECK-NEXT: slti a0, a0, 0 ; CHECK-NEXT: addi a0, a0, -1 ; CHECK-NEXT: ret %red = call i1 @llvm.vector.reduce.smin.nxv32i1( %v) @@ -572,8 +572,8 @@ ; CHECK-LABEL: vreduce_or_nxv64i1: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a0, zero, e8, m8, ta, ma -; CHECK-NEXT: vcpop.m a0, v0 -; CHECK-NEXT: seqz a0, a0 +; CHECK-NEXT: vfirst.m a0, v0 +; CHECK-NEXT: slti a0, a0, 0 ; CHECK-NEXT: addi a0, a0, -1 ; CHECK-NEXT: ret %red = call i1 @llvm.vector.reduce.or.nxv64i1( %v) @@ -594,9 +594,9 @@ ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a0, zero, e8, m8, ta, ma ; CHECK-NEXT: vmnot.m v8, v0 -; CHECK-NEXT: vcpop.m a0, v8 -; CHECK-NEXT: snez a0, a0 -; CHECK-NEXT: addi a0, a0, -1 +; CHECK-NEXT: vfirst.m a0, v8 +; CHECK-NEXT: slti a0, a0, 0 +; CHECK-NEXT: neg a0, a0 ; CHECK-NEXT: ret %red = call i1 @llvm.vector.reduce.and.nxv64i1( %v) ret i1 %red @@ -608,8 +608,8 @@ ; CHECK-LABEL: vreduce_umax_nxv64i1: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a0, zero, e8, m8, ta, ma -; CHECK-NEXT: vcpop.m a0, v0 -; CHECK-NEXT: seqz a0, a0 +; CHECK-NEXT: vfirst.m a0, v0 +; CHECK-NEXT: slti a0, a0, 0 ; CHECK-NEXT: addi a0, a0, -1 ; CHECK-NEXT: ret %red = call i1 @llvm.vector.reduce.umax.nxv64i1( %v) @@ -623,9 +623,9 @@ ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a0, zero, e8, m8, ta, ma ; CHECK-NEXT: vmnot.m v8, v0 -; CHECK-NEXT: vcpop.m a0, v8 -; CHECK-NEXT: snez a0, a0 -; CHECK-NEXT: addi a0, a0, -1 +; CHECK-NEXT: vfirst.m a0, v8 +; CHECK-NEXT: slti a0, a0, 0 +; CHECK-NEXT: neg a0, a0 ; CHECK-NEXT: ret %red = call i1 @llvm.vector.reduce.smax.nxv64i1( %v) ret i1 %red @@ -638,9 +638,9 @@ ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a0, zero, e8, m8, ta, ma ; CHECK-NEXT: vmnot.m v8, v0 -; CHECK-NEXT: vcpop.m a0, v8 -; CHECK-NEXT: snez a0, a0 -; CHECK-NEXT: addi a0, a0, -1 +; CHECK-NEXT: vfirst.m a0, v8 +; CHECK-NEXT: slti a0, a0, 0 +; CHECK-NEXT: neg a0, a0 ; CHECK-NEXT: ret %red = call i1 @llvm.vector.reduce.umin.nxv64i1( %v) ret i1 %red @@ -652,8 +652,8 @@ ; CHECK-LABEL: vreduce_smin_nxv64i1: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a0, zero, e8, m8, ta, ma -; CHECK-NEXT: vcpop.m a0, v0 -; CHECK-NEXT: seqz a0, a0 +; CHECK-NEXT: vfirst.m a0, v0 +; CHECK-NEXT: slti a0, a0, 0 ; CHECK-NEXT: addi a0, a0, -1 ; CHECK-NEXT: ret %red = call i1 @llvm.vector.reduce.smin.nxv64i1( %v)