diff --git a/llvm/lib/Target/RISCV/AsmParser/RISCVAsmParser.cpp b/llvm/lib/Target/RISCV/AsmParser/RISCVAsmParser.cpp --- a/llvm/lib/Target/RISCV/AsmParser/RISCVAsmParser.cpp +++ b/llvm/lib/Target/RISCV/AsmParser/RISCVAsmParser.cpp @@ -2316,7 +2316,7 @@ void RISCVAsmParser::emitToStreamer(MCStreamer &S, const MCInst &Inst) { MCInst CInst; - bool Res = compressInst(CInst, Inst, getSTI(), S.getContext()); + bool Res = compressInst(CInst, Inst, getSTI()); if (Res) ++RISCVNumInstrsCompressed; S.emitInstruction((Res ? CInst : Inst), getSTI()); diff --git a/llvm/lib/Target/RISCV/MCTargetDesc/RISCVInstPrinter.cpp b/llvm/lib/Target/RISCV/MCTargetDesc/RISCVInstPrinter.cpp --- a/llvm/lib/Target/RISCV/MCTargetDesc/RISCVInstPrinter.cpp +++ b/llvm/lib/Target/RISCV/MCTargetDesc/RISCVInstPrinter.cpp @@ -70,7 +70,7 @@ const MCInst *NewMI = MI; MCInst UncompressedMI; if (PrintAliases && !NoAliases) - Res = uncompressInst(UncompressedMI, *MI, MRI, STI); + Res = uncompressInst(UncompressedMI, *MI, STI); if (Res) NewMI = const_cast(&UncompressedMI); if (!PrintAliases || NoAliases || !printAliasInstr(NewMI, Address, STI, O)) diff --git a/llvm/lib/Target/RISCV/RISCVAsmPrinter.cpp b/llvm/lib/Target/RISCV/RISCVAsmPrinter.cpp --- a/llvm/lib/Target/RISCV/RISCVAsmPrinter.cpp +++ b/llvm/lib/Target/RISCV/RISCVAsmPrinter.cpp @@ -93,7 +93,7 @@ #include "RISCVGenCompressInstEmitter.inc" void RISCVAsmPrinter::EmitToStreamer(MCStreamer &S, const MCInst &Inst) { MCInst CInst; - bool Res = compressInst(CInst, Inst, *STI, OutStreamer->getContext()); + bool Res = compressInst(CInst, Inst, *STI); if (Res) ++RISCVNumInstrsCompressed; AsmPrinter::EmitToStreamer(*OutStreamer, Res ? CInst : Inst); diff --git a/llvm/lib/Target/RISCV/RISCVInstrInfo.cpp b/llvm/lib/Target/RISCV/RISCVInstrInfo.cpp --- a/llvm/lib/Target/RISCV/RISCVInstrInfo.cpp +++ b/llvm/lib/Target/RISCV/RISCVInstrInfo.cpp @@ -1207,10 +1207,9 @@ if (MI.getParent() && MI.getParent()->getParent()) { const auto MF = MI.getMF(); const auto &TM = static_cast(MF->getTarget()); - const MCRegisterInfo &MRI = *TM.getMCRegisterInfo(); const MCSubtargetInfo &STI = *TM.getMCSubtargetInfo(); const RISCVSubtarget &ST = MF->getSubtarget(); - if (isCompressibleInst(MI, &ST, MRI, STI)) + if (isCompressibleInst(MI, &ST, STI)) return 2; } return get(Opcode).getSize(); diff --git a/llvm/test/TableGen/AsmPredicateCombiningRISCV.td b/llvm/test/TableGen/AsmPredicateCombiningRISCV.td --- a/llvm/test/TableGen/AsmPredicateCombiningRISCV.td +++ b/llvm/test/TableGen/AsmPredicateCombiningRISCV.td @@ -61,7 +61,7 @@ def : CompressPat<(BigInst Regs:$r), (SmallInst1 Regs:$r), [AsmPred1]>; // COMPRESS: if (STI.getFeatureBits()[arch::AsmCond1] && // COMPRESS-NEXT: (MI.getOperand(0).isReg()) && -// COMPRESS-NEXT: (MRI.getRegClass(arch::RegsRegClassID).contains(MI.getOperand(0).getReg()))) { +// COMPRESS-NEXT: (archMCRegisterClasses[arch::RegsRegClassID].contains(MI.getOperand(0).getReg()))) { // COMPRESS-NEXT: // SmallInst1 $r def SmallInst2 : RVInst16<2, []>; @@ -69,14 +69,14 @@ // COMPRESS: if (STI.getFeatureBits()[arch::AsmCond2a] && // COMPRESS-NEXT: STI.getFeatureBits()[arch::AsmCond2b] && // COMPRESS-NEXT: (MI.getOperand(0).isReg()) && -// COMPRESS-NEXT: (MRI.getRegClass(arch::RegsRegClassID).contains(MI.getOperand(0).getReg()))) { +// COMPRESS-NEXT: (archMCRegisterClasses[arch::RegsRegClassID].contains(MI.getOperand(0).getReg()))) { // COMPRESS-NEXT: // SmallInst2 $r def SmallInst3 : RVInst16<2, []>; def : CompressPat<(BigInst Regs:$r), (SmallInst3 Regs:$r), [AsmPred3]>; // COMPRESS: if ((STI.getFeatureBits()[arch::AsmCond3a] || STI.getFeatureBits()[arch::AsmCond3b]) && // COMPRESS-NEXT: (MI.getOperand(0).isReg()) && -// COMPRESS-NEXT: (MRI.getRegClass(arch::RegsRegClassID).contains(MI.getOperand(0).getReg()))) { +// COMPRESS-NEXT: (archMCRegisterClasses[arch::RegsRegClassID].contains(MI.getOperand(0).getReg()))) { // COMPRESS-NEXT: // SmallInst3 $r def SmallInst4 : RVInst16<2, []>; @@ -85,7 +85,7 @@ // COMPRESS-NEXT: STI.getFeatureBits()[arch::AsmCond2a] && // COMPRESS-NEXT: STI.getFeatureBits()[arch::AsmCond2b] && // COMPRESS-NEXT: (MI.getOperand(0).isReg()) && -// COMPRESS-NEXT: (MRI.getRegClass(arch::RegsRegClassID).contains(MI.getOperand(0).getReg()))) { +// COMPRESS-NEXT: (archMCRegisterClasses[arch::RegsRegClassID].contains(MI.getOperand(0).getReg()))) { // COMPRESS-NEXT: // SmallInst4 $r def SmallInst5 : RVInst16<2, []>; @@ -93,7 +93,7 @@ // COMPRESS: if (STI.getFeatureBits()[arch::AsmCond1] && // COMPRESS-NEXT: (STI.getFeatureBits()[arch::AsmCond3a] || STI.getFeatureBits()[arch::AsmCond3b]) && // COMPRESS-NEXT: (MI.getOperand(0).isReg()) && -// COMPRESS-NEXT: (MRI.getRegClass(arch::RegsRegClassID).contains(MI.getOperand(0).getReg()))) { +// COMPRESS-NEXT: (archMCRegisterClasses[arch::RegsRegClassID].contains(MI.getOperand(0).getReg()))) { // COMPRESS-NEXT: // SmallInst5 $r // COMPRESS-LABEL: static bool uncompressInst diff --git a/llvm/utils/TableGen/CompressInstEmitter.cpp b/llvm/utils/TableGen/CompressInstEmitter.cpp --- a/llvm/utils/TableGen/CompressInstEmitter.cpp +++ b/llvm/utils/TableGen/CompressInstEmitter.cpp @@ -45,11 +45,9 @@ // instructions, plus some helper functions: // // bool compressInst(MCInst &OutInst, const MCInst &MI, -// const MCSubtargetInfo &STI, -// MCContext &Context); +// const MCSubtargetInfo &STI); // // bool uncompressInst(MCInst &OutInst, const MCInst &MI, -// const MCRegisterInfo &MRI, // const MCSubtargetInfo &STI); // // In addition, it exports a function for checking whether @@ -57,7 +55,6 @@ // // bool isCompressibleInst(const MachineInstr& MI, // const Subtarget *Subtarget, -// const MCRegisterInfo &MRI, // const MCSubtargetInfo &STI); // // The clients that include this auto-generated header file and @@ -595,7 +592,6 @@ std::string FH; raw_string_ostream Func(F); raw_string_ostream FuncH(FH); - bool NeedMRI = false; if (EType == EmitterType::Compress) o << "\n#ifdef GEN_COMPRESS_INSTR\n" @@ -610,17 +606,14 @@ if (EType == EmitterType::Compress) { FuncH << "static bool compressInst(MCInst &OutInst,\n"; FuncH.indent(25) << "const MCInst &MI,\n"; - FuncH.indent(25) << "const MCSubtargetInfo &STI,\n"; - FuncH.indent(25) << "MCContext &Context) {\n"; + FuncH.indent(25) << "const MCSubtargetInfo &STI) {\n"; } else if (EType == EmitterType::Uncompress) { FuncH << "static bool uncompressInst(MCInst &OutInst,\n"; FuncH.indent(27) << "const MCInst &MI,\n"; - FuncH.indent(27) << "const MCRegisterInfo &MRI,\n"; FuncH.indent(27) << "const MCSubtargetInfo &STI) {\n"; } else if (EType == EmitterType::CheckCompress) { FuncH << "static bool isCompressibleInst(const MachineInstr &MI,\n"; FuncH.indent(27) << "const " << TargetName << "Subtarget *Subtarget,\n"; - FuncH.indent(27) << "const MCRegisterInfo &MRI,\n"; FuncH.indent(27) << "const MCSubtargetInfo &STI) {\n"; } @@ -762,16 +755,15 @@ auto *ClassRec = DestOperand.Rec->isSubClassOf("RegisterClass") ? DestOperand.Rec : DestOperand.Rec->getValueAsDef("RegClass"); - NeedMRI = true; // This is a register operand. Check the register class. // Don't check register class if this is a tied operand, it was done // for the operand its tied to. if (DestOperand.getTiedRegister() == -1) CondStream.indent(6) << "(MI.getOperand(" << OpIdx << ").isReg()) &&\n" - << " (MRI.getRegClass(" << TargetName - << "::" << ClassRec->getName() - << "RegClassID).contains(MI.getOperand(" << OpIdx + << " (" << TargetName << "MCRegisterClasses[" + << TargetName << "::" << ClassRec->getName() + << "RegClassID].contains(MI.getOperand(" << OpIdx << ").getReg())) &&\n"; if (CompressOrUncompress) @@ -880,8 +872,6 @@ } o << FuncH.str(); - if (NeedMRI && EType == EmitterType::Compress) - o.indent(2) << "const MCRegisterInfo &MRI = *Context.getRegisterInfo();\n"; o << Func.str(); if (EType == EmitterType::Compress)