Index: llvm/lib/Target/AArch64/AArch64SystemOperands.td
===================================================================
--- llvm/lib/Target/AArch64/AArch64SystemOperands.td
+++ llvm/lib/Target/AArch64/AArch64SystemOperands.td
@@ -168,8 +168,8 @@
 }
 
 let Requires = [{ {AArch64::FeatureMEC} }] in {
-def : DC<"CIGDPAE", 0b100, 0b0111, 0b1110, 0b000>;
-def : DC<"CIPAE",   0b100, 0b0111, 0b1110, 0b111>;
+def : DC<"CIPAE",   0b100, 0b0111, 0b1110, 0b000>;
+def : DC<"CIGDPAE", 0b100, 0b0111, 0b1110, 0b111>;
 }
 
 //===----------------------------------------------------------------------===//
Index: llvm/test/MC/AArch64/armv9a-mec.s
===================================================================
--- llvm/test/MC/AArch64/armv9a-mec.s
+++ llvm/test/MC/AArch64/armv9a-mec.s
@@ -49,8 +49,8 @@
 // CHECK-NO-MEC: [[@LINE-2]]:15: error: expected writable system register or pstate
 
           dc cigdpae, x0
-// CHECK: dc cigdpae, x0             // encoding: [0x00,0x7e,0x0c,0xd5]
+// CHECK: dc cigdpae, x0             // encoding: [0xe0,0x7e,0x0c,0xd5]
 // CHECK-NO-MEC: [[@LINE-2]]:14: error: DC CIGDPAE requires: mec
           dc cipae, x0
-// CHECK: dc cipae, x0               // encoding: [0xe0,0x7e,0x0c,0xd5]
+// CHECK: dc cipae, x0               // encoding: [0x00,0x7e,0x0c,0xd5]
 // CHECK-NO-MEC: [[@LINE-2]]:14: error: DC CIPAE requires: mec
Index: llvm/test/MC/Disassembler/AArch64/armv9a-mec.txt
===================================================================
--- llvm/test/MC/Disassembler/AArch64/armv9a-mec.txt
+++ llvm/test/MC/Disassembler/AArch64/armv9a-mec.txt
@@ -47,9 +47,9 @@
 [0x20,0xaa,0x1e,0xd5]
 # CHECK: msr MECID_RL_A_EL3, x0
 # CHECK-NO-MEC: msr S3_6_C10_C10_1, x0
-[0x00,0x7e,0x0c,0xd5]
-# CHECK: dc cigdpae, x0
-# CHECK-NO-MEC: sys #4, c7, c14, #0, x0
 [0xe0,0x7e,0x0c,0xd5]
-# CHECK: dc cipae, x0
+# CHECK: dc cigdpae, x0
 # CHECK-NO-MEC: sys #4, c7, c14, #7, x0
+[0x00,0x7e,0x0c,0xd5]
+# CHECK: dc cipae, x0
+# CHECK-NO-MEC: sys #4, c7, c14, #0, x0