diff --git a/clang/test/Preprocessor/riscv-target-features.c b/clang/test/Preprocessor/riscv-target-features.c --- a/clang/test/Preprocessor/riscv-target-features.c +++ b/clang/test/Preprocessor/riscv-target-features.c @@ -49,6 +49,15 @@ // CHECK-NOT: __riscv_zcd {{.*$}} // CHECK-NOT: __riscv_zcf {{.*$}} // CHECK-NOT: __riscv_h {{.*$}} +// CHECK-NOT: __riscv_zvkb {{.*$}} +// CHECK-NOT: __riscv_zvkg {{.*$}} +// CHECK-NOT: __riscv_zvkn {{.*$}} +// CHECK-NOT: __riscv_zvknha {{.*$}} +// CHECK-NOT: __riscv_zvknhb {{.*$}} +// CHECK-NOT: __riscv_zvkned {{.*$}} +// CHECK-NOT: __riscv_zvks {{.*$}} +// CHECK-NOT: __riscv_zvksed {{.*$}} +// CHECK-NOT: __riscv_zvksh {{.*$}} // RUN: %clang -target riscv32-unknown-linux-gnu -march=rv32i -x c -E -dM %s \ // RUN: -o - | FileCheck %s @@ -514,3 +523,75 @@ // RUN: -march=rv64izfa0p1 -x c -E -dM %s \ // RUN: -o - | FileCheck --check-prefix=CHECK-ZFA-EXT %s // CHECK-ZFA-EXT: __riscv_zfa 1000{{$}} + +// RUN: %clang -target riscv32 -menable-experimental-extensions \ +// RUN: -march=rv32i_zve64x_zvkb0p3 -x c -E -dM %s \ +// RUN: -o - | FileCheck --check-prefix=CHECK-ZVKB-EXT %s +// RUN: %clang -target riscv64 -menable-experimental-extensions \ +// RUN: -march=rv64i_zve64x_zvkb0p3 -x c -E -dM %s \ +// RUN: -o - | FileCheck --check-prefix=CHECK-ZVKB-EXT %s +// CHECK-ZVKB-EXT: __riscv_zvkb 3000{{$}} + +// RUN: %clang -target riscv32 -menable-experimental-extensions \ +// RUN: -march=rv32i_zve32x_zvkg0p3 -x c -E -dM %s \ +// RUN: -o - | FileCheck --check-prefix=CHECK-ZVKG-EXT %s +// RUN: %clang -target riscv64 -menable-experimental-extensions \ +// RUN: -march=rv64i_zve32x_zvkg0p3 -x c -E -dM %s \ +// RUN: -o - | FileCheck --check-prefix=CHECK-ZVKG-EXT %s +// CHECK-ZVKG-EXT: __riscv_zvkg 3000{{$}} + +// RUN: %clang -target riscv32 -menable-experimental-extensions \ +// RUN: -march=rv32i_zve64x_zvkn0p3 -x c -E -dM %s \ +// RUN: -o - | FileCheck --check-prefix=CHECK-ZVKN-EXT %s +// RUN: %clang -target riscv64 -menable-experimental-extensions \ +// RUN: -march=rv64i_zve64x_zvkn0p3 -x c -E -dM %s \ +// RUN: -o - | FileCheck --check-prefix=CHECK-ZVKN-EXT %s +// CHECK-ZVKN-EXT: __riscv_zvkn 3000{{$}} + +// RUN: %clang -target riscv32 -menable-experimental-extensions \ +// RUN: -march=rv32i_zve32x_zvknha0p3 -x c -E -dM %s \ +// RUN: -o - | FileCheck --check-prefix=CHECK-ZVKNHA-EXT %s +// RUN: %clang -target riscv64 -menable-experimental-extensions \ +// RUN: -march=rv64i_zve32x_zvknha0p3 -x c -E -dM %s \ +// RUN: -o - | FileCheck --check-prefix=CHECK-ZVKNHA-EXT %s +// CHECK-ZVKNHA-EXT: __riscv_zvknha 3000{{$}} + +// RUN: %clang -target riscv32 -menable-experimental-extensions \ +// RUN: -march=rv32i_zve64x_zvknhb0p3 -x c -E -dM %s \ +// RUN: -o - | FileCheck --check-prefix=CHECK-ZVKNHB-EXT %s +// RUN: %clang -target riscv64 -menable-experimental-extensions \ +// RUN: -march=rv64i_zve64x_zvknhb0p3 -x c -E -dM %s \ +// RUN: -o - | FileCheck --check-prefix=CHECK-ZVKNHB-EXT %s +// CHECK-ZVKNHB-EXT: __riscv_zvknhb 3000{{$}} + +// RUN: %clang -target riscv32 -menable-experimental-extensions \ +// RUN: -march=rv32i_zve32x_zvkned0p3 -x c -E -dM %s \ +// RUN: -o - | FileCheck --check-prefix=CHECK-ZVKNED-EXT %s +// RUN: %clang -target riscv64 -menable-experimental-extensions \ +// RUN: -march=rv64i_zve32x_zvkned0p3 -x c -E -dM %s \ +// RUN: -o - | FileCheck --check-prefix=CHECK-ZVKNED-EXT %s +// CHECK-ZVKNED-EXT: __riscv_zvkned 3000{{$}} + +// RUN: %clang -target riscv32 -menable-experimental-extensions \ +// RUN: -march=rv32i_zve32x_zvks0p3 -x c -E -dM %s \ +// RUN: -o - | FileCheck --check-prefix=CHECK-ZVKS-EXT %s +// RUN: %clang -target riscv64 -menable-experimental-extensions \ +// RUN: -march=rv64i_zve32x_zvks0p3 -x c -E -dM %s \ +// RUN: -o - | FileCheck --check-prefix=CHECK-ZVKS-EXT %s +// CHECK-ZVKS-EXT: __riscv_zvks 3000{{$}} + +// RUN: %clang -target riscv32 -menable-experimental-extensions \ +// RUN: -march=rv32i_zve32x_zvksed0p3 -x c -E -dM %s \ +// RUN: -o - | FileCheck --check-prefix=CHECK-ZVKSED-EXT %s +// RUN: %clang -target riscv64 -menable-experimental-extensions \ +// RUN: -march=rv64i_zve32x_zvksed0p3 -x c -E -dM %s \ +// RUN: -o - | FileCheck --check-prefix=CHECK-ZVKSED-EXT %s +// CHECK-ZVKSED-EXT: __riscv_zvksed 3000{{$}} + +// RUN: %clang -target riscv32 -menable-experimental-extensions \ +// RUN: -march=rv32i_zve32x_zvksh0p3 -x c -E -dM %s \ +// RUN: -o - | FileCheck --check-prefix=CHECK-ZVKSH-EXT %s +// RUN: %clang -target riscv64 -menable-experimental-extensions \ +// RUN: -march=rv64i_zve32x_zvksh0p3 -x c -E -dM %s \ +// RUN: -o - | FileCheck --check-prefix=CHECK-ZVKSH-EXT %s +// CHECK-ZVKSH-EXT: __riscv_zvksh 3000{{$}} diff --git a/llvm/docs/RISCVUsage.rst b/llvm/docs/RISCVUsage.rst --- a/llvm/docs/RISCVUsage.rst +++ b/llvm/docs/RISCVUsage.rst @@ -164,6 +164,9 @@ ``experimental-zvfh`` LLVM implements `this draft text `_. +``experimental-zvkb``, ``experimental-zvkg``, ``experimental-zvkn``, ``experimental-zvknha``, ``experimental-zvknhb``, ``experimental-zvkns``, ``experimental-zvks``, ``experimental-zvksed``, ``experimental-zvksh`` + LLVM implements the `0.3 draft specification `_. Note that current vector crypto extension version can be found in: . + To use an experimental extension from `clang`, you must add `-menable-experimental-extensions` to the command line, and specify the exact version of the experimental extension you are using. To use an experimental extension with LLVM's internal developer tools (e.g. `llc`, `llvm-objdump`, `llvm-mc`), you must prefix the extension name with `experimental-`. Note that you don't need to specify the version with internal tools, and shouldn't include the `experimental-` prefix with `clang`. Vendor Extensions diff --git a/llvm/lib/Support/RISCVISAInfo.cpp b/llvm/lib/Support/RISCVISAInfo.cpp --- a/llvm/lib/Support/RISCVISAInfo.cpp +++ b/llvm/lib/Support/RISCVISAInfo.cpp @@ -137,6 +137,17 @@ {"zfa", RISCVExtensionVersion{0, 1}}, {"zvfh", RISCVExtensionVersion{0, 1}}, {"ztso", RISCVExtensionVersion{0, 1}}, + + // vector crypto + {"zvkb", RISCVExtensionVersion{0, 3}}, + {"zvkg", RISCVExtensionVersion{0, 3}}, + {"zvkn", RISCVExtensionVersion{0, 3}}, + {"zvknha", RISCVExtensionVersion{0, 3}}, + {"zvknhb", RISCVExtensionVersion{0, 3}}, + {"zvkned", RISCVExtensionVersion{0, 3}}, + {"zvks", RISCVExtensionVersion{0, 3}}, + {"zvksed", RISCVExtensionVersion{0, 3}}, + {"zvksh", RISCVExtensionVersion{0, 3}}, }; static bool stripExperimentalPrefix(StringRef &Ext) { @@ -857,6 +868,19 @@ errc::invalid_argument, "'zvl*b' requires 'v' or 'zve*' extension to also be specified"); + if ((Exts.count("zvkb") || Exts.count("zvkg") || Exts.count("zvkn") || + Exts.count("zvknha") || Exts.count("zvkned") || Exts.count("zvks") || + Exts.count("zvksed") || Exts.count("zvksh")) && + !HasVector) + return createStringError( + errc::invalid_argument, + "'zvk*' requires 'v' or 'zve*' extension to also be specified"); + + if (Exts.count("zvknhb") && !Exts.count("zve64x")) + return createStringError( + errc::invalid_argument, + "'zvknhb' requires 'v' or 'zve64*' extension to also be specified"); + // Additional dependency checks. // TODO: The 'q' extension requires rv64. // TODO: It is illegal to specify 'e' extensions with 'f' and 'd'. @@ -892,6 +916,9 @@ "zkne", "zknd", "zknh"}; static const char *ImpliedExtsZks[] = {"zbkb", "zbkc", "zbkx", "zksed", "zksh"}; static const char *ImpliedExtsZvfh[] = {"zve32f"}; +static const char *ImpliedExtsZvkn[] = {"zvkned", "zvknhb", "zvkb"}; +static const char *ImpliedExtsZvknhb[] = {"zvknha"}; +static const char *ImpliedExtsZvks[] = {"zvksed", "zvksh", "zvkb"}; static const char *ImpliedExtsXTHeadVdot[] = {"v"}; static const char *ImpliedExtsZcb[] = {"zca"}; static const char *ImpliedExtsZfa[] = {"f"}; @@ -928,6 +955,9 @@ {{"zve64f"}, {ImpliedExtsZve64f}}, {{"zve64x"}, {ImpliedExtsZve64x}}, {{"zvfh"}, {ImpliedExtsZvfh}}, + {{"zvkn"}, {ImpliedExtsZvkn}}, + {{"zvknhb"}, {ImpliedExtsZvknhb}}, + {{"zvks"}, {ImpliedExtsZvks}}, {{"zvl1024b"}, {ImpliedExtsZvl1024b}}, {{"zvl128b"}, {ImpliedExtsZvl128b}}, {{"zvl16384b"}, {ImpliedExtsZvl16384b}}, diff --git a/llvm/lib/Target/RISCV/AsmParser/RISCVAsmParser.cpp b/llvm/lib/Target/RISCV/AsmParser/RISCVAsmParser.cpp --- a/llvm/lib/Target/RISCV/AsmParser/RISCVAsmParser.cpp +++ b/llvm/lib/Target/RISCV/AsmParser/RISCVAsmParser.cpp @@ -570,6 +570,7 @@ bool isUImm2() const { return IsUImm<2>(); } bool isUImm3() const { return IsUImm<3>(); } bool isUImm5() const { return IsUImm<5>(); } + bool isUImm6() const { return IsUImm<6>(); } bool isUImm7() const { return IsUImm<7>(); } bool isRnumArg() const { @@ -582,6 +583,36 @@ VK == RISCVMCExpr::VK_RISCV_None; } + bool isRnumArg_0_7() const { + int64_t Imm; + RISCVMCExpr::VariantKind VK = RISCVMCExpr::VK_RISCV_None; + if (!isImm()) + return false; + bool IsConstantImm = evaluateConstantImm(getImm(), Imm, VK); + return IsConstantImm && Imm >= INT64_C(0) && Imm <= INT64_C(7) && + VK == RISCVMCExpr::VK_RISCV_None; + } + + bool isRnumArg_1_10() const { + int64_t Imm; + RISCVMCExpr::VariantKind VK = RISCVMCExpr::VK_RISCV_None; + if (!isImm()) + return false; + bool IsConstantImm = evaluateConstantImm(getImm(), Imm, VK); + return IsConstantImm && Imm >= INT64_C(1) && Imm <= INT64_C(10) && + VK == RISCVMCExpr::VK_RISCV_None; + } + + bool isRnumArg_2_14() const { + int64_t Imm; + RISCVMCExpr::VariantKind VK = RISCVMCExpr::VK_RISCV_None; + if (!isImm()) + return false; + bool IsConstantImm = evaluateConstantImm(getImm(), Imm, VK); + return IsConstantImm && Imm >= INT64_C(2) && Imm <= INT64_C(14) && + VK == RISCVMCExpr::VK_RISCV_None; + } + bool isSImm5() const { if (!isImm()) return false; @@ -1345,6 +1376,15 @@ case Match_InvalidRnumArg: { return generateImmOutOfRangeError(Operands, ErrorInfo, 0, 10); } + case Match_InvalidRnumArg_0_7: { + return generateImmOutOfRangeError(Operands, ErrorInfo, 0, 7); + } + case Match_InvalidRnumArg_1_10: { + return generateImmOutOfRangeError(Operands, ErrorInfo, 1, 10); + } + case Match_InvalidRnumArg_2_14: { + return generateImmOutOfRangeError(Operands, ErrorInfo, 2, 14); + } } llvm_unreachable("Unknown match type detected!"); diff --git a/llvm/lib/Target/RISCV/MCTargetDesc/RISCVBaseInfo.h b/llvm/lib/Target/RISCV/MCTargetDesc/RISCVBaseInfo.h --- a/llvm/lib/Target/RISCV/MCTargetDesc/RISCVBaseInfo.h +++ b/llvm/lib/Target/RISCV/MCTargetDesc/RISCVBaseInfo.h @@ -245,6 +245,7 @@ OPERAND_UIMM3, OPERAND_UIMM4, OPERAND_UIMM5, + OPERAND_UIMM6, OPERAND_UIMM7, OPERAND_UIMM7_LSB00, OPERAND_UIMM8_LSB00, @@ -267,7 +268,10 @@ OPERAND_VTYPEI10, OPERAND_VTYPEI11, OPERAND_RVKRNUM, - OPERAND_LAST_RISCV_IMM = OPERAND_RVKRNUM, + OPERAND_RVKRNUM_0_7, + OPERAND_RVKRNUM_1_10, + OPERAND_RVKRNUM_2_14, + OPERAND_LAST_RISCV_IMM = OPERAND_RVKRNUM_2_14, // Operand is either a register or uimm5, this is used by V extension pseudo // instructions to represent a value that be passed as AVL to either vsetvli // or vsetivli. diff --git a/llvm/lib/Target/RISCV/RISCVFeatures.td b/llvm/lib/Target/RISCV/RISCVFeatures.td --- a/llvm/lib/Target/RISCV/RISCVFeatures.td +++ b/llvm/lib/Target/RISCV/RISCVFeatures.td @@ -479,6 +479,63 @@ AssemblerPredicate<(all_of FeatureStdExtZawrs), "'Zawrs' (Wait on Reservation Set)">; +def FeatureStdExtZvkb + : SubtargetFeature<"experimental-zvkb", "HasStdExtZvkb", "true", + "'Zvkb' (Vector Bitmanip instructions for Cryptography.)">; +def HasStdExtZvkb : Predicate<"Subtarget->hasStdExtZvkb()">, + AssemblerPredicate<(all_of FeatureStdExtZvkb), + "'Zvkb' (Vector Bitmanip instructions for Cryptography.)">; + +def FeatureStdExtZvkg + : SubtargetFeature<"experimental-zvkg", "HasStdExtZvkg", "true", + "'Zvkg' (Vector GCM instructions for Cryptography.)">; +def HasStdExtZvkg : Predicate<"Subtarget->hasStdExtZvkg()">, + AssemblerPredicate<(all_of FeatureStdExtZvkg), + "'Zvkg' (Vector GCM instructions for Cryptography.)">; + +def FeatureStdExtZvkn + : SubtargetFeature<"experimental-zvkn", "HasStdExtZvkn", "true", + "This extension is shorthand for the following set of " + "other extensions: Zvkned, Zvknhb and Zvkb.">; + +def FeatureStdExtZvknha + : SubtargetFeature<"experimental-zvknha", "HasStdExtZvknha", "true", + "'Zvknha' (Vector SHA-2. (SHA-256 only))">; + +def FeatureStdExtZvknhb + : SubtargetFeature<"experimental-zvknhb", "HasStdExtZvknhb", "true", + "'Zvknhb' (Vector SHA-2. (SHA-256 and SHA-512))", + [FeatureStdExtZvknha]>; +def HasStdExtZvknha : Predicate<"Subtarget->hasStdExtZvknha()">, + AssemblerPredicate<(all_of FeatureStdExtZvknha), + "'Zvknha' (Vector SHA-2. (SHA-256 only))">; + +def FeatureStdExtZvkned + : SubtargetFeature<"experimental-zvkned", "HasStdExtZvkned", "true", + "'Zvkned' (Vector AES Encryption & Decryption (Single Round))">; +def HasStdExtZvkned : Predicate<"Subtarget->hasStdExtZvkned()">, + AssemblerPredicate<(all_of FeatureStdExtZvkned), + "'Zvkned' (Vector AES Encryption & Decryption (Single Round))">; + +def FeatureStdExtZvks + : SubtargetFeature<"experimental-zvks", "HasStdExtZvks", "true", + "This extension is shorthand for the following set of " + "other extensions: Zvksed, Zvksh and Zvkb.">; + +def FeatureStdExtZvksed + : SubtargetFeature<"experimental-zvksed", "HasStdExtZvksed", "true", + "'Zvksed' (SM4 Block Cipher Instructions.)">; +def HasStdExtZvksed : Predicate<"Subtarget->hasStdExtZvksed()">, + AssemblerPredicate<(all_of FeatureStdExtZvksed), + "'Zvksed' (SM4 Block Cipher Instructions.)">; + +def FeatureStdExtZvksh + : SubtargetFeature<"experimental-zvksh", "HasStdExtZvksh", "true", + "'Zvksh' (SM3 Hash Function Instructions.)">; +def HasStdExtZvksh : Predicate<"Subtarget->hasStdExtZvksh()">, + AssemblerPredicate<(all_of FeatureStdExtZvksh), + "'Zvksh' (SM3 Hash Function Instructions.)">; + //===----------------------------------------------------------------------===// // Vendor extensions //===----------------------------------------------------------------------===// diff --git a/llvm/lib/Target/RISCV/RISCVInstrFormats.td b/llvm/lib/Target/RISCV/RISCVInstrFormats.td --- a/llvm/lib/Target/RISCV/RISCVInstrFormats.td +++ b/llvm/lib/Target/RISCV/RISCVInstrFormats.td @@ -153,6 +153,7 @@ def OPC_JALR : RISCVOpcode<"JALR", 0b1100111>; def OPC_JAL : RISCVOpcode<"JAL", 0b1101111>; def OPC_SYSTEM : RISCVOpcode<"SYSTEM", 0b1110011>; +def OPC_OP_P : RISCVOpcode<"OP_P", 0b1110111>; def OPC_CUSTOM_3 : RISCVOpcode<"CUSTOM_3", 0b1111011>; class RVInst= 0 && Imm <= 10; break; + case RISCVOp::OPERAND_RVKRNUM_0_7: + Ok = Imm >= 0 && Imm <= 7; + break; + case RISCVOp::OPERAND_RVKRNUM_1_10: + Ok = Imm >= 1 && Imm <= 10; + break; + case RISCVOp::OPERAND_RVKRNUM_2_14: + Ok = Imm >= 2 && Imm <= 14; + break; } if (!Ok) { ErrInfo = "Invalid immediate"; diff --git a/llvm/lib/Target/RISCV/RISCVInstrInfo.td b/llvm/lib/Target/RISCV/RISCVInstrInfo.td --- a/llvm/lib/Target/RISCV/RISCVInstrInfo.td +++ b/llvm/lib/Target/RISCV/RISCVInstrInfo.td @@ -225,6 +225,13 @@ let PredicateMethod = "isImm"; } +def uimm6 : Operand { + let ParserMatchClass = UImmAsmOperand<6>; + let DecoderMethod = "decodeUImmOperand<6>"; + let OperandType = "OPERAND_UIMM6"; + let OperandNamespace = "RISCVOp"; +} + def uimm7_opcode : Operand { let ParserMatchClass = InsnDirectiveOpcode; let DecoderMethod = "decodeUImmOperand<7>"; diff --git a/llvm/lib/Target/RISCV/RISCVInstrInfoV.td b/llvm/lib/Target/RISCV/RISCVInstrInfoV.td --- a/llvm/lib/Target/RISCV/RISCVInstrInfoV.td +++ b/llvm/lib/Target/RISCV/RISCVInstrInfoV.td @@ -410,6 +410,14 @@ : RVInstV; + +// op vd, vs2 (use vs1 as instruction encoding) +class VALUVs2NoVm funct6, bits<5> vs1, RISCVVFormat opv, string opcodestr> + : RVInstV { + let vm = 1; +} } // hasSideEffects = 0, mayLoad = 0, mayStore = 0 //===----------------------------------------------------------------------===// @@ -1773,4 +1781,5 @@ } } // Predicates = [HasVInstructionsI64, IsRV64] +include "RISCVInstrInfoZvk.td" include "RISCVInstrInfoVPseudos.td" diff --git a/llvm/lib/Target/RISCV/RISCVInstrInfoZvk.td b/llvm/lib/Target/RISCV/RISCVInstrInfoZvk.td new file mode 100644 --- /dev/null +++ b/llvm/lib/Target/RISCV/RISCVInstrInfoZvk.td @@ -0,0 +1,170 @@ +//===-- RISCVInstrInfoZvk.td - RISC-V 'Zvk' instructions -------*- tablegen -*-===// +// +// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. +// See https://llvm.org/LICENSE.txt for license information. +// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception +// +//===----------------------------------------------------------------------===// +// +// This file describes the RISC-V instructions from the standard 'Zvk', +// Vector Cryptography Instructions extension, version 0.3. +// +//===----------------------------------------------------------------------===// + +let hasSideEffects = 0, mayLoad = 0, mayStore = 0 in { +multiclass VCLMUL_MV_V_X funct6> { + def V : VALUVV, + Sched<[WriteVIALUV_UpperBound, ReadVIALUV_UpperBound, + ReadVIALUV_UpperBound, ReadVMask]>; + def X : VALUVX, + Sched<[WriteVIALUX_UpperBound, ReadVIALUV_UpperBound, + ReadVIALUX_UpperBound, ReadVMask]>; +} + +class RVInstIVI_VROR funct6, dag outs, dag ins, string opcodestr, + string argstr> + : RVInst { + bits<5> vs2; + bits<6> imm; + bits<5> vd; + bit vm; + + let Inst{31-27} = funct6{5-1}; + let Inst{26} = imm{5}; + let Inst{25} = vm; + let Inst{24-20} = vs2; + let Inst{19-15} = imm{4-0}; + let Inst{14-12} = OPIVI.Value; + let Inst{11-7} = vd; + let Opcode = OPC_OP_V.Value; + + let Uses = [VTYPE, VL]; + let RVVConstraint = VMConstraint; +} + +multiclass VROR_IV_V_X_I funct6, + Operand optype = uimm6, string vw = "v"> + : VALU_IV_V_X { + def I : RVInstIVI_VROR, + Sched<[WriteVIALUI_UpperBound, ReadVIALUV_UpperBound, + ReadVMask]>; +} + +// op vd, vs2, vs1 +class PALUVVNoVm funct6, RISCVVFormat opv, string opcodestr> + : VALUVVNoVm { + let Opcode = OPC_OP_P.Value; +} + +// op vd, vs2, imm, vm +class PALUVINoVm funct6, string opcodestr, Operand optype = simm5> + : VALUVINoVm { + let Opcode = OPC_OP_P.Value; + let Inst{14-12} = OPMVV.Value; +} + +// op vd, vs2 (use vs1 as instruction encoding) +class PALUVs2NoVm funct6, bits<5> vs1, RISCVVFormat opv, string opcodestr> + : VALUVs2NoVm { + let Opcode = OPC_OP_P.Value; +} + +multiclass VAES_MV_V_S funct6_vv, bits<6> funct6_vs, bits<5> vs1, + RISCVVFormat opv, string opcodestr> { + def NAME # _VV : PALUVs2NoVm; + def NAME # _VS : PALUVs2NoVm; +} + +// vaeskf1.vi and vaeskf2.vi uses different opcode and format, we need +// to customize one for them. +class VAESKF_MV_I funct6, string opcodestr, Operand optype> + : VALUVINoVm { + let Opcode = OPC_OP_P.Value; + let Inst{14-12} = OPMVV.Value; +} +} // hasSideEffects = 0, mayLoad = 0, mayStore = 0 + +def RnumArg_0_7 : AsmOperandClass { + let Name = "RnumArg_0_7"; + let RenderMethod = "addImmOperands"; + let DiagnosticType = "InvalidRnumArg_0_7"; +} + +def RnumArg_1_10 : AsmOperandClass { + let Name = "RnumArg_1_10"; + let RenderMethod = "addImmOperands"; + let DiagnosticType = "InvalidRnumArg_1_10"; +} + +def RnumArg_2_14 : AsmOperandClass { + let Name = "RnumArg_2_14"; + let RenderMethod = "addImmOperands"; + let DiagnosticType = "InvalidRnumArg_2_14"; +} + +def rnum_0_7 : Operand, ImmLeaf { + let ParserMatchClass = RnumArg_0_7; + let DecoderMethod = "decodeUImmOperand<5>"; + let OperandType = "OPERAND_RVKRNUM_0_7"; + let OperandNamespace = "RISCVOp"; +} + +def rnum_1_10 : Operand, ImmLeaf { + let ParserMatchClass = RnumArg_1_10; + let DecoderMethod = "decodeUImmOperand<5>"; + let OperandType = "OPERAND_RVKRNUM_1_10"; + let OperandNamespace = "RISCVOp"; +} + +def rnum_2_14 : Operand, ImmLeaf { + let ParserMatchClass = RnumArg_2_14; + let DecoderMethod = "decodeUImmOperand<5>"; + let OperandType = "OPERAND_RVKRNUM_2_14"; + let OperandNamespace = "RISCVOp"; +} + +let Predicates = [HasStdExtZvkb] in { + defm VANDN_V : VALU_IV_V_X<"vandn", 0b000001>; + def VBREV8_V : VALUVs2<0b010010, 0b01000, OPMVV, "vbrev8.v">; + defm VCLMUL_V : VCLMUL_MV_V_X<"vclmul", 0b001100>; + defm VCLMULH_V : VCLMUL_MV_V_X<"vclmulh", 0b001101>; + def VREV8_V : VALUVs2<0b010010, 0b01001, OPMVV, "vrev8.v">; + defm VROL_V : VALU_IV_V_X<"vrol", 0b010101>; + defm VROR_V : VROR_IV_V_X_I<"vror", 0b010100>; +} // Predicates = [HasStdExtZvkb] + +let Predicates = [HasStdExtZvkg], RVVConstraint = NoConstraint in { + def VGHSH_VV : PALUVVNoVm<0b101100, OPMVV, "vghsh.vv">; + def VGMUL_VV : PALUVs2NoVm<0b101000, 0b10001, OPMVV, "vgmul.vv">; +} // Predicates = [HasStdExtZvkg] + +let Predicates = [HasStdExtZvknha], RVVConstraint = NoConstraint in { + def VSHA2CH_VV : PALUVVNoVm<0b101110, OPMVV, "vsha2ch.vv">; + def VSHA2CL_VV : PALUVVNoVm<0b101111, OPMVV, "vsha2cl.vv">; + def VSHA2MS_VV : PALUVVNoVm<0b101101, OPMVV, "vsha2ms.vv">; +} // Predicates = [HasStdExtZvknha] + +let Predicates = [HasStdExtZvkned], RVVConstraint = NoConstraint in { + defm VAESDF : VAES_MV_V_S<0b101000, 0b101001, 0b00001, OPMVV, "vaesdf">; + defm VAESDM : VAES_MV_V_S<0b101000, 0b101001, 0b00000, OPMVV, "vaesdm">; + defm VAESEF : VAES_MV_V_S<0b101000, 0b101001, 0b00011, OPMVV, "vaesef">; + defm VAESEM : VAES_MV_V_S<0b101000, 0b101001, 0b00010, OPMVV, "vaesem">; + def VAESKF1_VI : VAESKF_MV_I<0b100010, "vaeskf1.vi", rnum_1_10>; + def VAESKF2_VI : VAESKF_MV_I<0b101010, "vaeskf2.vi", rnum_2_14>; + def VAESZ_VS : PALUVs2NoVm<0b101001, 0b00111, OPMVV, "vaesz.vs">; +} // Predicates = [HasStdExtZvkned] + +let Predicates = [HasStdExtZvksed], RVVConstraint = NoConstraint in { + def VSM4K_VI : PALUVINoVm<0b100001, "vsm4k.vi", rnum_0_7>; + defm VSM4R : VAES_MV_V_S<0b101000, 0b101001, 0b10000, OPMVV, "vsm4r">; +} // Predicates = [HasStdExtZvksed] + +let Predicates = [HasStdExtZvksh], RVVConstraint = NoConstraint in { + def VSM3C_VI : PALUVINoVm<0b101011, "vsm3c.vi", uimm5>; + def VSM3ME_VV : PALUVVNoVm<0b100000, OPMVV, "vsm3me.vv">; +} // Predicates = [HasStdExtZvksh] diff --git a/llvm/test/CodeGen/RISCV/attributes.ll b/llvm/test/CodeGen/RISCV/attributes.ll --- a/llvm/test/CodeGen/RISCV/attributes.ll +++ b/llvm/test/CodeGen/RISCV/attributes.ll @@ -55,6 +55,15 @@ ; RUN: llc -mtriple=riscv32 -mattr=+zicsr %s -o - | FileCheck --check-prefixes=CHECK,RV32ZICSR %s ; RUN: llc -mtriple=riscv32 -mattr=+zifencei %s -o - | FileCheck --check-prefixes=CHECK,RV32ZIFENCEI %s ; RUN: llc -mtriple=riscv32 -mattr=+experimental-zfa %s -o - | FileCheck --check-prefixes=CHECK,RV32ZFA %s +; RUN: llc -mtriple=riscv32 -mattr=+zve64x -mattr=+experimental-zvkb %s -o - | FileCheck --check-prefix=RV32ZVKB %s +; RUN: llc -mtriple=riscv32 -mattr=+zve32x -mattr=+experimental-zvkg %s -o - | FileCheck --check-prefix=RV32ZVKG %s +; RUN: llc -mtriple=riscv32 -mattr=+zve64x -mattr=+experimental-zvkn %s -o - | FileCheck --check-prefix=RV32ZVKN %s +; RUN: llc -mtriple=riscv32 -mattr=+zve32x -mattr=+experimental-zvknha %s -o - | FileCheck --check-prefix=RV32ZVKNHA %s +; RUN: llc -mtriple=riscv32 -mattr=+zve64x -mattr=+experimental-zvknhb %s -o - | FileCheck --check-prefix=RV32ZVKNHB %s +; RUN: llc -mtriple=riscv32 -mattr=+zve32x -mattr=+experimental-zvkned %s -o - | FileCheck --check-prefix=RV32ZVKNED %s +; RUN: llc -mtriple=riscv32 -mattr=+zve32x -mattr=+experimental-zvks %s -o - | FileCheck --check-prefix=RV32ZVKS %s +; RUN: llc -mtriple=riscv32 -mattr=+zve32x -mattr=+experimental-zvksed %s -o - | FileCheck --check-prefix=RV32ZVKSED %s +; RUN: llc -mtriple=riscv32 -mattr=+zve32x -mattr=+experimental-zvksh %s -o - | FileCheck --check-prefix=RV32ZVKSH %s ; RUN: llc -mtriple=riscv64 %s -o - | FileCheck %s ; RUN: llc -mtriple=riscv64 -mattr=+m %s -o - | FileCheck --check-prefixes=CHECK,RV64M %s @@ -117,6 +126,15 @@ ; RUN: llc -mtriple=riscv64 -mattr=+zicsr %s -o - | FileCheck --check-prefixes=CHECK,RV64ZICSR %s ; RUN: llc -mtriple=riscv64 -mattr=+zifencei %s -o - | FileCheck --check-prefixes=CHECK,RV64ZIFENCEI %s ; RUN: llc -mtriple=riscv64 -mattr=+experimental-zfa %s -o - | FileCheck --check-prefixes=CHECK,RV64ZFA %s +; RUN: llc -mtriple=riscv64 -mattr=+zve64x -mattr=+experimental-zvkb %s -o - | FileCheck --check-prefix=RV64ZVKB %s +; RUN: llc -mtriple=riscv64 -mattr=+zve32x -mattr=+experimental-zvkg %s -o - | FileCheck --check-prefix=RV64ZVKG %s +; RUN: llc -mtriple=riscv64 -mattr=+zve64x -mattr=+experimental-zvkn %s -o - | FileCheck --check-prefix=RV64ZVKN %s +; RUN: llc -mtriple=riscv64 -mattr=+zve32x -mattr=+experimental-zvknha %s -o - | FileCheck --check-prefix=RV64ZVKNHA %s +; RUN: llc -mtriple=riscv64 -mattr=+zve64x -mattr=+experimental-zvknhb %s -o - | FileCheck --check-prefix=RV64ZVKNHB %s +; RUN: llc -mtriple=riscv64 -mattr=+zve32x -mattr=+experimental-zvkned %s -o - | FileCheck --check-prefix=RV64ZVKNED %s +; RUN: llc -mtriple=riscv64 -mattr=+zve32x -mattr=+experimental-zvks %s -o - | FileCheck --check-prefix=RV64ZVKS %s +; RUN: llc -mtriple=riscv64 -mattr=+zve32x -mattr=+experimental-zvksed %s -o - | FileCheck --check-prefix=RV64ZVKSED %s +; RUN: llc -mtriple=riscv64 -mattr=+zve32x -mattr=+experimental-zvksh %s -o - | FileCheck --check-prefix=RV64ZVKSH %s ; CHECK: .attribute 4, 16 @@ -174,6 +192,15 @@ ; RV32ZICSR: .attribute 5, "rv32i2p0_zicsr2p0" ; RV32ZIFENCEI: .attribute 5, "rv32i2p0_zifencei2p0" ; RV32ZFA: .attribute 5, "rv32i2p0_f2p0_zfa0p1" +; RV32ZVKB: .attribute 5, "rv32i2p0_zve32x1p0_zve64x1p0_zvkb0p3_zvl32b1p0_zvl64b1p0" +; RV32ZVKG: .attribute 5, "rv32i2p0_zve32x1p0_zvkg0p3_zvl32b1p0" +; RV32ZVKN: .attribute 5, "rv32i2p0_zve32x1p0_zve64x1p0_zvkb0p3_zvkn0p3_zvkned0p3_zvknha0p3_zvknhb0p3_zvl32b1p0_zvl64b1p0" +; RV32ZVKNHA: .attribute 5, "rv32i2p0_zve32x1p0_zvknha0p3_zvl32b1p0" +; RV32ZVKNHB: .attribute 5, "rv32i2p0_zve32x1p0_zve64x1p0_zvknha0p3_zvknhb0p3_zvl32b1p0_zvl64b1p0" +; RV32ZVKNED: .attribute 5, "rv32i2p0_zve32x1p0_zvkned0p3_zvl32b1p0" +; RV32ZVKS: .attribute 5, "rv32i2p0_zve32x1p0_zvkb0p3_zvks0p3_zvksed0p3_zvksh0p3_zvl32b1p0" +; RV32ZVKSED: .attribute 5, "rv32i2p0_zve32x1p0_zvksed0p3_zvl32b1p0" +; RV32ZVKSH: .attribute 5, "rv32i2p0_zve32x1p0_zvksh0p3_zvl32b1p0" ; RV64M: .attribute 5, "rv64i2p0_m2p0" ; RV64ZMMUL: .attribute 5, "rv64i2p0_zmmul1p0" @@ -235,6 +262,15 @@ ; RV64ZICSR: .attribute 5, "rv64i2p0_zicsr2p0" ; RV64ZIFENCEI: .attribute 5, "rv64i2p0_zifencei2p0" ; RV64ZFA: .attribute 5, "rv64i2p0_f2p0_zfa0p1" +; RV64ZVKB: .attribute 5, "rv64i2p0_zve32x1p0_zve64x1p0_zvkb0p3_zvl32b1p0_zvl64b1p0" +; RV64ZVKG: .attribute 5, "rv64i2p0_zve32x1p0_zvkg0p3_zvl32b1p0" +; RV64ZVKN: .attribute 5, "rv64i2p0_zve32x1p0_zve64x1p0_zvkb0p3_zvkn0p3_zvkned0p3_zvknha0p3_zvknhb0p3_zvl32b1p0_zvl64b1p0" +; RV64ZVKNHA: .attribute 5, "rv64i2p0_zve32x1p0_zvknha0p3_zvl32b1p0" +; RV64ZVKNHB: .attribute 5, "rv64i2p0_zve32x1p0_zve64x1p0_zvknha0p3_zvknhb0p3_zvl32b1p0_zvl64b1p0" +; RV64ZVKNED: .attribute 5, "rv64i2p0_zve32x1p0_zvkned0p3_zvl32b1p0" +; RV64ZVKS: .attribute 5, "rv64i2p0_zve32x1p0_zvkb0p3_zvks0p3_zvksed0p3_zvksh0p3_zvl32b1p0" +; RV64ZVKSED: .attribute 5, "rv64i2p0_zve32x1p0_zvksed0p3_zvl32b1p0" +; RV64ZVKSH: .attribute 5, "rv64i2p0_zve32x1p0_zvksh0p3_zvl32b1p0" define i32 @addi(i32 %a) { %1 = add i32 %a, 1 diff --git a/llvm/test/MC/RISCV/attribute-arch.s b/llvm/test/MC/RISCV/attribute-arch.s --- a/llvm/test/MC/RISCV/attribute-arch.s +++ b/llvm/test/MC/RISCV/attribute-arch.s @@ -114,6 +114,33 @@ .attribute arch, "rv32izbc1p0" # CHECK: attribute 5, "rv32i2p0_zbc1p0" +.attribute arch, "rv32i_zve64x_zvkb0p3" +# CHECK: attribute 5, "rv32i2p0_zve32x1p0_zve64x1p0_zvkb0p3_zvl32b1p0_zvl64b1p0" + +.attribute arch, "rv32i_zve32x_zvkg0p3" +# CHECK: attribute 5, "rv32i2p0_zve32x1p0_zvkg0p3_zvl32b1p0" + +.attribute arch, "rv32i_zve64x_zvkn0p3" +# CHECK: attribute 5, "rv32i2p0_zve32x1p0_zve64x1p0_zvkb0p3_zvkn0p3_zvkned0p3_zvknha0p3_zvknhb0p3_zvl32b1p0_zvl64b1p0" + +.attribute arch, "rv32i_zve32x_zvknha0p3" +# CHECK: attribute 5, "rv32i2p0_zve32x1p0_zvknha0p3_zvl32b1p0" + +.attribute arch, "rv32i_zve64x_zvknhb0p3" +# CHECK: attribute 5, "rv32i2p0_zve32x1p0_zve64x1p0_zvknha0p3_zvknhb0p3_zvl32b1p0_zvl64b1p0" + +.attribute arch, "rv32i_zve32x_zvkned0p3" +# CHECK: attribute 5, "rv32i2p0_zve32x1p0_zvkned0p3_zvl32b1p0" + +.attribute arch, "rv32i_zve32x_zvks0p3" +# CHECK: attribute 5, "rv32i2p0_zve32x1p0_zvkb0p3_zvks0p3_zvksed0p3_zvksh0p3_zvl32b1p0" + +.attribute arch, "rv32i_zve32x_zvksed0p3" +# CHECK: attribute 5, "rv32i2p0_zve32x1p0_zvksed0p3_zvl32b1p0" + +.attribute arch, "rv32i_zve32x_zvksh0p3" +# CHECK: attribute 5, "rv32i2p0_zve32x1p0_zvksh0p3_zvl32b1p0" + .attribute arch, "rv32izbs1p0" # CHECK: attribute 5, "rv32i2p0_zbs1p0" diff --git a/llvm/test/MC/RISCV/rvv/zvkb.s b/llvm/test/MC/RISCV/rvv/zvkb.s new file mode 100644 --- /dev/null +++ b/llvm/test/MC/RISCV/rvv/zvkb.s @@ -0,0 +1,87 @@ +# RUN: llvm-mc -triple=riscv32 -show-encoding --mattr=+zve32x --mattr=+experimental-zvkb %s \ +# RUN: | FileCheck %s --check-prefixes=CHECK-ENCODING,CHECK-INST +# RUN: not llvm-mc -triple=riscv32 -show-encoding %s 2>&1 \ +# RUN: | FileCheck %s --check-prefix=CHECK-ERROR +# RUN: llvm-mc -triple=riscv32 -filetype=obj --mattr=+zve32x --mattr=+experimental-zvkb %s \ +# RUN: | llvm-objdump -d --mattr=+zve32x --mattr=+experimental-zvkb - \ +# RUN: | FileCheck %s --check-prefix=CHECK-INST +# RUN: llvm-mc -triple=riscv32 -filetype=obj --mattr=+zve32x --mattr=+experimental-zvkb %s \ +# RUN: | llvm-objdump -d - | FileCheck %s --check-prefix=CHECK-UNKNOWN + +vandn.vv v10, v9, v8, v0.t +# CHECK-INST: vandn.vv v10, v9, v8, v0.t +# CHECK-ENCODING: [0x57,0x05,0x94,0x04] +# CHECK-ERROR: instruction requires the following: 'Zvkb' (Vector Bitmanip instructions for Cryptography.){{$}} +# CHECK-UNKNOWN: 57 05 94 04 + +vandn.vx v10, v9, a0, v0.t +# CHECK-INST: vandn.vx v10, v9, a0, v0.t +# CHECK-ENCODING: [0x57,0x45,0x95,0x04] +# CHECK-ERROR: instruction requires the following: 'Zvkb' (Vector Bitmanip instructions for Cryptography.){{$}} +# CHECK-UNKNOWN: 57 45 95 04 + +vbrev8.v v10, v9, v0.t +# CHECK-INST: vbrev8.v v10, v9, v0.t +# CHECK-ENCODING: [0x57,0x25,0x94,0x48] +# CHECK-ERROR: instruction requires the following: 'Zvkb' (Vector Bitmanip instructions for Cryptography.){{$}} +# CHECK-UNKNOWN: 57 25 94 48 + +vclmul.vv v10, v9, v8 +# CHECK-INST: vclmul.vv v10, v9, v8 +# CHECK-ENCODING: [0x57,0x25,0x94,0x32] +# CHECK-ERROR: instruction requires the following: 'Zvkb' (Vector Bitmanip instructions for Cryptography.){{$}} +# CHECK-UNKNOWN: 57 25 94 32 + +vclmul.vx v10, v9, a0 +# CHECK-INST: vclmul.vx v10, v9, a0 +# CHECK-ENCODING: [0x57,0x65,0x95,0x32] +# CHECK-ERROR: instruction requires the following: 'Zvkb' (Vector Bitmanip instructions for Cryptography.){{$}} +# CHECK-UNKNOWN: 57 65 95 32 + +vclmulh.vv v10, v9, v8 +# CHECK-INST: vclmulh.vv v10, v9, v8 +# CHECK-ENCODING: [0x57,0x25,0x94,0x36] +# CHECK-ERROR: instruction requires the following: 'Zvkb' (Vector Bitmanip instructions for Cryptography.){{$}} +# CHECK-UNKNOWN: 57 25 94 36 + +vclmulh.vx v10, v9, a0 +# CHECK-INST: vclmulh.vx v10, v9, a0 +# CHECK-ENCODING: [0x57,0x65,0x95,0x36] +# CHECK-ERROR: instruction requires the following: 'Zvkb' (Vector Bitmanip instructions for Cryptography.){{$}} +# CHECK-UNKNOWN: 57 65 95 36 + +vrev8.v v10, v9, v0.t +# CHECK-INST: vrev8.v v10, v9, v0.t +# CHECK-ENCODING: [0x57,0xa5,0x94,0x48] +# CHECK-ERROR: instruction requires the following: 'Zvkb' (Vector Bitmanip instructions for Cryptography.){{$}} +# CHECK-UNKNOWN: 57 a5 94 48 + +vrol.vv v10, v9, v8, v0.t +# CHECK-INST: vrol.vv v10, v9, v8, v0.t +# CHECK-ENCODING: [0x57,0x05,0x94,0x54] +# CHECK-ERROR: instruction requires the following: 'Zvkb' (Vector Bitmanip instructions for Cryptography.){{$}} +# CHECK-UNKNOWN: 57 05 94 54 + +vrol.vx v10, v9, a0, v0.t +# CHECK-INST: vrol.vx v10, v9, a0, v0.t +# CHECK-ENCODING: [0x57,0x45,0x95,0x54] +# CHECK-ERROR: instruction requires the following: 'Zvkb' (Vector Bitmanip instructions for Cryptography.){{$}} +# CHECK-UNKNOWN: 57 45 95 54 + +vror.vv v10, v9, v8, v0.t +# CHECK-INST: vror.vv v10, v9, v8, v0.t +# CHECK-ENCODING: [0x57,0x05,0x94,0x50] +# CHECK-ERROR: instruction requires the following: 'Zvkb' (Vector Bitmanip instructions for Cryptography.){{$}} +# CHECK-UNKNOWN: 57 05 94 50 + +vror.vx v10, v9, a0, v0.t +# CHECK-INST: vror.vx v10, v9, a0, v0.t +# CHECK-ENCODING: [0x57,0x45,0x95,0x50] +# CHECK-ERROR: instruction requires the following: 'Zvkb' (Vector Bitmanip instructions for Cryptography.){{$}} +# CHECK-UNKNOWN: 57 45 95 50 + +vror.vi v10, v9, 33, v0.t +# CHECK-INST: vror.vi v10, v9, 33, v0.t +# CHECK-ENCODING: [0x57,0xb5,0x90,0x54] +# CHECK-ERROR: instruction requires the following: 'Zvkb' (Vector Bitmanip instructions for Cryptography.){{$}} +# CHECK-UNKNOWN: 57 b5 90 54 diff --git a/llvm/test/MC/RISCV/rvv/zvkg.s b/llvm/test/MC/RISCV/rvv/zvkg.s new file mode 100644 --- /dev/null +++ b/llvm/test/MC/RISCV/rvv/zvkg.s @@ -0,0 +1,15 @@ +# RUN: llvm-mc -triple=riscv32 -show-encoding --mattr=+zve32x --mattr=+experimental-zvkg %s \ +# RUN: | FileCheck %s --check-prefixes=CHECK-ENCODING,CHECK-INST +# RUN: not llvm-mc -triple=riscv32 -show-encoding %s 2>&1 \ +# RUN: | FileCheck %s --check-prefix=CHECK-ERROR +# RUN: llvm-mc -triple=riscv32 -filetype=obj --mattr=+zve32x --mattr=+experimental-zvkg %s \ +# RUN: | llvm-objdump -d --mattr=+zve32x --mattr=+experimental-zvkg - \ +# RUN: | FileCheck %s --check-prefix=CHECK-INST +# RUN: llvm-mc -triple=riscv32 -filetype=obj --mattr=+zve32x --mattr=+experimental-zvkg %s \ +# RUN: | llvm-objdump -d - | FileCheck %s --check-prefix=CHECK-UNKNOWN + +vghsh.vv v10, v9, v8 +# CHECK-INST: vghsh.vv v10, v9, v8 +# CHECK-ENCODING: [0x77,0x25,0x94,0xb2] +# CHECK-ERROR: instruction requires the following: 'Zvkg' (Vector GCM instructions for Cryptography.){{$}} +# CHECK-UNKNOWN: 77 25 94 b2 diff --git a/llvm/test/MC/RISCV/rvv/zvkned-invalid.s b/llvm/test/MC/RISCV/rvv/zvkned-invalid.s new file mode 100644 --- /dev/null +++ b/llvm/test/MC/RISCV/rvv/zvkned-invalid.s @@ -0,0 +1,8 @@ +# RUN: not llvm-mc -triple=riscv32 -show-encoding --mattr=+zve32x --mattr=+experimental-zvkned %s 2>&1 \ +# RUN: | FileCheck %s --check-prefix=CHECK-ERROR + +vaeskf1.vi v10, v9, 0 +# CHECK-ERROR: immediate must be an integer in the range [1, 10] + +vaeskf2.vi v10, v9, 0 +# CHECK-ERROR: immediate must be an integer in the range [2, 14] diff --git a/llvm/test/MC/RISCV/rvv/zvkned.s b/llvm/test/MC/RISCV/rvv/zvkned.s new file mode 100644 --- /dev/null +++ b/llvm/test/MC/RISCV/rvv/zvkned.s @@ -0,0 +1,75 @@ +# RUN: llvm-mc -triple=riscv32 -show-encoding --mattr=+zve32x --mattr=+experimental-zvkned %s \ +# RUN: | FileCheck %s --check-prefixes=CHECK-ENCODING,CHECK-INST +# RUN: not llvm-mc -triple=riscv32 -show-encoding %s 2>&1 \ +# RUN: | FileCheck %s --check-prefix=CHECK-ERROR +# RUN: llvm-mc -triple=riscv32 -filetype=obj --mattr=+zve32x --mattr=+experimental-zvkned %s \ +# RUN: | llvm-objdump -d --mattr=+zve32x --mattr=+experimental-zvkned - \ +# RUN: | FileCheck %s --check-prefix=CHECK-INST +# RUN: llvm-mc -triple=riscv32 -filetype=obj --mattr=+zve32x --mattr=+experimental-zvkned %s \ +# RUN: | llvm-objdump -d - | FileCheck %s --check-prefix=CHECK-UNKNOWN + +vaesdf.vv v10, v9 +# CHECK-INST: vaesdf.vv v10, v9 +# CHECK-ENCODING: [0x77,0xa5,0x90,0xa2] +# CHECK-ERROR: instruction requires the following: 'Zvkned' (Vector AES Encryption & Decryption (Single Round)){{$}} +# CHECK-UNKNOWN: 77 a5 90 a2 + +vaesdf.vs v10, v9 +# CHECK-INST: vaesdf.vs v10, v9 +# CHECK-ENCODING: [0x77,0xa5,0x90,0xa6] +# CHECK-ERROR: instruction requires the following: 'Zvkned' (Vector AES Encryption & Decryption (Single Round)){{$}} +# CHECK-UNKNOWN: 77 a5 90 a6 + +vaesef.vv v10, v9 +# CHECK-INST: vaesef.vv v10, v9 +# CHECK-ENCODING: [0x77,0xa5,0x91,0xa2] +# CHECK-ERROR: instruction requires the following: 'Zvkned' (Vector AES Encryption & Decryption (Single Round)){{$}} +# CHECK-UNKNOWN: 77 a5 91 a2 + +vaesef.vs v10, v9 +# CHECK-INST: vaesef.vs v10, v9 +# CHECK-ENCODING: [0x77,0xa5,0x91,0xa6] +# CHECK-ERROR: instruction requires the following: 'Zvkned' (Vector AES Encryption & Decryption (Single Round)){{$}} +# CHECK-UNKNOWN: 77 a5 91 a6 + +vaesdm.vv v10, v9 +# CHECK-INST: vaesdm.vv v10, v9 +# CHECK-ENCODING: [0x77,0x25,0x90,0xa2] +# CHECK-ERROR: instruction requires the following: 'Zvkned' (Vector AES Encryption & Decryption (Single Round)){{$}} +# CHECK-UNKNOWN: 77 25 90 a2 + +vaesdm.vs v10, v9 +# CHECK-INST: vaesdm.vs v10, v9 +# CHECK-ENCODING: [0x77,0x25,0x90,0xa6] +# CHECK-ERROR: instruction requires the following: 'Zvkned' (Vector AES Encryption & Decryption (Single Round)){{$}} +# CHECK-UNKNOWN: 77 25 90 a6 + +vaesem.vv v10, v9 +# CHECK-INST: vaesem.vv v10, v9 +# CHECK-ENCODING: [0x77,0x25,0x91,0xa2] +# CHECK-ERROR: instruction requires the following: 'Zvkned' (Vector AES Encryption & Decryption (Single Round)){{$}} +# CHECK-UNKNOWN: 77 25 91 a2 + +vaesem.vs v10, v9 +# CHECK-INST: vaesem.vs v10, v9 +# CHECK-ENCODING: [0x77,0x25,0x91,0xa6] +# CHECK-ERROR: instruction requires the following: 'Zvkned' (Vector AES Encryption & Decryption (Single Round)){{$}} +# CHECK-UNKNOWN: 77 25 91 a6 + +vaeskf1.vi v10, v9, 1 +# CHECK-INST: vaeskf1.vi v10, v9, 1 +# CHECK-ENCODING: [0x77,0xa5,0x90,0x8a] +# CHECK-ERROR: instruction requires the following: 'Zvkned' (Vector AES Encryption & Decryption (Single Round)){{$}} +# CHECK-UNKNOWN: 77 a5 90 8a + +vaeskf2.vi v10, v9, 2 +# CHECK-INST: vaeskf2.vi v10, v9, 2 +# CHECK-ENCODING: [0x77,0x25,0x91,0xaa] +# CHECK-ERROR: instruction requires the following: 'Zvkned' (Vector AES Encryption & Decryption (Single Round)){{$}} +# CHECK-UNKNOWN: 77 25 91 aa + +vaesz.vs v10, v9 +# CHECK-INST: vaesz.vs v10, v9 +# CHECK-ENCODING: [0x77,0xa5,0x93,0xa6] +# CHECK-ERROR: instruction requires the following: 'Zvkned' (Vector AES Encryption & Decryption (Single Round)){{$}} +# CHECK-UNKNOWN: 77 a5 93 a6 diff --git a/llvm/test/MC/RISCV/rvv/zvknh.s b/llvm/test/MC/RISCV/rvv/zvknh.s new file mode 100644 --- /dev/null +++ b/llvm/test/MC/RISCV/rvv/zvknh.s @@ -0,0 +1,34 @@ +# RUN: llvm-mc -triple=riscv32 -show-encoding --mattr=+zve32x --mattr=+experimental-zvknha %s \ +# RUN: | FileCheck %s --check-prefixes=CHECK-ENCODING,CHECK-INST +# RUN: llvm-mc -triple=riscv64 -show-encoding --mattr=+zve64x --mattr=+experimental-zvknhb %s \ +# RUN: | FileCheck %s --check-prefixes=CHECK-ENCODING,CHECK-INST +# RUN: llvm-mc -triple=riscv32 -filetype=obj --mattr=+zve32x --mattr=+experimental-zvknha %s \ +# RUN: | llvm-objdump -d --mattr=+zve32x --mattr=+experimental-zvknha - \ +# RUN: | FileCheck %s --check-prefix=CHECK-INST +# RUN: llvm-mc -triple=riscv64 -filetype=obj --mattr=+zve64x --mattr=+experimental-zvknhb %s \ +# RUN: | llvm-objdump -d --mattr=+zve64x --mattr=+experimental-zvknhb - \ +# RUN: | FileCheck %s --check-prefix=CHECK-INST +# RUN: llvm-mc -triple=riscv32 -filetype=obj --mattr=+zve32x --mattr=+experimental-zvknha %s \ +# RUN: | llvm-objdump -d - | FileCheck %s --check-prefix=CHECK-UNKNOWN +# RUN: llvm-mc -triple=riscv64 -filetype=obj --mattr=+zve64x --mattr=+experimental-zvknhb %s \ +# RUN: | llvm-objdump -d - | FileCheck %s --check-prefix=CHECK-UNKNOWN +# RUN: not llvm-mc -triple=riscv32 -show-encoding %s 2>&1 \ +# RUN: | FileCheck %s --check-prefix=CHECK-ERROR + +vsha2ms.vv v10, v9, v8 +# CHECK-INST: vsha2ms.vv v10, v9, v8 +# CHECK-ENCODING: [0x77,0x25,0x94,0xb6] +# CHECK-UNKNOWN: 77 25 94 b6 +# CHECK-ERROR: instruction requires the following: 'Zvknha' (Vector SHA-2. (SHA-256 only)){{$}} + +vsha2ch.vv v10, v9, v8 +# CHECK-INST: vsha2ch.vv v10, v9, v8 +# CHECK-ENCODING: [0x77,0x25,0x94,0xba] +# CHECK-UNKNOWN: 77 25 94 ba +# CHECK-ERROR: instruction requires the following: 'Zvknha' (Vector SHA-2. (SHA-256 only)){{$}} + +vsha2cl.vv v10, v9, v8 +# CHECK-INST: vsha2cl.vv v10, v9, v8 +# CHECK-ENCODING: [0x77,0x25,0x94,0xbe] +# CHECK-UNKNOWN: 77 25 94 be +# CHECK-ERROR: instruction requires the following: 'Zvknha' (Vector SHA-2. (SHA-256 only)){{$}} diff --git a/llvm/test/MC/RISCV/rvv/zvksed-invalid.s b/llvm/test/MC/RISCV/rvv/zvksed-invalid.s new file mode 100644 --- /dev/null +++ b/llvm/test/MC/RISCV/rvv/zvksed-invalid.s @@ -0,0 +1,5 @@ +# RUN: not llvm-mc -triple=riscv32 --mattr=+zve32x --mattr=+experimental-zvksed -show-encoding %s 2>&1 \ +# RUN: | FileCheck %s --check-prefix=CHECK-ERROR + +vsm4k.vi v10, v9, 8 +# CHECK-ERROR: immediate must be an integer in the range [0, 7] diff --git a/llvm/test/MC/RISCV/rvv/zvksed.s b/llvm/test/MC/RISCV/rvv/zvksed.s new file mode 100644 --- /dev/null +++ b/llvm/test/MC/RISCV/rvv/zvksed.s @@ -0,0 +1,27 @@ +# RUN: llvm-mc -triple=riscv32 -show-encoding --mattr=+zve32x --mattr=+experimental-zvksed %s \ +# RUN: | FileCheck %s --check-prefixes=CHECK-ENCODING,CHECK-INST +# RUN: not llvm-mc -triple=riscv32 -show-encoding %s 2>&1 \ +# RUN: | FileCheck %s --check-prefix=CHECK-ERROR +# RUN: llvm-mc -triple=riscv32 -filetype=obj --mattr=+zve32x --mattr=+experimental-zvksed %s \ +# RUN: | llvm-objdump -d --mattr=+zve32x --mattr=+experimental-zvksed - \ +# RUN: | FileCheck %s --check-prefix=CHECK-INST +# RUN: llvm-mc -triple=riscv32 -filetype=obj --mattr=+zve32x --mattr=+experimental-zvksed %s \ +# RUN: | llvm-objdump -d - | FileCheck %s --check-prefix=CHECK-UNKNOWN + +vsm4k.vi v10, v9, 7 +# CHECK-INST: vsm4k.vi v10, v9, 7 +# CHECK-ENCODING: [0x77,0xa5,0x93,0x86] +# CHECK-ERROR: instruction requires the following: 'Zvksed' (SM4 Block Cipher Instructions.){{$}} +# CHECK-UNKNOWN: 77 a5 93 86 + +vsm4r.vv v10, v9 +# CHECK-INST: vsm4r.vv v10, v9 +# CHECK-ENCODING: [0x77,0x25,0x98,0xa2] +# CHECK-ERROR: instruction requires the following: 'Zvksed' (SM4 Block Cipher Instructions.){{$}} +# CHECK-UNKNOWN: 77 25 98 a2 + +vsm4r.vs v10, v9 +# CHECK-INST: vsm4r.vs v10, v9 +# CHECK-ENCODING: [0x77,0x25,0x98,0xa6] +# CHECK-ERROR: instruction requires the following: 'Zvksed' (SM4 Block Cipher Instructions.){{$}} +# CHECK-UNKNOWN: 77 25 98 a6 diff --git a/llvm/test/MC/RISCV/rvv/zvksh.s b/llvm/test/MC/RISCV/rvv/zvksh.s new file mode 100644 --- /dev/null +++ b/llvm/test/MC/RISCV/rvv/zvksh.s @@ -0,0 +1,21 @@ +# RUN: llvm-mc -triple=riscv32 -show-encoding --mattr=+zve32x --mattr=+experimental-zvksh %s \ +# RUN: | FileCheck %s --check-prefixes=CHECK-ENCODING,CHECK-INST +# RUN: not llvm-mc -triple=riscv32 -show-encoding %s 2>&1 \ +# RUN: | FileCheck %s --check-prefix=CHECK-ERROR +# RUN: llvm-mc -triple=riscv32 -filetype=obj --mattr=+zve32x --mattr=+experimental-zvksh %s \ +# RUN: | llvm-objdump -d --mattr=+zve32x --mattr=+experimental-zvksh - \ +# RUN: | FileCheck %s --check-prefix=CHECK-INST +# RUN: llvm-mc -triple=riscv32 -filetype=obj --mattr=+zve32x --mattr=+experimental-zvksh %s \ +# RUN: | llvm-objdump -d - | FileCheck %s --check-prefix=CHECK-UNKNOWN + +vsm3c.vi v10, v9, 7 +# CHECK-INST: vsm3c.vi v10, v9, 7 +# CHECK-ENCODING: [0x77,0xa5,0x93,0xae] +# CHECK-ERROR: instruction requires the following: 'Zvksh' (SM3 Hash Function Instructions.){{$}} +# CHECK-UNKNOWN: 77 a5 93 ae + +vsm3me.vv v10, v9, v8 +# CHECK-INST: vsm3me.vv v10, v9, v8 +# CHECK-ENCODING: [0x77,0x25,0x94,0x82] +# CHECK-ERROR: instruction requires the following: 'Zvksh' (SM3 Hash Function Instructions.){{$}} +# CHECK-UNKNOWN: 77 25 94 82