diff --git a/llvm/lib/Target/Mips/AsmParser/MipsAsmParser.cpp b/llvm/lib/Target/Mips/AsmParser/MipsAsmParser.cpp
--- a/llvm/lib/Target/Mips/AsmParser/MipsAsmParser.cpp
+++ b/llvm/lib/Target/Mips/AsmParser/MipsAsmParser.cpp
@@ -1749,16 +1749,6 @@
 
 } // end anonymous namespace
 
-namespace llvm {
-
-extern const MCInstrDesc MipsInsts[];
-
-} // end namespace llvm
-
-static const MCInstrDesc &getInstDesc(unsigned Opcode) {
-  return MipsInsts[Opcode];
-}
-
 static bool hasShortDelaySlot(MCInst &Inst) {
   switch (Inst.getOpcode()) {
     case Mips::BEQ_MM:
@@ -1839,9 +1829,7 @@
   return false;
 }
 
-static bool needsExpandMemInst(MCInst &Inst) {
-  const MCInstrDesc &MCID = getInstDesc(Inst.getOpcode());
-
+static bool needsExpandMemInst(MCInst &Inst, const MCInstrDesc &MCID) {
   unsigned NumOp = MCID.getNumOperands();
   if (NumOp != 3 && NumOp != 4)
     return false;
@@ -1878,7 +1866,7 @@
                                        const MCSubtargetInfo *STI) {
   MipsTargetStreamer &TOut = getTargetStreamer();
   const unsigned Opcode = Inst.getOpcode();
-  const MCInstrDesc &MCID = getInstDesc(Opcode);
+  const MCInstrDesc &MCID = MII.get(Opcode);
   bool ExpandedJalSym = false;
 
   Inst.setLoc(IDLoc);
@@ -2159,8 +2147,7 @@
   if (MCID.mayLoad() || MCID.mayStore()) {
     // Check the offset of memory operand, if it is a symbol
     // reference or immediate we may have to expand instructions.
-    if (needsExpandMemInst(Inst)) {
-      const MCInstrDesc &MCID = getInstDesc(Inst.getOpcode());
+    if (needsExpandMemInst(Inst, MCID)) {
       switch (MCID.OpInfo[MCID.getNumOperands() - 1].OperandType) {
       case MipsII::OPERAND_MEM_SIMM9:
         expandMem9Inst(Inst, IDLoc, Out, STI, MCID.mayLoad());
@@ -2674,7 +2661,7 @@
 
   // If .set reorder is active and branch instruction has a delay slot,
   // emit a NOP after it.
-  const MCInstrDesc &MCID = getInstDesc(JalrInst.getOpcode());
+  const MCInstrDesc &MCID = MII.get(JalrInst.getOpcode());
   if (MCID.hasDelaySlot() && AssemblerOptions.back()->isReorder())
     TOut.emitEmptyDelaySlot(hasShortDelaySlot(JalrInst), IDLoc,
                             STI);
@@ -3572,7 +3559,7 @@
                                                const MCSubtargetInfo *STI) {
   MipsTargetStreamer &TOut = getTargetStreamer();
 
-  assert(getInstDesc(Inst.getOpcode()).getNumOperands() == 1 &&
+  assert(MII.get(Inst.getOpcode()).getNumOperands() == 1 &&
          "unexpected number of operands");
 
   MCOperand Offset = Inst.getOperand(0);
@@ -3605,7 +3592,7 @@
 
   // If .set reorder is active and branch instruction has a delay slot,
   // emit a NOP after it.
-  const MCInstrDesc &MCID = getInstDesc(Inst.getOpcode());
+  const MCInstrDesc &MCID = MII.get(Inst.getOpcode());
   if (MCID.hasDelaySlot() && AssemblerOptions.back()->isReorder())
     TOut.emitEmptyDelaySlot(true, IDLoc, STI);
 
@@ -3696,7 +3683,7 @@
   unsigned BaseReg = BaseRegOp.getReg();
   unsigned TmpReg = DstReg;
 
-  const MCInstrDesc &Desc = getInstDesc(OpCode);
+  const MCInstrDesc &Desc = MII.get(OpCode);
   int16_t DstRegClass = Desc.OpInfo[StartOp].RegClass;
   unsigned DstRegClassID =
       getContext().getRegisterInfo()->getRegClass(DstRegClass).getID();
@@ -3823,7 +3810,7 @@
   unsigned BaseReg = BaseRegOp.getReg();
   unsigned TmpReg = DstReg;
 
-  const MCInstrDesc &Desc = getInstDesc(OpCode);
+  const MCInstrDesc &Desc = MII.get(OpCode);
   int16_t DstRegClass = Desc.OpInfo[StartOp].RegClass;
   unsigned DstRegClassID =
       getContext().getRegisterInfo()->getRegClass(DstRegClass).getID();
@@ -5906,7 +5893,7 @@
     return Match_Success;
   }
 
-  uint64_t TSFlags = getInstDesc(Inst.getOpcode()).TSFlags;
+  uint64_t TSFlags = MII.get(Inst.getOpcode()).TSFlags;
   if ((TSFlags & MipsII::HasFCCRegOperand) &&
       (Inst.getOperand(0).getReg() != Mips::FCC0) && !hasEightFccRegisters())
     return Match_NoFCCRegisterForCurrentISA;