Index: lib/Target/ARM/Disassembler/ARMDisassembler.cpp =================================================================== --- lib/Target/ARM/Disassembler/ARMDisassembler.cpp +++ lib/Target/ARM/Disassembler/ARMDisassembler.cpp @@ -966,8 +966,13 @@ static DecodeStatus DecoderGPRRegisterClass(MCInst &Inst, unsigned RegNo, uint64_t Address, const void *Decoder) { DecodeStatus S = MCDisassembler::Success; - if (RegNo == 13 || RegNo == 15) + + const FeatureBitset &featureBits = + ((const MCDisassembler*)Decoder)->getSubtargetInfo().getFeatureBits(); + + if ((RegNo == 13 && !featureBits[ARM::HasV8Ops]) || RegNo == 15) S = MCDisassembler::SoftFail; + Check(S, DecodeGPRRegisterClass(Inst, RegNo, Address, Decoder)); return S; } @@ -1127,7 +1132,7 @@ unsigned imm = fieldFromInstruction(Val, 7, 5); // Register-immediate - if (!Check(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder))) + if (!Check(S, DecoderGPRRegisterClass(Inst, Rm, Address, Decoder))) return MCDisassembler::Fail; ARM_AM::ShiftOpc Shift = ARM_AM::lsl; Index: test/MC/Disassembler/ARM/invalid-thumbv7.txt =================================================================== --- test/MC/Disassembler/ARM/invalid-thumbv7.txt +++ test/MC/Disassembler/ARM/invalid-thumbv7.txt @@ -1,4 +1,5 @@ -# RUN: not llvm-mc -disassemble %s -mcpu cortex-a8 -triple thumbv7 2>&1 | FileCheck %s +# RUN: not llvm-mc -disassemble %s -mcpu cortex-a8 -triple thumbv7 2>&1 | FileCheck %s --check-prefix=CHECK --check-prefix=CHECK-V7 +# RUN: not llvm-mc -disassemble %s -mcpu cortex-a53 -triple thumbv8 2>&1 | FileCheck %s # This file is checking Thumbv7 encodings which are globally invalid, usually due # to the constraints of the instructions not being met. For example invalid @@ -359,10 +360,22 @@ # 32-bit Thumb STM instructions cannot have a writeback register which appears # in the list. -[0xa1,0xe8,0x07,0x04] +[0xa1 0xe8 0x07 0x04] # CHECK: warning: potentially undefined instruction encoding -# CHECK-NEXT: [0xa1,0xe8,0x07,0x04] +# CHECK-NEXT: [0xa1 0xe8 0x07 0x04] -[0x21,0xe9,0x07,0x04] +[0x21 0xe9 0x07 0x04] # CHECK: warning: potentially undefined instruction encoding -# CHECK-NEXT: [0x21,0xe9,0x07,0x04] +# CHECK-NEXT: [0x21 0xe9 0x07 0x04] + +#------------------------------------------------------------------------------ +# SP is invalid as rGPR before ARMv8 +#------------------------------------------------------------------------------ + +[0x00 0xf0 0x00 0x0d] +# CHECK-V7: warning: potentially undefined instruction encoding +# CHECK-V7-NEXT: [0x00 0xf0 0x00 0x0d] + +[0x63 0xeb 0x2d 0x46] +# CHECK-V7: warning: potentially undefined instruction encoding +# CHECK-V7-NEXT: [0x63 0xeb 0x2d 0x46] Index: test/MC/Disassembler/ARM/thumb-v8.txt =================================================================== --- test/MC/Disassembler/ARM/thumb-v8.txt +++ test/MC/Disassembler/ARM/thumb-v8.txt @@ -1,4 +1,5 @@ -# RUN: llvm-mc -disassemble -triple thumbv8 -mattr=+db -show-encoding < %s | FileCheck %s +# RUN: llvm-mc -disassemble -triple thumbv8 -mattr=+db -show-encoding 2>%t < %s | FileCheck %s +# RUN: FileCheck -allow-empty -check-prefix=STDERR < %t %s 0x80 0xba # CHECK: hlt #0 @@ -26,3 +27,10 @@ # CHECK: dmb oshld # CHECK: dmb nshld # CHECK: dmb ld + +[0x00 0xf0 0x00 0x0d] +[0x63 0xeb 0x2d 0x46] +# CHECK: and sp, r0, #0 +# CHECK: sbc.w r6, r3, sp, asr #16 + +# STDERR-NOT: warning