diff --git a/llvm/lib/Target/ARM/ARMLowOverheadLoops.cpp b/llvm/lib/Target/ARM/ARMLowOverheadLoops.cpp --- a/llvm/lib/Target/ARM/ARMLowOverheadLoops.cpp +++ b/llvm/lib/Target/ARM/ARMLowOverheadLoops.cpp @@ -916,6 +916,8 @@ // false lane zeros, so we can ignore the uses. SmallPtrSet Defs; RDA.getGlobalReachingDefs(&MI, MO.getReg(), Defs); + if (Defs.empty()) + return false; for (auto *Def : Defs) { if (Def == &MI || FalseLanesZero.count(Def) || IsZeroInit(Def)) continue; diff --git a/llvm/test/CodeGen/Thumb2/LowOverheadLoops/mve-reduct-livein-arg.mir b/llvm/test/CodeGen/Thumb2/LowOverheadLoops/mve-reduct-livein-arg.mir new file mode 100644 --- /dev/null +++ b/llvm/test/CodeGen/Thumb2/LowOverheadLoops/mve-reduct-livein-arg.mir @@ -0,0 +1,208 @@ +# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py +# RUN: llc -mtriple=thumbv8.1m.main -mattr=+mve -run-pass=arm-low-overhead-loops %s -o - | FileCheck %s + +# Make sure we do not treat an argument as having zero false lanes + +--- | + target datalayout = "e-m:e-p:32:32-Fi8-i64:64-v128:64:128-a:0:32-n32-S64" + target triple = "thumbv8.1m.main-arm-none-eabihf" + + define zeroext i8 @test7(ptr nocapture noundef readonly %a, ptr nocapture noundef readonly %b, ptr nocapture noundef readnone %c, i32 noundef %n, <16 x i8> noundef %vx) { + entry: + %cmp10 = icmp sgt i32 %n, 0 + br i1 %cmp10, label %while.body.preheader, label %while.end + + while.body.preheader: ; preds = %entry + %0 = add i32 %n, 15 + %umin = call i32 @llvm.umin.i32(i32 %n, i32 16) + %1 = sub i32 %0, %umin + %2 = lshr i32 %1, 4 + %3 = add nuw nsw i32 %2, 1 + %4 = call i32 @llvm.start.loop.iterations.i32(i32 %3) + br label %while.body + + while.body: ; preds = %while.body.preheader, %while.body + %a.addr.014 = phi ptr [ %add.ptr, %while.body ], [ %a, %while.body.preheader ] + %b.addr.013 = phi ptr [ %add.ptr2, %while.body ], [ %b, %while.body.preheader ] + %n.addr.012 = phi i32 [ %12, %while.body ], [ %n, %while.body.preheader ] + %sum.011 = phi i8 [ %conv1, %while.body ], [ 0, %while.body.preheader ] + %5 = phi i32 [ %4, %while.body.preheader ], [ %13, %while.body ] + %6 = tail call <16 x i1> @llvm.arm.mve.vctp8(i32 %n.addr.012) + %7 = tail call <16 x i8> @llvm.masked.load.v16i8.p0(ptr %a.addr.014, i32 1, <16 x i1> %6, <16 x i8> zeroinitializer) + %8 = tail call <16 x i8> @llvm.masked.load.v16i8.p0(ptr %b.addr.013, i32 1, <16 x i1> %6, <16 x i8> zeroinitializer) + %9 = tail call <16 x i8> @llvm.arm.mve.add.predicated.v16i8.v16i1(<16 x i8> %7, <16 x i8> %8, <16 x i1> %6, <16 x i8> %vx) + %10 = tail call i32 @llvm.arm.mve.addv.v16i8(<16 x i8> %9, i32 1) + %11 = trunc i32 %10 to i8 + %conv1 = add i8 %sum.011, %11 + %add.ptr = getelementptr inbounds i8, ptr %a.addr.014, i32 16 + %add.ptr2 = getelementptr inbounds i8, ptr %b.addr.013, i32 16 + %12 = add i32 %n.addr.012, -16 + %13 = call i32 @llvm.loop.decrement.reg.i32(i32 %5, i32 1) + %14 = icmp ne i32 %13, 0 + br i1 %14, label %while.body, label %while.end + + while.end: ; preds = %while.body, %entry + %sum.0.lcssa = phi i8 [ 0, %entry ], [ %conv1, %while.body ] + ret i8 %sum.0.lcssa + } + + declare <16 x i1> @llvm.arm.mve.vctp8(i32) + declare <16 x i8> @llvm.masked.load.v16i8.p0(ptr nocapture, i32 immarg, <16 x i1>, <16 x i8>) + declare <16 x i8> @llvm.arm.mve.add.predicated.v16i8.v16i1(<16 x i8>, <16 x i8>, <16 x i1>, <16 x i8>) + declare i32 @llvm.arm.mve.addv.v16i8(<16 x i8>, i32) + declare i32 @llvm.umin.i32(i32, i32) + declare i32 @llvm.start.loop.iterations.i32(i32) + declare i32 @llvm.loop.decrement.reg.i32(i32, i32) + +... +--- +name: test7 +alignment: 2 +exposesReturnsTwice: false +legalized: false +regBankSelected: false +selected: false +failedISel: false +tracksRegLiveness: true +hasWinCFI: false +callsEHReturn: false +callsUnwindInit: false +hasEHCatchret: false +hasEHScopes: false +hasEHFunclets: false +failsVerification: false +tracksDebugUserValues: true +registers: [] +liveins: + - { reg: '$r0', virtual-reg: '' } + - { reg: '$r1', virtual-reg: '' } + - { reg: '$r3', virtual-reg: '' } + - { reg: '$q0', virtual-reg: '' } +frameInfo: + isFrameAddressTaken: false + isReturnAddressTaken: false + hasStackMap: false + hasPatchPoint: false + stackSize: 8 + offsetAdjustment: 0 + maxAlignment: 4 + adjustsStack: false + hasCalls: false + stackProtector: '' + functionContext: '' + maxCallFrameSize: 0 + cvBytesOfCalleeSavedRegisters: 0 + hasOpaqueSPAdjustment: false + hasVAStart: false + hasMustTailInVarArgFunc: false + hasTailCall: false + localFrameSize: 0 + savePoint: '' + restorePoint: '' +fixedStack: [] +stack: + - { id: 0, name: '', type: spill-slot, offset: -4, size: 4, alignment: 4, + stack-id: default, callee-saved-register: '$lr', callee-saved-restored: false, + debug-info-variable: '', debug-info-expression: '', debug-info-location: '' } + - { id: 1, name: '', type: spill-slot, offset: -8, size: 4, alignment: 4, + stack-id: default, callee-saved-register: '$r7', callee-saved-restored: true, + debug-info-variable: '', debug-info-expression: '', debug-info-location: '' } +callSites: [] +debugValueSubstitutions: [] +constants: [] +machineFunctionInfo: {} +body: | + ; CHECK-LABEL: name: test7 + ; CHECK: bb.0.entry: + ; CHECK-NEXT: successors: %bb.1(0x50000000), %bb.3(0x30000000) + ; CHECK-NEXT: liveins: $lr, $q0, $r0, $r1, $r3, $r7 + ; CHECK-NEXT: {{ $}} + ; CHECK-NEXT: frame-setup tPUSH 14 /* CC::al */, $noreg, killed $r7, killed $lr, implicit-def $sp, implicit $sp + ; CHECK-NEXT: frame-setup CFI_INSTRUCTION def_cfa_offset 8 + ; CHECK-NEXT: frame-setup CFI_INSTRUCTION offset $lr, -4 + ; CHECK-NEXT: frame-setup CFI_INSTRUCTION offset $r7, -8 + ; CHECK-NEXT: dead $r7 = frame-setup tMOVr $sp, 14 /* CC::al */, $noreg + ; CHECK-NEXT: frame-setup CFI_INSTRUCTION def_cfa_register $r7 + ; CHECK-NEXT: tCMPi8 renamable $r3, 1, 14 /* CC::al */, $noreg, implicit-def $cpsr + ; CHECK-NEXT: renamable $r12 = t2MOVi 0, 14 /* CC::al */, $noreg, $noreg + ; CHECK-NEXT: tBcc %bb.3, 11 /* CC::lt */, killed $cpsr + ; CHECK-NEXT: {{ $}} + ; CHECK-NEXT: bb.1.while.body.preheader: + ; CHECK-NEXT: successors: %bb.2(0x80000000) + ; CHECK-NEXT: liveins: $q0, $r0, $r1, $r3, $r12 + ; CHECK-NEXT: {{ $}} + ; CHECK-NEXT: renamable $r2 = t2SUBri renamable $r3, 16, 14 /* CC::al */, $noreg, def $cpsr + ; CHECK-NEXT: renamable $r2 = t2CSEL killed renamable $r2, renamable $r12, 2, implicit killed $cpsr + ; CHECK-NEXT: renamable $lr = t2ADDri killed renamable $r2, 15, 14 /* CC::al */, $noreg, $noreg + ; CHECK-NEXT: renamable $r2, dead $cpsr = tMOVi8 1, 14 /* CC::al */, $noreg + ; CHECK-NEXT: renamable $r2 = nuw nsw t2ADDrs killed renamable $r2, killed renamable $lr, 35, 14 /* CC::al */, $noreg, $noreg + ; CHECK-NEXT: $lr = t2DLS killed renamable $r2 + ; CHECK-NEXT: {{ $}} + ; CHECK-NEXT: bb.2.while.body (align 4): + ; CHECK-NEXT: successors: %bb.2(0x7c000000), %bb.3(0x04000000) + ; CHECK-NEXT: liveins: $lr, $q0, $r0, $r1, $r3, $r12 + ; CHECK-NEXT: {{ $}} + ; CHECK-NEXT: renamable $vpr = MVE_VCTP8 renamable $r3, 0, $noreg, $noreg + ; CHECK-NEXT: MVE_VPST 4, implicit $vpr + ; CHECK-NEXT: renamable $r0, renamable $q1 = MVE_VLDRBU8_post killed renamable $r0, 16, 1, renamable $vpr, renamable $lr :: (load unknown-size from %ir.a.addr.014, align 1) + ; CHECK-NEXT: renamable $r1, renamable $q2 = MVE_VLDRBU8_post killed renamable $r1, 16, 1, renamable $vpr, renamable $lr :: (load unknown-size from %ir.b.addr.013, align 1) + ; CHECK-NEXT: $q3 = MVE_VORR $q0, $q0, 0, $noreg, $noreg, undef $q3 + ; CHECK-NEXT: MVE_VPST 8, implicit $vpr + ; CHECK-NEXT: renamable $q3 = MVE_VADDi8 killed renamable $q1, killed renamable $q2, 1, killed renamable $vpr, renamable $lr, killed renamable $q3 + ; CHECK-NEXT: renamable $r12 = MVE_VADDVu8acc killed renamable $r12, killed renamable $q3, 0, $noreg, renamable $lr + ; CHECK-NEXT: renamable $r3, dead $cpsr = tSUBi8 killed renamable $r3, 16, 14 /* CC::al */, $noreg + ; CHECK-NEXT: $lr = t2LEUpdate killed renamable $lr, %bb.2 + ; CHECK-NEXT: {{ $}} + ; CHECK-NEXT: bb.3.while.end: + ; CHECK-NEXT: liveins: $r12 + ; CHECK-NEXT: {{ $}} + ; CHECK-NEXT: renamable $r0 = t2UXTB killed renamable $r12, 0, 14 /* CC::al */, $noreg + ; CHECK-NEXT: frame-destroy tPOP_RET 14 /* CC::al */, $noreg, def $r7, def $pc, implicit killed $r0 + bb.0.entry: + successors: %bb.1(0x50000000), %bb.3(0x30000000) + liveins: $q0, $r0, $r1, $r3, $r7, $lr + + frame-setup tPUSH 14 /* CC::al */, $noreg, $r7, killed $lr, implicit-def $sp, implicit $sp + frame-setup CFI_INSTRUCTION def_cfa_offset 8 + frame-setup CFI_INSTRUCTION offset $lr, -4 + frame-setup CFI_INSTRUCTION offset $r7, -8 + $r7 = frame-setup tMOVr $sp, 14 /* CC::al */, $noreg + frame-setup CFI_INSTRUCTION def_cfa_register $r7 + tCMPi8 renamable $r3, 1, 14 /* CC::al */, $noreg, implicit-def $cpsr + renamable $r12 = t2MOVi 0, 14 /* CC::al */, $noreg, $noreg + tBcc %bb.3, 11 /* CC::lt */, killed $cpsr + + bb.1.while.body.preheader: + successors: %bb.2(0x80000000) + liveins: $q0, $r0, $r1, $r3, $r12 + + renamable $r2 = t2SUBri renamable $r3, 16, 14 /* CC::al */, $noreg, def $cpsr + renamable $r2 = t2CSEL killed renamable $r2, renamable $r12, 2, implicit killed $cpsr + renamable $lr = t2ADDri killed renamable $r2, 15, 14 /* CC::al */, $noreg, $noreg + renamable $r2, dead $cpsr = tMOVi8 1, 14 /* CC::al */, $noreg + renamable $r2 = nuw nsw t2ADDrs killed renamable $r2, killed renamable $lr, 35, 14 /* CC::al */, $noreg, $noreg + renamable $lr = t2DoLoopStartTP killed renamable $r2, renamable $r3 + + bb.2.while.body (align 4): + successors: %bb.2(0x7c000000), %bb.3(0x04000000) + liveins: $lr, $q0, $r0, $r1, $r3, $r12 + + renamable $vpr = MVE_VCTP8 renamable $r3, 0, $noreg, $noreg + MVE_VPST 4, implicit $vpr + renamable $r0, renamable $q1 = MVE_VLDRBU8_post killed renamable $r0, 16, 1, renamable $vpr, renamable $lr :: (load unknown-size from %ir.a.addr.014, align 1) + renamable $r1, renamable $q2 = MVE_VLDRBU8_post killed renamable $r1, 16, 1, renamable $vpr, renamable $lr :: (load unknown-size from %ir.b.addr.013, align 1) + $q3 = MQPRCopy $q0 + MVE_VPST 8, implicit $vpr + renamable $q3 = MVE_VADDi8 killed renamable $q1, killed renamable $q2, 1, killed renamable $vpr, renamable $lr, killed renamable $q3 + renamable $r12 = MVE_VADDVu8acc killed renamable $r12, killed renamable $q3, 0, $noreg, renamable $lr + renamable $r3, dead $cpsr = tSUBi8 killed renamable $r3, 16, 14 /* CC::al */, $noreg + renamable $lr = t2LoopEndDec killed renamable $lr, %bb.2, implicit-def dead $cpsr + tB %bb.3, 14 /* CC::al */, $noreg + + bb.3.while.end: + liveins: $r12 + + renamable $r0 = t2UXTB killed renamable $r12, 0, 14 /* CC::al */, $noreg + frame-destroy tPOP_RET 14 /* CC::al */, $noreg, def $r7, def $pc, implicit killed $r0 + +...