diff --git a/llvm/lib/Target/AArch64/AArch64SystemOperands.td b/llvm/lib/Target/AArch64/AArch64SystemOperands.td
--- a/llvm/lib/Target/AArch64/AArch64SystemOperands.td
+++ b/llvm/lib/Target/AArch64/AArch64SystemOperands.td
@@ -1698,8 +1698,8 @@
 def : RWSysReg<"CNTISCALE_EL2",    0b11, 0b100, 0b1110, 0b0000, 0b101>;
 def : RWSysReg<"CNTPOFF_EL2",      0b11, 0b100, 0b1110, 0b0000, 0b110>;
 def : RWSysReg<"CNTVFRQ_EL2",      0b11, 0b100, 0b1110, 0b0000, 0b111>;
-def : RWSysReg<"CNTPCTSS_EL0",     0b11, 0b011, 0b1110, 0b0000, 0b101>;
-def : RWSysReg<"CNTVCTSS_EL0",     0b11, 0b011, 0b1110, 0b0000, 0b110>;
+def : ROSysReg<"CNTPCTSS_EL0",     0b11, 0b011, 0b1110, 0b0000, 0b101>;
+def : ROSysReg<"CNTVCTSS_EL0",     0b11, 0b011, 0b1110, 0b0000, 0b110>;
 }
 
 // v8.7a LD64B/ST64B Accelerator Extension system register
diff --git a/llvm/test/MC/AArch64/armv8.6a-ecv.s b/llvm/test/MC/AArch64/armv8.6a-ecv.s
--- a/llvm/test/MC/AArch64/armv8.6a-ecv.s
+++ b/llvm/test/MC/AArch64/armv8.6a-ecv.s
@@ -1,25 +1,35 @@
-// RUN:     llvm-mc -triple aarch64 -show-encoding -mattr=+ecv   < %s | FileCheck %s
-// RUN:     llvm-mc -triple aarch64 -show-encoding -mattr=+v8.6a < %s | FileCheck %s
-// RUN: not llvm-mc -triple aarch64 -show-encoding  < %s 2>&1         | FileCheck %s --check-prefix=NOECV
+// RUN: not llvm-mc -triple aarch64 -show-encoding -mattr=+ecv   < %s 2> %t | FileCheck %s
+// RUN: FileCheck --check-prefix=ERROR %s < %t
+// RUN: not llvm-mc -triple aarch64 -show-encoding -mattr=+v8.6a < %s 2> %t | FileCheck %s
+// RUN: FileCheck --check-prefix=ERROR %s < %t
+// RUN: not llvm-mc -triple aarch64 -show-encoding               < %s 2> %t | FileCheck --check-prefix=NOECV-OUT %s
+// RUN: FileCheck --check-prefix=NOECV %s < %t
 
+// Expect no successful code generation at all with ECV disabled
+// NOECV-OUT-NOT: {{msr|mrs}}
+
+// Writable system registers
 msr CNTSCALE_EL2, x1
 msr CNTISCALE_EL2, x11
 msr CNTPOFF_EL2, x22
 msr CNTVFRQ_EL2, x3
-msr CNTPCTSS_EL0, x13
-msr CNTVCTSS_EL0, x23
 // CHECK: msr     CNTSCALE_EL2, x1        // encoding: [0x81,0xe0,0x1c,0xd5]
 // CHECK: msr     CNTISCALE_EL2, x11      // encoding: [0xab,0xe0,0x1c,0xd5]
 // CHECK: msr     CNTPOFF_EL2, x22        // encoding: [0xd6,0xe0,0x1c,0xd5]
 // CHECK: msr     CNTVFRQ_EL2, x3         // encoding: [0xe3,0xe0,0x1c,0xd5]
-// CHECK: msr     CNTPCTSS_EL0, x13       // encoding: [0xad,0xe0,0x1b,0xd5]
-// CHECK: msr     CNTVCTSS_EL0, x23       // encoding: [0xd7,0xe0,0x1b,0xd5]
-// NOECV: error: expected writable system register or pstate
-// NOECV: error: expected writable system register or pstate
-// NOECV: error: expected writable system register or pstate
-// NOECV: error: expected writable system register or pstate
-// NOECV: error: expected writable system register or pstate
-// NOECV: error: expected writable system register or pstate
+// NOECV: :[[@LINE-8]]:5: error: expected writable system register or pstate
+// NOECV: :[[@LINE-8]]:5: error: expected writable system register or pstate
+// NOECV: :[[@LINE-8]]:5: error: expected writable system register or pstate
+// NOECV: :[[@LINE-8]]:5: error: expected writable system register or pstate
+
+// Readonly system registers: writing them gives an error even with
+// ECV enabled
+msr CNTPCTSS_EL0, x13
+msr CNTVCTSS_EL0, x23
+// ERROR: :[[@LINE-2]]:5: error: expected writable system register or pstate
+// ERROR: :[[@LINE-2]]:5: error: expected writable system register or pstate
+// NOECV: :[[@LINE-4]]:5: error: expected writable system register or pstate
+// NOECV: :[[@LINE-4]]:5: error: expected writable system register or pstate
 
 mrs x0, CNTSCALE_EL2
 mrs x5, CNTISCALE_EL2
@@ -33,9 +43,9 @@
 // CHECK: mrs     x15, CNTVFRQ_EL2        // encoding: [0xef,0xe0,0x3c,0xd5]
 // CHECK: mrs     x20, CNTPCTSS_EL0       // encoding: [0xb4,0xe0,0x3b,0xd5]
 // CHECK: mrs     x30, CNTVCTSS_EL0       // encoding: [0xde,0xe0,0x3b,0xd5]
-// NOECV: error: expected readable system register
-// NOECV: error: expected readable system register
-// NOECV: error: expected readable system register
-// NOECV: error: expected readable system register
-// NOECV: error: expected readable system register
-// NOECV: error: expected readable system register
+// NOECV: :[[@LINE-12]]:9: error: expected readable system register
+// NOECV: :[[@LINE-12]]:9: error: expected readable system register
+// NOECV: :[[@LINE-12]]:10: error: expected readable system register
+// NOECV: :[[@LINE-12]]:10: error: expected readable system register
+// NOECV: :[[@LINE-12]]:10: error: expected readable system register
+// NOECV: :[[@LINE-12]]:10: error: expected readable system register
diff --git a/llvm/test/MC/Disassembler/AArch64/armv8.6a-ecv.txt b/llvm/test/MC/Disassembler/AArch64/armv8.6a-ecv.txt
--- a/llvm/test/MC/Disassembler/AArch64/armv8.6a-ecv.txt
+++ b/llvm/test/MC/Disassembler/AArch64/armv8.6a-ecv.txt
@@ -11,8 +11,8 @@
 # CHECK: msr CNTISCALE_EL2, x11
 # CHECK: msr CNTPOFF_EL2, x22
 # CHECK: msr CNTVFRQ_EL2, x3
-# CHECK: msr CNTPCTSS_EL0, x13
-# CHECK: msr CNTVCTSS_EL0, x23
+# CHECK: msr S3_3_C14_C0_5, x13
+# CHECK: msr S3_3_C14_C0_6, x23
 # NOFGT: msr S3_4_C14_C0_4, x1
 # NOFGT: msr S3_4_C14_C0_5, x11
 # NOFGT: msr S3_4_C14_C0_6, x22