diff --git a/llvm/include/llvm/CodeGen/FastISel.h b/llvm/include/llvm/CodeGen/FastISel.h --- a/llvm/include/llvm/CodeGen/FastISel.h +++ b/llvm/include/llvm/CodeGen/FastISel.h @@ -213,7 +213,6 @@ const TargetRegisterInfo &TRI; const TargetLibraryInfo *LibInfo; bool SkipTargetIndependentISel; - bool UseInstrRefDebugInfo = false; /// The position of the last instruction for materializing constants /// for use in the current block. It resets to EmitStartPt when it makes sense @@ -320,12 +319,6 @@ /// Reset InsertPt to the given old insert position. void leaveLocalValueArea(SavePoint Old); - /// Signal whether instruction referencing variable locations are desired for - /// this function's debug-info. - void useInstrRefDebugInfo(bool Flag) { - UseInstrRefDebugInfo = Flag; - } - protected: explicit FastISel(FunctionLoweringInfo &FuncInfo, const TargetLibraryInfo *LibInfo, diff --git a/llvm/include/llvm/CodeGen/MIRYamlMapping.h b/llvm/include/llvm/CodeGen/MIRYamlMapping.h --- a/llvm/include/llvm/CodeGen/MIRYamlMapping.h +++ b/llvm/include/llvm/CodeGen/MIRYamlMapping.h @@ -707,6 +707,7 @@ bool FailsVerification = false; bool TracksDebugUserValues = false; + bool UseDebugInstrRef = false; std::vector VirtualRegisters; std::vector LiveIns; std::optional> CalleeSavedRegisters; @@ -741,6 +742,7 @@ YamlIO.mapOptional("hasEHCatchret", MF.HasEHCatchret, false); YamlIO.mapOptional("hasEHScopes", MF.HasEHScopes, false); YamlIO.mapOptional("hasEHFunclets", MF.HasEHFunclets, false); + YamlIO.mapOptional("debugInstrRef", MF.UseDebugInstrRef, false); YamlIO.mapOptional("failsVerification", MF.FailsVerification, false); YamlIO.mapOptional("tracksDebugUserValues", MF.TracksDebugUserValues, diff --git a/llvm/include/llvm/CodeGen/MachineFunction.h b/llvm/include/llvm/CodeGen/MachineFunction.h --- a/llvm/include/llvm/CodeGen/MachineFunction.h +++ b/llvm/include/llvm/CodeGen/MachineFunction.h @@ -527,6 +527,10 @@ /// during register allocation. See DebugPHIRegallocPos. DenseMap DebugPHIPositions; + /// Flag for whether this function contains DBG_VALUEs (false) or + /// DBG_INSTR_REF (true). + bool UseDebugInstrRef = false; + /// Create a substitution between one value to a different, /// new value. void makeDebugValueSubstitution(DebugInstrOperandPair, DebugInstrOperandPair, @@ -567,10 +571,17 @@ /// (or DBG_PHI). void finalizeDebugInstrRefs(); - /// Returns true if the function's variable locations should be tracked with + /// Determine whether, in the current machine configuration, we should use + /// instruction referencing or not. + bool shouldUseDebugInstrRef() const; + + /// Returns true if the function's variable locations are tracked with /// instruction referencing. bool useDebugInstrRef() const; + /// Set whether this function will use instruction referencing or not. + void setUseDebugInstrRef(bool UseInstrRef); + /// A reserved operand number representing the instructions memory operand, /// for instructions that have a stack spill fused into them. const static unsigned int DebugOperandMemNumber; diff --git a/llvm/include/llvm/CodeGen/SelectionDAG.h b/llvm/include/llvm/CodeGen/SelectionDAG.h --- a/llvm/include/llvm/CodeGen/SelectionDAG.h +++ b/llvm/include/llvm/CodeGen/SelectionDAG.h @@ -293,9 +293,6 @@ /// benefits (see discussion with @thakis in D120714). uint16_t NextPersistentId = 0; - /// Are instruction referencing variable locations desired for this function? - bool UseInstrRefDebugInfo = false; - public: /// Clients of various APIs that cause global effects on /// the DAG can optionally implement this interface. This allows the clients @@ -1901,16 +1898,6 @@ /// function mirrors \c llvm::salvageDebugInfo. void salvageDebugInfo(SDNode &N); - /// Signal whether instruction referencing variable locations are desired for - /// this function's debug-info. - void useInstrRefDebugInfo(bool Flag) { - UseInstrRefDebugInfo = Flag; - } - - bool getUseInstrRefDebugInfo() const { - return UseInstrRefDebugInfo; - } - void dump() const; /// In most cases this function returns the ABI alignment for a given type, diff --git a/llvm/include/llvm/CodeGen/SelectionDAGISel.h b/llvm/include/llvm/CodeGen/SelectionDAGISel.h --- a/llvm/include/llvm/CodeGen/SelectionDAGISel.h +++ b/llvm/include/llvm/CodeGen/SelectionDAGISel.h @@ -56,7 +56,6 @@ const TargetLowering *TLI; bool FastISelFailed; SmallPtrSet ElidedArgCopyInstrs; - bool UseInstrRefDebugInfo = false; /// Current optimization remark emitter. /// Used to report things like combines and FastISel failures. diff --git a/llvm/lib/CodeGen/MIRParser/MIRParser.cpp b/llvm/lib/CodeGen/MIRParser/MIRParser.cpp --- a/llvm/lib/CodeGen/MIRParser/MIRParser.cpp +++ b/llvm/lib/CodeGen/MIRParser/MIRParser.cpp @@ -443,6 +443,9 @@ MF.makeDebugValueSubstitution({Sub.SrcInst, Sub.SrcOp}, {Sub.DstInst, Sub.DstOp}, Sub.Subreg); } + + // Flag for whether we're supposed to be using DBG_INSTR_REF. + MF.setUseDebugInstrRef(YamlMF.UseDebugInstrRef); } bool diff --git a/llvm/lib/CodeGen/MIRPrinter.cpp b/llvm/lib/CodeGen/MIRPrinter.cpp --- a/llvm/lib/CodeGen/MIRPrinter.cpp +++ b/llvm/lib/CodeGen/MIRPrinter.cpp @@ -200,6 +200,7 @@ YamlMF.HasEHCatchret = MF.hasEHCatchret(); YamlMF.HasEHScopes = MF.hasEHScopes(); YamlMF.HasEHFunclets = MF.hasEHFunclets(); + YamlMF.UseDebugInstrRef = MF.useDebugInstrRef(); YamlMF.Legalized = MF.getProperties().hasProperty( MachineFunctionProperties::Property::Legalized); diff --git a/llvm/lib/CodeGen/MachineFunction.cpp b/llvm/lib/CodeGen/MachineFunction.cpp --- a/llvm/lib/CodeGen/MachineFunction.cpp +++ b/llvm/lib/CodeGen/MachineFunction.cpp @@ -1195,7 +1195,7 @@ } } -bool MachineFunction::useDebugInstrRef() const { +bool MachineFunction::shouldUseDebugInstrRef() const { // Disable instr-ref at -O0: it's very slow (in compile time). We can still // have optimized code inlined into this unoptimized code, however with // fewer and less aggressive optimizations happening, coverage and accuracy @@ -1213,6 +1213,14 @@ return false; } +bool MachineFunction::useDebugInstrRef() const { + return UseDebugInstrRef; +} + +void MachineFunction::setUseDebugInstrRef(bool Use) { + UseDebugInstrRef = Use; +} + // Use one million as a high / reserved number. const unsigned MachineFunction::DebugOperandMemNumber = 1000000; diff --git a/llvm/lib/CodeGen/SelectionDAG/FastISel.cpp b/llvm/lib/CodeGen/SelectionDAG/FastISel.cpp --- a/llvm/lib/CodeGen/SelectionDAG/FastISel.cpp +++ b/llvm/lib/CodeGen/SelectionDAG/FastISel.cpp @@ -1247,7 +1247,7 @@ if (Op) { assert(DI->getVariable()->isValidLocationForIntrinsic(MIMD.getDL()) && "Expected inlined-at fields to agree"); - if (UseInstrRefDebugInfo && Op->isReg()) { + if (FuncInfo.MF->useDebugInstrRef() && Op->isReg()) { // If using instruction referencing, produce this as a DBG_INSTR_REF, // to be later patched up by finalizeDebugInstrRefs. Tack a deref onto // the expression, we don't have an "indirect" flag in DBG_INSTR_REF. @@ -1309,7 +1309,7 @@ .addMetadata(DI->getExpression()); } else if (Register Reg = lookUpRegForValue(V)) { // FIXME: This does not handle register-indirect values at offset 0. - if (!UseInstrRefDebugInfo) { + if (!FuncInfo.MF->useDebugInstrRef()) { bool IsIndirect = false; BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, MIMD.getDL(), II, IsIndirect, Reg, DI->getVariable(), DI->getExpression()); diff --git a/llvm/lib/CodeGen/SelectionDAG/InstrEmitter.h b/llvm/lib/CodeGen/SelectionDAG/InstrEmitter.h --- a/llvm/lib/CodeGen/SelectionDAG/InstrEmitter.h +++ b/llvm/lib/CodeGen/SelectionDAG/InstrEmitter.h @@ -156,8 +156,7 @@ /// InstrEmitter - Construct an InstrEmitter and set it to start inserting /// at the given position in the given block. InstrEmitter(const TargetMachine &TM, MachineBasicBlock *mbb, - MachineBasicBlock::iterator insertpos, - bool UseInstrRefDebugInfo); + MachineBasicBlock::iterator insertpos); private: void EmitMachineNode(SDNode *Node, bool IsClone, bool IsCloned, diff --git a/llvm/lib/CodeGen/SelectionDAG/InstrEmitter.cpp b/llvm/lib/CodeGen/SelectionDAG/InstrEmitter.cpp --- a/llvm/lib/CodeGen/SelectionDAG/InstrEmitter.cpp +++ b/llvm/lib/CodeGen/SelectionDAG/InstrEmitter.cpp @@ -1395,12 +1395,11 @@ /// InstrEmitter - Construct an InstrEmitter and set it to start inserting /// at the given position in the given block. InstrEmitter::InstrEmitter(const TargetMachine &TM, MachineBasicBlock *mbb, - MachineBasicBlock::iterator insertpos, - bool UseInstrRefDebugInfo) + MachineBasicBlock::iterator insertpos) : MF(mbb->getParent()), MRI(&MF->getRegInfo()), TII(MF->getSubtarget().getInstrInfo()), TRI(MF->getSubtarget().getRegisterInfo()), TLI(MF->getSubtarget().getTargetLowering()), MBB(mbb), InsertPos(insertpos) { - EmitDebugInstrRefs = UseInstrRefDebugInfo; + EmitDebugInstrRefs = mbb->getParent()->useDebugInstrRef(); } diff --git a/llvm/lib/CodeGen/SelectionDAG/ScheduleDAGFast.cpp b/llvm/lib/CodeGen/SelectionDAG/ScheduleDAGFast.cpp --- a/llvm/lib/CodeGen/SelectionDAG/ScheduleDAGFast.cpp +++ b/llvm/lib/CodeGen/SelectionDAG/ScheduleDAGFast.cpp @@ -778,8 +778,7 @@ MachineBasicBlock* ScheduleDAGLinearize::EmitSchedule(MachineBasicBlock::iterator &InsertPos) { - InstrEmitter Emitter(DAG->getTarget(), BB, InsertPos, - DAG->getUseInstrRefDebugInfo()); + InstrEmitter Emitter(DAG->getTarget(), BB, InsertPos); DenseMap VRBaseMap; LLVM_DEBUG({ dbgs() << "\n*** Final schedule ***\n"; }); diff --git a/llvm/lib/CodeGen/SelectionDAG/ScheduleDAGSDNodes.cpp b/llvm/lib/CodeGen/SelectionDAG/ScheduleDAGSDNodes.cpp --- a/llvm/lib/CodeGen/SelectionDAG/ScheduleDAGSDNodes.cpp +++ b/llvm/lib/CodeGen/SelectionDAG/ScheduleDAGSDNodes.cpp @@ -848,8 +848,7 @@ /// not necessarily refer to returned BB. The emitter may split blocks. MachineBasicBlock *ScheduleDAGSDNodes:: EmitSchedule(MachineBasicBlock::iterator &InsertPos) { - InstrEmitter Emitter(DAG->getTarget(), BB, InsertPos, - DAG->getUseInstrRefDebugInfo()); + InstrEmitter Emitter(DAG->getTarget(), BB, InsertPos); DenseMap VRBaseMap; DenseMap CopyVRBaseMap; SmallVector, 32> Orders; diff --git a/llvm/lib/CodeGen/SelectionDAG/SelectionDAGISel.cpp b/llvm/lib/CodeGen/SelectionDAG/SelectionDAGISel.cpp --- a/llvm/lib/CodeGen/SelectionDAG/SelectionDAGISel.cpp +++ b/llvm/lib/CodeGen/SelectionDAG/SelectionDAGISel.cpp @@ -392,8 +392,8 @@ // Decide what flavour of variable location debug-info will be used, before // we change the optimisation level. - UseInstrRefDebugInfo = mf.useDebugInstrRef(); - CurDAG->useInstrRefDebugInfo(UseInstrRefDebugInfo); + bool InstrRef = mf.shouldUseDebugInstrRef(); + mf.setUseDebugInstrRef(InstrRef); // Reset the target options before resetting the optimization // level below. @@ -546,7 +546,6 @@ LiveInMap.insert(LI); // Insert DBG_VALUE instructions for function arguments to the entry block. - bool InstrRef = MF->useDebugInstrRef(); for (unsigned i = 0, e = FuncInfo->ArgDbgValues.size(); i != e; ++i) { MachineInstr *MI = FuncInfo->ArgDbgValues[e - i - 1]; assert(MI->getOpcode() != TargetOpcode::DBG_VALUE_LIST && @@ -624,7 +623,7 @@ // For debug-info, in instruction referencing mode, we need to perform some // post-isel maintenence. - if (UseInstrRefDebugInfo) + if (MF->useDebugInstrRef()) MF->finalizeDebugInstrRefs(); // Determine if there are any calls in this machine function. @@ -1380,8 +1379,6 @@ if (TM.Options.EnableFastISel) { LLVM_DEBUG(dbgs() << "Enabling fast-isel\n"); FastIS = TLI->createFastISel(*FuncInfo, LibInfo); - if (FastIS) - FastIS->useInstrRefDebugInfo(UseInstrRefDebugInfo); } ReversePostOrderTraversal RPOT(&Fn); diff --git a/llvm/test/CodeGen/X86/dbg-value-superreg-copy2.mir b/llvm/test/CodeGen/X86/dbg-value-superreg-copy2.mir --- a/llvm/test/CodeGen/X86/dbg-value-superreg-copy2.mir +++ b/llvm/test/CodeGen/X86/dbg-value-superreg-copy2.mir @@ -32,6 +32,7 @@ --- name: foo tracksRegLiveness: true +debugInstrRef: true debugValueSubstitutions: - { srcinst: 2, srcop: 0, dstinst: 1, dstop: 0, subreg: 2 } body: | diff --git a/llvm/test/DebugInfo/MIR/InstrRef/accept-nonlive-reg-phis.mir b/llvm/test/DebugInfo/MIR/InstrRef/accept-nonlive-reg-phis.mir --- a/llvm/test/DebugInfo/MIR/InstrRef/accept-nonlive-reg-phis.mir +++ b/llvm/test/DebugInfo/MIR/InstrRef/accept-nonlive-reg-phis.mir @@ -73,6 +73,7 @@ alignment: 16 tracksRegLiveness: true tracksDebugUserValues: true +debugInstrRef: true frameInfo: maxAlignment: 4 machineFunctionInfo: {} diff --git a/llvm/test/DebugInfo/MIR/InstrRef/dbg-phi-subregister-location.mir b/llvm/test/DebugInfo/MIR/InstrRef/dbg-phi-subregister-location.mir --- a/llvm/test/DebugInfo/MIR/InstrRef/dbg-phi-subregister-location.mir +++ b/llvm/test/DebugInfo/MIR/InstrRef/dbg-phi-subregister-location.mir @@ -50,6 +50,7 @@ name: foo alignment: 16 tracksRegLiveness: true +debugInstrRef: true liveins: - { reg: '$edi' } frameInfo: diff --git a/llvm/test/DebugInfo/MIR/InstrRef/dbg-phis-in-ldv.mir b/llvm/test/DebugInfo/MIR/InstrRef/dbg-phis-in-ldv.mir --- a/llvm/test/DebugInfo/MIR/InstrRef/dbg-phis-in-ldv.mir +++ b/llvm/test/DebugInfo/MIR/InstrRef/dbg-phis-in-ldv.mir @@ -86,6 +86,7 @@ name: foo alignment: 16 tracksRegLiveness: true +debugInstrRef: true liveins: - { reg: '$rdi' } - { reg: '$rsi' } diff --git a/llvm/test/DebugInfo/MIR/InstrRef/dbg-phis-in-ldv2.mir b/llvm/test/DebugInfo/MIR/InstrRef/dbg-phis-in-ldv2.mir --- a/llvm/test/DebugInfo/MIR/InstrRef/dbg-phis-in-ldv2.mir +++ b/llvm/test/DebugInfo/MIR/InstrRef/dbg-phis-in-ldv2.mir @@ -45,6 +45,7 @@ name: foo alignment: 16 tracksRegLiveness: true +debugInstrRef: true liveins: - { reg: '$rdi' } - { reg: '$rsi' } diff --git a/llvm/test/DebugInfo/MIR/InstrRef/dbg-phis-merging-in-ldv.mir b/llvm/test/DebugInfo/MIR/InstrRef/dbg-phis-merging-in-ldv.mir --- a/llvm/test/DebugInfo/MIR/InstrRef/dbg-phis-merging-in-ldv.mir +++ b/llvm/test/DebugInfo/MIR/InstrRef/dbg-phis-merging-in-ldv.mir @@ -98,6 +98,7 @@ name: foo alignment: 16 tracksRegLiveness: true +debugInstrRef: true liveins: - { reg: '$rdi' } - { reg: '$rsi' } diff --git a/llvm/test/DebugInfo/MIR/InstrRef/dbg-phis-with-loops.mir b/llvm/test/DebugInfo/MIR/InstrRef/dbg-phis-with-loops.mir --- a/llvm/test/DebugInfo/MIR/InstrRef/dbg-phis-with-loops.mir +++ b/llvm/test/DebugInfo/MIR/InstrRef/dbg-phis-with-loops.mir @@ -99,6 +99,7 @@ name: foo alignment: 16 tracksRegLiveness: true +debugInstrRef: true liveins: - { reg: '$rdi' } - { reg: '$rsi' } diff --git a/llvm/test/DebugInfo/MIR/InstrRef/deref-spills-with-size.mir b/llvm/test/DebugInfo/MIR/InstrRef/deref-spills-with-size.mir --- a/llvm/test/DebugInfo/MIR/InstrRef/deref-spills-with-size.mir +++ b/llvm/test/DebugInfo/MIR/InstrRef/deref-spills-with-size.mir @@ -138,6 +138,7 @@ name: _ZNSt5dequeIPN4llvm4LoopESaIS2_EE13_M_insert_auxESt15_Deque_iteratorIS2_RS2_PS2_EmRKS2_ alignment: 16 tracksRegLiveness: true +debugInstrRef: true liveins: - { reg: '$rdi' } - { reg: '$rsi' } diff --git a/llvm/test/DebugInfo/MIR/InstrRef/follow-spill-of-indir-value.mir b/llvm/test/DebugInfo/MIR/InstrRef/follow-spill-of-indir-value.mir --- a/llvm/test/DebugInfo/MIR/InstrRef/follow-spill-of-indir-value.mir +++ b/llvm/test/DebugInfo/MIR/InstrRef/follow-spill-of-indir-value.mir @@ -99,6 +99,7 @@ name: _Z3foo10NonTrivial alignment: 16 tracksRegLiveness: true +debugInstrRef: true tracksDebugUserValues: true liveins: - { reg: '$rdi' } diff --git a/llvm/test/DebugInfo/MIR/InstrRef/follow-spill-of-live-value.mir b/llvm/test/DebugInfo/MIR/InstrRef/follow-spill-of-live-value.mir --- a/llvm/test/DebugInfo/MIR/InstrRef/follow-spill-of-live-value.mir +++ b/llvm/test/DebugInfo/MIR/InstrRef/follow-spill-of-live-value.mir @@ -178,6 +178,7 @@ name: _ZNSt5dequeIPN4llvm4LoopESaIS2_EE13_M_insert_auxESt15_Deque_iteratorIS2_RS2_PS2_EmRKS2_ alignment: 16 tracksRegLiveness: true +debugInstrRef: true liveins: - { reg: '$rdi' } - { reg: '$rsi' } diff --git a/llvm/test/DebugInfo/MIR/InstrRef/instr-ref-roundtrip.mir b/llvm/test/DebugInfo/MIR/InstrRef/instr-ref-roundtrip.mir --- a/llvm/test/DebugInfo/MIR/InstrRef/instr-ref-roundtrip.mir +++ b/llvm/test/DebugInfo/MIR/InstrRef/instr-ref-roundtrip.mir @@ -2,10 +2,12 @@ # # REQUIRES: x86-registered-target # +# CHECK: debugInstrRef: true # CHECK: MOV64rr $rdi, debug-instr-number 1 --- name: test tracksRegLiveness: true +debugInstrRef: true liveins: - { reg: '$rdi', virtual-reg: '' } body: | diff --git a/llvm/test/DebugInfo/MIR/InstrRef/livedebugvalues-transfer-variadic-instr-ref.mir b/llvm/test/DebugInfo/MIR/InstrRef/livedebugvalues-transfer-variadic-instr-ref.mir --- a/llvm/test/DebugInfo/MIR/InstrRef/livedebugvalues-transfer-variadic-instr-ref.mir +++ b/llvm/test/DebugInfo/MIR/InstrRef/livedebugvalues-transfer-variadic-instr-ref.mir @@ -155,6 +155,7 @@ alignment: 16 tracksRegLiveness: true tracksDebugUserValues: true +debugInstrRef: true registers: [] liveins: - { reg: '$edi', virtual-reg: '' } diff --git a/llvm/test/DebugInfo/MIR/InstrRef/livedebugvalues_illegal_locs.mir b/llvm/test/DebugInfo/MIR/InstrRef/livedebugvalues_illegal_locs.mir --- a/llvm/test/DebugInfo/MIR/InstrRef/livedebugvalues_illegal_locs.mir +++ b/llvm/test/DebugInfo/MIR/InstrRef/livedebugvalues_illegal_locs.mir @@ -37,6 +37,7 @@ ... --- name: _Z8bb_to_bb +debugInstrRef: true debugValueSubstitutions: - { srcinst: 4, srcop: 0, dstinst: 3, dstop: 0, subreg: 0 } body: | diff --git a/llvm/test/DebugInfo/MIR/InstrRef/livedebugvalues_instrref_tolocs.mir b/llvm/test/DebugInfo/MIR/InstrRef/livedebugvalues_instrref_tolocs.mir --- a/llvm/test/DebugInfo/MIR/InstrRef/livedebugvalues_instrref_tolocs.mir +++ b/llvm/test/DebugInfo/MIR/InstrRef/livedebugvalues_instrref_tolocs.mir @@ -31,6 +31,7 @@ ... --- name: _Z8bb_to_bb +debugInstrRef: true debugValueSubstitutions: - { srcinst: 4, srcop: 0, dstinst: 3, dstop: 0, subreg: 0 } body: | diff --git a/llvm/test/DebugInfo/MIR/InstrRef/livedebugvalues_recover_clobbers.mir b/llvm/test/DebugInfo/MIR/InstrRef/livedebugvalues_recover_clobbers.mir --- a/llvm/test/DebugInfo/MIR/InstrRef/livedebugvalues_recover_clobbers.mir +++ b/llvm/test/DebugInfo/MIR/InstrRef/livedebugvalues_recover_clobbers.mir @@ -50,6 +50,7 @@ ... --- name: _Z8bb_to_bb +debugInstrRef: true stack: - { id: 0, type: spill-slot, offset: -12, size: 4, alignment: 4 } body: | diff --git a/llvm/test/DebugInfo/MIR/InstrRef/livedebugvalues_stackslot_subregs.mir b/llvm/test/DebugInfo/MIR/InstrRef/livedebugvalues_stackslot_subregs.mir --- a/llvm/test/DebugInfo/MIR/InstrRef/livedebugvalues_stackslot_subregs.mir +++ b/llvm/test/DebugInfo/MIR/InstrRef/livedebugvalues_stackslot_subregs.mir @@ -29,6 +29,7 @@ --- name: test tracksRegLiveness: true +debugInstrRef: true liveins: - { reg: '$rdi', virtual-reg: '' } stack: diff --git a/llvm/test/DebugInfo/MIR/InstrRef/livedebugvalues_subreg_substitutions.mir b/llvm/test/DebugInfo/MIR/InstrRef/livedebugvalues_subreg_substitutions.mir --- a/llvm/test/DebugInfo/MIR/InstrRef/livedebugvalues_subreg_substitutions.mir +++ b/llvm/test/DebugInfo/MIR/InstrRef/livedebugvalues_subreg_substitutions.mir @@ -31,6 +31,7 @@ --- name: test tracksRegLiveness: true +debugInstrRef: true liveins: - { reg: '$rdi', virtual-reg: '' } debugValueSubstitutions: diff --git a/llvm/test/DebugInfo/MIR/InstrRef/memory-operand-folding-tieddef.mir b/llvm/test/DebugInfo/MIR/InstrRef/memory-operand-folding-tieddef.mir --- a/llvm/test/DebugInfo/MIR/InstrRef/memory-operand-folding-tieddef.mir +++ b/llvm/test/DebugInfo/MIR/InstrRef/memory-operand-folding-tieddef.mir @@ -57,6 +57,7 @@ name: _ZNK4llvm5APInt5magicEv alignment: 16 tracksRegLiveness: true +debugInstrRef: true registers: - { id: 0, class: gr64 } - { id: 1, class: gr32 } diff --git a/llvm/test/DebugInfo/MIR/InstrRef/memory-operand-folding.mir b/llvm/test/DebugInfo/MIR/InstrRef/memory-operand-folding.mir --- a/llvm/test/DebugInfo/MIR/InstrRef/memory-operand-folding.mir +++ b/llvm/test/DebugInfo/MIR/InstrRef/memory-operand-folding.mir @@ -49,6 +49,7 @@ --- name: beans tracksRegLiveness: True +debugInstrRef: true body: | bb.0: liveins: $edi diff --git a/llvm/test/DebugInfo/MIR/InstrRef/memory-operand-load-folding.mir b/llvm/test/DebugInfo/MIR/InstrRef/memory-operand-load-folding.mir --- a/llvm/test/DebugInfo/MIR/InstrRef/memory-operand-load-folding.mir +++ b/llvm/test/DebugInfo/MIR/InstrRef/memory-operand-load-folding.mir @@ -68,6 +68,7 @@ --- name: foo tracksRegLiveness: true +debugInstrRef: true registers: - { id: 0, class: gr32, preferred-register: '' } - { id: 1, class: fr32, preferred-register: '' } diff --git a/llvm/test/DebugInfo/MIR/InstrRef/memory-operand-tracking.mir b/llvm/test/DebugInfo/MIR/InstrRef/memory-operand-tracking.mir --- a/llvm/test/DebugInfo/MIR/InstrRef/memory-operand-tracking.mir +++ b/llvm/test/DebugInfo/MIR/InstrRef/memory-operand-tracking.mir @@ -36,6 +36,7 @@ --- name: test tracksRegLiveness: true +debugInstrRef: true liveins: - { reg: '$rdi', virtual-reg: '' } debugValueSubstitutions: diff --git a/llvm/test/DebugInfo/MIR/InstrRef/no-duplicates.mir b/llvm/test/DebugInfo/MIR/InstrRef/no-duplicates.mir --- a/llvm/test/DebugInfo/MIR/InstrRef/no-duplicates.mir +++ b/llvm/test/DebugInfo/MIR/InstrRef/no-duplicates.mir @@ -28,6 +28,7 @@ --- name: test tracksRegLiveness: true +debugInstrRef: true liveins: - { reg: '$rdi', virtual-reg: '' } body: | diff --git a/llvm/test/DebugInfo/MIR/InstrRef/no-metainstrs.mir b/llvm/test/DebugInfo/MIR/InstrRef/no-metainstrs.mir --- a/llvm/test/DebugInfo/MIR/InstrRef/no-metainstrs.mir +++ b/llvm/test/DebugInfo/MIR/InstrRef/no-metainstrs.mir @@ -28,6 +28,7 @@ --- name: test tracksRegLiveness: true +debugInstrRef: true liveins: - { reg: '$rdi', virtual-reg: '' } body: | diff --git a/llvm/test/DebugInfo/MIR/InstrRef/out-of-scope-blocks.mir b/llvm/test/DebugInfo/MIR/InstrRef/out-of-scope-blocks.mir --- a/llvm/test/DebugInfo/MIR/InstrRef/out-of-scope-blocks.mir +++ b/llvm/test/DebugInfo/MIR/InstrRef/out-of-scope-blocks.mir @@ -86,6 +86,7 @@ name: main alignment: 16 tracksRegLiveness: true +debugInstrRef: true liveins: - { reg: '$rsi' } frameInfo: diff --git a/llvm/test/DebugInfo/MIR/InstrRef/phi-coalesce-subreg.mir b/llvm/test/DebugInfo/MIR/InstrRef/phi-coalesce-subreg.mir --- a/llvm/test/DebugInfo/MIR/InstrRef/phi-coalesce-subreg.mir +++ b/llvm/test/DebugInfo/MIR/InstrRef/phi-coalesce-subreg.mir @@ -91,6 +91,7 @@ name: foo alignment: 16 tracksRegLiveness: true +debugInstrRef: true liveins: - { reg: '$edi', virtual-reg: '%3' } - { reg: '$esi', virtual-reg: '%4' } diff --git a/llvm/test/DebugInfo/MIR/InstrRef/phi-coalescing.mir b/llvm/test/DebugInfo/MIR/InstrRef/phi-coalescing.mir --- a/llvm/test/DebugInfo/MIR/InstrRef/phi-coalescing.mir +++ b/llvm/test/DebugInfo/MIR/InstrRef/phi-coalescing.mir @@ -100,6 +100,7 @@ name: foo alignment: 16 tracksRegLiveness: true +debugInstrRef: true liveins: - { reg: '$rdi', virtual-reg: '%3' } - { reg: '$rsi', virtual-reg: '%5' } diff --git a/llvm/test/DebugInfo/MIR/InstrRef/phi-on-stack-coalesced.mir b/llvm/test/DebugInfo/MIR/InstrRef/phi-on-stack-coalesced.mir --- a/llvm/test/DebugInfo/MIR/InstrRef/phi-on-stack-coalesced.mir +++ b/llvm/test/DebugInfo/MIR/InstrRef/phi-on-stack-coalesced.mir @@ -58,6 +58,7 @@ name: foo alignment: 16 tracksRegLiveness: true +debugInstrRef: true registers: - { id: 0, class: gr16 } - { id: 1, class: gr32 } diff --git a/llvm/test/DebugInfo/MIR/InstrRef/phi-on-stack-coalesced2.mir b/llvm/test/DebugInfo/MIR/InstrRef/phi-on-stack-coalesced2.mir --- a/llvm/test/DebugInfo/MIR/InstrRef/phi-on-stack-coalesced2.mir +++ b/llvm/test/DebugInfo/MIR/InstrRef/phi-on-stack-coalesced2.mir @@ -59,6 +59,7 @@ name: foo alignment: 16 tracksRegLiveness: true +debugInstrRef: true registers: - { id: 0, class: gr8 } - { id: 1, class: gr32_abcd } diff --git a/llvm/test/DebugInfo/MIR/InstrRef/phi-regallocd-to-stack.mir b/llvm/test/DebugInfo/MIR/InstrRef/phi-regallocd-to-stack.mir --- a/llvm/test/DebugInfo/MIR/InstrRef/phi-regallocd-to-stack.mir +++ b/llvm/test/DebugInfo/MIR/InstrRef/phi-regallocd-to-stack.mir @@ -53,6 +53,7 @@ name: foo alignment: 16 tracksRegLiveness: true +debugInstrRef: true registers: - { id: 0, class: gr32 } - { id: 1, class: gr32 } diff --git a/llvm/test/DebugInfo/MIR/InstrRef/phi-through-regalloc.mir b/llvm/test/DebugInfo/MIR/InstrRef/phi-through-regalloc.mir --- a/llvm/test/DebugInfo/MIR/InstrRef/phi-through-regalloc.mir +++ b/llvm/test/DebugInfo/MIR/InstrRef/phi-through-regalloc.mir @@ -82,6 +82,7 @@ name: foo alignment: 16 tracksRegLiveness: true +debugInstrRef: true registers: - { id: 0, class: gr32 } - { id: 1, class: gr32 } diff --git a/llvm/test/DebugInfo/MIR/InstrRef/pick-vphi-in-shifting-loop.mir b/llvm/test/DebugInfo/MIR/InstrRef/pick-vphi-in-shifting-loop.mir --- a/llvm/test/DebugInfo/MIR/InstrRef/pick-vphi-in-shifting-loop.mir +++ b/llvm/test/DebugInfo/MIR/InstrRef/pick-vphi-in-shifting-loop.mir @@ -77,6 +77,7 @@ name: bees alignment: 16 tracksRegLiveness: true +debugInstrRef: true frameInfo: maxAlignment: 1 maxCallFrameSize: 0 diff --git a/llvm/test/DebugInfo/MIR/InstrRef/restore-clobber-with-indirectness.mir b/llvm/test/DebugInfo/MIR/InstrRef/restore-clobber-with-indirectness.mir --- a/llvm/test/DebugInfo/MIR/InstrRef/restore-clobber-with-indirectness.mir +++ b/llvm/test/DebugInfo/MIR/InstrRef/restore-clobber-with-indirectness.mir @@ -46,6 +46,7 @@ name: _ZNSt5dequeIPN4llvm4LoopESaIS2_EE13_M_insert_auxESt15_Deque_iteratorIS2_RS2_PS2_EmRKS2_ alignment: 16 tracksRegLiveness: true +debugInstrRef: true liveins: - { reg: '$rdi' } - { reg: '$rsi' } diff --git a/llvm/test/DebugInfo/MIR/InstrRef/restore-to-rsp-crash.mir b/llvm/test/DebugInfo/MIR/InstrRef/restore-to-rsp-crash.mir --- a/llvm/test/DebugInfo/MIR/InstrRef/restore-to-rsp-crash.mir +++ b/llvm/test/DebugInfo/MIR/InstrRef/restore-to-rsp-crash.mir @@ -43,6 +43,7 @@ name: foo alignment: 16 tracksRegLiveness: true +debugInstrRef: true frameInfo: stackSize: 24 offsetAdjustment: -24 diff --git a/llvm/test/DebugInfo/MIR/InstrRef/single-assign-propagation.mir b/llvm/test/DebugInfo/MIR/InstrRef/single-assign-propagation.mir --- a/llvm/test/DebugInfo/MIR/InstrRef/single-assign-propagation.mir +++ b/llvm/test/DebugInfo/MIR/InstrRef/single-assign-propagation.mir @@ -2,10 +2,6 @@ # RUN: -experimental-debug-variable-locations=true \ # RUN: | FileCheck %s -implicit-check-not=DBG_VALUE \ # RUN: --check-prefixes=CHECK,COMMON -# RUN: llc %s -march=x86-64 -run-pass=livedebugvalues -o - \ -# RUN: -experimental-debug-variable-locations=false \ -# RUN: | FileCheck %s -implicit-check-not=DBG_VALUE \ -# RUN: --check-prefixes=VARLOC,COMMON # # This test is designed to stimulate a simplification of variable-value # propagation in InstrRefBasedLDV. When we only have a single assignment of @@ -57,13 +53,14 @@ # ## VarLocBasedLDV will take the DBG_VALUE in the assignment block, propagate ## to bb.3, but not into bb.4 because of the intervening out-of-scope block. +## Disabled actual testing of this because it's just for comparison purposes. # -# VARLOC-LABEL: bb.1: -# VARLOC: DBG_VALUE -# VARLOC-LABEL: bb.2: +# varloc-label: bb.1: +# varloc: DBG_VALUE +# varloc-label: bb.2: ## No location here because it's out-of-scope. -# VARLOC-LABEL: bb.3: -# VARLOC: DBG_VALUE +# varloc-label: bb.3: +# varloc: DBG_VALUE # ## Common tail for 'test2' -- this is checking that the assignment of undef or ## $noreg in single-assignment mode doesn't lead to trouble further down the @@ -118,6 +115,7 @@ ... --- name: _Z8bb_to_bb +debugInstrRef: true debugValueSubstitutions: - { srcinst: 4, srcop: 0, dstinst: 3, dstop: 0, subreg: 0 } body: | diff --git a/llvm/test/DebugInfo/MIR/InstrRef/spill-slot-limits.mir b/llvm/test/DebugInfo/MIR/InstrRef/spill-slot-limits.mir --- a/llvm/test/DebugInfo/MIR/InstrRef/spill-slot-limits.mir +++ b/llvm/test/DebugInfo/MIR/InstrRef/spill-slot-limits.mir @@ -57,6 +57,7 @@ --- name: test tracksRegLiveness: true +debugInstrRef: true liveins: - { reg: '$rdi', virtual-reg: '' } stack: diff --git a/llvm/test/DebugInfo/MIR/InstrRef/stack-coloring-dbg-phi.mir b/llvm/test/DebugInfo/MIR/InstrRef/stack-coloring-dbg-phi.mir --- a/llvm/test/DebugInfo/MIR/InstrRef/stack-coloring-dbg-phi.mir +++ b/llvm/test/DebugInfo/MIR/InstrRef/stack-coloring-dbg-phi.mir @@ -1,29 +1,17 @@ -# RUN: sed 's_;AAAAAA __' < %s \ -# RUN: | llc -x mir -o - -start-before=phi-node-elimination \ +# RUN: llc %s -o - -start-before=phi-node-elimination \ # RUN: -stop-after=stack-slot-coloring -simplify-mir \ # RUN: -experimental-debug-variable-locations=true \ # RUN: | FileCheck %s --check-prefix=DBGPHIS -# RUN: sed 's_;BBBBBB __' < %s \ -# RUN: | llc -x mir -o - -start-before=phi-node-elimination \ -# RUN: -stop-after=stack-slot-coloring -simplify-mir \ -# RUN: -experimental-debug-variable-locations=false \ -# RUN: | FileCheck %s --check-prefix=DBGVALS # # Test that DBG_PHI instructions do not add "weight" to stack slots and cause # their coalescing / coloring to change. This is hard to trigger, because it's # closely coupled with the register allocator. Thus, the test is very # complicated and hard to reduce. # -# In block 13 there are two implementations of variable location tracking, but -# both are commented out. Use sed in the command lines above to un-comment -# each one and test what it does: in each case, the PHI should occur in -# %stack.4 rather than anywhere else. -# # Future register allocator changes might change the slot; in that case, just # update the slot number, so long as it's the same between each RUN. # # DBGPHIS: DBG_PHI %stack.4, -# DBGVALS: DBG_VALUE %stack.4, --- | target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i64:64-f80:128-n8:16:32:64-S128" @@ -55,6 +43,7 @@ name: amd64_push_arguments alignment: 16 tracksRegLiveness: true +debugInstrRef: true registers: - { id: 0, class: gr32 } - { id: 1, class: gr32 } @@ -216,11 +205,9 @@ %2:gr32 = PHI undef %35:gr32, %bb.11, %14, %bb.21 %3:gr64 = PHI %36, %bb.11, %13, %bb.21 - ;AAAAAA %4:gr32 = PHI %0, %bb.11, %10, %bb.21, debug-instr-number 1 - ;BBBBBB %4:gr32 = PHI %0, %bb.11, %10, %bb.21 + %4:gr32 = PHI %0, %bb.11, %10, %bb.21, debug-instr-number 1 %5:gr32 = PHI undef %35:gr32, %bb.11, %9, %bb.21 - ;AAAAAA DBG_INSTR_REF !10, !DIExpression(DW_OP_LLVM_arg, 0), dbg-instr-ref(1, 0), debug-location !9 - ;BBBBBB DBG_VALUE %4, 0, !10, !DIExpression(), debug-location !9 + DBG_INSTR_REF !10, !DIExpression(DW_OP_LLVM_arg, 0), dbg-instr-ref(1, 0), debug-location !9 %39:gr8 = COPY %27.sub_8bit TEST8rr killed %39, %39, implicit-def $eflags, debug-location !9 JCC_1 %bb.18, 5, implicit killed $eflags, debug-location !9 diff --git a/llvm/test/DebugInfo/MIR/InstrRef/substitusions-roundtrip.mir b/llvm/test/DebugInfo/MIR/InstrRef/substitusions-roundtrip.mir --- a/llvm/test/DebugInfo/MIR/InstrRef/substitusions-roundtrip.mir +++ b/llvm/test/DebugInfo/MIR/InstrRef/substitusions-roundtrip.mir @@ -11,6 +11,7 @@ --- name: test tracksRegLiveness: true +debugInstrRef: true liveins: - { reg: '$rdi', virtual-reg: '' } debugValueSubstitutions: diff --git a/llvm/test/DebugInfo/MIR/InstrRef/survives-livedebugvars.mir b/llvm/test/DebugInfo/MIR/InstrRef/survives-livedebugvars.mir --- a/llvm/test/DebugInfo/MIR/InstrRef/survives-livedebugvars.mir +++ b/llvm/test/DebugInfo/MIR/InstrRef/survives-livedebugvars.mir @@ -99,6 +99,7 @@ name: bar alignment: 16 tracksRegLiveness: true +debugInstrRef: true registers: - { id: 0, class: gr64 } - { id: 1, class: gr32 } diff --git a/llvm/test/DebugInfo/MIR/InstrRef/twoaddr-to-threeaddr-sub.mir b/llvm/test/DebugInfo/MIR/InstrRef/twoaddr-to-threeaddr-sub.mir --- a/llvm/test/DebugInfo/MIR/InstrRef/twoaddr-to-threeaddr-sub.mir +++ b/llvm/test/DebugInfo/MIR/InstrRef/twoaddr-to-threeaddr-sub.mir @@ -18,6 +18,7 @@ name: test1 alignment: 16 tracksRegLiveness: true +debugInstrRef: true registers: - { id: 0, class: gr32 } - { id: 1, class: gr32 } diff --git a/llvm/test/DebugInfo/MIR/InstrRef/win32-chkctk-modifies-esp.mir b/llvm/test/DebugInfo/MIR/InstrRef/win32-chkctk-modifies-esp.mir --- a/llvm/test/DebugInfo/MIR/InstrRef/win32-chkctk-modifies-esp.mir +++ b/llvm/test/DebugInfo/MIR/InstrRef/win32-chkctk-modifies-esp.mir @@ -109,6 +109,7 @@ name: "\x01?foo@@YAXH@Z" alignment: 16 tracksRegLiveness: true +debugInstrRef: true hasWinCFI: true frameInfo: stackSize: 8 diff --git a/llvm/test/DebugInfo/MIR/InstrRef/x86-drop-compare-inst.mir b/llvm/test/DebugInfo/MIR/InstrRef/x86-drop-compare-inst.mir --- a/llvm/test/DebugInfo/MIR/InstrRef/x86-drop-compare-inst.mir +++ b/llvm/test/DebugInfo/MIR/InstrRef/x86-drop-compare-inst.mir @@ -66,6 +66,7 @@ name: soup alignment: 16 tracksRegLiveness: true +debugInstrRef: true registers: - { id: 0, class: gr64 } - { id: 1, class: gr64 } diff --git a/llvm/test/DebugInfo/MIR/InstrRef/x86-fixup-bw-inst-subreb.mir b/llvm/test/DebugInfo/MIR/InstrRef/x86-fixup-bw-inst-subreb.mir --- a/llvm/test/DebugInfo/MIR/InstrRef/x86-fixup-bw-inst-subreb.mir +++ b/llvm/test/DebugInfo/MIR/InstrRef/x86-fixup-bw-inst-subreb.mir @@ -16,6 +16,7 @@ name: test1 alignment: 16 tracksRegLiveness: true +debugInstrRef: true liveins: - { reg: '$rax' } # CHECK: debugValueSubstitutions: @@ -36,6 +37,7 @@ name: test3 alignment: 16 tracksRegLiveness: true +debugInstrRef: true liveins: - { reg: '$rdi' } # CHECK: debugValueSubstitutions: diff --git a/llvm/test/DebugInfo/MIR/InstrRef/x86-fp-stackifier-drop-locations.mir b/llvm/test/DebugInfo/MIR/InstrRef/x86-fp-stackifier-drop-locations.mir --- a/llvm/test/DebugInfo/MIR/InstrRef/x86-fp-stackifier-drop-locations.mir +++ b/llvm/test/DebugInfo/MIR/InstrRef/x86-fp-stackifier-drop-locations.mir @@ -106,6 +106,7 @@ name: foo alignment: 16 tracksRegLiveness: true +debugInstrRef: true frameInfo: hasCalls: true fixedStack: diff --git a/llvm/test/DebugInfo/MIR/InstrRef/x86-lea-fixup-2.mir b/llvm/test/DebugInfo/MIR/InstrRef/x86-lea-fixup-2.mir --- a/llvm/test/DebugInfo/MIR/InstrRef/x86-lea-fixup-2.mir +++ b/llvm/test/DebugInfo/MIR/InstrRef/x86-lea-fixup-2.mir @@ -7,6 +7,7 @@ # CHECK: name: test2add_32 alignment: 16 tracksRegLiveness: true +debugInstrRef: true liveins: - { reg: '$eax' } - { reg: '$ebp' } @@ -26,6 +27,7 @@ # CHECK-LABEL: name: test1mov1add_ebp_32 alignment: 16 tracksRegLiveness: true +debugInstrRef: true liveins: - { reg: '$eax' } - { reg: '$ebx' } @@ -46,6 +48,7 @@ # CHECK-LABEL: name: testleaadd_ebp_index_32 alignment: 16 tracksRegLiveness: true +debugInstrRef: true liveins: - { reg: '$ebx' } - { reg: '$ebp' } diff --git a/llvm/test/DebugInfo/MIR/InstrRef/x86-lea-fixup.mir b/llvm/test/DebugInfo/MIR/InstrRef/x86-lea-fixup.mir --- a/llvm/test/DebugInfo/MIR/InstrRef/x86-lea-fixup.mir +++ b/llvm/test/DebugInfo/MIR/InstrRef/x86-lea-fixup.mir @@ -13,6 +13,7 @@ name: pr43758 alignment: 16 tracksRegLiveness: true +debugInstrRef: true liveins: - { reg: '$rax' } - { reg: '$rbp' } @@ -32,6 +33,7 @@ # HASWELL-LABEL: name: test_mul_spec alignment: 16 tracksRegLiveness: true +debugInstrRef: true liveins: - { reg: '$edi' } frameInfo: @@ -59,6 +61,7 @@ # ATOM-LABEL: name: testthree alignment: 16 tracksRegLiveness: true +debugInstrRef: true frameInfo: maxAlignment: 1 maxCallFrameSize: 0 @@ -84,6 +87,7 @@ alignment: 16 tracksRegLiveness: true tracksDebugUserValues: true +debugInstrRef: true liveins: - { reg: '$esi' } frameInfo: diff --git a/llvm/test/DebugInfo/MIR/X86/entry-value-of-modified-param.mir b/llvm/test/DebugInfo/MIR/X86/entry-value-of-modified-param.mir --- a/llvm/test/DebugInfo/MIR/X86/entry-value-of-modified-param.mir +++ b/llvm/test/DebugInfo/MIR/X86/entry-value-of-modified-param.mir @@ -1,10 +1,10 @@ -# RUN: llc -run-pass=livedebugvalues -march=x86-64 -o - %s \ -# RUN: -experimental-debug-variable-locations=false \ -# RUN: | FileCheck %s --check-prefixes=CHECK,VARLOCLDV # RUN: llc -run-pass=livedebugvalues -march=x86-64 -o - %s \ # RUN: -experimental-debug-variable-locations=true \ # RUN: | FileCheck %s --check-prefixes=CHECK,INSTRREFLDV # +# NB: clone of this test for VarLocBasedLDV is in +# entry-value-of-modified-param2.mir. +# #extern void fn1 (int, int, int); # #__attribute__((noinline)) @@ -25,9 +25,7 @@ # CHECK: ![[ARG_B:.*]] = !DILocalVariable(name: "b" # CHECK: ![[ARG_C:.*]] = !DILocalVariable(name: "c" ## TODO: Support KILL instruction, which doesn't clobber parameter value. -# VARLOCLDV: DBG_VALUE $edi, $noreg, ![[ARG_A]], !DIExpression() # CHECK: DBG_VALUE $edx, $noreg, ![[ARG_C]], !DIExpression(DW_OP_LLVM_entry_value, 1) -# VARLOCLDV-NOT: DBG_VALUE $edi, $noreg, ![[ARG_A]], !DIExpression(DW_OP_LLVM_entry_value, 1) # INSTRREFLDV: DBG_VALUE $edi, $noreg, ![[ARG_A]], !DIExpression(DW_OP_LLVM_entry_value, 1) # CHECK-NOT: DBG_VALUE $esi, $noreg, ![[ARG_B]], !DIExpression(DW_OP_LLVM_entry_value, 1) # @@ -93,6 +91,7 @@ --- name: fn2 alignment: 16 +debugInstrRef: true body: | bb.0.entry: liveins: $edi, $esi, $rbx diff --git a/llvm/test/DebugInfo/MIR/X86/entry-value-of-modified-param.mir b/llvm/test/DebugInfo/MIR/X86/entry-value-of-modified-param2.mir copy from llvm/test/DebugInfo/MIR/X86/entry-value-of-modified-param.mir copy to llvm/test/DebugInfo/MIR/X86/entry-value-of-modified-param2.mir --- a/llvm/test/DebugInfo/MIR/X86/entry-value-of-modified-param.mir +++ b/llvm/test/DebugInfo/MIR/X86/entry-value-of-modified-param2.mir @@ -1,9 +1,9 @@ # RUN: llc -run-pass=livedebugvalues -march=x86-64 -o - %s \ # RUN: -experimental-debug-variable-locations=false \ # RUN: | FileCheck %s --check-prefixes=CHECK,VARLOCLDV -# RUN: llc -run-pass=livedebugvalues -march=x86-64 -o - %s \ -# RUN: -experimental-debug-variable-locations=true \ -# RUN: | FileCheck %s --check-prefixes=CHECK,INSTRREFLDV +# +# NB: clone of this file testing InstrRefBasedLDV is in +# llvm/test/DebugInfo/MIR/X86/entry-value-of-modified-param.mir # #extern void fn1 (int, int, int); # @@ -28,7 +28,6 @@ # VARLOCLDV: DBG_VALUE $edi, $noreg, ![[ARG_A]], !DIExpression() # CHECK: DBG_VALUE $edx, $noreg, ![[ARG_C]], !DIExpression(DW_OP_LLVM_entry_value, 1) # VARLOCLDV-NOT: DBG_VALUE $edi, $noreg, ![[ARG_A]], !DIExpression(DW_OP_LLVM_entry_value, 1) -# INSTRREFLDV: DBG_VALUE $edi, $noreg, ![[ARG_A]], !DIExpression(DW_OP_LLVM_entry_value, 1) # CHECK-NOT: DBG_VALUE $esi, $noreg, ![[ARG_B]], !DIExpression(DW_OP_LLVM_entry_value, 1) # --- | diff --git a/llvm/test/DebugInfo/MIR/X86/instr-ref-join-def-vphi.mir b/llvm/test/DebugInfo/MIR/X86/instr-ref-join-def-vphi.mir --- a/llvm/test/DebugInfo/MIR/X86/instr-ref-join-def-vphi.mir +++ b/llvm/test/DebugInfo/MIR/X86/instr-ref-join-def-vphi.mir @@ -129,6 +129,7 @@ hasEHFunclets: false failsVerification: false tracksDebugUserValues: true +debugInstrRef: true registers: [] liveins: - { reg: '$ecx', virtual-reg: '' } diff --git a/llvm/test/DebugInfo/MIR/X86/kill-entry-value-after-diamond-bbs.mir b/llvm/test/DebugInfo/MIR/X86/kill-entry-value-after-diamond-bbs.mir --- a/llvm/test/DebugInfo/MIR/X86/kill-entry-value-after-diamond-bbs.mir +++ b/llvm/test/DebugInfo/MIR/X86/kill-entry-value-after-diamond-bbs.mir @@ -1,4 +1,3 @@ -# RUN: llc -debug-entry-values -run-pass=livedebugvalues -march=x86-64 -o - %s -experimental-debug-variable-locations=false | FileCheck %s --check-prefixes=CHECK,VARLOCLDV # RUN: llc -debug-entry-values -run-pass=livedebugvalues -march=x86-64 -o - %s -experimental-debug-variable-locations=true | FileCheck %s --check-prefixes=CHECK,INSTRREFLDV # # The test case was artificially adjusted, in order to make proper diamond basic @@ -22,12 +21,10 @@ # CHECK-NEXT: $ebp = MOV32ri 2 # CHECK-NEXT: DBG_VALUE $esi, $noreg, ![[ARG_B]], !DIExpression(DW_OP_LLVM_entry_value, 1) # CHECK: bb.3.if.end -# VARLOCLDV-NOT: DBG_VALUE $esi, $noreg, ![[ARG_B]], !DIExpression(DW_OP_LLVM_entry_value, 1) # INSTRREFLDV: DBG_VALUE $esi, $noreg, ![[ARG_B]], !DIExpression(DW_OP_LLVM_entry_value, 1) # -## Final two lines: VarLoc LiveDebugValues cannot determine that the DBG_VALUEs -## down either path of the diamond set the variable to be its original value, -## wheras instruction referencing LiveDebugValues can. +## NB: an identical test in llvm/test/DebugInfo/MIR/X86/kill-entry-value-after-diamond-bbs2.mir +## checks the same things for VarLocBasedLDV. # --- | ; ModuleID = 'test.c' @@ -114,6 +111,7 @@ --- name: fn2 alignment: 16 +debugInstrRef: true fixedStack: - { id: 0, type: spill-slot, offset: -24, size: 8, alignment: 8, stack-id: default, callee-saved-register: '$rbx', callee-saved-restored: true, debug-info-variable: '', diff --git a/llvm/test/DebugInfo/MIR/X86/kill-entry-value-after-diamond-bbs.mir b/llvm/test/DebugInfo/MIR/X86/kill-entry-value-after-diamond-bbs2.mir copy from llvm/test/DebugInfo/MIR/X86/kill-entry-value-after-diamond-bbs.mir copy to llvm/test/DebugInfo/MIR/X86/kill-entry-value-after-diamond-bbs2.mir --- a/llvm/test/DebugInfo/MIR/X86/kill-entry-value-after-diamond-bbs.mir +++ b/llvm/test/DebugInfo/MIR/X86/kill-entry-value-after-diamond-bbs2.mir @@ -1,5 +1,4 @@ # RUN: llc -debug-entry-values -run-pass=livedebugvalues -march=x86-64 -o - %s -experimental-debug-variable-locations=false | FileCheck %s --check-prefixes=CHECK,VARLOCLDV -# RUN: llc -debug-entry-values -run-pass=livedebugvalues -march=x86-64 -o - %s -experimental-debug-variable-locations=true | FileCheck %s --check-prefixes=CHECK,INSTRREFLDV # # The test case was artificially adjusted, in order to make proper diamond basic # block structure relevant to the debug entry values clobbering. @@ -23,11 +22,13 @@ # CHECK-NEXT: DBG_VALUE $esi, $noreg, ![[ARG_B]], !DIExpression(DW_OP_LLVM_entry_value, 1) # CHECK: bb.3.if.end # VARLOCLDV-NOT: DBG_VALUE $esi, $noreg, ![[ARG_B]], !DIExpression(DW_OP_LLVM_entry_value, 1) -# INSTRREFLDV: DBG_VALUE $esi, $noreg, ![[ARG_B]], !DIExpression(DW_OP_LLVM_entry_value, 1) # ## Final two lines: VarLoc LiveDebugValues cannot determine that the DBG_VALUEs ## down either path of the diamond set the variable to be its original value, ## wheras instruction referencing LiveDebugValues can. +## +## An identical test in llvm/test/DebugInfo/MIR/X86/kill-entry-value-after-diamond-bbs.mir +## checks this for InstrRefBasedLDV. # --- | ; ModuleID = 'test.c' diff --git a/llvm/test/DebugInfo/MIR/X86/live-debug-values-bad-transfer.mir b/llvm/test/DebugInfo/MIR/X86/live-debug-values-bad-transfer.mir --- a/llvm/test/DebugInfo/MIR/X86/live-debug-values-bad-transfer.mir +++ b/llvm/test/DebugInfo/MIR/X86/live-debug-values-bad-transfer.mir @@ -1,4 +1,3 @@ -# RUN: llc %s -mtriple=x86_64-unknown-unknown -o - -run-pass=livedebugvalues -experimental-debug-variable-locations=false | FileCheck %s --implicit-check-not=DBG_VALUE # RUN: llc %s -mtriple=x86_64-unknown-unknown -o - -run-pass=livedebugvalues -experimental-debug-variable-locations=true | FileCheck %s -check-prefix=NEWLDV --implicit-check-not=DBG_VALUE # # Test that the DBG_VALUE of ecx below does not get propagated. It is considered @@ -7,19 +6,8 @@ # loop. There should be no transfer from ecx to ebx -- this is ensured by the # FileCheck implicit-check-not option. # -# FIXME: we successfully prevent the false location (ebx) from being -# propagated into block 2, but the original transfer isn't yet eliminated. -# Thus we get no DBG_VALUe in block 2, but an invalid one in block 1. -# -# CHECK-LABEL: name: foo -# CHECK-LABEL: bb.0.entry: -# CHECK: $ecx = MOV32ri 0 -# CHECK-NEXT: DBG_VALUE -# CHECK-LABEL: bb.1.loop: -# CHECK: $ebx = COPY killed $ecx -# CHECK-NEXT: DBG_VALUE -# -# This doesn't occur under value-tracking LiveDebugValues though. +# An identical test in llvm/test/DebugInfo/MIR/X86/live-debug-values-bad-transfer2.mir +# checks this for VarLocBasedLDV. # # NEWLDV-LABEL: name: foo # NEWLDV-LABEL: bb.0.entry: @@ -61,6 +49,7 @@ name: foo alignment: 4 tracksRegLiveness: true +debugInstrRef: true liveins: - { reg: '$edi' } frameInfo: diff --git a/llvm/test/DebugInfo/MIR/X86/live-debug-values-bad-transfer.mir b/llvm/test/DebugInfo/MIR/X86/live-debug-values-bad-transfer2.mir copy from llvm/test/DebugInfo/MIR/X86/live-debug-values-bad-transfer.mir copy to llvm/test/DebugInfo/MIR/X86/live-debug-values-bad-transfer2.mir --- a/llvm/test/DebugInfo/MIR/X86/live-debug-values-bad-transfer.mir +++ b/llvm/test/DebugInfo/MIR/X86/live-debug-values-bad-transfer2.mir @@ -1,5 +1,4 @@ # RUN: llc %s -mtriple=x86_64-unknown-unknown -o - -run-pass=livedebugvalues -experimental-debug-variable-locations=false | FileCheck %s --implicit-check-not=DBG_VALUE -# RUN: llc %s -mtriple=x86_64-unknown-unknown -o - -run-pass=livedebugvalues -experimental-debug-variable-locations=true | FileCheck %s -check-prefix=NEWLDV --implicit-check-not=DBG_VALUE # # Test that the DBG_VALUE of ecx below does not get propagated. It is considered # live-in on LiveDebugValues' first pass through the loop, but on the second it @@ -19,12 +18,8 @@ # CHECK: $ebx = COPY killed $ecx # CHECK-NEXT: DBG_VALUE # -# This doesn't occur under value-tracking LiveDebugValues though. -# -# NEWLDV-LABEL: name: foo -# NEWLDV-LABEL: bb.0.entry: -# NEWLDV: $ecx = MOV32ri 0 -# NEWLDV-NEXT: DBG_VALUE +# An identical test in llvm/test/DebugInfo/MIR/X86/live-debug-values-bad-transfer.mir +# checks this for InstrRefBasedLDV. --- | source_filename = "live-debug-values-remove-range.ll" diff --git a/llvm/test/DebugInfo/MIR/X86/live-debug-values-fragments.mir b/llvm/test/DebugInfo/MIR/X86/live-debug-values-fragments.mir --- a/llvm/test/DebugInfo/MIR/X86/live-debug-values-fragments.mir +++ b/llvm/test/DebugInfo/MIR/X86/live-debug-values-fragments.mir @@ -202,6 +202,7 @@ --- name: foo tracksRegLiveness: true +debugInstrRef: true registers: [] liveins: - { reg: '$rdi', virtual-reg: '' } @@ -245,6 +246,7 @@ --- name: bar tracksRegLiveness: true +debugInstrRef: true registers: [] liveins: - { reg: '$rdi', virtual-reg: '' } @@ -290,6 +292,7 @@ --- name: baz tracksRegLiveness: true +debugInstrRef: true registers: [] liveins: - { reg: '$rdi', virtual-reg: '' } diff --git a/llvm/test/DebugInfo/MIR/X86/live-debug-values-reg-copy.mir b/llvm/test/DebugInfo/MIR/X86/live-debug-values-reg-copy.mir --- a/llvm/test/DebugInfo/MIR/X86/live-debug-values-reg-copy.mir +++ b/llvm/test/DebugInfo/MIR/X86/live-debug-values-reg-copy.mir @@ -111,6 +111,7 @@ regBankSelected: false selected: false tracksRegLiveness: true +debugInstrRef: true registers: liveins: - { reg: '$edi', virtual-reg: '' } diff --git a/llvm/test/DebugInfo/MIR/X86/live-debug-values-restore.mir b/llvm/test/DebugInfo/MIR/X86/live-debug-values-restore.mir --- a/llvm/test/DebugInfo/MIR/X86/live-debug-values-restore.mir +++ b/llvm/test/DebugInfo/MIR/X86/live-debug-values-restore.mir @@ -265,6 +265,7 @@ selected: false failedISel: false tracksRegLiveness: true +debugInstrRef: true hasWinCFI: false registers: [] liveins: @@ -385,6 +386,7 @@ name: g alignment: 16 tracksRegLiveness: true +debugInstrRef: true liveins: - { reg: '$rdi', virtual-reg: '' } frameInfo: @@ -462,6 +464,7 @@ name: h alignment: 16 tracksRegLiveness: true +debugInstrRef: true liveins: - { reg: '$rdi', virtual-reg: '' } frameInfo: @@ -576,6 +579,7 @@ name: i alignment: 16 tracksRegLiveness: true +debugInstrRef: true liveins: - { reg: '$rdi', virtual-reg: '' } frameInfo: @@ -690,6 +694,7 @@ name: j tracksRegLiveness: true +debugInstrRef: true liveins: - { reg: '$rdi', virtual-reg: '' } frameInfo: @@ -800,6 +805,7 @@ name: k alignment: 16 tracksRegLiveness: true +debugInstrRef: true liveins: - { reg: '$rdi', virtual-reg: '' } - { reg: '$r10', virtual-reg: '' } diff --git a/llvm/test/DebugInfo/MIR/X86/live-debug-values-stack-clobber.mir b/llvm/test/DebugInfo/MIR/X86/live-debug-values-stack-clobber.mir --- a/llvm/test/DebugInfo/MIR/X86/live-debug-values-stack-clobber.mir +++ b/llvm/test/DebugInfo/MIR/X86/live-debug-values-stack-clobber.mir @@ -105,6 +105,7 @@ --- name: f tracksRegLiveness: true +debugInstrRef: true liveins: - { reg: '$rdi', virtual-reg: '' } - { reg: '$rsi', virtual-reg: '' } diff --git a/llvm/test/DebugInfo/MIR/X86/livedebugvalues_load_in_loop.mir b/llvm/test/DebugInfo/MIR/X86/livedebugvalues_load_in_loop.mir --- a/llvm/test/DebugInfo/MIR/X86/livedebugvalues_load_in_loop.mir +++ b/llvm/test/DebugInfo/MIR/X86/livedebugvalues_load_in_loop.mir @@ -69,6 +69,7 @@ --- name: _Z8bb_to_bb tracksRegLiveness: true +debugInstrRef: true liveins: - { reg: '$rdi', virtual-reg: '' } stack: diff --git a/llvm/test/DebugInfo/X86/instr-ref-flag.ll b/llvm/test/DebugInfo/X86/instr-ref-flag.ll --- a/llvm/test/DebugInfo/X86/instr-ref-flag.ll +++ b/llvm/test/DebugInfo/X86/instr-ref-flag.ll @@ -13,7 +13,9 @@ ;; by llc by default, and that it can be turned explicitly on or off as ;; desired. +; INSTRREFON: debugInstrRef: true ; INSTRREFON: DBG_INSTR_REF +; INSTRREFOFF: debugInstrRef: false ; INSTRREFOFF: DBG_VALUE target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i64:64-f80:128-n8:16:32:64-S128" diff --git a/llvm/test/DebugInfo/X86/instr-ref-track-clobbers.mir b/llvm/test/DebugInfo/X86/instr-ref-track-clobbers.mir --- a/llvm/test/DebugInfo/X86/instr-ref-track-clobbers.mir +++ b/llvm/test/DebugInfo/X86/instr-ref-track-clobbers.mir @@ -90,6 +90,7 @@ hasEHFunclets: false failsVerification: false tracksDebugUserValues: true +debugInstrRef: true registers: [] liveins: - { reg: '$rdi', virtual-reg: '' }