Index: llvm/include/llvm/CodeGen/FastISel.h =================================================================== --- llvm/include/llvm/CodeGen/FastISel.h +++ llvm/include/llvm/CodeGen/FastISel.h @@ -213,7 +213,6 @@ const TargetRegisterInfo &TRI; const TargetLibraryInfo *LibInfo; bool SkipTargetIndependentISel; - bool UseInstrRefDebugInfo = false; /// The position of the last instruction for materializing constants /// for use in the current block. It resets to EmitStartPt when it makes sense @@ -320,12 +319,6 @@ /// Reset InsertPt to the given old insert position. void leaveLocalValueArea(SavePoint Old); - /// Signal whether instruction referencing variable locations are desired for - /// this function's debug-info. - void useInstrRefDebugInfo(bool Flag) { - UseInstrRefDebugInfo = Flag; - } - protected: explicit FastISel(FunctionLoweringInfo &FuncInfo, const TargetLibraryInfo *LibInfo, Index: llvm/include/llvm/CodeGen/MIRYamlMapping.h =================================================================== --- llvm/include/llvm/CodeGen/MIRYamlMapping.h +++ llvm/include/llvm/CodeGen/MIRYamlMapping.h @@ -707,6 +707,7 @@ bool FailsVerification = false; bool TracksDebugUserValues = false; + bool UseDebugInstrRef = false; std::vector VirtualRegisters; std::vector LiveIns; std::optional> CalleeSavedRegisters; @@ -741,6 +742,7 @@ YamlIO.mapOptional("hasEHCatchret", MF.HasEHCatchret, false); YamlIO.mapOptional("hasEHScopes", MF.HasEHScopes, false); YamlIO.mapOptional("hasEHFunclets", MF.HasEHFunclets, false); + YamlIO.mapOptional("debugInstrRef", MF.UseDebugInstrRef, false); YamlIO.mapOptional("failsVerification", MF.FailsVerification, false); YamlIO.mapOptional("tracksDebugUserValues", MF.TracksDebugUserValues, Index: llvm/include/llvm/CodeGen/MachineFunction.h =================================================================== --- llvm/include/llvm/CodeGen/MachineFunction.h +++ llvm/include/llvm/CodeGen/MachineFunction.h @@ -524,6 +524,10 @@ /// during register allocation. See DebugPHIRegallocPos. DenseMap DebugPHIPositions; + /// Flag for whether this function contains DBG_VALUEs (false) or + /// DBG_INSTR_REF (true). + bool UseDebugInstrRef = false; + /// Create a substitution between one value to a different, /// new value. void makeDebugValueSubstitution(DebugInstrOperandPair, DebugInstrOperandPair, @@ -564,10 +568,17 @@ /// (or DBG_PHI). void finalizeDebugInstrRefs(); - /// Returns true if the function's variable locations should be tracked with + /// Determine whether, in the current machine configuration, we should use + /// instruction referencing or not. + bool shouldUseDebugInstrRef() const; + + /// Returns true if the function's variable locations are tracked with /// instruction referencing. bool useDebugInstrRef() const; + /// Set whether this function will use instruction referencing or not. + void setUseDebugInstrRef(bool UseInstrRef); + /// A reserved operand number representing the instructions memory operand, /// for instructions that have a stack spill fused into them. const static unsigned int DebugOperandMemNumber; Index: llvm/include/llvm/CodeGen/SelectionDAG.h =================================================================== --- llvm/include/llvm/CodeGen/SelectionDAG.h +++ llvm/include/llvm/CodeGen/SelectionDAG.h @@ -293,9 +293,6 @@ /// benefits (see discussion with @thakis in D120714). uint16_t NextPersistentId = 0; - /// Are instruction referencing variable locations desired for this function? - bool UseInstrRefDebugInfo = false; - public: /// Clients of various APIs that cause global effects on /// the DAG can optionally implement this interface. This allows the clients @@ -1869,16 +1866,6 @@ /// function mirrors \c llvm::salvageDebugInfo. void salvageDebugInfo(SDNode &N); - /// Signal whether instruction referencing variable locations are desired for - /// this function's debug-info. - void useInstrRefDebugInfo(bool Flag) { - UseInstrRefDebugInfo = Flag; - } - - bool getUseInstrRefDebugInfo() const { - return UseInstrRefDebugInfo; - } - void dump() const; /// In most cases this function returns the ABI alignment for a given type, Index: llvm/include/llvm/CodeGen/SelectionDAGISel.h =================================================================== --- llvm/include/llvm/CodeGen/SelectionDAGISel.h +++ llvm/include/llvm/CodeGen/SelectionDAGISel.h @@ -56,7 +56,6 @@ const TargetLowering *TLI; bool FastISelFailed; SmallPtrSet ElidedArgCopyInstrs; - bool UseInstrRefDebugInfo = false; /// Current optimization remark emitter. /// Used to report things like combines and FastISel failures. Index: llvm/lib/CodeGen/MIRParser/MIRParser.cpp =================================================================== --- llvm/lib/CodeGen/MIRParser/MIRParser.cpp +++ llvm/lib/CodeGen/MIRParser/MIRParser.cpp @@ -441,6 +441,9 @@ MF.makeDebugValueSubstitution({Sub.SrcInst, Sub.SrcOp}, {Sub.DstInst, Sub.DstOp}, Sub.Subreg); } + + // Flag for whether we're supposed to be using DBG_INSTR_REF. + MF.setUseDebugInstrRef(YamlMF.UseDebugInstrRef); } bool Index: llvm/lib/CodeGen/MIRPrinter.cpp =================================================================== --- llvm/lib/CodeGen/MIRPrinter.cpp +++ llvm/lib/CodeGen/MIRPrinter.cpp @@ -200,6 +200,7 @@ YamlMF.HasEHCatchret = MF.hasEHCatchret(); YamlMF.HasEHScopes = MF.hasEHScopes(); YamlMF.HasEHFunclets = MF.hasEHFunclets(); + YamlMF.UseDebugInstrRef = MF.useDebugInstrRef(); YamlMF.Legalized = MF.getProperties().hasProperty( MachineFunctionProperties::Property::Legalized); Index: llvm/lib/CodeGen/MachineFunction.cpp =================================================================== --- llvm/lib/CodeGen/MachineFunction.cpp +++ llvm/lib/CodeGen/MachineFunction.cpp @@ -1247,7 +1247,7 @@ } } -bool MachineFunction::useDebugInstrRef() const { +bool MachineFunction::shouldUseDebugInstrRef() const { // Disable instr-ref at -O0: it's very slow (in compile time). We can still // have optimized code inlined into this unoptimized code, however with // fewer and less aggressive optimizations happening, coverage and accuracy @@ -1265,6 +1265,14 @@ return false; } +bool MachineFunction::useDebugInstrRef() const { + return UseDebugInstrRef; +} + +void MachineFunction::setUseDebugInstrRef(bool Use) { + UseDebugInstrRef = Use; +} + // Use one million as a high / reserved number. const unsigned MachineFunction::DebugOperandMemNumber = 1000000; Index: llvm/lib/CodeGen/SelectionDAG/FastISel.cpp =================================================================== --- llvm/lib/CodeGen/SelectionDAG/FastISel.cpp +++ llvm/lib/CodeGen/SelectionDAG/FastISel.cpp @@ -1262,7 +1262,7 @@ // If using instruction referencing, mutate this into a DBG_INSTR_REF, // to be later patched up by finalizeDebugInstrRefs. Tack a deref onto // the expression, we don't have an "indirect" flag in DBG_INSTR_REF. - if (UseInstrRefDebugInfo && Op->isReg()) { + if (FuncInfo.MF->useDebugInstrRef() && Op->isReg()) { Builder->setDesc(TII.get(TargetOpcode::DBG_INSTR_REF)); Builder->getOperand(1).ChangeToImmediate(0); auto *NewExpr = @@ -1321,7 +1321,7 @@ // If using instruction referencing, mutate this into a DBG_INSTR_REF, // to be later patched up by finalizeDebugInstrRefs. - if (UseInstrRefDebugInfo) { + if (FuncInfo.MF->useDebugInstrRef()) { Builder->setDesc(TII.get(TargetOpcode::DBG_INSTR_REF)); Builder->getOperand(1).ChangeToImmediate(0); } Index: llvm/lib/CodeGen/SelectionDAG/InstrEmitter.h =================================================================== --- llvm/lib/CodeGen/SelectionDAG/InstrEmitter.h +++ llvm/lib/CodeGen/SelectionDAG/InstrEmitter.h @@ -152,8 +152,7 @@ /// InstrEmitter - Construct an InstrEmitter and set it to start inserting /// at the given position in the given block. InstrEmitter(const TargetMachine &TM, MachineBasicBlock *mbb, - MachineBasicBlock::iterator insertpos, - bool UseInstrRefDebugInfo); + MachineBasicBlock::iterator insertpos); private: void EmitMachineNode(SDNode *Node, bool IsClone, bool IsCloned, Index: llvm/lib/CodeGen/SelectionDAG/InstrEmitter.cpp =================================================================== --- llvm/lib/CodeGen/SelectionDAG/InstrEmitter.cpp +++ llvm/lib/CodeGen/SelectionDAG/InstrEmitter.cpp @@ -1360,12 +1360,11 @@ /// InstrEmitter - Construct an InstrEmitter and set it to start inserting /// at the given position in the given block. InstrEmitter::InstrEmitter(const TargetMachine &TM, MachineBasicBlock *mbb, - MachineBasicBlock::iterator insertpos, - bool UseInstrRefDebugInfo) + MachineBasicBlock::iterator insertpos) : MF(mbb->getParent()), MRI(&MF->getRegInfo()), TII(MF->getSubtarget().getInstrInfo()), TRI(MF->getSubtarget().getRegisterInfo()), TLI(MF->getSubtarget().getTargetLowering()), MBB(mbb), InsertPos(insertpos) { - EmitDebugInstrRefs = UseInstrRefDebugInfo; + EmitDebugInstrRefs = mbb->getParent()->useDebugInstrRef(); } Index: llvm/lib/CodeGen/SelectionDAG/ScheduleDAGFast.cpp =================================================================== --- llvm/lib/CodeGen/SelectionDAG/ScheduleDAGFast.cpp +++ llvm/lib/CodeGen/SelectionDAG/ScheduleDAGFast.cpp @@ -777,8 +777,7 @@ MachineBasicBlock* ScheduleDAGLinearize::EmitSchedule(MachineBasicBlock::iterator &InsertPos) { - InstrEmitter Emitter(DAG->getTarget(), BB, InsertPos, - DAG->getUseInstrRefDebugInfo()); + InstrEmitter Emitter(DAG->getTarget(), BB, InsertPos); DenseMap VRBaseMap; LLVM_DEBUG({ dbgs() << "\n*** Final schedule ***\n"; }); Index: llvm/lib/CodeGen/SelectionDAG/ScheduleDAGSDNodes.cpp =================================================================== --- llvm/lib/CodeGen/SelectionDAG/ScheduleDAGSDNodes.cpp +++ llvm/lib/CodeGen/SelectionDAG/ScheduleDAGSDNodes.cpp @@ -848,8 +848,7 @@ /// not necessarily refer to returned BB. The emitter may split blocks. MachineBasicBlock *ScheduleDAGSDNodes:: EmitSchedule(MachineBasicBlock::iterator &InsertPos) { - InstrEmitter Emitter(DAG->getTarget(), BB, InsertPos, - DAG->getUseInstrRefDebugInfo()); + InstrEmitter Emitter(DAG->getTarget(), BB, InsertPos); DenseMap VRBaseMap; DenseMap CopyVRBaseMap; SmallVector, 32> Orders; Index: llvm/lib/CodeGen/SelectionDAG/SelectionDAGISel.cpp =================================================================== --- llvm/lib/CodeGen/SelectionDAG/SelectionDAGISel.cpp +++ llvm/lib/CodeGen/SelectionDAG/SelectionDAGISel.cpp @@ -392,8 +392,8 @@ // Decide what flavour of variable location debug-info will be used, before // we change the optimisation level. - UseInstrRefDebugInfo = mf.useDebugInstrRef(); - CurDAG->useInstrRefDebugInfo(UseInstrRefDebugInfo); + bool InstrRef = mf.shouldUseDebugInstrRef(); + mf.setUseDebugInstrRef(InstrRef); // Reset the target options before resetting the optimization // level below. @@ -546,7 +546,6 @@ LiveInMap.insert(LI); // Insert DBG_VALUE instructions for function arguments to the entry block. - bool InstrRef = MF->useDebugInstrRef(); for (unsigned i = 0, e = FuncInfo->ArgDbgValues.size(); i != e; ++i) { MachineInstr *MI = FuncInfo->ArgDbgValues[e - i - 1]; assert(MI->getOpcode() != TargetOpcode::DBG_VALUE_LIST && @@ -624,7 +623,7 @@ // For debug-info, in instruction referencing mode, we need to perform some // post-isel maintenence. - if (UseInstrRefDebugInfo) + if (MF->useDebugInstrRef()) MF->finalizeDebugInstrRefs(); // Determine if there are any calls in this machine function. @@ -1380,8 +1379,6 @@ if (TM.Options.EnableFastISel) { LLVM_DEBUG(dbgs() << "Enabling fast-isel\n"); FastIS = TLI->createFastISel(*FuncInfo, LibInfo); - if (FastIS) - FastIS->useInstrRefDebugInfo(UseInstrRefDebugInfo); } ReversePostOrderTraversal RPOT(&Fn); Index: llvm/test/CodeGen/X86/dbg-value-superreg-copy2.mir =================================================================== --- llvm/test/CodeGen/X86/dbg-value-superreg-copy2.mir +++ llvm/test/CodeGen/X86/dbg-value-superreg-copy2.mir @@ -32,6 +32,7 @@ --- name: foo tracksRegLiveness: true +debugInstrRef: true debugValueSubstitutions: - { srcinst: 2, srcop: 0, dstinst: 1, dstop: 0, subreg: 2 } body: | Index: llvm/test/DebugInfo/MIR/InstrRef/accept-nonlive-reg-phis.mir =================================================================== --- llvm/test/DebugInfo/MIR/InstrRef/accept-nonlive-reg-phis.mir +++ llvm/test/DebugInfo/MIR/InstrRef/accept-nonlive-reg-phis.mir @@ -73,6 +73,7 @@ alignment: 16 tracksRegLiveness: true tracksDebugUserValues: true +debugInstrRef: true frameInfo: maxAlignment: 4 machineFunctionInfo: {} Index: llvm/test/DebugInfo/MIR/InstrRef/dbg-phi-subregister-location.mir =================================================================== --- llvm/test/DebugInfo/MIR/InstrRef/dbg-phi-subregister-location.mir +++ llvm/test/DebugInfo/MIR/InstrRef/dbg-phi-subregister-location.mir @@ -50,6 +50,7 @@ name: foo alignment: 16 tracksRegLiveness: true +debugInstrRef: true liveins: - { reg: '$edi' } frameInfo: Index: llvm/test/DebugInfo/MIR/InstrRef/dbg-phis-in-ldv.mir =================================================================== --- llvm/test/DebugInfo/MIR/InstrRef/dbg-phis-in-ldv.mir +++ llvm/test/DebugInfo/MIR/InstrRef/dbg-phis-in-ldv.mir @@ -86,6 +86,7 @@ name: foo alignment: 16 tracksRegLiveness: true +debugInstrRef: true liveins: - { reg: '$rdi' } - { reg: '$rsi' } Index: llvm/test/DebugInfo/MIR/InstrRef/dbg-phis-in-ldv2.mir =================================================================== --- llvm/test/DebugInfo/MIR/InstrRef/dbg-phis-in-ldv2.mir +++ llvm/test/DebugInfo/MIR/InstrRef/dbg-phis-in-ldv2.mir @@ -45,6 +45,7 @@ name: foo alignment: 16 tracksRegLiveness: true +debugInstrRef: true liveins: - { reg: '$rdi' } - { reg: '$rsi' } Index: llvm/test/DebugInfo/MIR/InstrRef/dbg-phis-merging-in-ldv.mir =================================================================== --- llvm/test/DebugInfo/MIR/InstrRef/dbg-phis-merging-in-ldv.mir +++ llvm/test/DebugInfo/MIR/InstrRef/dbg-phis-merging-in-ldv.mir @@ -98,6 +98,7 @@ name: foo alignment: 16 tracksRegLiveness: true +debugInstrRef: true liveins: - { reg: '$rdi' } - { reg: '$rsi' } Index: llvm/test/DebugInfo/MIR/InstrRef/dbg-phis-with-loops.mir =================================================================== --- llvm/test/DebugInfo/MIR/InstrRef/dbg-phis-with-loops.mir +++ llvm/test/DebugInfo/MIR/InstrRef/dbg-phis-with-loops.mir @@ -99,6 +99,7 @@ name: foo alignment: 16 tracksRegLiveness: true +debugInstrRef: true liveins: - { reg: '$rdi' } - { reg: '$rsi' } Index: llvm/test/DebugInfo/MIR/InstrRef/deref-spills-with-size.mir =================================================================== --- llvm/test/DebugInfo/MIR/InstrRef/deref-spills-with-size.mir +++ llvm/test/DebugInfo/MIR/InstrRef/deref-spills-with-size.mir @@ -138,6 +138,7 @@ name: _ZNSt5dequeIPN4llvm4LoopESaIS2_EE13_M_insert_auxESt15_Deque_iteratorIS2_RS2_PS2_EmRKS2_ alignment: 16 tracksRegLiveness: true +debugInstrRef: true liveins: - { reg: '$rdi' } - { reg: '$rsi' } Index: llvm/test/DebugInfo/MIR/InstrRef/follow-spill-of-indir-value.mir =================================================================== --- llvm/test/DebugInfo/MIR/InstrRef/follow-spill-of-indir-value.mir +++ llvm/test/DebugInfo/MIR/InstrRef/follow-spill-of-indir-value.mir @@ -99,6 +99,7 @@ name: _Z3foo10NonTrivial alignment: 16 tracksRegLiveness: true +debugInstrRef: true tracksDebugUserValues: true liveins: - { reg: '$rdi' } Index: llvm/test/DebugInfo/MIR/InstrRef/follow-spill-of-live-value.mir =================================================================== --- llvm/test/DebugInfo/MIR/InstrRef/follow-spill-of-live-value.mir +++ llvm/test/DebugInfo/MIR/InstrRef/follow-spill-of-live-value.mir @@ -178,6 +178,7 @@ name: _ZNSt5dequeIPN4llvm4LoopESaIS2_EE13_M_insert_auxESt15_Deque_iteratorIS2_RS2_PS2_EmRKS2_ alignment: 16 tracksRegLiveness: true +debugInstrRef: true liveins: - { reg: '$rdi' } - { reg: '$rsi' } Index: llvm/test/DebugInfo/MIR/InstrRef/instr-ref-roundtrip.mir =================================================================== --- llvm/test/DebugInfo/MIR/InstrRef/instr-ref-roundtrip.mir +++ llvm/test/DebugInfo/MIR/InstrRef/instr-ref-roundtrip.mir @@ -2,10 +2,12 @@ # # REQUIRES: x86-registered-target # +# CHECK: debugInstrRef: true # CHECK: MOV64rr $rdi, debug-instr-number 1 --- name: test tracksRegLiveness: true +debugInstrRef: true liveins: - { reg: '$rdi', virtual-reg: '' } body: | Index: llvm/test/DebugInfo/MIR/InstrRef/livedebugvalues_illegal_locs.mir =================================================================== --- llvm/test/DebugInfo/MIR/InstrRef/livedebugvalues_illegal_locs.mir +++ llvm/test/DebugInfo/MIR/InstrRef/livedebugvalues_illegal_locs.mir @@ -37,6 +37,7 @@ ... --- name: _Z8bb_to_bb +debugInstrRef: true debugValueSubstitutions: - { srcinst: 4, srcop: 0, dstinst: 3, dstop: 0, subreg: 0 } body: | Index: llvm/test/DebugInfo/MIR/InstrRef/livedebugvalues_instrref_tolocs.mir =================================================================== --- llvm/test/DebugInfo/MIR/InstrRef/livedebugvalues_instrref_tolocs.mir +++ llvm/test/DebugInfo/MIR/InstrRef/livedebugvalues_instrref_tolocs.mir @@ -31,6 +31,7 @@ ... --- name: _Z8bb_to_bb +debugInstrRef: true debugValueSubstitutions: - { srcinst: 4, srcop: 0, dstinst: 3, dstop: 0, subreg: 0 } body: | Index: llvm/test/DebugInfo/MIR/InstrRef/livedebugvalues_recover_clobbers.mir =================================================================== --- llvm/test/DebugInfo/MIR/InstrRef/livedebugvalues_recover_clobbers.mir +++ llvm/test/DebugInfo/MIR/InstrRef/livedebugvalues_recover_clobbers.mir @@ -50,6 +50,7 @@ ... --- name: _Z8bb_to_bb +debugInstrRef: true stack: - { id: 0, type: spill-slot, offset: -12, size: 4, alignment: 4 } body: | Index: llvm/test/DebugInfo/MIR/InstrRef/livedebugvalues_stackslot_subregs.mir =================================================================== --- llvm/test/DebugInfo/MIR/InstrRef/livedebugvalues_stackslot_subregs.mir +++ llvm/test/DebugInfo/MIR/InstrRef/livedebugvalues_stackslot_subregs.mir @@ -29,6 +29,7 @@ --- name: test tracksRegLiveness: true +debugInstrRef: true liveins: - { reg: '$rdi', virtual-reg: '' } stack: Index: llvm/test/DebugInfo/MIR/InstrRef/livedebugvalues_subreg_substitutions.mir =================================================================== --- llvm/test/DebugInfo/MIR/InstrRef/livedebugvalues_subreg_substitutions.mir +++ llvm/test/DebugInfo/MIR/InstrRef/livedebugvalues_subreg_substitutions.mir @@ -31,6 +31,7 @@ --- name: test tracksRegLiveness: true +debugInstrRef: true liveins: - { reg: '$rdi', virtual-reg: '' } debugValueSubstitutions: Index: llvm/test/DebugInfo/MIR/InstrRef/memory-operand-folding-tieddef.mir =================================================================== --- llvm/test/DebugInfo/MIR/InstrRef/memory-operand-folding-tieddef.mir +++ llvm/test/DebugInfo/MIR/InstrRef/memory-operand-folding-tieddef.mir @@ -57,6 +57,7 @@ name: _ZNK4llvm5APInt5magicEv alignment: 16 tracksRegLiveness: true +debugInstrRef: true registers: - { id: 0, class: gr64 } - { id: 1, class: gr32 } Index: llvm/test/DebugInfo/MIR/InstrRef/memory-operand-folding.mir =================================================================== --- llvm/test/DebugInfo/MIR/InstrRef/memory-operand-folding.mir +++ llvm/test/DebugInfo/MIR/InstrRef/memory-operand-folding.mir @@ -49,6 +49,7 @@ --- name: beans tracksRegLiveness: True +debugInstrRef: true body: | bb.0: liveins: $edi Index: llvm/test/DebugInfo/MIR/InstrRef/memory-operand-load-folding.mir =================================================================== --- llvm/test/DebugInfo/MIR/InstrRef/memory-operand-load-folding.mir +++ llvm/test/DebugInfo/MIR/InstrRef/memory-operand-load-folding.mir @@ -68,6 +68,7 @@ --- name: foo tracksRegLiveness: true +debugInstrRef: true registers: - { id: 0, class: gr32, preferred-register: '' } - { id: 1, class: fr32, preferred-register: '' } Index: llvm/test/DebugInfo/MIR/InstrRef/memory-operand-tracking.mir =================================================================== --- llvm/test/DebugInfo/MIR/InstrRef/memory-operand-tracking.mir +++ llvm/test/DebugInfo/MIR/InstrRef/memory-operand-tracking.mir @@ -36,6 +36,7 @@ --- name: test tracksRegLiveness: true +debugInstrRef: true liveins: - { reg: '$rdi', virtual-reg: '' } debugValueSubstitutions: Index: llvm/test/DebugInfo/MIR/InstrRef/no-duplicates.mir =================================================================== --- llvm/test/DebugInfo/MIR/InstrRef/no-duplicates.mir +++ llvm/test/DebugInfo/MIR/InstrRef/no-duplicates.mir @@ -28,6 +28,7 @@ --- name: test tracksRegLiveness: true +debugInstrRef: true liveins: - { reg: '$rdi', virtual-reg: '' } body: | Index: llvm/test/DebugInfo/MIR/InstrRef/no-metainstrs.mir =================================================================== --- llvm/test/DebugInfo/MIR/InstrRef/no-metainstrs.mir +++ llvm/test/DebugInfo/MIR/InstrRef/no-metainstrs.mir @@ -28,6 +28,7 @@ --- name: test tracksRegLiveness: true +debugInstrRef: true liveins: - { reg: '$rdi', virtual-reg: '' } body: | Index: llvm/test/DebugInfo/MIR/InstrRef/out-of-scope-blocks.mir =================================================================== --- llvm/test/DebugInfo/MIR/InstrRef/out-of-scope-blocks.mir +++ llvm/test/DebugInfo/MIR/InstrRef/out-of-scope-blocks.mir @@ -86,6 +86,7 @@ name: main alignment: 16 tracksRegLiveness: true +debugInstrRef: true liveins: - { reg: '$rsi' } frameInfo: Index: llvm/test/DebugInfo/MIR/InstrRef/phi-coalesce-subreg.mir =================================================================== --- llvm/test/DebugInfo/MIR/InstrRef/phi-coalesce-subreg.mir +++ llvm/test/DebugInfo/MIR/InstrRef/phi-coalesce-subreg.mir @@ -91,6 +91,7 @@ name: foo alignment: 16 tracksRegLiveness: true +debugInstrRef: true liveins: - { reg: '$edi', virtual-reg: '%3' } - { reg: '$esi', virtual-reg: '%4' } Index: llvm/test/DebugInfo/MIR/InstrRef/phi-coalescing.mir =================================================================== --- llvm/test/DebugInfo/MIR/InstrRef/phi-coalescing.mir +++ llvm/test/DebugInfo/MIR/InstrRef/phi-coalescing.mir @@ -100,6 +100,7 @@ name: foo alignment: 16 tracksRegLiveness: true +debugInstrRef: true liveins: - { reg: '$rdi', virtual-reg: '%3' } - { reg: '$rsi', virtual-reg: '%5' } Index: llvm/test/DebugInfo/MIR/InstrRef/phi-on-stack-coalesced.mir =================================================================== --- llvm/test/DebugInfo/MIR/InstrRef/phi-on-stack-coalesced.mir +++ llvm/test/DebugInfo/MIR/InstrRef/phi-on-stack-coalesced.mir @@ -58,6 +58,7 @@ name: foo alignment: 16 tracksRegLiveness: true +debugInstrRef: true registers: - { id: 0, class: gr16 } - { id: 1, class: gr32 } Index: llvm/test/DebugInfo/MIR/InstrRef/phi-on-stack-coalesced2.mir =================================================================== --- llvm/test/DebugInfo/MIR/InstrRef/phi-on-stack-coalesced2.mir +++ llvm/test/DebugInfo/MIR/InstrRef/phi-on-stack-coalesced2.mir @@ -59,6 +59,7 @@ name: foo alignment: 16 tracksRegLiveness: true +debugInstrRef: true registers: - { id: 0, class: gr8 } - { id: 1, class: gr32_abcd } Index: llvm/test/DebugInfo/MIR/InstrRef/phi-regallocd-to-stack.mir =================================================================== --- llvm/test/DebugInfo/MIR/InstrRef/phi-regallocd-to-stack.mir +++ llvm/test/DebugInfo/MIR/InstrRef/phi-regallocd-to-stack.mir @@ -53,6 +53,7 @@ name: foo alignment: 16 tracksRegLiveness: true +debugInstrRef: true registers: - { id: 0, class: gr32 } - { id: 1, class: gr32 } Index: llvm/test/DebugInfo/MIR/InstrRef/phi-through-regalloc.mir =================================================================== --- llvm/test/DebugInfo/MIR/InstrRef/phi-through-regalloc.mir +++ llvm/test/DebugInfo/MIR/InstrRef/phi-through-regalloc.mir @@ -82,6 +82,7 @@ name: foo alignment: 16 tracksRegLiveness: true +debugInstrRef: true registers: - { id: 0, class: gr32 } - { id: 1, class: gr32 } Index: llvm/test/DebugInfo/MIR/InstrRef/pick-vphi-in-shifting-loop.mir =================================================================== --- llvm/test/DebugInfo/MIR/InstrRef/pick-vphi-in-shifting-loop.mir +++ llvm/test/DebugInfo/MIR/InstrRef/pick-vphi-in-shifting-loop.mir @@ -77,6 +77,7 @@ name: bees alignment: 16 tracksRegLiveness: true +debugInstrRef: true frameInfo: maxAlignment: 1 maxCallFrameSize: 0 Index: llvm/test/DebugInfo/MIR/InstrRef/restore-clobber-with-indirectness.mir =================================================================== --- llvm/test/DebugInfo/MIR/InstrRef/restore-clobber-with-indirectness.mir +++ llvm/test/DebugInfo/MIR/InstrRef/restore-clobber-with-indirectness.mir @@ -46,6 +46,7 @@ name: _ZNSt5dequeIPN4llvm4LoopESaIS2_EE13_M_insert_auxESt15_Deque_iteratorIS2_RS2_PS2_EmRKS2_ alignment: 16 tracksRegLiveness: true +debugInstrRef: true liveins: - { reg: '$rdi' } - { reg: '$rsi' } Index: llvm/test/DebugInfo/MIR/InstrRef/restore-to-rsp-crash.mir =================================================================== --- llvm/test/DebugInfo/MIR/InstrRef/restore-to-rsp-crash.mir +++ llvm/test/DebugInfo/MIR/InstrRef/restore-to-rsp-crash.mir @@ -43,6 +43,7 @@ name: foo alignment: 16 tracksRegLiveness: true +debugInstrRef: true frameInfo: stackSize: 24 offsetAdjustment: -24 Index: llvm/test/DebugInfo/MIR/InstrRef/single-assign-propagation.mir =================================================================== --- llvm/test/DebugInfo/MIR/InstrRef/single-assign-propagation.mir +++ llvm/test/DebugInfo/MIR/InstrRef/single-assign-propagation.mir @@ -2,10 +2,6 @@ # RUN: -experimental-debug-variable-locations=true \ # RUN: | FileCheck %s -implicit-check-not=DBG_VALUE \ # RUN: --check-prefixes=CHECK,COMMON -# RUN: llc %s -march=x86-64 -run-pass=livedebugvalues -o - \ -# RUN: -experimental-debug-variable-locations=false \ -# RUN: | FileCheck %s -implicit-check-not=DBG_VALUE \ -# RUN: --check-prefixes=VARLOC,COMMON # # This test is designed to stimulate a simplification of variable-value # propagation in InstrRefBasedLDV. When we only have a single assignment of @@ -57,13 +53,14 @@ # ## VarLocBasedLDV will take the DBG_VALUE in the assignment block, propagate ## to bb.3, but not into bb.4 because of the intervening out-of-scope block. +## Disabled actual testing of this because it's just for comparison purposes. # -# VARLOC-LABEL: bb.1: -# VARLOC: DBG_VALUE -# VARLOC-LABEL: bb.2: +# varloc-label: bb.1: +# varloc: DBG_VALUE +# varloc-label: bb.2: ## No location here because it's out-of-scope. -# VARLOC-LABEL: bb.3: -# VARLOC: DBG_VALUE +# varloc-label: bb.3: +# varloc: DBG_VALUE # ## Common tail for 'test2' -- this is checking that the assignment of undef or ## $noreg in single-assignment mode doesn't lead to trouble further down the @@ -118,6 +115,7 @@ ... --- name: _Z8bb_to_bb +debugInstrRef: true debugValueSubstitutions: - { srcinst: 4, srcop: 0, dstinst: 3, dstop: 0, subreg: 0 } body: | Index: llvm/test/DebugInfo/MIR/InstrRef/spill-slot-limits.mir =================================================================== --- llvm/test/DebugInfo/MIR/InstrRef/spill-slot-limits.mir +++ llvm/test/DebugInfo/MIR/InstrRef/spill-slot-limits.mir @@ -57,6 +57,7 @@ --- name: test tracksRegLiveness: true +debugInstrRef: true liveins: - { reg: '$rdi', virtual-reg: '' } stack: Index: llvm/test/DebugInfo/MIR/InstrRef/stack-coloring-dbg-phi.mir =================================================================== --- llvm/test/DebugInfo/MIR/InstrRef/stack-coloring-dbg-phi.mir +++ llvm/test/DebugInfo/MIR/InstrRef/stack-coloring-dbg-phi.mir @@ -1,29 +1,17 @@ -# RUN: sed 's_;AAAAAA __' < %s \ -# RUN: | llc -x mir -o - -start-before=phi-node-elimination \ +# RUN: llc %s -o - -start-before=phi-node-elimination \ # RUN: -stop-after=stack-slot-coloring -simplify-mir \ # RUN: -experimental-debug-variable-locations=true \ # RUN: | FileCheck %s --check-prefix=DBGPHIS -# RUN: sed 's_;BBBBBB __' < %s \ -# RUN: | llc -x mir -o - -start-before=phi-node-elimination \ -# RUN: -stop-after=stack-slot-coloring -simplify-mir \ -# RUN: -experimental-debug-variable-locations=false \ -# RUN: | FileCheck %s --check-prefix=DBGVALS # # Test that DBG_PHI instructions do not add "weight" to stack slots and cause # their coalescing / coloring to change. This is hard to trigger, because it's # closely coupled with the register allocator. Thus, the test is very # complicated and hard to reduce. # -# In block 13 there are two implementations of variable location tracking, but -# both are commented out. Use sed in the command lines above to un-comment -# each one and test what it does: in each case, the PHI should occur in -# %stack.4 rather than anywhere else. -# # Future register allocator changes might change the slot; in that case, just # update the slot number, so long as it's the same between each RUN. # # DBGPHIS: DBG_PHI %stack.4, -# DBGVALS: DBG_VALUE %stack.4, --- | target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i64:64-f80:128-n8:16:32:64-S128" @@ -55,6 +43,7 @@ name: amd64_push_arguments alignment: 16 tracksRegLiveness: true +debugInstrRef: true registers: - { id: 0, class: gr32 } - { id: 1, class: gr32 } @@ -216,11 +205,9 @@ %2:gr32 = PHI undef %35:gr32, %bb.11, %14, %bb.21 %3:gr64 = PHI %36, %bb.11, %13, %bb.21 - ;AAAAAA %4:gr32 = PHI %0, %bb.11, %10, %bb.21, debug-instr-number 1 - ;BBBBBB %4:gr32 = PHI %0, %bb.11, %10, %bb.21 + %4:gr32 = PHI %0, %bb.11, %10, %bb.21, debug-instr-number 1 %5:gr32 = PHI undef %35:gr32, %bb.11, %9, %bb.21 - ;AAAAAA DBG_INSTR_REF 1, 0, !10, !DIExpression(), debug-location !9 - ;BBBBBB DBG_VALUE %4, 0, !10, !DIExpression(), debug-location !9 + DBG_INSTR_REF 1, 0, !10, !DIExpression(), debug-location !9 %39:gr8 = COPY %27.sub_8bit TEST8rr killed %39, %39, implicit-def $eflags, debug-location !9 JCC_1 %bb.18, 5, implicit killed $eflags, debug-location !9 Index: llvm/test/DebugInfo/MIR/InstrRef/substitusions-roundtrip.mir =================================================================== --- llvm/test/DebugInfo/MIR/InstrRef/substitusions-roundtrip.mir +++ llvm/test/DebugInfo/MIR/InstrRef/substitusions-roundtrip.mir @@ -11,6 +11,7 @@ --- name: test tracksRegLiveness: true +debugInstrRef: true liveins: - { reg: '$rdi', virtual-reg: '' } debugValueSubstitutions: Index: llvm/test/DebugInfo/MIR/InstrRef/survives-livedebugvars.mir =================================================================== --- llvm/test/DebugInfo/MIR/InstrRef/survives-livedebugvars.mir +++ llvm/test/DebugInfo/MIR/InstrRef/survives-livedebugvars.mir @@ -89,6 +89,7 @@ name: bar alignment: 16 tracksRegLiveness: true +debugInstrRef: true registers: - { id: 0, class: gr64 } - { id: 1, class: gr32 } Index: llvm/test/DebugInfo/MIR/InstrRef/twoaddr-to-threeaddr-sub.mir =================================================================== --- llvm/test/DebugInfo/MIR/InstrRef/twoaddr-to-threeaddr-sub.mir +++ llvm/test/DebugInfo/MIR/InstrRef/twoaddr-to-threeaddr-sub.mir @@ -18,6 +18,7 @@ name: test1 alignment: 16 tracksRegLiveness: true +debugInstrRef: true registers: - { id: 0, class: gr32 } - { id: 1, class: gr32 } Index: llvm/test/DebugInfo/MIR/InstrRef/win32-chkctk-modifies-esp.mir =================================================================== --- llvm/test/DebugInfo/MIR/InstrRef/win32-chkctk-modifies-esp.mir +++ llvm/test/DebugInfo/MIR/InstrRef/win32-chkctk-modifies-esp.mir @@ -109,6 +109,7 @@ name: "\x01?foo@@YAXH@Z" alignment: 16 tracksRegLiveness: true +debugInstrRef: true hasWinCFI: true frameInfo: stackSize: 8 Index: llvm/test/DebugInfo/MIR/InstrRef/x86-drop-compare-inst.mir =================================================================== --- llvm/test/DebugInfo/MIR/InstrRef/x86-drop-compare-inst.mir +++ llvm/test/DebugInfo/MIR/InstrRef/x86-drop-compare-inst.mir @@ -66,6 +66,7 @@ name: soup alignment: 16 tracksRegLiveness: true +debugInstrRef: true registers: - { id: 0, class: gr64 } - { id: 1, class: gr64 } Index: llvm/test/DebugInfo/MIR/InstrRef/x86-fixup-bw-inst-subreb.mir =================================================================== --- llvm/test/DebugInfo/MIR/InstrRef/x86-fixup-bw-inst-subreb.mir +++ llvm/test/DebugInfo/MIR/InstrRef/x86-fixup-bw-inst-subreb.mir @@ -16,6 +16,7 @@ name: test1 alignment: 16 tracksRegLiveness: true +debugInstrRef: true liveins: - { reg: '$rax' } # CHECK: debugValueSubstitutions: @@ -36,6 +37,7 @@ name: test3 alignment: 16 tracksRegLiveness: true +debugInstrRef: true liveins: - { reg: '$rdi' } # CHECK: debugValueSubstitutions: Index: llvm/test/DebugInfo/MIR/InstrRef/x86-fp-stackifier-drop-locations.mir =================================================================== --- llvm/test/DebugInfo/MIR/InstrRef/x86-fp-stackifier-drop-locations.mir +++ llvm/test/DebugInfo/MIR/InstrRef/x86-fp-stackifier-drop-locations.mir @@ -106,6 +106,7 @@ name: foo alignment: 16 tracksRegLiveness: true +debugInstrRef: true frameInfo: hasCalls: true fixedStack: Index: llvm/test/DebugInfo/MIR/InstrRef/x86-lea-fixup-2.mir =================================================================== --- llvm/test/DebugInfo/MIR/InstrRef/x86-lea-fixup-2.mir +++ llvm/test/DebugInfo/MIR/InstrRef/x86-lea-fixup-2.mir @@ -7,6 +7,7 @@ # CHECK: name: test2add_32 alignment: 16 tracksRegLiveness: true +debugInstrRef: true liveins: - { reg: '$eax' } - { reg: '$ebp' } @@ -26,6 +27,7 @@ # CHECK-LABEL: name: test1mov1add_ebp_32 alignment: 16 tracksRegLiveness: true +debugInstrRef: true liveins: - { reg: '$eax' } - { reg: '$ebx' } @@ -46,6 +48,7 @@ # CHECK-LABEL: name: testleaadd_ebp_index_32 alignment: 16 tracksRegLiveness: true +debugInstrRef: true liveins: - { reg: '$ebx' } - { reg: '$ebp' } Index: llvm/test/DebugInfo/MIR/InstrRef/x86-lea-fixup.mir =================================================================== --- llvm/test/DebugInfo/MIR/InstrRef/x86-lea-fixup.mir +++ llvm/test/DebugInfo/MIR/InstrRef/x86-lea-fixup.mir @@ -13,6 +13,7 @@ name: pr43758 alignment: 16 tracksRegLiveness: true +debugInstrRef: true liveins: - { reg: '$rax' } - { reg: '$rbp' } @@ -32,6 +33,7 @@ # HASWELL-LABEL: name: test_mul_spec alignment: 16 tracksRegLiveness: true +debugInstrRef: true liveins: - { reg: '$edi' } frameInfo: @@ -59,6 +61,7 @@ # ATOM-LABEL: name: testthree alignment: 16 tracksRegLiveness: true +debugInstrRef: true frameInfo: maxAlignment: 1 maxCallFrameSize: 0 @@ -84,6 +87,7 @@ alignment: 16 tracksRegLiveness: true tracksDebugUserValues: true +debugInstrRef: true liveins: - { reg: '$esi' } frameInfo: Index: llvm/test/DebugInfo/MIR/X86/entry-value-of-modified-param.mir =================================================================== --- llvm/test/DebugInfo/MIR/X86/entry-value-of-modified-param.mir +++ llvm/test/DebugInfo/MIR/X86/entry-value-of-modified-param.mir @@ -1,10 +1,10 @@ -# RUN: llc -run-pass=livedebugvalues -march=x86-64 -o - %s \ -# RUN: -experimental-debug-variable-locations=false \ -# RUN: | FileCheck %s --check-prefixes=CHECK,VARLOCLDV # RUN: llc -run-pass=livedebugvalues -march=x86-64 -o - %s \ # RUN: -experimental-debug-variable-locations=true \ # RUN: | FileCheck %s --check-prefixes=CHECK,INSTRREFLDV # +# NB: clone of this test for VarLocBasedLDV is in +# entry-value-of-modified-param2.mir. +# #extern void fn1 (int, int, int); # #__attribute__((noinline)) @@ -25,9 +25,7 @@ # CHECK: ![[ARG_B:.*]] = !DILocalVariable(name: "b" # CHECK: ![[ARG_C:.*]] = !DILocalVariable(name: "c" ## TODO: Support KILL instruction, which doesn't clobber parameter value. -# VARLOCLDV: DBG_VALUE $edi, $noreg, ![[ARG_A]], !DIExpression() # CHECK: DBG_VALUE $edx, $noreg, ![[ARG_C]], !DIExpression(DW_OP_LLVM_entry_value, 1) -# VARLOCLDV-NOT: DBG_VALUE $edi, $noreg, ![[ARG_A]], !DIExpression(DW_OP_LLVM_entry_value, 1) # INSTRREFLDV: DBG_VALUE $edi, $noreg, ![[ARG_A]], !DIExpression(DW_OP_LLVM_entry_value, 1) # CHECK-NOT: DBG_VALUE $esi, $noreg, ![[ARG_B]], !DIExpression(DW_OP_LLVM_entry_value, 1) # @@ -93,6 +91,7 @@ --- name: fn2 alignment: 16 +debugInstrRef: true body: | bb.0.entry: liveins: $edi, $esi, $rbx Index: llvm/test/DebugInfo/MIR/X86/entry-value-of-modified-param2.mir =================================================================== --- /dev/null +++ llvm/test/DebugInfo/MIR/X86/entry-value-of-modified-param2.mir @@ -0,0 +1,122 @@ +# RUN: llc -run-pass=livedebugvalues -march=x86-64 -o - %s \ +# RUN: -experimental-debug-variable-locations=false \ +# RUN: | FileCheck %s --check-prefixes=CHECK,VARLOCLDV +# +# NB: clone of this file testing InstrRefBasedLDV is in +# llvm/test/DebugInfo/MIR/X86/entry-value-of-modified-param.mir +# +#extern void fn1 (int, int, int); +# +#__attribute__((noinline)) +#int +#fn2 (int a, int b, int c) { +# int q = 2 + a; +# +# fn1 (5, 6, q); +# +# b = b + 7; +# if (b < 17) +# return 1; +# else +# return 0; +#} +# +# CHECK: ![[ARG_A:.*]] = !DILocalVariable(name: "a" +# CHECK: ![[ARG_B:.*]] = !DILocalVariable(name: "b" +# CHECK: ![[ARG_C:.*]] = !DILocalVariable(name: "c" +## TODO: Support KILL instruction, which doesn't clobber parameter value. +# VARLOCLDV: DBG_VALUE $edi, $noreg, ![[ARG_A]], !DIExpression() +# CHECK: DBG_VALUE $edx, $noreg, ![[ARG_C]], !DIExpression(DW_OP_LLVM_entry_value, 1) +# VARLOCLDV-NOT: DBG_VALUE $edi, $noreg, ![[ARG_A]], !DIExpression(DW_OP_LLVM_entry_value, 1) +# CHECK-NOT: DBG_VALUE $esi, $noreg, ![[ARG_B]], !DIExpression(DW_OP_LLVM_entry_value, 1) +# +--- | + ; ModuleID = 'test.c' + source_filename = "test.c" + target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i64:64-f80:128-n8:16:32:64-S128" + target triple = "x86_64-unknown-linux-gnu" + + ; Function Attrs: noinline nounwind uwtable + define dso_local i32 @fn2(i32 %a, i32 %b, i32 %c) local_unnamed_addr !dbg !12 { + entry: + call void @llvm.dbg.value(metadata i32 %a, metadata !16, metadata !DIExpression()), !dbg !20 + call void @llvm.dbg.value(metadata i32 %b, metadata !17, metadata !DIExpression()), !dbg !20 + call void @llvm.dbg.value(metadata i32 %c, metadata !18, metadata !DIExpression()), !dbg !20 + %add = add nsw i32 %a, 2, !dbg !21 + call void @llvm.dbg.value(metadata i32 %add, metadata !19, metadata !DIExpression()), !dbg !20 + tail call void @fn1(i32 5, i32 6, i32 %add), !dbg !22 + call void @llvm.dbg.value(metadata i32 %b, metadata !17, metadata !DIExpression(DW_OP_plus_uconst, 7, DW_OP_stack_value)), !dbg !20 + %cmp = icmp slt i32 %b, 10, !dbg !23 + %. = zext i1 %cmp to i32, !dbg !25 + ret i32 %., !dbg !26 + } + + declare !dbg !4 dso_local void @fn1(i32, i32, i32) local_unnamed_addr + + ; Function Attrs: nounwind readnone speculatable willreturn + declare void @llvm.dbg.value(metadata, metadata, metadata) + + !llvm.dbg.cu = !{!0} + !llvm.module.flags = !{!8, !9, !10} + !llvm.ident = !{!11} + + !0 = distinct !DICompileUnit(language: DW_LANG_C99, file: !1, producer: "clang version 10.0.0", isOptimized: true, runtimeVersion: 0, emissionKind: FullDebug, enums: !2, retainedTypes: !3, nameTableKind: None) + !1 = !DIFile(filename: "test.c", directory: "/dir") + !2 = !{} + !3 = !{!4} + !4 = !DISubprogram(name: "fn1", scope: !1, file: !1, line: 1, type: !5, flags: DIFlagPrototyped, spFlags: DISPFlagOptimized, retainedNodes: !2) + !5 = !DISubroutineType(types: !6) + !6 = !{null, !7, !7, !7} + !7 = !DIBasicType(name: "int", size: 32, encoding: DW_ATE_signed) + !8 = !{i32 2, !"Dwarf Version", i32 4} + !9 = !{i32 2, !"Debug Info Version", i32 3} + !10 = !{i32 1, !"wchar_size", i32 4} + !11 = !{!"clang version 10.0.0"} + !12 = distinct !DISubprogram(name: "fn2", scope: !1, file: !1, line: 5, type: !13, scopeLine: 6, flags: DIFlagPrototyped | DIFlagAllCallsDescribed, spFlags: DISPFlagDefinition | DISPFlagOptimized, unit: !0, retainedNodes: !15) + !13 = !DISubroutineType(types: !14) + !14 = !{!7, !7, !7, !7} + !15 = !{!16, !17, !18, !19} + !16 = !DILocalVariable(name: "a", arg: 1, scope: !12, file: !1, line: 5, type: !7) + !17 = !DILocalVariable(name: "b", arg: 2, scope: !12, file: !1, line: 5, type: !7) + !18 = !DILocalVariable(name: "c", arg: 3, scope: !12, file: !1, line: 5, type: !7) + !19 = !DILocalVariable(name: "q", scope: !12, file: !1, line: 7, type: !7) + !20 = !DILocation(line: 0, scope: !12) + !21 = !DILocation(line: 7, column: 15, scope: !12) + !22 = !DILocation(line: 9, column: 5, scope: !12) + !23 = !DILocation(line: 12, column: 11, scope: !24) + !24 = distinct !DILexicalBlock(scope: !12, file: !1, line: 12, column: 9) + !25 = !DILocation(line: 0, scope: !24) + !26 = !DILocation(line: 16, column: 1, scope: !12) + +... +--- +name: fn2 +alignment: 16 +body: | + bb.0.entry: + liveins: $edi, $esi, $rbx + + DBG_VALUE $edi, $noreg, !16, !DIExpression(), debug-location !20 + DBG_VALUE $esi, $noreg, !17, !DIExpression(), debug-location !20 + DBG_VALUE $edx, $noreg, !18, !DIExpression(), debug-location !20 + frame-setup PUSH64r killed $rbx, implicit-def $rsp, implicit $rsp + CFI_INSTRUCTION def_cfa_offset 16 + CFI_INSTRUCTION offset $rbx, -16 + $ebx = MOV32rr $esi + DBG_VALUE $ebx, $noreg, !17, !DIExpression(), debug-location !20 + renamable $edi = KILL $edi, implicit-def $rdi + DBG_VALUE $edi, $noreg, !16, !DIExpression(), debug-location !20 + renamable $edx = LEA64_32r killed renamable $rdi, 1, $noreg, 2, $noreg, debug-location !21 + DBG_VALUE $edx, $noreg, !19, !DIExpression(), debug-location !20 + $edi = MOV32ri 5, debug-location !22 + $esi = MOV32ri 6, debug-location !22 + CALL64pcrel32 @fn1, csr_64, implicit $rsp, implicit $ssp, implicit $edi, implicit $esi, implicit $edx, implicit-def $rsp, implicit-def $ssp, debug-location !22 + DBG_VALUE $ebx, $noreg, !17, !DIExpression(DW_OP_plus_uconst, 7, DW_OP_stack_value), debug-location !20 + renamable $eax = XOR32rr undef $eax, undef $eax, implicit-def dead $eflags, debug-location !23 + CMP32ri8 killed renamable $ebx, 10, implicit-def $eflags, debug-location !23 + renamable $al = SETCCr 12, implicit killed $eflags, implicit killed $eax, implicit-def $eax, debug-location !23 + $rbx = frame-destroy POP64r implicit-def $rsp, implicit $rsp, debug-location !26 + CFI_INSTRUCTION def_cfa_offset 8, debug-location !26 + RET64 $eax, debug-location !26 + +... Index: llvm/test/DebugInfo/MIR/X86/instr-ref-join-def-vphi.mir =================================================================== --- llvm/test/DebugInfo/MIR/X86/instr-ref-join-def-vphi.mir +++ llvm/test/DebugInfo/MIR/X86/instr-ref-join-def-vphi.mir @@ -129,6 +129,7 @@ hasEHFunclets: false failsVerification: false tracksDebugUserValues: true +debugInstrRef: true registers: [] liveins: - { reg: '$ecx', virtual-reg: '' } Index: llvm/test/DebugInfo/MIR/X86/kill-entry-value-after-diamond-bbs.mir =================================================================== --- llvm/test/DebugInfo/MIR/X86/kill-entry-value-after-diamond-bbs.mir +++ llvm/test/DebugInfo/MIR/X86/kill-entry-value-after-diamond-bbs.mir @@ -1,4 +1,3 @@ -# RUN: llc -debug-entry-values -run-pass=livedebugvalues -march=x86-64 -o - %s -experimental-debug-variable-locations=false | FileCheck %s --check-prefixes=CHECK,VARLOCLDV # RUN: llc -debug-entry-values -run-pass=livedebugvalues -march=x86-64 -o - %s -experimental-debug-variable-locations=true | FileCheck %s --check-prefixes=CHECK,INSTRREFLDV # # The test case was artificially adjusted, in order to make proper diamond basic @@ -22,12 +21,10 @@ # CHECK-NEXT: $ebp = MOV32ri 2 # CHECK-NEXT: DBG_VALUE $esi, $noreg, ![[ARG_B]], !DIExpression(DW_OP_LLVM_entry_value, 1) # CHECK: bb.3.if.end -# VARLOCLDV-NOT: DBG_VALUE $esi, $noreg, ![[ARG_B]], !DIExpression(DW_OP_LLVM_entry_value, 1) # INSTRREFLDV: DBG_VALUE $esi, $noreg, ![[ARG_B]], !DIExpression(DW_OP_LLVM_entry_value, 1) # -## Final two lines: VarLoc LiveDebugValues cannot determine that the DBG_VALUEs -## down either path of the diamond set the variable to be its original value, -## wheras instruction referencing LiveDebugValues can. +## NB: an identical test in llvm/test/DebugInfo/MIR/X86/kill-entry-value-after-diamond-bbs2.mir +## checks the same things for VarLocBasedLDV. # --- | ; ModuleID = 'test.c' @@ -114,6 +111,7 @@ --- name: fn2 alignment: 16 +debugInstrRef: true fixedStack: - { id: 0, type: spill-slot, offset: -24, size: 8, alignment: 8, stack-id: default, callee-saved-register: '$rbx', callee-saved-restored: true, debug-info-variable: '', Index: llvm/test/DebugInfo/MIR/X86/kill-entry-value-after-diamond-bbs2.mir =================================================================== --- /dev/null +++ llvm/test/DebugInfo/MIR/X86/kill-entry-value-after-diamond-bbs2.mir @@ -0,0 +1,187 @@ +# RUN: llc -debug-entry-values -run-pass=livedebugvalues -march=x86-64 -o - %s -experimental-debug-variable-locations=false | FileCheck %s --check-prefixes=CHECK,VARLOCLDV +# +# The test case was artificially adjusted, in order to make proper diamond basic +# block structure relevant to the debug entry values clobbering. +# +# CHECK: ![[ARG_B:.*]] = !DILocalVariable(name: "b" +# CHECK: bb.0.entry +# CHECK: DBG_VALUE $esi, $noreg, ![[ARG_B]], !DIExpression() +# CHECK: bb.1.if.then +# CHECK: DBG_VALUE $esi, $noreg, ![[ARG_B]], !DIExpression() +# CHECK: $ebx = MOV32rr $esi +# CHECK-NEXT: DBG_VALUE $ebx, $noreg, ![[ARG_B]], !DIExpression() +# CHECK-NEXT: $esi = MOV32ri 5 +# CHECK-NEXT: $ebx = MOV32ri 1 +# CHECK-NEXT: DBG_VALUE $esi, $noreg, ![[ARG_B]], !DIExpression(DW_OP_LLVM_entry_value, 1) +# CHECK: bb.2.if.else +# CHECK: DBG_VALUE $esi, $noreg, ![[ARG_B]], !DIExpression() +# CHECK: $ebp = MOV32rr $esi +# CHECK: DBG_VALUE $ebp, $noreg, ![[ARG_B]], !DIExpression() +# CHECK-NEXT: $esi = MOV32ri 1 +# CHECK-NEXT: $ebp = MOV32ri 2 +# CHECK-NEXT: DBG_VALUE $esi, $noreg, ![[ARG_B]], !DIExpression(DW_OP_LLVM_entry_value, 1) +# CHECK: bb.3.if.end +# VARLOCLDV-NOT: DBG_VALUE $esi, $noreg, ![[ARG_B]], !DIExpression(DW_OP_LLVM_entry_value, 1) +# +## Final two lines: VarLoc LiveDebugValues cannot determine that the DBG_VALUEs +## down either path of the diamond set the variable to be its original value, +## wheras instruction referencing LiveDebugValues can. +## +## An identical test in llvm/test/DebugInfo/MIR/X86/kill-entry-value-after-diamond-bbs.mir +## checks this for InstrRefBasedLDV. +# +--- | + ; ModuleID = 'test.c' + source_filename = "test.c" + target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i64:64-f80:128-n8:16:32:64-S128" + target triple = "x86_64-unknown-linux-gnu" + + ; Function Attrs: noinline nounwind uwtable + define dso_local i32 @fn2(i32 %a, i32 %b, i32 %c) local_unnamed_addr !dbg !12 { + entry: + call void @llvm.dbg.value(metadata i32 %a, metadata !16, metadata !DIExpression()), !dbg !20 + call void @llvm.dbg.value(metadata i32 %b, metadata !17, metadata !DIExpression()), !dbg !20 + call void @llvm.dbg.value(metadata i32 %c, metadata !18, metadata !DIExpression()), !dbg !20 + %add = add nsw i32 %a, 2, !dbg !21 + call void @llvm.dbg.value(metadata i32 %add, metadata !19, metadata !DIExpression()), !dbg !20 + tail call void @fn1(i32 5, i32 6, i32 %add), !dbg !22 + %cmp = icmp slt i32 %b, 17, !dbg !23 + br i1 %cmp, label %if.then, label %if.else, !dbg !25 + + if.then: ; preds = %entry + %add1 = add nsw i32 %b, 7, !dbg !26 + call void @llvm.dbg.value(metadata i32 %add1, metadata !17, metadata !DIExpression()), !dbg !20 + tail call void @fn1(i32 5, i32 %add1, i32 %c), !dbg !28 + br label %if.end, !dbg !29 + + if.else: ; preds = %entry + %add2 = add nuw nsw i32 %b, 1, !dbg !30 + call void @llvm.dbg.value(metadata i32 %add2, metadata !17, metadata !DIExpression()), !dbg !20 + tail call void @fn1(i32 1, i32 %add2, i32 %c), !dbg !32 + br label %if.end + + if.end: ; preds = %if.else, %if.then + %b.addr.0 = phi i32 [ %add1, %if.then ], [ %add2, %if.else ], !dbg !33 + call void @llvm.dbg.value(metadata i32 %b.addr.0, metadata !17, metadata !DIExpression()), !dbg !20 + ret i32 %b.addr.0, !dbg !34 + } + + declare !dbg !4 dso_local void @fn1(i32, i32, i32) local_unnamed_addr + + ; Function Attrs: nounwind readnone speculatable willreturn + declare void @llvm.dbg.value(metadata, metadata, metadata) + + !llvm.dbg.cu = !{!0} + !llvm.module.flags = !{!8, !9, !10} + !llvm.ident = !{!11} + + !0 = distinct !DICompileUnit(language: DW_LANG_C99, file: !1, producer: "clang version 10.0.0", isOptimized: true, runtimeVersion: 0, emissionKind: FullDebug, enums: !2, retainedTypes: !3, nameTableKind: None) + !1 = !DIFile(filename: "test.c", directory: "/dir") + !2 = !{} + !3 = !{!4} + !4 = !DISubprogram(name: "fn1", scope: !1, file: !1, line: 1, type: !5, flags: DIFlagPrototyped, spFlags: DISPFlagOptimized, retainedNodes: !2) + !5 = !DISubroutineType(types: !6) + !6 = !{null, !7, !7, !7} + !7 = !DIBasicType(name: "int", size: 32, encoding: DW_ATE_signed) + !8 = !{i32 2, !"Dwarf Version", i32 4} + !9 = !{i32 2, !"Debug Info Version", i32 3} + !10 = !{i32 1, !"wchar_size", i32 4} + !11 = !{!"clang version 10.0.0"} + !12 = distinct !DISubprogram(name: "fn2", scope: !1, file: !1, line: 5, type: !13, scopeLine: 6, flags: DIFlagPrototyped | DIFlagAllCallsDescribed, spFlags: DISPFlagDefinition | DISPFlagOptimized, unit: !0, retainedNodes: !15) + !13 = !DISubroutineType(types: !14) + !14 = !{!7, !7, !7, !7} + !15 = !{!16, !17, !18, !19} + !16 = !DILocalVariable(name: "a", arg: 1, scope: !12, file: !1, line: 5, type: !7) + !17 = !DILocalVariable(name: "b", arg: 2, scope: !12, file: !1, line: 5, type: !7) + !18 = !DILocalVariable(name: "c", arg: 3, scope: !12, file: !1, line: 5, type: !7) + !19 = !DILocalVariable(name: "q", scope: !12, file: !1, line: 7, type: !7) + !20 = !DILocation(line: 0, scope: !12) + !21 = !DILocation(line: 7, column: 15, scope: !12) + !22 = !DILocation(line: 9, column: 5, scope: !12) + !23 = !DILocation(line: 11, column: 11, scope: !24) + !24 = distinct !DILexicalBlock(scope: !12, file: !1, line: 11, column: 9) + !25 = !DILocation(line: 11, column: 9, scope: !12) + !26 = !DILocation(line: 12, column: 13, scope: !27) + !27 = distinct !DILexicalBlock(scope: !24, file: !1, line: 11, column: 17) + !28 = !DILocation(line: 13, column: 8, scope: !27) + !29 = !DILocation(line: 14, column: 5, scope: !27) + !30 = !DILocation(line: 15, column: 13, scope: !31) + !31 = distinct !DILexicalBlock(scope: !24, file: !1, line: 14, column: 12) + !32 = !DILocation(line: 16, column: 7, scope: !31) + !33 = !DILocation(line: 0, scope: !24) + !34 = !DILocation(line: 19, column: 5, scope: !12) + +... +--- +name: fn2 +alignment: 16 +fixedStack: + - { id: 0, type: spill-slot, offset: -24, size: 8, alignment: 8, stack-id: default, + callee-saved-register: '$rbx', callee-saved-restored: true, debug-info-variable: '', + debug-info-expression: '', debug-info-location: '' } + - { id: 1, type: spill-slot, offset: -16, size: 8, alignment: 16, stack-id: default, + callee-saved-register: '$rbp', callee-saved-restored: true, debug-info-variable: '', + debug-info-expression: '', debug-info-location: '' } +body: | + bb.0.entry: + successors: %bb.1(0x40000000), %bb.2(0x40000000) + liveins: $edi, $edx, $esi, $rbp, $rbx + + DBG_VALUE $edi, $noreg, !16, !DIExpression(), debug-location !20 + DBG_VALUE $esi, $noreg, !17, !DIExpression(), debug-location !20 + DBG_VALUE $edx, $noreg, !18, !DIExpression(), debug-location !20 + frame-setup PUSH64r killed $rbp, implicit-def $rsp, implicit $rsp + CFI_INSTRUCTION def_cfa_offset 16 + frame-setup PUSH64r killed $rbx, implicit-def $rsp, implicit $rsp + CFI_INSTRUCTION def_cfa_offset 24 + frame-setup PUSH64r undef $rax, implicit-def $rsp, implicit $rsp + CFI_INSTRUCTION def_cfa_offset 32 + CFI_INSTRUCTION offset $rbx, -24 + CFI_INSTRUCTION offset $rbp, -16 + $ebp = MOV32rr $edx + DBG_VALUE $ebp, $noreg, !18, !DIExpression(), debug-location !20 + renamable $edi = KILL $edi, implicit-def $rdi + DBG_VALUE $edi, $noreg, !16, !DIExpression(), debug-location !20 + renamable $edx = LEA64_32r killed renamable $rdi, 1, $noreg, 2, $noreg, debug-location !21 + DBG_VALUE $edx, $noreg, !19, !DIExpression(), debug-location !20 + $edi = MOV32ri 5, debug-location !22 + CMP32ri8 renamable $ebp, 16, implicit-def $eflags, debug-location !23 + JCC_1 %bb.2, 15, implicit killed $eflags, debug-location !25 + + bb.1.if.then: + successors: %bb.3(0x80000000) + liveins: $ebp, $ebx, $esi + + $ebx = MOV32rr $esi + DBG_VALUE $ebx, $noreg, !17, !DIExpression(), debug-location !20 + $esi = MOV32ri 5, debug-location !28 + $ebx = MOV32ri 1 + JMP_1 %bb.3 + + bb.2.if.else: + successors: %bb.3(0x80000000) + liveins: $ebp, $ebx, $esi + + $ebp = MOV32rr $esi + DBG_VALUE $ebp, $noreg, !17, !DIExpression(), debug-location !20 + $esi = MOV32ri 1, debug-location !32 + $ebp = MOV32ri 2 + + bb.3.if.end: + liveins: $ebx, $edi, $ebp + + $esi = MOV32rr $ebx, debug-location !33 + $edx = MOV32rr killed $ebp, debug-location !33 + CALL64pcrel32 @fn1, csr_64, implicit $rsp, implicit $ssp, implicit $edi, implicit $esi, implicit $edx, implicit-def $rsp, implicit-def $ssp, debug-location !33 + DBG_VALUE $ebx, $noreg, !17, !DIExpression(), debug-location !20 + $eax = MOV32rr killed $ebx, debug-location !34 + $rsp = frame-destroy ADD64ri8 $rsp, 8, implicit-def dead $eflags, debug-location !34 + CFI_INSTRUCTION def_cfa_offset 24, debug-location !34 + $rbx = frame-destroy POP64r implicit-def $rsp, implicit $rsp, debug-location !34 + CFI_INSTRUCTION def_cfa_offset 16, debug-location !34 + $rbp = frame-destroy POP64r implicit-def $rsp, implicit $rsp, debug-location !34 + CFI_INSTRUCTION def_cfa_offset 8, debug-location !34 + RET64 killed $eax, debug-location !34 + +... + Index: llvm/test/DebugInfo/MIR/X86/live-debug-values-bad-transfer.mir =================================================================== --- llvm/test/DebugInfo/MIR/X86/live-debug-values-bad-transfer.mir +++ llvm/test/DebugInfo/MIR/X86/live-debug-values-bad-transfer.mir @@ -1,4 +1,3 @@ -# RUN: llc %s -mtriple=x86_64-unknown-unknown -o - -run-pass=livedebugvalues -experimental-debug-variable-locations=false | FileCheck %s --implicit-check-not=DBG_VALUE # RUN: llc %s -mtriple=x86_64-unknown-unknown -o - -run-pass=livedebugvalues -experimental-debug-variable-locations=true | FileCheck %s -check-prefix=NEWLDV --implicit-check-not=DBG_VALUE # # Test that the DBG_VALUE of ecx below does not get propagated. It is considered @@ -7,19 +6,8 @@ # loop. There should be no transfer from ecx to ebx -- this is ensured by the # FileCheck implicit-check-not option. # -# FIXME: we successfully prevent the false location (ebx) from being -# propagated into block 2, but the original transfer isn't yet eliminated. -# Thus we get no DBG_VALUe in block 2, but an invalid one in block 1. -# -# CHECK-LABEL: name: foo -# CHECK-LABEL: bb.0.entry: -# CHECK: $ecx = MOV32ri 0 -# CHECK-NEXT: DBG_VALUE -# CHECK-LABEL: bb.1.loop: -# CHECK: $ebx = COPY killed $ecx -# CHECK-NEXT: DBG_VALUE -# -# This doesn't occur under value-tracking LiveDebugValues though. +# An identical test in llvm/test/DebugInfo/MIR/X86/live-debug-values-bad-transfer2.mir +# checks this for VarLocBasedLDV # # NEWLDV-LABEL: name: foo # NEWLDV-LABEL: bb.0.entry: @@ -61,6 +49,7 @@ name: foo alignment: 4 tracksRegLiveness: true +debugInstrRef: true liveins: - { reg: '$edi' } frameInfo: Index: llvm/test/DebugInfo/MIR/X86/live-debug-values-bad-transfer2.mir =================================================================== --- /dev/null +++ llvm/test/DebugInfo/MIR/X86/live-debug-values-bad-transfer2.mir @@ -0,0 +1,106 @@ +# RUN: llc %s -mtriple=x86_64-unknown-unknown -o - -run-pass=livedebugvalues -experimental-debug-variable-locations=false | FileCheck %s --implicit-check-not=DBG_VALUE +# +# Test that the DBG_VALUE of ecx below does not get propagated. It is considered +# live-in on LiveDebugValues' first pass through the loop, but on the second it +# should be removed from the InLocs set because it gets clobbered inside the +# loop. There should be no transfer from ecx to ebx -- this is ensured by the +# FileCheck implicit-check-not option. +# +# FIXME: we successfully prevent the false location (ebx) from being +# propagated into block 2, but the original transfer isn't yet eliminated. +# Thus we get no DBG_VALUe in block 2, but an invalid one in block 1. +# +# CHECK-LABEL: name: foo +# CHECK-LABEL: bb.0.entry: +# CHECK: $ecx = MOV32ri 0 +# CHECK-NEXT: DBG_VALUE +# CHECK-LABEL: bb.1.loop: +# CHECK: $ebx = COPY killed $ecx +# CHECK-NEXT: DBG_VALUE +# +# An identical test in llvm/test/DebugInfo/MIR/X86/live-debug-values-bad-transfer.mir +# checks this for InstrRefBasedLDV. + +--- | + source_filename = "live-debug-values-remove-range.ll" + target datalayout = "e-m:e-i64:64-f80:128-n8:16:32:64-S128" + + declare void @llvm.dbg.value(metadata, metadata, metadata) + + define i32 @foo(i32 %bar) !dbg !4 { + entry: + br label %loop + loop: + br label %loop + exit: + ret i32 %bar + } + + !llvm.module.flags = !{!0, !1} + !llvm.dbg.cu = !{!2} + + !0 = !{i32 2, !"Debug Info Version", i32 3} + !1 = !{i32 2, !"Dwarf Version", i32 4} + !2 = distinct !DICompileUnit(language: DW_LANG_C_plus_plus, file: !3, producer: "beards", isOptimized: true, runtimeVersion: 0, emissionKind: FullDebug) + !3 = !DIFile(filename: "bees.cpp", directory: ".") + !4 = distinct !DISubprogram(name: "nope", scope: !3, file: !3, line: 1, type: !5, spFlags: DISPFlagDefinition, unit: !2, retainedNodes: !8) + !5 = !DISubroutineType(types: !6) + !6 = !{!7} + !7 = !DIBasicType(name: "int", size: 32, align: 32, encoding: DW_ATE_signed) + !8 = !{!9} + !9 = !DILocalVariable(name: "thin", scope: !4, file: !3, line: 1, type: !7) + !10 = !DILocation(line: 1, scope: !4) + +... +--- +name: foo +alignment: 4 +tracksRegLiveness: true +liveins: + - { reg: '$edi' } +frameInfo: + stackSize: 8 + offsetAdjustment: -8 + maxAlignment: 1 + adjustsStack: true + hasCalls: true + maxCallFrameSize: 0 + cvBytesOfCalleeSavedRegisters: 8 +fixedStack: + - { id: 0, type: spill-slot, offset: -16, size: 8, alignment: 16, callee-saved-register: '$rbx' } +machineFunctionInfo: {} +body: | + bb.0.entry: + liveins: $edi, $rbx + + frame-setup PUSH64r killed $rbx, implicit-def $rsp, implicit $rsp + CFI_INSTRUCTION def_cfa_offset 16 + CFI_INSTRUCTION offset $rbx, -16 + $ebx = MOV32rr $edi + $eax = MOV32ri 0, debug-location !10 + $ecx = MOV32ri 0, debug-location !10 + DBG_VALUE $ecx, $noreg, !9, !DIExpression(), debug-location !10 + $edi = MOV32ri 0, debug-location !10 + $esi = MOV32ri 0, debug-location !10 + + bb.1.loop: + successors: %bb.1, %bb.2 + liveins: $ebx, $eax, $ecx, $edi, $esi + + $eax = COPY $ecx, debug-location !10 + $ebx = COPY killed $ecx, debug-location !10 + $ecx = COPY killed $edi, debug-location !10 + $edi = COPY killed $esi, debug-location !10 + $esi = MOV32ri 1, debug-location !10 + TEST8ri killed renamable $al, 1, implicit-def $eflags + JCC_1 %bb.1, 5, implicit killed $eflags, debug-location !10 + + bb.2.exit: + liveins: $ebx + + $eax = MOV32rr killed $ebx, debug-location !10 + $rbx = frame-destroy POP64r implicit-def $rsp, implicit $rsp + CFI_INSTRUCTION def_cfa_offset 8 + RET64 $eax, debug-location !10 + +... Index: llvm/test/DebugInfo/MIR/X86/live-debug-values-fragments.mir =================================================================== --- llvm/test/DebugInfo/MIR/X86/live-debug-values-fragments.mir +++ llvm/test/DebugInfo/MIR/X86/live-debug-values-fragments.mir @@ -202,6 +202,7 @@ --- name: foo tracksRegLiveness: true +debugInstrRef: true registers: [] liveins: - { reg: '$rdi', virtual-reg: '' } @@ -245,6 +246,7 @@ --- name: bar tracksRegLiveness: true +debugInstrRef: true registers: [] liveins: - { reg: '$rdi', virtual-reg: '' } @@ -290,6 +292,7 @@ --- name: baz tracksRegLiveness: true +debugInstrRef: true registers: [] liveins: - { reg: '$rdi', virtual-reg: '' } Index: llvm/test/DebugInfo/MIR/X86/live-debug-values-reg-copy.mir =================================================================== --- llvm/test/DebugInfo/MIR/X86/live-debug-values-reg-copy.mir +++ llvm/test/DebugInfo/MIR/X86/live-debug-values-reg-copy.mir @@ -111,6 +111,7 @@ regBankSelected: false selected: false tracksRegLiveness: true +debugInstrRef: true registers: liveins: - { reg: '$edi', virtual-reg: '' } Index: llvm/test/DebugInfo/MIR/X86/live-debug-values-restore.mir =================================================================== --- llvm/test/DebugInfo/MIR/X86/live-debug-values-restore.mir +++ llvm/test/DebugInfo/MIR/X86/live-debug-values-restore.mir @@ -265,6 +265,7 @@ selected: false failedISel: false tracksRegLiveness: true +debugInstrRef: true hasWinCFI: false registers: [] liveins: @@ -385,6 +386,7 @@ name: g alignment: 16 tracksRegLiveness: true +debugInstrRef: true liveins: - { reg: '$rdi', virtual-reg: '' } frameInfo: @@ -462,6 +464,7 @@ name: h alignment: 16 tracksRegLiveness: true +debugInstrRef: true liveins: - { reg: '$rdi', virtual-reg: '' } frameInfo: @@ -576,6 +579,7 @@ name: i alignment: 16 tracksRegLiveness: true +debugInstrRef: true liveins: - { reg: '$rdi', virtual-reg: '' } frameInfo: @@ -690,6 +694,7 @@ name: j tracksRegLiveness: true +debugInstrRef: true liveins: - { reg: '$rdi', virtual-reg: '' } frameInfo: @@ -800,6 +805,7 @@ name: k alignment: 16 tracksRegLiveness: true +debugInstrRef: true liveins: - { reg: '$rdi', virtual-reg: '' } - { reg: '$r10', virtual-reg: '' } Index: llvm/test/DebugInfo/MIR/X86/live-debug-values-stack-clobber.mir =================================================================== --- llvm/test/DebugInfo/MIR/X86/live-debug-values-stack-clobber.mir +++ llvm/test/DebugInfo/MIR/X86/live-debug-values-stack-clobber.mir @@ -105,6 +105,7 @@ --- name: f tracksRegLiveness: true +debugInstrRef: true liveins: - { reg: '$rdi', virtual-reg: '' } - { reg: '$rsi', virtual-reg: '' } Index: llvm/test/DebugInfo/MIR/X86/livedebugvalues_load_in_loop.mir =================================================================== --- llvm/test/DebugInfo/MIR/X86/livedebugvalues_load_in_loop.mir +++ llvm/test/DebugInfo/MIR/X86/livedebugvalues_load_in_loop.mir @@ -69,6 +69,7 @@ --- name: _Z8bb_to_bb tracksRegLiveness: true +debugInstrRef: true liveins: - { reg: '$rdi', virtual-reg: '' } stack: Index: llvm/test/DebugInfo/X86/instr-ref-flag.ll =================================================================== --- llvm/test/DebugInfo/X86/instr-ref-flag.ll +++ llvm/test/DebugInfo/X86/instr-ref-flag.ll @@ -13,7 +13,9 @@ ;; by llc by default, and that it can be turned explicitly on or off as ;; desired. +; INSTRREFON: debugInstrRef: true ; INSTRREFON: DBG_INSTR_REF +; INSTRREFOFF: debugInstrRef: false ; INSTRREFOFF: DBG_VALUE target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i64:64-f80:128-n8:16:32:64-S128" Index: llvm/test/DebugInfo/X86/instr-ref-track-clobbers.mir =================================================================== --- llvm/test/DebugInfo/X86/instr-ref-track-clobbers.mir +++ llvm/test/DebugInfo/X86/instr-ref-track-clobbers.mir @@ -90,6 +90,7 @@ hasEHFunclets: false failsVerification: false tracksDebugUserValues: true +debugInstrRef: true registers: [] liveins: - { reg: '$rdi', virtual-reg: '' }