diff --git a/llvm/lib/Target/RISCV/RISCVInstrInfoVPseudos.td b/llvm/lib/Target/RISCV/RISCVInstrInfoVPseudos.td --- a/llvm/lib/Target/RISCV/RISCVInstrInfoVPseudos.td +++ b/llvm/lib/Target/RISCV/RISCVInstrInfoVPseudos.td @@ -5111,11 +5111,11 @@ } //===----------------------------------------------------------------------===// -// 12. Vector Integer Arithmetic Instructions +// 11. Vector Integer Arithmetic Instructions //===----------------------------------------------------------------------===// //===----------------------------------------------------------------------===// -// 12.1. Vector Single-Width Integer Add and Subtract +// 11.1. Vector Single-Width Integer Add and Subtract //===----------------------------------------------------------------------===// defm PseudoVADD : VPseudoVALU_VV_VX_VI; defm PseudoVSUB : VPseudoVALU_VV_VX; @@ -5185,7 +5185,7 @@ } //===----------------------------------------------------------------------===// -// 12.2. Vector Widening Integer Add/Subtract +// 11.2. Vector Widening Integer Add/Subtract //===----------------------------------------------------------------------===// defm PseudoVWADDU : VPseudoVWALU_VV_VX; defm PseudoVWSUBU : VPseudoVWALU_VV_VX; @@ -5197,7 +5197,7 @@ defm PseudoVWSUB : VPseudoVWALU_WV_WX; //===----------------------------------------------------------------------===// -// 12.3. Vector Integer Extension +// 11.3. Vector Integer Extension //===----------------------------------------------------------------------===// defm PseudoVZEXT_VF2 : PseudoVEXT_VF2; defm PseudoVZEXT_VF4 : PseudoVEXT_VF4; @@ -5207,7 +5207,7 @@ defm PseudoVSEXT_VF8 : PseudoVEXT_VF8; //===----------------------------------------------------------------------===// -// 12.4. Vector Integer Add-with-Carry / Subtract-with-Borrow Instructions +// 11.4. Vector Integer Add-with-Carry / Subtract-with-Borrow Instructions //===----------------------------------------------------------------------===// defm PseudoVADC : VPseudoVCALU_VM_XM_IM; defm PseudoVMADC : VPseudoVCALUM_VM_XM_IM<"@earlyclobber $rd">; @@ -5218,27 +5218,27 @@ defm PseudoVMSBC : VPseudoVCALUM_V_X<"@earlyclobber $rd">; //===----------------------------------------------------------------------===// -// 12.5. Vector Bitwise Logical Instructions +// 11.5. Vector Bitwise Logical Instructions //===----------------------------------------------------------------------===// defm PseudoVAND : VPseudoVALU_VV_VX_VI; defm PseudoVOR : VPseudoVALU_VV_VX_VI; defm PseudoVXOR : VPseudoVALU_VV_VX_VI; //===----------------------------------------------------------------------===// -// 12.6. Vector Single-Width Bit Shift Instructions +// 11.6. Vector Single-Width Bit Shift Instructions //===----------------------------------------------------------------------===// defm PseudoVSLL : VPseudoVSHT_VV_VX_VI; defm PseudoVSRL : VPseudoVSHT_VV_VX_VI; defm PseudoVSRA : VPseudoVSHT_VV_VX_VI; //===----------------------------------------------------------------------===// -// 12.7. Vector Narrowing Integer Right Shift Instructions +// 11.7. Vector Narrowing Integer Right Shift Instructions //===----------------------------------------------------------------------===// defm PseudoVNSRL : VPseudoVNSHT_WV_WX_WI; defm PseudoVNSRA : VPseudoVNSHT_WV_WX_WI; //===----------------------------------------------------------------------===// -// 12.8. Vector Integer Comparison Instructions +// 11.8. Vector Integer Comparison Instructions //===----------------------------------------------------------------------===// defm PseudoVMSEQ : VPseudoVCMPM_VV_VX_VI; defm PseudoVMSNE : VPseudoVCMPM_VV_VX_VI; @@ -5250,7 +5250,7 @@ defm PseudoVMSGT : VPseudoVCMPM_VX_VI; //===----------------------------------------------------------------------===// -// 12.9. Vector Integer Min/Max Instructions +// 11.9. Vector Integer Min/Max Instructions //===----------------------------------------------------------------------===// defm PseudoVMINU : VPseudoVMINMAX_VV_VX; defm PseudoVMIN : VPseudoVMINMAX_VV_VX; @@ -5258,7 +5258,7 @@ defm PseudoVMAX : VPseudoVMINMAX_VV_VX; //===----------------------------------------------------------------------===// -// 12.10. Vector Single-Width Integer Multiply Instructions +// 11.10. Vector Single-Width Integer Multiply Instructions //===----------------------------------------------------------------------===// defm PseudoVMUL : VPseudoVMUL_VV_VX; defm PseudoVMULH : VPseudoVMUL_VV_VX; @@ -5266,7 +5266,7 @@ defm PseudoVMULHSU : VPseudoVMUL_VV_VX; //===----------------------------------------------------------------------===// -// 12.11. Vector Integer Divide Instructions +// 11.11. Vector Integer Divide Instructions //===----------------------------------------------------------------------===// defm PseudoVDIVU : VPseudoVDIV_VV_VX; defm PseudoVDIV : VPseudoVDIV_VV_VX; @@ -5274,14 +5274,14 @@ defm PseudoVREM : VPseudoVDIV_VV_VX; //===----------------------------------------------------------------------===// -// 12.12. Vector Widening Integer Multiply Instructions +// 11.12. Vector Widening Integer Multiply Instructions //===----------------------------------------------------------------------===// defm PseudoVWMUL : VPseudoVWMUL_VV_VX; defm PseudoVWMULU : VPseudoVWMUL_VV_VX; defm PseudoVWMULSU : VPseudoVWMUL_VV_VX; //===----------------------------------------------------------------------===// -// 12.13. Vector Single-Width Integer Multiply-Add Instructions +// 11.13. Vector Single-Width Integer Multiply-Add Instructions //===----------------------------------------------------------------------===// defm PseudoVMACC : VPseudoVMAC_VV_VX_AAXA; defm PseudoVNMSAC : VPseudoVMAC_VV_VX_AAXA; @@ -5289,7 +5289,7 @@ defm PseudoVNMSUB : VPseudoVMAC_VV_VX_AAXA; //===----------------------------------------------------------------------===// -// 12.14. Vector Widening Integer Multiply-Add Instructions +// 11.14. Vector Widening Integer Multiply-Add Instructions //===----------------------------------------------------------------------===// defm PseudoVWMACCU : VPseudoVWMAC_VV_VX; defm PseudoVWMACC : VPseudoVWMAC_VV_VX; @@ -5297,17 +5297,21 @@ defm PseudoVWMACCUS : VPseudoVWMAC_VX; //===----------------------------------------------------------------------===// -// 12.15. Vector Integer Merge Instructions +// 11.15. Vector Integer Merge Instructions //===----------------------------------------------------------------------===// defm PseudoVMERGE : VPseudoVMRG_VM_XM_IM; //===----------------------------------------------------------------------===// -// 12.16. Vector Integer Move Instructions +// 11.16. Vector Integer Move Instructions //===----------------------------------------------------------------------===// defm PseudoVMV_V : VPseudoUnaryVMV_V_X_I; //===----------------------------------------------------------------------===// -// 13.1. Vector Single-Width Saturating Add and Subtract +// 12. Vector Fixed-Point Arithmetic Instructions +//===----------------------------------------------------------------------===// + +//===----------------------------------------------------------------------===// +// 12.1. Vector Single-Width Saturating Add and Subtract //===----------------------------------------------------------------------===// let Defs = [VXSAT], hasSideEffects = 1 in { defm PseudoVSADDU : VPseudoVSALU_VV_VX_VI; @@ -5317,7 +5321,7 @@ } //===----------------------------------------------------------------------===// -// 13.2. Vector Single-Width Averaging Add and Subtract +// 12.2. Vector Single-Width Averaging Add and Subtract //===----------------------------------------------------------------------===// let Uses = [VXRM], hasSideEffects = 1 in { defm PseudoVAADDU : VPseudoVAALU_VV_VX; @@ -5327,14 +5331,14 @@ } //===----------------------------------------------------------------------===// -// 13.3. Vector Single-Width Fractional Multiply with Rounding and Saturation +// 12.3. Vector Single-Width Fractional Multiply with Rounding and Saturation //===----------------------------------------------------------------------===// let Uses = [VXRM], Defs = [VXSAT], hasSideEffects = 1 in { defm PseudoVSMUL : VPseudoVSMUL_VV_VX; } //===----------------------------------------------------------------------===// -// 13.4. Vector Single-Width Scaling Shift Instructions +// 12.4. Vector Single-Width Scaling Shift Instructions //===----------------------------------------------------------------------===// let Uses = [VXRM], hasSideEffects = 1 in { defm PseudoVSSRL : VPseudoVSSHT_VV_VX_VI; @@ -5342,7 +5346,7 @@ } //===----------------------------------------------------------------------===// -// 13.5. Vector Narrowing Fixed-Point Clip Instructions +// 12.5. Vector Narrowing Fixed-Point Clip Instructions //===----------------------------------------------------------------------===// let Uses = [VXRM], Defs = [VXSAT], hasSideEffects = 1 in { defm PseudoVNCLIP : VPseudoVNCLP_WV_WX_WI; @@ -5351,9 +5355,13 @@ } // Predicates = [HasVInstructions] +//===----------------------------------------------------------------------===// +// 13. Vector Floating-Point Instructions +//===----------------------------------------------------------------------===// + let Predicates = [HasVInstructionsAnyF] in { //===----------------------------------------------------------------------===// -// 14.2. Vector Single-Width Floating-Point Add/Subtract Instructions +// 13.2. Vector Single-Width Floating-Point Add/Subtract Instructions //===----------------------------------------------------------------------===// let Uses = [FRM], mayRaiseFPException = true in { defm PseudoVFADD : VPseudoVALU_VV_VF; @@ -5362,7 +5370,7 @@ } //===----------------------------------------------------------------------===// -// 14.3. Vector Widening Floating-Point Add/Subtract Instructions +// 13.3. Vector Widening Floating-Point Add/Subtract Instructions //===----------------------------------------------------------------------===// let Uses = [FRM], mayRaiseFPException = true in { defm PseudoVFWADD : VPseudoVFWALU_VV_VF; @@ -5372,7 +5380,7 @@ } //===----------------------------------------------------------------------===// -// 14.4. Vector Single-Width Floating-Point Multiply/Divide Instructions +// 13.4. Vector Single-Width Floating-Point Multiply/Divide Instructions //===----------------------------------------------------------------------===// let Uses = [FRM], mayRaiseFPException = true in { defm PseudoVFMUL : VPseudoVFMUL_VV_VF; @@ -5381,14 +5389,14 @@ } //===----------------------------------------------------------------------===// -// 14.5. Vector Widening Floating-Point Multiply +// 13.5. Vector Widening Floating-Point Multiply //===----------------------------------------------------------------------===// let Uses = [FRM], mayRaiseFPException = true in { defm PseudoVFWMUL : VPseudoVWMUL_VV_VF; } //===----------------------------------------------------------------------===// -// 14.6. Vector Single-Width Floating-Point Fused Multiply-Add Instructions +// 13.6. Vector Single-Width Floating-Point Fused Multiply-Add Instructions //===----------------------------------------------------------------------===// let Uses = [FRM], mayRaiseFPException = true in { defm PseudoVFMACC : VPseudoVMAC_VV_VF_AAXA; @@ -5402,7 +5410,7 @@ } //===----------------------------------------------------------------------===// -// 14.7. Vector Widening Floating-Point Fused Multiply-Add Instructions +// 13.7. Vector Widening Floating-Point Fused Multiply-Add Instructions //===----------------------------------------------------------------------===// let Uses = [FRM], mayRaiseFPException = true in { defm PseudoVFWMACC : VPseudoVWMAC_VV_VF; @@ -5412,25 +5420,25 @@ } //===----------------------------------------------------------------------===// -// 14.8. Vector Floating-Point Square-Root Instruction +// 13.8. Vector Floating-Point Square-Root Instruction //===----------------------------------------------------------------------===// let Uses = [FRM], mayRaiseFPException = true in defm PseudoVFSQRT : VPseudoVSQR_V; //===----------------------------------------------------------------------===// -// 14.9. Vector Floating-Point Reciprocal Square-Root Estimate Instruction +// 13.9. Vector Floating-Point Reciprocal Square-Root Estimate Instruction //===----------------------------------------------------------------------===// let mayRaiseFPException = true in defm PseudoVFRSQRT7 : VPseudoVRCP_V; //===----------------------------------------------------------------------===// -// 14.10. Vector Floating-Point Reciprocal Estimate Instruction +// 13.10. Vector Floating-Point Reciprocal Estimate Instruction //===----------------------------------------------------------------------===// let Uses = [FRM], mayRaiseFPException = true in defm PseudoVFREC7 : VPseudoVRCP_V; //===----------------------------------------------------------------------===// -// 14.11. Vector Floating-Point Min/Max Instructions +// 13.11. Vector Floating-Point Min/Max Instructions //===----------------------------------------------------------------------===// let mayRaiseFPException = true in { defm PseudoVFMIN : VPseudoVMAX_VV_VF; @@ -5438,14 +5446,14 @@ } //===----------------------------------------------------------------------===// -// 14.12. Vector Floating-Point Sign-Injection Instructions +// 13.12. Vector Floating-Point Sign-Injection Instructions //===----------------------------------------------------------------------===// defm PseudoVFSGNJ : VPseudoVSGNJ_VV_VF; defm PseudoVFSGNJN : VPseudoVSGNJ_VV_VF; defm PseudoVFSGNJX : VPseudoVSGNJ_VV_VF; //===----------------------------------------------------------------------===// -// 14.13. Vector Floating-Point Compare Instructions +// 13.13. Vector Floating-Point Compare Instructions //===----------------------------------------------------------------------===// let mayRaiseFPException = true in { defm PseudoVMFEQ : VPseudoVCMPM_VV_VF; @@ -5457,22 +5465,22 @@ } //===----------------------------------------------------------------------===// -// 14.14. Vector Floating-Point Classify Instruction +// 13.14. Vector Floating-Point Classify Instruction //===----------------------------------------------------------------------===// defm PseudoVFCLASS : VPseudoVCLS_V; //===----------------------------------------------------------------------===// -// 14.15. Vector Floating-Point Merge Instruction +// 13.15. Vector Floating-Point Merge Instruction //===----------------------------------------------------------------------===// defm PseudoVFMERGE : VPseudoVMRG_FM; //===----------------------------------------------------------------------===// -// 14.16. Vector Floating-Point Move Instruction +// 13.16. Vector Floating-Point Move Instruction //===----------------------------------------------------------------------===// defm PseudoVFMV_V : VPseudoVMV_F; //===----------------------------------------------------------------------===// -// 14.17. Single-Width Floating-Point/Integer Type-Convert Instructions +// 13.17. Single-Width Floating-Point/Integer Type-Convert Instructions //===----------------------------------------------------------------------===// let mayRaiseFPException = true in { let Uses = [FRM] in { @@ -5490,7 +5498,7 @@ } // mayRaiseFPException = true //===----------------------------------------------------------------------===// -// 14.18. Widening Floating-Point/Integer Type-Convert Instructions +// 13.18. Widening Floating-Point/Integer Type-Convert Instructions //===----------------------------------------------------------------------===// let mayRaiseFPException = true in { let Uses = [FRM] in { @@ -5505,7 +5513,7 @@ } // mayRaiseFPException = true //===----------------------------------------------------------------------===// -// 14.19. Narrowing Floating-Point/Integer Type-Convert Instructions +// 13.19. Narrowing Floating-Point/Integer Type-Convert Instructions //===----------------------------------------------------------------------===// let mayRaiseFPException = true in { let Uses = [FRM] in { @@ -5523,9 +5531,13 @@ } // mayRaiseFPException = true } // Predicates = [HasVInstructionsAnyF] +//===----------------------------------------------------------------------===// +// 14. Vector Reduction Operations +//===----------------------------------------------------------------------===// + let Predicates = [HasVInstructions] in { //===----------------------------------------------------------------------===// -// 15.1. Vector Single-Width Integer Reduction Instructions +// 14.1. Vector Single-Width Integer Reduction Instructions //===----------------------------------------------------------------------===// defm PseudoVREDSUM : VPseudoVRED_VS; defm PseudoVREDAND : VPseudoVRED_VS; @@ -5537,7 +5549,7 @@ defm PseudoVREDMAX : VPseudoVRED_VS; //===----------------------------------------------------------------------===// -// 15.2. Vector Widening Integer Reduction Instructions +// 14.2. Vector Widening Integer Reduction Instructions //===----------------------------------------------------------------------===// let IsRVVWideningReduction = 1 in { defm PseudoVWREDSUMU : VPseudoVWRED_VS; @@ -5547,7 +5559,7 @@ let Predicates = [HasVInstructionsAnyF] in { //===----------------------------------------------------------------------===// -// 15.3. Vector Single-Width Floating-Point Reduction Instructions +// 14.3. Vector Single-Width Floating-Point Reduction Instructions //===----------------------------------------------------------------------===// let Uses = [FRM], mayRaiseFPException = true in { defm PseudoVFREDOSUM : VPseudoVFREDO_VS; @@ -5559,7 +5571,7 @@ } //===----------------------------------------------------------------------===// -// 15.4. Vector Widening Floating-Point Reduction Instructions +// 14.4. Vector Widening Floating-Point Reduction Instructions //===----------------------------------------------------------------------===// let IsRVVWideningReduction = 1, Uses = [FRM], @@ -5571,11 +5583,11 @@ } // Predicates = [HasVInstructionsAnyF] //===----------------------------------------------------------------------===// -// 16. Vector Mask Instructions +// 15. Vector Mask Instructions //===----------------------------------------------------------------------===// //===----------------------------------------------------------------------===// -// 16.1 Vector Mask-Register Logical Instructions +// 15.1 Vector Mask-Register Logical Instructions //===----------------------------------------------------------------------===// defm PseudoVMAND: VPseudoVALU_MM; @@ -5592,48 +5604,48 @@ defm PseudoVMSET : VPseudoNullaryPseudoM<"VMXNOR">; //===----------------------------------------------------------------------===// -// 16.2. Vector mask population count vcpop +// 15.2. Vector mask population count vcpop //===----------------------------------------------------------------------===// defm PseudoVCPOP: VPseudoVPOP_M; //===----------------------------------------------------------------------===// -// 16.3. vfirst find-first-set mask bit +// 15.3. vfirst find-first-set mask bit //===----------------------------------------------------------------------===// defm PseudoVFIRST: VPseudoV1ST_M; //===----------------------------------------------------------------------===// -// 16.4. vmsbf.m set-before-first mask bit +// 15.4. vmsbf.m set-before-first mask bit //===----------------------------------------------------------------------===// defm PseudoVMSBF: VPseudoVSFS_M; //===----------------------------------------------------------------------===// -// 16.5. vmsif.m set-including-first mask bit +// 15.5. vmsif.m set-including-first mask bit //===----------------------------------------------------------------------===// defm PseudoVMSIF: VPseudoVSFS_M; //===----------------------------------------------------------------------===// -// 16.6. vmsof.m set-only-first mask bit +// 15.6. vmsof.m set-only-first mask bit //===----------------------------------------------------------------------===// defm PseudoVMSOF: VPseudoVSFS_M; //===----------------------------------------------------------------------===// -// 16.8. Vector Iota Instruction +// 15.8. Vector Iota Instruction //===----------------------------------------------------------------------===// defm PseudoVIOTA_M: VPseudoVIOT_M; //===----------------------------------------------------------------------===// -// 16.9. Vector Element Index Instruction +// 15.9. Vector Element Index Instruction //===----------------------------------------------------------------------===// defm PseudoVID : VPseudoVID_V; //===----------------------------------------------------------------------===// -// 17. Vector Permutation Instructions +// 16. Vector Permutation Instructions //===----------------------------------------------------------------------===// //===----------------------------------------------------------------------===// -// 17.1. Integer Scalar Move Instructions +// 16.1. Integer Scalar Move Instructions //===----------------------------------------------------------------------===// let Predicates = [HasVInstructions] in { @@ -5665,7 +5677,7 @@ } // Predicates = [HasVInstructions] //===----------------------------------------------------------------------===// -// 17.2. Floating-Point Scalar Move Instructions +// 16.2. Floating-Point Scalar Move Instructions //===----------------------------------------------------------------------===// let Predicates = [HasVInstructionsAnyF] in { @@ -5701,7 +5713,7 @@ } // Predicates = [HasVInstructionsAnyF] //===----------------------------------------------------------------------===// -// 17.3. Vector Slide Instructions +// 16.3. Vector Slide Instructions //===----------------------------------------------------------------------===// let Predicates = [HasVInstructions] in { defm PseudoVSLIDEUP : VPseudoVSLD_VX_VI; @@ -5716,13 +5728,13 @@ } // Predicates = [HasVInstructionsAnyF] //===----------------------------------------------------------------------===// -// 17.4. Vector Register Gather Instructions +// 16.4. Vector Register Gather Instructions //===----------------------------------------------------------------------===// defm PseudoVRGATHER : VPseudoVGTR_VV_VX_VI; defm PseudoVRGATHEREI16 : VPseudoVGTR_VV_EEW; //===----------------------------------------------------------------------===// -// 17.5. Vector Compress Instruction +// 16.5. Vector Compress Instruction //===----------------------------------------------------------------------===// defm PseudoVCOMPRESS : VPseudoVCPR_V; @@ -5731,19 +5743,19 @@ //===----------------------------------------------------------------------===// //===----------------------------------------------------------------------===// -// 12. Vector Integer Arithmetic Instructions +// 11. Vector Integer Arithmetic Instructions //===----------------------------------------------------------------------===// let Predicates = [HasVInstructions] in { //===----------------------------------------------------------------------===// -// 12.1. Vector Single-Width Integer Add and Subtract +// 11.1. Vector Single-Width Integer Add and Subtract //===----------------------------------------------------------------------===// defm : VPatBinaryV_VV_VX_VI<"int_riscv_vadd", "PseudoVADD", AllIntegerVectors>; defm : VPatBinaryV_VV_VX<"int_riscv_vsub", "PseudoVSUB", AllIntegerVectors>; defm : VPatBinaryV_VX_VI<"int_riscv_vrsub", "PseudoVRSUB", AllIntegerVectors>; //===----------------------------------------------------------------------===// -// 12.2. Vector Widening Integer Add/Subtract +// 11.2. Vector Widening Integer Add/Subtract //===----------------------------------------------------------------------===// defm : VPatBinaryW_VV_VX<"int_riscv_vwaddu", "PseudoVWADDU", AllWidenableIntVectors>; defm : VPatBinaryW_VV_VX<"int_riscv_vwsubu", "PseudoVWSUBU", AllWidenableIntVectors>; @@ -5755,7 +5767,7 @@ defm : VPatBinaryW_WV_WX<"int_riscv_vwsub_w", "PseudoVWSUB", AllWidenableIntVectors>; //===----------------------------------------------------------------------===// -// 12.3. Vector Integer Extension +// 11.3. Vector Integer Extension //===----------------------------------------------------------------------===// defm : VPatUnaryV_VF<"int_riscv_vzext", "PseudoVZEXT", "VF2", AllFractionableVF2IntVectors>; @@ -5771,7 +5783,7 @@ AllFractionableVF8IntVectors>; //===----------------------------------------------------------------------===// -// 12.4. Vector Integer Add-with-Carry / Subtract-with-Borrow Instructions +// 11.4. Vector Integer Add-with-Carry / Subtract-with-Borrow Instructions //===----------------------------------------------------------------------===// defm : VPatBinaryV_VM_XM_IM<"int_riscv_vadc", "PseudoVADC">; defm : VPatBinaryM_VM_XM_IM<"int_riscv_vmadc_carry_in", "PseudoVMADC">; @@ -5782,14 +5794,14 @@ defm : VPatBinaryM_V_X<"int_riscv_vmsbc", "PseudoVMSBC">; //===----------------------------------------------------------------------===// -// 12.5. Vector Bitwise Logical Instructions +// 11.5. Vector Bitwise Logical Instructions //===----------------------------------------------------------------------===// defm : VPatBinaryV_VV_VX_VI<"int_riscv_vand", "PseudoVAND", AllIntegerVectors>; defm : VPatBinaryV_VV_VX_VI<"int_riscv_vor", "PseudoVOR", AllIntegerVectors>; defm : VPatBinaryV_VV_VX_VI<"int_riscv_vxor", "PseudoVXOR", AllIntegerVectors>; //===----------------------------------------------------------------------===// -// 12.6. Vector Single-Width Bit Shift Instructions +// 11.6. Vector Single-Width Bit Shift Instructions //===----------------------------------------------------------------------===// defm : VPatBinaryV_VV_VX_VI<"int_riscv_vsll", "PseudoVSLL", AllIntegerVectors, uimm5>; @@ -5824,13 +5836,13 @@ } //===----------------------------------------------------------------------===// -// 12.7. Vector Narrowing Integer Right Shift Instructions +// 11.7. Vector Narrowing Integer Right Shift Instructions //===----------------------------------------------------------------------===// defm : VPatBinaryV_WV_WX_WI<"int_riscv_vnsrl", "PseudoVNSRL", AllWidenableIntVectors>; defm : VPatBinaryV_WV_WX_WI<"int_riscv_vnsra", "PseudoVNSRA", AllWidenableIntVectors>; //===----------------------------------------------------------------------===// -// 12.8. Vector Integer Comparison Instructions +// 11.8. Vector Integer Comparison Instructions //===----------------------------------------------------------------------===// defm : VPatBinaryM_VV_VX_VI<"int_riscv_vmseq", "PseudoVMSEQ", AllIntegerVectors>; defm : VPatBinaryM_VV_VX_VI<"int_riscv_vmsne", "PseudoVMSNE", AllIntegerVectors>; @@ -5861,7 +5873,7 @@ defm : VPatCompare_VI<"int_riscv_vmsgeu", "PseudoVMSGTU", simm5_plus1_nonzero>; //===----------------------------------------------------------------------===// -// 12.9. Vector Integer Min/Max Instructions +// 11.9. Vector Integer Min/Max Instructions //===----------------------------------------------------------------------===// defm : VPatBinaryV_VV_VX<"int_riscv_vminu", "PseudoVMINU", AllIntegerVectors>; defm : VPatBinaryV_VV_VX<"int_riscv_vmin", "PseudoVMIN", AllIntegerVectors>; @@ -5869,7 +5881,7 @@ defm : VPatBinaryV_VV_VX<"int_riscv_vmax", "PseudoVMAX", AllIntegerVectors>; //===----------------------------------------------------------------------===// -// 12.10. Vector Single-Width Integer Multiply Instructions +// 11.10. Vector Single-Width Integer Multiply Instructions //===----------------------------------------------------------------------===// defm : VPatBinaryV_VV_VX<"int_riscv_vmul", "PseudoVMUL", AllIntegerVectors>; defm : VPatBinaryV_VV_VX<"int_riscv_vmulh", "PseudoVMULH", AllIntegerVectors>; @@ -5877,7 +5889,7 @@ defm : VPatBinaryV_VV_VX<"int_riscv_vmulhsu", "PseudoVMULHSU", AllIntegerVectors>; //===----------------------------------------------------------------------===// -// 12.11. Vector Integer Divide Instructions +// 11.11. Vector Integer Divide Instructions //===----------------------------------------------------------------------===// defm : VPatBinaryV_VV_VX<"int_riscv_vdivu", "PseudoVDIVU", AllIntegerVectors>; defm : VPatBinaryV_VV_VX<"int_riscv_vdiv", "PseudoVDIV", AllIntegerVectors>; @@ -5885,14 +5897,14 @@ defm : VPatBinaryV_VV_VX<"int_riscv_vrem", "PseudoVREM", AllIntegerVectors>; //===----------------------------------------------------------------------===// -// 12.12. Vector Widening Integer Multiply Instructions +// 11.12. Vector Widening Integer Multiply Instructions //===----------------------------------------------------------------------===// defm : VPatBinaryW_VV_VX<"int_riscv_vwmul", "PseudoVWMUL", AllWidenableIntVectors>; defm : VPatBinaryW_VV_VX<"int_riscv_vwmulu", "PseudoVWMULU", AllWidenableIntVectors>; defm : VPatBinaryW_VV_VX<"int_riscv_vwmulsu", "PseudoVWMULSU", AllWidenableIntVectors>; //===----------------------------------------------------------------------===// -// 12.13. Vector Single-Width Integer Multiply-Add Instructions +// 11.13. Vector Single-Width Integer Multiply-Add Instructions //===----------------------------------------------------------------------===// defm : VPatTernaryV_VV_VX_AAXA<"int_riscv_vmadd", "PseudoVMADD", AllIntegerVectors>; defm : VPatTernaryV_VV_VX_AAXA<"int_riscv_vnmsub", "PseudoVNMSUB", AllIntegerVectors>; @@ -5900,7 +5912,7 @@ defm : VPatTernaryV_VV_VX_AAXA<"int_riscv_vnmsac", "PseudoVNMSAC", AllIntegerVectors>; //===----------------------------------------------------------------------===// -// 12.14. Vector Widening Integer Multiply-Add Instructions +// 11.14. Vector Widening Integer Multiply-Add Instructions //===----------------------------------------------------------------------===// defm : VPatTernaryW_VV_VX<"int_riscv_vwmaccu", "PseudoVWMACCU", AllWidenableIntVectors>; defm : VPatTernaryW_VV_VX<"int_riscv_vwmacc", "PseudoVWMACC", AllWidenableIntVectors>; @@ -5908,12 +5920,12 @@ defm : VPatTernaryW_VX<"int_riscv_vwmaccus", "PseudoVWMACCUS", AllWidenableIntVectors>; //===----------------------------------------------------------------------===// -// 12.15. Vector Integer Merge Instructions +// 11.15. Vector Integer Merge Instructions //===----------------------------------------------------------------------===// defm : VPatBinaryV_VM_XM_IM<"int_riscv_vmerge", "PseudoVMERGE">; //===----------------------------------------------------------------------===// -// 12.16. Vector Integer Move Instructions +// 11.16. Vector Integer Move Instructions //===----------------------------------------------------------------------===// foreach vti = AllVectors in { def : Pat<(vti.Vector (int_riscv_vmv_v_v (vti.Vector undef), @@ -5931,7 +5943,11 @@ } //===----------------------------------------------------------------------===// -// 13.1. Vector Single-Width Saturating Add and Subtract +// 12. Vector Fixed-Point Arithmetic Instructions +//===----------------------------------------------------------------------===// + +//===----------------------------------------------------------------------===// +// 12.1. Vector Single-Width Saturating Add and Subtract //===----------------------------------------------------------------------===// defm : VPatBinaryV_VV_VX_VI<"int_riscv_vsaddu", "PseudoVSADDU", AllIntegerVectors>; defm : VPatBinaryV_VV_VX_VI<"int_riscv_vsadd", "PseudoVSADD", AllIntegerVectors>; @@ -5939,7 +5955,7 @@ defm : VPatBinaryV_VV_VX<"int_riscv_vssub", "PseudoVSSUB", AllIntegerVectors>; //===----------------------------------------------------------------------===// -// 13.2. Vector Single-Width Averaging Add and Subtract +// 12.2. Vector Single-Width Averaging Add and Subtract //===----------------------------------------------------------------------===// defm : VPatBinaryV_VV_VX<"int_riscv_vaaddu", "PseudoVAADDU", AllIntegerVectors>; defm : VPatBinaryV_VV_VX<"int_riscv_vaadd", "PseudoVAADD", AllIntegerVectors>; @@ -5947,12 +5963,12 @@ defm : VPatBinaryV_VV_VX<"int_riscv_vasub", "PseudoVASUB", AllIntegerVectors>; //===----------------------------------------------------------------------===// -// 13.3. Vector Single-Width Fractional Multiply with Rounding and Saturation +// 12.3. Vector Single-Width Fractional Multiply with Rounding and Saturation //===----------------------------------------------------------------------===// defm : VPatBinaryV_VV_VX<"int_riscv_vsmul", "PseudoVSMUL", AllIntegerVectors>; //===----------------------------------------------------------------------===// -// 13.4. Vector Single-Width Scaling Shift Instructions +// 12.4. Vector Single-Width Scaling Shift Instructions //===----------------------------------------------------------------------===// defm : VPatBinaryV_VV_VX_VI<"int_riscv_vssrl", "PseudoVSSRL", AllIntegerVectors, uimm5>; @@ -5960,23 +5976,27 @@ uimm5>; //===----------------------------------------------------------------------===// -// 13.5. Vector Narrowing Fixed-Point Clip Instructions +// 12.5. Vector Narrowing Fixed-Point Clip Instructions //===----------------------------------------------------------------------===// defm : VPatBinaryV_WV_WX_WI<"int_riscv_vnclipu", "PseudoVNCLIPU", AllWidenableIntVectors>; defm : VPatBinaryV_WV_WX_WI<"int_riscv_vnclip", "PseudoVNCLIP", AllWidenableIntVectors>; } // Predicates = [HasVInstructions] +//===----------------------------------------------------------------------===// +// 13. Vector Floating-Point Instructions +//===----------------------------------------------------------------------===// + let Predicates = [HasVInstructionsAnyF] in { //===----------------------------------------------------------------------===// -// 14.2. Vector Single-Width Floating-Point Add/Subtract Instructions +// 13.2. Vector Single-Width Floating-Point Add/Subtract Instructions //===----------------------------------------------------------------------===// defm : VPatBinaryV_VV_VX<"int_riscv_vfadd", "PseudoVFADD", AllFloatVectors>; defm : VPatBinaryV_VV_VX<"int_riscv_vfsub", "PseudoVFSUB", AllFloatVectors>; defm : VPatBinaryV_VX<"int_riscv_vfrsub", "PseudoVFRSUB", AllFloatVectors>; //===----------------------------------------------------------------------===// -// 14.3. Vector Widening Floating-Point Add/Subtract Instructions +// 13.3. Vector Widening Floating-Point Add/Subtract Instructions //===----------------------------------------------------------------------===// defm : VPatBinaryW_VV_VX<"int_riscv_vfwadd", "PseudoVFWADD", AllWidenableFloatVectors>; defm : VPatBinaryW_VV_VX<"int_riscv_vfwsub", "PseudoVFWSUB", AllWidenableFloatVectors>; @@ -5984,19 +6004,19 @@ defm : VPatBinaryW_WV_WX<"int_riscv_vfwsub_w", "PseudoVFWSUB", AllWidenableFloatVectors>; //===----------------------------------------------------------------------===// -// 14.4. Vector Single-Width Floating-Point Multiply/Divide Instructions +// 13.4. Vector Single-Width Floating-Point Multiply/Divide Instructions //===----------------------------------------------------------------------===// defm : VPatBinaryV_VV_VX<"int_riscv_vfmul", "PseudoVFMUL", AllFloatVectors>; defm : VPatBinaryV_VV_VX<"int_riscv_vfdiv", "PseudoVFDIV", AllFloatVectors>; defm : VPatBinaryV_VX<"int_riscv_vfrdiv", "PseudoVFRDIV", AllFloatVectors>; //===----------------------------------------------------------------------===// -// 14.5. Vector Widening Floating-Point Multiply +// 13.5. Vector Widening Floating-Point Multiply //===----------------------------------------------------------------------===// defm : VPatBinaryW_VV_VX<"int_riscv_vfwmul", "PseudoVFWMUL", AllWidenableFloatVectors>; //===----------------------------------------------------------------------===// -// 14.6. Vector Single-Width Floating-Point Fused Multiply-Add Instructions +// 13.6. Vector Single-Width Floating-Point Fused Multiply-Add Instructions //===----------------------------------------------------------------------===// defm : VPatTernaryV_VV_VX_AAXA<"int_riscv_vfmacc", "PseudoVFMACC", AllFloatVectors>; defm : VPatTernaryV_VV_VX_AAXA<"int_riscv_vfnmacc", "PseudoVFNMACC", AllFloatVectors>; @@ -6008,7 +6028,7 @@ defm : VPatTernaryV_VV_VX_AAXA<"int_riscv_vfnmsub", "PseudoVFNMSUB", AllFloatVectors>; //===----------------------------------------------------------------------===// -// 14.7. Vector Widening Floating-Point Fused Multiply-Add Instructions +// 13.7. Vector Widening Floating-Point Fused Multiply-Add Instructions //===----------------------------------------------------------------------===// defm : VPatTernaryW_VV_VX<"int_riscv_vfwmacc", "PseudoVFWMACC", AllWidenableFloatVectors>; defm : VPatTernaryW_VV_VX<"int_riscv_vfwnmacc", "PseudoVFWNMACC", AllWidenableFloatVectors>; @@ -6016,35 +6036,35 @@ defm : VPatTernaryW_VV_VX<"int_riscv_vfwnmsac", "PseudoVFWNMSAC", AllWidenableFloatVectors>; //===----------------------------------------------------------------------===// -// 14.8. Vector Floating-Point Square-Root Instruction +// 13.8. Vector Floating-Point Square-Root Instruction //===----------------------------------------------------------------------===// defm : VPatUnaryV_V<"int_riscv_vfsqrt", "PseudoVFSQRT", AllFloatVectors>; //===----------------------------------------------------------------------===// -// 14.9. Vector Floating-Point Reciprocal Square-Root Estimate Instruction +// 13.9. Vector Floating-Point Reciprocal Square-Root Estimate Instruction //===----------------------------------------------------------------------===// defm : VPatUnaryV_V<"int_riscv_vfrsqrt7", "PseudoVFRSQRT7", AllFloatVectors>; //===----------------------------------------------------------------------===// -// 14.10. Vector Floating-Point Reciprocal Estimate Instruction +// 13.10. Vector Floating-Point Reciprocal Estimate Instruction //===----------------------------------------------------------------------===// defm : VPatUnaryV_V<"int_riscv_vfrec7", "PseudoVFREC7", AllFloatVectors>; //===----------------------------------------------------------------------===// -// 14.11. Vector Floating-Point Min/Max Instructions +// 13.11. Vector Floating-Point Min/Max Instructions //===----------------------------------------------------------------------===// defm : VPatBinaryV_VV_VX<"int_riscv_vfmin", "PseudoVFMIN", AllFloatVectors>; defm : VPatBinaryV_VV_VX<"int_riscv_vfmax", "PseudoVFMAX", AllFloatVectors>; //===----------------------------------------------------------------------===// -// 14.12. Vector Floating-Point Sign-Injection Instructions +// 13.12. Vector Floating-Point Sign-Injection Instructions //===----------------------------------------------------------------------===// defm : VPatBinaryV_VV_VX<"int_riscv_vfsgnj", "PseudoVFSGNJ", AllFloatVectors>; defm : VPatBinaryV_VV_VX<"int_riscv_vfsgnjn", "PseudoVFSGNJN", AllFloatVectors>; defm : VPatBinaryV_VV_VX<"int_riscv_vfsgnjx", "PseudoVFSGNJX", AllFloatVectors>; //===----------------------------------------------------------------------===// -// 14.13. Vector Floating-Point Compare Instructions +// 13.13. Vector Floating-Point Compare Instructions //===----------------------------------------------------------------------===// defm : VPatBinaryM_VV_VX<"int_riscv_vmfeq", "PseudoVMFEQ", AllFloatVectors>; defm : VPatBinaryM_VV_VX<"int_riscv_vmfle", "PseudoVMFLE", AllFloatVectors>; @@ -6056,12 +6076,12 @@ defm : VPatBinarySwappedM_VV<"int_riscv_vmfge", "PseudoVMFLE", AllFloatVectors>; //===----------------------------------------------------------------------===// -// 14.14. Vector Floating-Point Classify Instruction +// 13.14. Vector Floating-Point Classify Instruction //===----------------------------------------------------------------------===// defm : VPatConversionVI_VF<"int_riscv_vfclass", "PseudoVFCLASS">; //===----------------------------------------------------------------------===// -// 14.15. Vector Floating-Point Merge Instruction +// 13.15. Vector Floating-Point Merge Instruction //===----------------------------------------------------------------------===// // We can use vmerge.vvm to support vector-vector vfmerge. // NOTE: Clang previously used int_riscv_vfmerge for vector-vector, but now uses @@ -6090,7 +6110,7 @@ } //===----------------------------------------------------------------------===// -// 14.17. Single-Width Floating-Point/Integer Type-Convert Instructions +// 13.17. Single-Width Floating-Point/Integer Type-Convert Instructions //===----------------------------------------------------------------------===// defm : VPatConversionVI_VF<"int_riscv_vfcvt_xu_f_v", "PseudoVFCVT_XU_F">; defm : VPatConversionVI_VF<"int_riscv_vfcvt_rtz_xu_f_v", "PseudoVFCVT_RTZ_XU_F">; @@ -6100,7 +6120,7 @@ defm : VPatConversionVF_VI<"int_riscv_vfcvt_f_xu_v", "PseudoVFCVT_F_XU">; //===----------------------------------------------------------------------===// -// 14.18. Widening Floating-Point/Integer Type-Convert Instructions +// 13.18. Widening Floating-Point/Integer Type-Convert Instructions //===----------------------------------------------------------------------===// defm : VPatConversionWI_VF<"int_riscv_vfwcvt_xu_f_v", "PseudoVFWCVT_XU_F">; defm : VPatConversionWI_VF<"int_riscv_vfwcvt_x_f_v", "PseudoVFWCVT_X_F">; @@ -6111,7 +6131,7 @@ defm : VPatConversionWF_VF<"int_riscv_vfwcvt_f_f_v", "PseudoVFWCVT_F_F">; //===----------------------------------------------------------------------===// -// 14.19. Narrowing Floating-Point/Integer Type-Convert Instructions +// 13.19. Narrowing Floating-Point/Integer Type-Convert Instructions //===----------------------------------------------------------------------===// defm : VPatConversionVI_WF<"int_riscv_vfncvt_xu_f_w", "PseudoVFNCVT_XU_F">; defm : VPatConversionVI_WF<"int_riscv_vfncvt_x_f_w", "PseudoVFNCVT_X_F">; @@ -6123,9 +6143,13 @@ defm : VPatConversionVF_WF<"int_riscv_vfncvt_rod_f_f_w", "PseudoVFNCVT_ROD_F_F">; } // Predicates = [HasVInstructionsAnyF] +//===----------------------------------------------------------------------===// +// 14. Vector Reduction Operations +//===----------------------------------------------------------------------===// + let Predicates = [HasVInstructions] in { //===----------------------------------------------------------------------===// -// 15.1. Vector Single-Width Integer Reduction Instructions +// 14.1. Vector Single-Width Integer Reduction Instructions //===----------------------------------------------------------------------===// defm : VPatReductionV_VS<"int_riscv_vredsum", "PseudoVREDSUM">; defm : VPatReductionV_VS<"int_riscv_vredand", "PseudoVREDAND">; @@ -6137,7 +6161,7 @@ defm : VPatReductionV_VS<"int_riscv_vredmax", "PseudoVREDMAX">; //===----------------------------------------------------------------------===// -// 15.2. Vector Widening Integer Reduction Instructions +// 14.2. Vector Widening Integer Reduction Instructions //===----------------------------------------------------------------------===// defm : VPatReductionW_VS<"int_riscv_vwredsumu", "PseudoVWREDSUMU">; defm : VPatReductionW_VS<"int_riscv_vwredsum", "PseudoVWREDSUM">; @@ -6145,7 +6169,7 @@ let Predicates = [HasVInstructionsAnyF] in { //===----------------------------------------------------------------------===// -// 15.3. Vector Single-Width Floating-Point Reduction Instructions +// 14.3. Vector Single-Width Floating-Point Reduction Instructions //===----------------------------------------------------------------------===// defm : VPatReductionV_VS<"int_riscv_vfredosum", "PseudoVFREDOSUM", /*IsFloat=*/1>; defm : VPatReductionV_VS<"int_riscv_vfredusum", "PseudoVFREDUSUM", /*IsFloat=*/1>; @@ -6153,7 +6177,7 @@ defm : VPatReductionV_VS<"int_riscv_vfredmax", "PseudoVFREDMAX", /*IsFloat=*/1>; //===----------------------------------------------------------------------===// -// 15.4. Vector Widening Floating-Point Reduction Instructions +// 14.4. Vector Widening Floating-Point Reduction Instructions //===----------------------------------------------------------------------===// defm : VPatReductionW_VS<"int_riscv_vfwredusum", "PseudoVFWREDUSUM", /*IsFloat=*/1>; defm : VPatReductionW_VS<"int_riscv_vfwredosum", "PseudoVFWREDOSUM", /*IsFloat=*/1>; @@ -6161,12 +6185,12 @@ } // Predicates = [HasVInstructionsAnyF] //===----------------------------------------------------------------------===// -// 16. Vector Mask Instructions +// 15. Vector Mask Instructions //===----------------------------------------------------------------------===// let Predicates = [HasVInstructions] in { //===----------------------------------------------------------------------===// -// 16.1 Vector Mask-Register Logical Instructions +// 15.1 Vector Mask-Register Logical Instructions //===----------------------------------------------------------------------===// defm : VPatBinaryM_MM<"int_riscv_vmand", "PseudoVMAND">; defm : VPatBinaryM_MM<"int_riscv_vmnand", "PseudoVMNAND">; @@ -6182,48 +6206,48 @@ defm : VPatNullaryM<"int_riscv_vmset", "PseudoVMSET">; //===----------------------------------------------------------------------===// -// 16.2. Vector count population in mask vcpop.m +// 15.2. Vector count population in mask vcpop.m //===----------------------------------------------------------------------===// defm : VPatUnaryS_M<"int_riscv_vcpop", "PseudoVCPOP">; //===----------------------------------------------------------------------===// -// 16.3. vfirst find-first-set mask bit +// 15.3. vfirst find-first-set mask bit //===----------------------------------------------------------------------===// defm : VPatUnaryS_M<"int_riscv_vfirst", "PseudoVFIRST">; //===----------------------------------------------------------------------===// -// 16.4. vmsbf.m set-before-first mask bit +// 15.4. vmsbf.m set-before-first mask bit //===----------------------------------------------------------------------===// defm : VPatUnaryM_M<"int_riscv_vmsbf", "PseudoVMSBF">; //===----------------------------------------------------------------------===// -// 16.5. vmsif.m set-including-first mask bit +// 15.5. vmsif.m set-including-first mask bit //===----------------------------------------------------------------------===// defm : VPatUnaryM_M<"int_riscv_vmsif", "PseudoVMSIF">; //===----------------------------------------------------------------------===// -// 16.6. vmsof.m set-only-first mask bit +// 15.6. vmsof.m set-only-first mask bit //===----------------------------------------------------------------------===// defm : VPatUnaryM_M<"int_riscv_vmsof", "PseudoVMSOF">; //===----------------------------------------------------------------------===// -// 16.8. Vector Iota Instruction +// 15.8. Vector Iota Instruction //===----------------------------------------------------------------------===// defm : VPatUnaryV_M<"int_riscv_viota", "PseudoVIOTA">; //===----------------------------------------------------------------------===// -// 16.9. Vector Element Index Instruction +// 15.9. Vector Element Index Instruction //===----------------------------------------------------------------------===// defm : VPatNullaryV<"int_riscv_vid", "PseudoVID">; } // Predicates = [HasVInstructions] //===----------------------------------------------------------------------===// -// 17. Vector Permutation Instructions +// 16. Vector Permutation Instructions //===----------------------------------------------------------------------===// //===----------------------------------------------------------------------===// -// 17.1. Integer Scalar Move Instructions +// 16.1. Integer Scalar Move Instructions //===----------------------------------------------------------------------===// let Predicates = [HasVInstructions] in { @@ -6235,7 +6259,7 @@ } // Predicates = [HasVInstructions] //===----------------------------------------------------------------------===// -// 17.2. Floating-Point Scalar Move Instructions +// 16.2. Floating-Point Scalar Move Instructions //===----------------------------------------------------------------------===// let Predicates = [HasVInstructionsAnyF] in { @@ -6261,7 +6285,7 @@ } // Predicates = [HasVInstructionsAnyF] //===----------------------------------------------------------------------===// -// 17.3. Vector Slide Instructions +// 16.3. Vector Slide Instructions //===----------------------------------------------------------------------===// let Predicates = [HasVInstructions] in { defm : VPatTernaryV_VX_VI<"int_riscv_vslideup", "PseudoVSLIDEUP", AllIntegerVectors, uimm5>; @@ -6278,7 +6302,7 @@ } // Predicates = [HasVInstructionsAnyF] //===----------------------------------------------------------------------===// -// 17.4. Vector Register Gather Instructions +// 16.4. Vector Register Gather Instructions //===----------------------------------------------------------------------===// let Predicates = [HasVInstructions] in { defm : VPatBinaryV_VV_VX_VI_INT<"int_riscv_vrgather", "PseudoVRGATHER", @@ -6295,7 +6319,7 @@ } // Predicates = [HasVInstructionsAnyF] //===----------------------------------------------------------------------===// -// 17.5. Vector Compress Instruction +// 16.5. Vector Compress Instruction //===----------------------------------------------------------------------===// let Predicates = [HasVInstructions] in { defm : VPatUnaryV_V_AnyMask<"int_riscv_vcompress", "PseudoVCOMPRESS", AllIntegerVectors>; diff --git a/llvm/lib/Target/RISCV/RISCVInstrInfoVSDPatterns.td b/llvm/lib/Target/RISCV/RISCVInstrInfoVSDPatterns.td --- a/llvm/lib/Target/RISCV/RISCVInstrInfoVSDPatterns.td +++ b/llvm/lib/Target/RISCV/RISCVInstrInfoVSDPatterns.td @@ -616,7 +616,9 @@ foreach mti = AllMasks in defm : VPatUSLoadStoreMaskSDNode; -// 12.1. Vector Single-Width Integer Add and Subtract +// 11. Vector Integer Arithmetic Instructions + +// 11.1. Vector Single-Width Integer Add and Subtract defm : VPatBinarySDNode_VV_VX_VI; defm : VPatBinarySDNode_VV_VX; // Handle VRSUB specially since it's the only integer binary op with reversed @@ -632,7 +634,7 @@ vti.RegClass:$rs1, simm5:$rs2, vti.AVL, vti.Log2SEW)>; } -// 12.2. Vector Widening Integer Add and Subtract +// 11.2. Vector Widening Integer Add and Subtract defm : VPatWidenBinarySDNode_VV_VX_WV_WX; defm : VPatWidenBinarySDNode_VV_VX_WV_WX; defm : VPatWidenBinarySDNode_VV_VX_WV_WX; @@ -641,7 +643,7 @@ defm : VPatWidenBinarySDNode_VV_VX_WV_WX; defm : VPatWidenBinarySDNode_VV_VX_WV_WX; -// 12.3. Vector Integer Extension +// 11.3. Vector Integer Extension defm : VPatExtendSDNode_V<[zext, anyext], "PseudoVZEXT", "VF2", AllFractionableVF2IntVectors>; defm : VPatExtendSDNode_V<[sext], "PseudoVSEXT", "VF2", @@ -655,12 +657,12 @@ defm : VPatExtendSDNode_V<[sext], "PseudoVSEXT", "VF8", AllFractionableVF8IntVectors>; -// 12.5. Vector Bitwise Logical Instructions +// 11.5. Vector Bitwise Logical Instructions defm : VPatBinarySDNode_VV_VX_VI; defm : VPatBinarySDNode_VV_VX_VI; defm : VPatBinarySDNode_VV_VX_VI; -// 12.6. Vector Single-Width Bit Shift Instructions +// 11.6. Vector Single-Width Bit Shift Instructions defm : VPatBinarySDNode_VV_VX_VI; defm : VPatBinarySDNode_VV_VX_VI; defm : VPatBinarySDNode_VV_VX_VI; @@ -674,7 +676,7 @@ } -// 12.8. Vector Integer Comparison Instructions +// 11.8. Vector Integer Comparison Instructions defm : VPatIntegerSetCCSDNode_VV<"PseudoVMSEQ", SETEQ>; defm : VPatIntegerSetCCSDNode_VV<"PseudoVMSNE", SETNE>; @@ -709,24 +711,24 @@ defm : VPatIntegerSetCCSDNode_VIPlus1<"PseudoVMSGTU", SETUGE, SplatPat_simm5_plus1_nonzero>; -// 12.9. Vector Integer Min/Max Instructions +// 11.9. Vector Integer Min/Max Instructions defm : VPatBinarySDNode_VV_VX; defm : VPatBinarySDNode_VV_VX; defm : VPatBinarySDNode_VV_VX; defm : VPatBinarySDNode_VV_VX; -// 12.10. Vector Single-Width Integer Multiply Instructions +// 11.10. Vector Single-Width Integer Multiply Instructions defm : VPatBinarySDNode_VV_VX; defm : VPatBinarySDNode_VV_VX; defm : VPatBinarySDNode_VV_VX; -// 12.11. Vector Integer Divide Instructions +// 11.11. Vector Integer Divide Instructions defm : VPatBinarySDNode_VV_VX; defm : VPatBinarySDNode_VV_VX; defm : VPatBinarySDNode_VV_VX; defm : VPatBinarySDNode_VV_VX; -// 12.12. Vector Widening Integer Multiply Instructions +// 11.12. Vector Widening Integer Multiply Instructions defm : VPatWidenBinarySDNode_VV_VX; defm : VPatWidenBinarySDNode_VV_VX; -// 12.13 Vector Single-Width Integer Multiply-Add Instructions. +// 11.13 Vector Single-Width Integer Multiply-Add Instructions. defm : VPatMultiplyAddSDNode_VV_VX; defm : VPatMultiplyAddSDNode_VV_VX; -// 12.14 Vector Widening Integer Multiply-Add Instructions +// 11.14 Vector Widening Integer Multiply-Add Instructions defm : VPatWidenMulAddSDNode_VV; defm : VPatWidenMulAddSDNode_VX; defm : VPatWidenMulAddSDNode_VV; @@ -753,7 +755,7 @@ defm : VPatWidenMulAddSDNode_VX; defm : VPatWidenMulAddSDNode_VX; -// 12.15. Vector Integer Merge Instructions +// 11.15. Vector Integer Merge Instructions foreach vti = AllIntegerVectors in { def : Pat<(vti.Vector (vselect (vti.Mask V0), vti.RegClass:$rs1, vti.RegClass:$rs2)), @@ -772,13 +774,17 @@ vti.RegClass:$rs2, simm5:$rs1, (vti.Mask V0), vti.AVL, vti.Log2SEW)>; } +// 12. Vector Fixed-Point Arithmetic Instructions + // 12.1. Vector Single-Width Saturating Add and Subtract defm : VPatBinarySDNode_VV_VX_VI; defm : VPatBinarySDNode_VV_VX_VI; defm : VPatBinarySDNode_VV_VX; defm : VPatBinarySDNode_VV_VX; -// 16.1. Vector Mask-Register Logical Instructions +// 15. Vector Mask Instructions + +// 15.1. Vector Mask-Register Logical Instructions foreach mti = AllMasks in { def : Pat<(mti.Mask (and VR:$rs1, VR:$rs2)), (!cast("PseudoVMAND_MM_"#mti.LMul.MX) @@ -815,26 +821,28 @@ } // Predicates = [HasVInstructions] +// 13. Vector Floating-Point Instructions + let Predicates = [HasVInstructionsAnyF] in { -// 14.2. Vector Single-Width Floating-Point Add/Subtract Instructions +// 13.2. Vector Single-Width Floating-Point Add/Subtract Instructions defm : VPatBinaryFPSDNode_VV_VF; defm : VPatBinaryFPSDNode_VV_VF; defm : VPatBinaryFPSDNode_R_VF; -// 14.3. Vector Widening Floating-Point Add/Subtract Instructions +// 13.3. Vector Widening Floating-Point Add/Subtract Instructions defm : VPatWidenBinaryFPSDNode_VV_VF_WV_WF; defm : VPatWidenBinaryFPSDNode_VV_VF_WV_WF; -// 14.4. Vector Single-Width Floating-Point Multiply/Divide Instructions +// 13.4. Vector Single-Width Floating-Point Multiply/Divide Instructions defm : VPatBinaryFPSDNode_VV_VF; defm : VPatBinaryFPSDNode_VV_VF; defm : VPatBinaryFPSDNode_R_VF; -// 14.5. Vector Widening Floating-Point Multiply Instructions +// 13.5. Vector Widening Floating-Point Multiply Instructions defm : VPatWidenBinaryFPSDNode_VV_VF; -// 14.6 Vector Single-Width Floating-Point Fused Multiply-Add Instructions. +// 13.6 Vector Single-Width Floating-Point Fused Multiply-Add Instructions. foreach fvti = AllFloatVectors in { // NOTE: We choose VFMADD because it has the most commuting freedom. So it // works best with how TwoAddressInstructionPass tries commuting. @@ -897,19 +905,19 @@ fvti.AVL, fvti.Log2SEW, TAIL_AGNOSTIC)>; } -// 14.7. Vector Widening Floating-Point Fused Multiply-Add Instructions +// 13.7. Vector Widening Floating-Point Fused Multiply-Add Instructions defm : VPatWidenFPMulAccSDNode_VV_VF<"PseudoVFWMACC">; defm : VPatWidenFPNegMulAccSDNode_VV_VF<"PseudoVFWNMACC">; defm : VPatWidenFPMulSacSDNode_VV_VF<"PseudoVFWMSAC">; defm : VPatWidenFPNegMulSacSDNode_VV_VF<"PseudoVFWNMSAC">; foreach vti = AllFloatVectors in { - // 14.8. Vector Floating-Point Square-Root Instruction + // 13.8. Vector Floating-Point Square-Root Instruction def : Pat<(fsqrt (vti.Vector vti.RegClass:$rs2)), (!cast("PseudoVFSQRT_V_"# vti.LMul.MX) vti.RegClass:$rs2, vti.AVL, vti.Log2SEW)>; - // 14.12. Vector Floating-Point Sign-Injection Instructions + // 13.12. Vector Floating-Point Sign-Injection Instructions def : Pat<(fabs (vti.Vector vti.RegClass:$rs)), (!cast("PseudoVFSGNJX_VV_"# vti.LMul.MX) vti.RegClass:$rs, vti.RegClass:$rs, vti.AVL, vti.Log2SEW)>; @@ -937,11 +945,11 @@ vti.RegClass:$rs1, vti.ScalarRegClass:$rs2, vti.AVL, vti.Log2SEW)>; } -// 14.11. Vector Floating-Point MIN/MAX Instructions +// 13.11. Vector Floating-Point MIN/MAX Instructions defm : VPatBinaryFPSDNode_VV_VF; defm : VPatBinaryFPSDNode_VV_VF; -// 14.13. Vector Floating-Point Compare Instructions +// 13.13. Vector Floating-Point Compare Instructions defm : VPatFPSetCCSDNode_VV_VF_FV; defm : VPatFPSetCCSDNode_VV_VF_FV; @@ -955,8 +963,8 @@ defm : VPatFPSetCCSDNode_VV_VF_FV; // Floating-point vselects: -// 12.15. Vector Integer Merge Instructions -// 14.15. Vector Floating-Point Merge Instruction +// 11.15. Vector Integer Merge Instructions +// 13.15. Vector Floating-Point Merge Instruction foreach fvti = AllFloatVectors in { def : Pat<(fvti.Vector (vselect (fvti.Mask V0), fvti.RegClass:$rs1, fvti.RegClass:$rs2)), @@ -979,19 +987,19 @@ fvti.RegClass:$rs2, 0, (fvti.Mask V0), fvti.AVL, fvti.Log2SEW)>; } -// 14.17. Vector Single-Width Floating-Point/Integer Type-Convert Instructions +// 13.17. Vector Single-Width Floating-Point/Integer Type-Convert Instructions defm : VPatConvertFP2ISDNode_V; defm : VPatConvertFP2ISDNode_V; defm : VPatConvertI2FPSDNode_V; defm : VPatConvertI2FPSDNode_V; -// 14.18. Widening Floating-Point/Integer Type-Convert Instructions +// 13.18. Widening Floating-Point/Integer Type-Convert Instructions defm : VPatWConvertFP2ISDNode_V; defm : VPatWConvertFP2ISDNode_V; defm : VPatWConvertI2FPSDNode_V; defm : VPatWConvertI2FPSDNode_V; -// 14.19. Narrowing Floating-Point/Integer Type-Convert Instructions +// 13.19. Narrowing Floating-Point/Integer Type-Convert Instructions defm : VPatNConvertFP2ISDNode_V; defm : VPatNConvertFP2ISDNode_V; defm : VPatNConvertI2FPSDNode_V; diff --git a/llvm/lib/Target/RISCV/RISCVInstrInfoVVLPatterns.td b/llvm/lib/Target/RISCV/RISCVInstrInfoVVLPatterns.td --- a/llvm/lib/Target/RISCV/RISCVInstrInfoVVLPatterns.td +++ b/llvm/lib/Target/RISCV/RISCVInstrInfoVVLPatterns.td @@ -1266,7 +1266,9 @@ let Predicates = [HasVInstructions] in { -// 12.1. Vector Single-Width Integer Add and Subtract +// 11. Vector Integer Arithmetic Instructions + +// 11.1. Vector Single-Width Integer Add and Subtract defm : VPatBinaryVL_VV_VX_VI; defm : VPatBinaryVL_VV_VX; // Handle VRSUB specially since it's the only integer binary op with reversed @@ -1286,13 +1288,13 @@ (vti.Mask V0), GPR:$vl, vti.Log2SEW, TAIL_AGNOSTIC)>; } -// 12.2. Vector Widening Integer Add/Subtract +// 11.2. Vector Widening Integer Add/Subtract defm : VPatBinaryWVL_VV_VX_WV_WX; defm : VPatBinaryWVL_VV_VX_WV_WX; defm : VPatBinaryWVL_VV_VX_WV_WX; defm : VPatBinaryWVL_VV_VX_WV_WX; -// 12.3. Vector Integer Extension +// 11.3. Vector Integer Extension defm : VPatExtendVL_V; defm : VPatExtendVL_V; -// 12.5. Vector Bitwise Logical Instructions +// 11.5. Vector Bitwise Logical Instructions defm : VPatBinaryVL_VV_VX_VI; defm : VPatBinaryVL_VV_VX_VI; defm : VPatBinaryVL_VV_VX_VI; -// 12.6. Vector Single-Width Bit Shift Instructions +// 11.6. Vector Single-Width Bit Shift Instructions defm : VPatBinaryVL_VV_VX_VI; defm : VPatBinaryVL_VV_VX_VI; defm : VPatBinaryVL_VV_VX_VI; @@ -1325,7 +1327,7 @@ vti.RegClass:$rs1, vti.RegClass:$rs1, GPR:$vl, vti.Log2SEW)>; } -// 12.7. Vector Narrowing Integer Right Shift Instructions +// 11.7. Vector Narrowing Integer Right Shift Instructions defm : VPatBinaryVL_WV_WX_WI; defm : VPatBinaryVL_WV_WX_WI; @@ -1349,7 +1351,7 @@ (vti.Mask V0), GPR:$vl, vti.Log2SEW, TA_MA)>; } -// 12.8. Vector Integer Comparison Instructions +// 11.8. Vector Integer Comparison Instructions foreach vti = AllIntegerVectors in { defm : VPatIntegerSetCCVL_VV; defm : VPatIntegerSetCCVL_VV; @@ -1386,35 +1388,35 @@ SplatPat_simm5_plus1_nonzero>; } // foreach vti = AllIntegerVectors -// 12.9. Vector Integer Min/Max Instructions +// 11.9. Vector Integer Min/Max Instructions defm : VPatBinaryVL_VV_VX; defm : VPatBinaryVL_VV_VX; defm : VPatBinaryVL_VV_VX; defm : VPatBinaryVL_VV_VX; -// 12.10. Vector Single-Width Integer Multiply Instructions +// 11.10. Vector Single-Width Integer Multiply Instructions defm : VPatBinaryVL_VV_VX; defm : VPatBinaryVL_VV_VX; defm : VPatBinaryVL_VV_VX; -// 12.11. Vector Integer Divide Instructions +// 11.11. Vector Integer Divide Instructions defm : VPatBinaryVL_VV_VX; defm : VPatBinaryVL_VV_VX; defm : VPatBinaryVL_VV_VX; defm : VPatBinaryVL_VV_VX; -// 12.12. Vector Widening Integer Multiply Instructions +// 11.12. Vector Widening Integer Multiply Instructions defm : VPatBinaryWVL_VV_VX; defm : VPatBinaryWVL_VV_VX; defm : VPatBinaryWVL_VV_VX; -// 12.13 Vector Single-Width Integer Multiply-Add Instructions +// 11.13 Vector Single-Width Integer Multiply-Add Instructions defm : VPatMultiplyAddVL_VV_VX; defm : VPatMultiplyAddVL_VV_VX; defm : VPatMultiplyAccVL_VV_VX; defm : VPatMultiplyAccVL_VV_VX; -// 12.14. Vector Widening Integer Multiply-Add Instructions +// 11.14. Vector Widening Integer Multiply-Add Instructions defm : VPatWidenMultiplyAddVL_VV_VX; defm : VPatWidenMultiplyAddVL_VV_VX; defm : VPatWidenMultiplyAddVL_VV_VX; @@ -1434,7 +1436,7 @@ GPR:$vl, vti.Log2SEW, TAIL_AGNOSTIC)>; } -// 12.15. Vector Integer Merge Instructions +// 11.15. Vector Integer Merge Instructions foreach vti = AllIntegerVectors in { def : Pat<(vti.Vector (riscv_vselect_vl (vti.Mask V0), vti.RegClass:$rs1, @@ -1483,7 +1485,7 @@ (vti.Mask V0), GPR:$vl, vti.Log2SEW)>; } -// 12.16. Vector Integer Move Instructions +// 11.16. Vector Integer Move Instructions foreach vti = AllIntegerVectors in { def : Pat<(vti.Vector (riscv_vmv_v_x_vl (vti.Vector undef), GPR:$rs2, VLOpFrag)), (!cast("PseudoVMV_V_X_"#vti.LMul.MX) @@ -1502,6 +1504,8 @@ $passthru, XLenVT:$imm5, GPR:$vl, vti.Log2SEW)>; } +// 12. Vector Fixed-Point Arithmetic Instructions + // 12.1. Vector Single-Width Saturating Add and Subtract defm : VPatBinaryVL_VV_VX_VI; defm : VPatBinaryVL_VV_VX_VI; @@ -1510,59 +1514,28 @@ } // Predicates = [HasVInstructions] -// 15.1. Vector Single-Width Integer Reduction Instructions -let Predicates = [HasVInstructions] in { -defm : VPatReductionVL; -defm : VPatReductionVL; -defm : VPatReductionVL; -defm : VPatReductionVL; -defm : VPatReductionVL; -defm : VPatReductionVL; -defm : VPatReductionVL; -defm : VPatReductionVL; +// 13. Vector Floating-Point Instructions -// 15.2. Vector Widening Integer Reduction Instructions -defm : VPatWidenReductionVL; -defm : VPatWidenReductionVL; -defm : VPatWidenReductionVL_Ext_VL; -defm : VPatWidenReductionVL; -defm : VPatWidenReductionVL_Ext_VL; -} // Predicates = [HasVInstructions] - -// 15.3. Vector Single-Width Floating-Point Reduction Instructions let Predicates = [HasVInstructionsAnyF] in { -defm : VPatReductionVL; -defm : VPatReductionVL; -defm : VPatReductionVL; -defm : VPatReductionVL; -// 15.4. Vector Widening Floating-Point Reduction Instructions -defm : VPatWidenReductionVL; -defm : VPatWidenReductionVL_Ext_VL; -defm : VPatWidenReductionVL; -defm : VPatWidenReductionVL_Ext_VL; -} // Predicates = [HasVInstructionsAnyF] - -let Predicates = [HasVInstructionsAnyF] in { - -// 14.2. Vector Single-Width Floating-Point Add/Subtract Instructions +// 13.2. Vector Single-Width Floating-Point Add/Subtract Instructions defm : VPatBinaryFPVL_VV_VF; defm : VPatBinaryFPVL_VV_VF; defm : VPatBinaryFPVL_R_VF; -// 14.3. Vector Widening Floating-Point Add/Subtract Instructions +// 13.3. Vector Widening Floating-Point Add/Subtract Instructions defm : VPatWidenBinaryFPVL_VV_VF_WV_WF; defm : VPatWidenBinaryFPVL_VV_VF_WV_WF; -// 14.4. Vector Single-Width Floating-Point Multiply/Divide Instructions +// 13.4. Vector Single-Width Floating-Point Multiply/Divide Instructions defm : VPatBinaryFPVL_VV_VF; defm : VPatBinaryFPVL_VV_VF; defm : VPatBinaryFPVL_R_VF; -// 14.5. Vector Widening Floating-Point Multiply Instructions +// 13.5. Vector Widening Floating-Point Multiply Instructions defm : VPatWidenBinaryFPVL_VV_VF; -// 14.6 Vector Single-Width Floating-Point Fused Multiply-Add Instructions. +// 13.6 Vector Single-Width Floating-Point Fused Multiply-Add Instructions. defm : VPatFPMulAddVL_VV_VF; defm : VPatFPMulAddVL_VV_VF; defm : VPatFPMulAddVL_VV_VF; @@ -1572,17 +1545,17 @@ defm : VPatFPMulAccVL_VV_VF; defm : VPatFPMulAccVL_VV_VF; -// 14.7. Vector Widening Floating-Point Fused Multiply-Add Instructions +// 13.7. Vector Widening Floating-Point Fused Multiply-Add Instructions defm : VPatWidenFPMulAccVL_VV_VF; defm : VPatWidenFPMulAccVL_VV_VF; defm : VPatWidenFPMulAccVL_VV_VF; defm : VPatWidenFPMulAccVL_VV_VF; -// 14.11. Vector Floating-Point MIN/MAX Instructions +// 13.11. Vector Floating-Point MIN/MAX Instructions defm : VPatBinaryFPVL_VV_VF; defm : VPatBinaryFPVL_VV_VF; -// 14.13. Vector Floating-Point Compare Instructions +// 13.13. Vector Floating-Point Compare Instructions defm : VPatFPSetCCVL_VV_VF_FV; defm : VPatFPSetCCVL_VV_VF_FV; @@ -1596,14 +1569,14 @@ defm : VPatFPSetCCVL_VV_VF_FV; foreach vti = AllFloatVectors in { - // 14.8. Vector Floating-Point Square-Root Instruction + // 13.8. Vector Floating-Point Square-Root Instruction def : Pat<(riscv_fsqrt_vl (vti.Vector vti.RegClass:$rs2), (vti.Mask V0), VLOpFrag), (!cast("PseudoVFSQRT_V_"# vti.LMul.MX #"_MASK") (vti.Vector (IMPLICIT_DEF)), vti.RegClass:$rs2, (vti.Mask V0), GPR:$vl, vti.Log2SEW, TA_MA)>; - // 14.12. Vector Floating-Point Sign-Injection Instructions + // 13.12. Vector Floating-Point Sign-Injection Instructions def : Pat<(riscv_fabs_vl (vti.Vector vti.RegClass:$rs), (vti.Mask V0), VLOpFrag), (!cast("PseudoVFSGNJX_VV_"# vti.LMul.MX #"_MASK") @@ -1658,8 +1631,8 @@ foreach fvti = AllFloatVectors in { // Floating-point vselects: - // 12.15. Vector Integer Merge Instructions - // 14.15. Vector Floating-Point Merge Instruction + // 11.15. Vector Integer Merge Instructions + // 13.15. Vector Floating-Point Merge Instruction def : Pat<(fvti.Vector (riscv_vselect_vl (fvti.Mask V0), fvti.RegClass:$rs1, fvti.RegClass:$rs2, @@ -1709,7 +1682,7 @@ fvti.RegClass:$rs2, fvti.RegClass:$rs2, 0, (fvti.Mask V0), GPR:$vl, fvti.Log2SEW)>; - // 14.16. Vector Floating-Point Move Instruction + // 13.16. Vector Floating-Point Move Instruction // If we're splatting fpimm0, use vmv.v.x vd, x0. def : Pat<(fvti.Vector (riscv_vfmv_v_f_vl (fvti.Vector undef), (fvti.Scalar (fpimm0)), VLOpFrag)), @@ -1733,7 +1706,7 @@ $passthru, (fvti.Scalar fvti.ScalarRegClass:$rs2), GPR:$vl, fvti.Log2SEW)>; - // 14.17. Vector Single-Width Floating-Point/Integer Type-Convert Instructions + // 13.17. Vector Single-Width Floating-Point/Integer Type-Convert Instructions defm : VPatConvertFP2I_RM_VL_V; defm : VPatConvertFP2IVL_V; defm : VPatConvertFP2IVL_V; @@ -1741,7 +1714,7 @@ defm : VPatConvertI2FPVL_V; defm : VPatConvertI2FPVL_V; - // 14.18. Widening Floating-Point/Integer Type-Convert Instructions + // 13.18. Widening Floating-Point/Integer Type-Convert Instructions defm : VPatWConvertFP2IVL_V; defm : VPatWConvertFP2IVL_V; defm : VPatWConvertI2FPVL_V; @@ -1757,7 +1730,7 @@ (fvti.Mask V0), GPR:$vl, fvti.Log2SEW, TA_MA)>; } - // 14.19 Narrowing Floating-Point/Integer Type-Convert Instructions + // 13.19 Narrowing Floating-Point/Integer Type-Convert Instructions defm : VPatNConvertFP2IVL_V; defm : VPatNConvertFP2IVL_V; defm : VPatNConvertI2FPVL_V; @@ -1783,10 +1756,47 @@ } // Predicates = [HasVInstructionsAnyF] +// 14. Vector Reduction Operations + +// 14.1. Vector Single-Width Integer Reduction Instructions +let Predicates = [HasVInstructions] in { +defm : VPatReductionVL; +defm : VPatReductionVL; +defm : VPatReductionVL; +defm : VPatReductionVL; +defm : VPatReductionVL; +defm : VPatReductionVL; +defm : VPatReductionVL; +defm : VPatReductionVL; + +// 14.2. Vector Widening Integer Reduction Instructions +defm : VPatWidenReductionVL; +defm : VPatWidenReductionVL; +defm : VPatWidenReductionVL_Ext_VL; +defm : VPatWidenReductionVL; +defm : VPatWidenReductionVL_Ext_VL; +} // Predicates = [HasVInstructions] + +// 14.3. Vector Single-Width Floating-Point Reduction Instructions +let Predicates = [HasVInstructionsAnyF] in { +defm : VPatReductionVL; +defm : VPatReductionVL; +defm : VPatReductionVL; +defm : VPatReductionVL; + +// 14.4. Vector Widening Floating-Point Reduction Instructions +defm : VPatWidenReductionVL; +defm : VPatWidenReductionVL_Ext_VL; +defm : VPatWidenReductionVL; +defm : VPatWidenReductionVL_Ext_VL; +} // Predicates = [HasVInstructionsAnyF] + +// 15. Vector Mask Instructions + let Predicates = [HasVInstructions] in { foreach mti = AllMasks in { - // 16.1 Vector Mask-Register Logical Instructions + // 15.1 Vector Mask-Register Logical Instructions def : Pat<(mti.Mask (riscv_vmset_vl VLOpFrag)), (!cast("PseudoVMSET_M_" # mti.BX) GPR:$vl, mti.Log2SEW)>; def : Pat<(mti.Mask (riscv_vmclr_vl VLOpFrag)), @@ -1840,7 +1850,7 @@ (!cast("PseudoVMNAND_MM_" # mti.LMul.MX) VR:$rs, VR:$rs, GPR:$vl, mti.Log2SEW)>; - // 16.2 Vector count population in mask vcpop.m + // 15.2 Vector count population in mask vcpop.m def : Pat<(XLenVT (riscv_vcpop_vl (mti.Mask VR:$rs2), (mti.Mask true_mask), VLOpFrag)), (!cast("PseudoVCPOP_M_" # mti.BX) @@ -1850,7 +1860,7 @@ (!cast("PseudoVCPOP_M_" # mti.BX # "_MASK") VR:$rs2, (mti.Mask V0), GPR:$vl, mti.Log2SEW)>; - // 16.3 vfirst find-first-set mask bit + // 15.3 vfirst find-first-set mask bit def : Pat<(XLenVT (riscv_vfirst_vl (mti.Mask VR:$rs2), (mti.Mask true_mask), VLOpFrag)), (!cast("PseudoVFIRST_M_" # mti.BX) @@ -1863,9 +1873,11 @@ } // Predicates = [HasVInstructions] +// 16. Vector Permutation Instructions + let Predicates = [HasVInstructions] in { -// 17.1. Integer Scalar Move Instructions -// 17.4. Vector Register Gather Instruction +// 16.1. Integer Scalar Move Instructions +// 16.4. Vector Register Gather Instruction foreach vti = AllIntegerVectors in { def : Pat<(vti.Vector (riscv_vmv_s_x_vl (vti.Vector vti.RegClass:$merge), vti.ScalarRegClass:$rs1, @@ -1923,7 +1935,7 @@ let Predicates = [HasVInstructionsAnyF] in { -// 17.2. Floating-Point Scalar Move Instructions +// 16.2. Floating-Point Scalar Move Instructions foreach vti = AllFloatVectors in { def : Pat<(vti.Vector (riscv_vfmv_s_f_vl (vti.Vector vti.RegClass:$merge), (vti.Scalar (fpimm0)),