diff --git a/llvm/lib/Target/PowerPC/GISel/PPCRegisterBankInfo.cpp b/llvm/lib/Target/PowerPC/GISel/PPCRegisterBankInfo.cpp
--- a/llvm/lib/Target/PowerPC/GISel/PPCRegisterBankInfo.cpp
+++ b/llvm/lib/Target/PowerPC/GISel/PPCRegisterBankInfo.cpp
@@ -175,6 +175,13 @@
            getValueMapping(PMI_GPR64)});
     break;
   }
+  case TargetOpcode::G_INTRINSIC_W_SIDE_EFFECTS: {
+    // FIXME: We have to check every operand in this MI and compute value
+    // mapping accordingly.
+    SmallVector<const ValueMapping *, 8> OpdsMapping(NumOperands);
+    OperandsMapping = getOperandsMapping(OpdsMapping);
+    break;
+  }
   default:
     return getInvalidInstructionMapping();
   }
diff --git a/llvm/test/CodeGen/PowerPC/GlobalISel/ppc-isel-sync.ll b/llvm/test/CodeGen/PowerPC/GlobalISel/ppc-isel-sync.ll
new file mode 100644
--- /dev/null
+++ b/llvm/test/CodeGen/PowerPC/GlobalISel/ppc-isel-sync.ll
@@ -0,0 +1,21 @@
+; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
+; RUN: llc -verify-machineinstrs -mtriple=powerpc64le -global-isel \
+; RUN:   -ppc-asm-full-reg-names < %s | FileCheck %s
+
+declare void @llvm.ppc.isync()
+declare void @llvm.ppc.sync()
+declare void @llvm.ppc.lwsync()
+
+define void @test_sync() {
+; CHECK-LABEL: test_sync:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    isync
+; CHECK-NEXT:    sync
+; CHECK-NEXT:    lwsync
+; CHECK-NEXT:    blr
+entry:
+  call void @llvm.ppc.isync()
+  call void @llvm.ppc.sync()
+  call void @llvm.ppc.lwsync()
+  ret void
+}