diff --git a/llvm/lib/Target/X86/X86ISelLowering.cpp b/llvm/lib/Target/X86/X86ISelLowering.cpp
--- a/llvm/lib/Target/X86/X86ISelLowering.cpp
+++ b/llvm/lib/Target/X86/X86ISelLowering.cpp
@@ -34113,7 +34113,7 @@
     Results.push_back(V);
     return;
   }
-  case ISD::BITREVERSE:{
+  case ISD::BITREVERSE: {
     assert(N->getValueType(0) == MVT::i64 && "Unexpected VT!");
     assert(Subtarget.hasXOP() && "Expected XOP");
     // We can use VPPERM by copying to a vector register and back. We'll need
@@ -34121,14 +34121,18 @@
     Results.push_back(LowerBITREVERSE(SDValue(N, 0), Subtarget, DAG));
     return;
   }
-  case ISD::EXTRACT_VECTOR_ELT:{
+  case ISD::EXTRACT_VECTOR_ELT: {
     // f16 = extract vxxf16 %vec, i64 %idx
     MVT SplitVT = N->getSimpleValueType(0);
-    assert(SplitVT == MVT::f16 && "Unexpected Value type of EXTRACT_VECTOR_ELT!");
-    SDValue VecOp = N->getOperand(0);
-    MVT ExtVT = MVT::getVectorVT(MVT::i16, VecOp.getValueType().getVectorNumElements());
+    assert(SplitVT == MVT::f16 &&
+           "Unexpected Value type of EXTRACT_VECTOR_ELT!");
+    assert(Subtarget.HasFP16() && "Expected FP16") SDValue VecOp =
+        N->getOperand(0);
+    MVT ExtVT =
+        MVT::getVectorVT(MVT::i16, VecOp.getValueType().getVectorNumElements());
     SDValue Split = DAG.getBitcast(ExtVT, N->getOperand(0));
-    Split = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::i16, Split, N->getOperand(1));
+    Split = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::i16, Split,
+                        N->getOperand(1));
     Split = DAG.getBitcast(MVT::f16, Split);
     Results.push_back(Split);
     return;