Index: clang/include/clang/Basic/riscvXthead_vector.td
===================================================================
--- /dev/null
+++ clang/include/clang/Basic/riscvXthead_vector.td
@@ -0,0 +1,34 @@
+//===-- riscvXthead_vector.td ------------------------------*- tablegen -*-===//
+//
+// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
+// See https://llvm.org/LICENSE.txt for license information.
+// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
+//
+//===----------------------------------------------------------------------===//
+//
+// This file describes the vendor extensions defined by T-Head of Alibaba.
+//
+//===----------------------------------------------------------------------===//
+
+multiclass TH_VdotOutOp1Op2BuiltinSet<string intrinsic_name, string type_range,
+                                      list<list<string>> suffixes_prototypes> {
+    let OverloadedName = NAME in
+    defm "" : RVVBuiltinSet<intrinsic_name, type_range, suffixes_prototypes, [-1, 1, 2]>;
+}
+
+let UnMaskedPolicyScheme = HasPolicyOperand,
+    IsPrototypeDefaultTU = true,
+    HasMaskedOffOperand = false,
+    Log2LMUL = [-1, 0, 1, 2, 3] in {
+defm th_vmaqau  : TH_VdotOutOp1Op2BuiltinSet<"th_vmaqau", "c",
+                                             [["vv", "Uh", "UhUhUvUv"],
+                                              ["vx", "Uh", "UhUhUeUv"]]>;
+defm th_vmaqa   : TH_VdotOutOp1Op2BuiltinSet<"th_vmaqa", "c",
+                                             [["vv", "h", "hhvv"],
+                                              ["vx", "h", "hhev"]]>;
+defm th_vmaqasu : TH_VdotOutOp1Op2BuiltinSet<"th_vmaqasu", "c",
+                                             [["vv", "h", "hhvUv"],
+                                              ["vx", "h", "hheUv"]]>;
+defm th_vmaqaus : TH_VdotOutOp1Op2BuiltinSet<"th_vmaqaus", "c",
+                                             [["vx", "h", "hhUev"]]>;
+}
Index: clang/include/clang/Basic/riscv_vector.td
===================================================================
--- clang/include/clang/Basic/riscv_vector.td
+++ clang/include/clang/Basic/riscv_vector.td
@@ -61,6 +61,9 @@
 //      element type which is four times as wide as the element type of 'v'
 //   o: computes a vector type identical to what 'v' computes except for the
 //      element type which is eight times as wide as the element type of 'v'
+//   h: computes a vector type identical to what 'v' computes except for the
+//      element type which is four times as wide as the element type of 'v',
+//      and keep LMUL same with the original vector type
 //   m: computes a vector type identical to what 'v' computes except for the
 //      element type which is bool
 //   0: void type, ignores "t"
@@ -2335,3 +2338,8 @@
     }
   }
 }
+
+//===----------------------------------------------------------------------===//
+// Vendor extensions
+//===----------------------------------------------------------------------===//
+include "clang/Basic/riscvXthead_vector.td"
Index: clang/include/clang/Support/RISCVVIntrinsicUtils.h
===================================================================
--- clang/include/clang/Support/RISCVVIntrinsicUtils.h
+++ clang/include/clang/Support/RISCVVIntrinsicUtils.h
@@ -35,6 +35,7 @@
   Widening2XVector,
   Widening4XVector,
   Widening8XVector,
+  Widening4XSEW,
   MaskVector,
   Log2EEW3,
   Log2EEW4,
Index: clang/lib/Support/RISCVVIntrinsicUtils.cpp
===================================================================
--- clang/lib/Support/RISCVVIntrinsicUtils.cpp
+++ clang/lib/Support/RISCVVIntrinsicUtils.cpp
@@ -393,6 +393,10 @@
     PT = BaseTypeModifier::Vector;
     VTM = VectorTypeModifier::Widening8XVector;
     break;
+  case 'h':
+    PT = BaseTypeModifier::Vector;
+    VTM = VectorTypeModifier::Widening4XSEW;
+    break;
   case 'm':
     PT = BaseTypeModifier::Vector;
     VTM = VectorTypeModifier::MaskVector;
@@ -630,6 +634,10 @@
     LMUL.MulLog2LMUL(3);
     Scale = LMUL.getScale(ElementBitwidth);
     break;
+  case VectorTypeModifier::Widening4XSEW:
+    ElementBitwidth *= 4;
+    Scale = LMUL.getScale(ElementBitwidth);
+    break;
   case VectorTypeModifier::MaskVector:
     ScalarType = ScalarTypeKind::Boolean;
     Scale = LMUL.getScale(ElementBitwidth);
@@ -1078,7 +1086,7 @@
 
 SmallVector<PrototypeDescriptor> parsePrototypes(StringRef Prototypes) {
   SmallVector<PrototypeDescriptor> PrototypeDescriptors;
-  const StringRef Primaries("evwqom0ztul");
+  const StringRef Primaries("evwqohm0ztul");
   while (!Prototypes.empty()) {
     size_t Idx = 0;
     // Skip over complex prototype because it could contain primitive type
Index: clang/test/CodeGen/RISCV/rvv-intrinsics-overloaded/xtheadvdot-vmaqa.c
===================================================================
--- /dev/null
+++ clang/test/CodeGen/RISCV/rvv-intrinsics-overloaded/xtheadvdot-vmaqa.c
@@ -0,0 +1,574 @@
+// NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py
+// REQUIRES: riscv-registered-target
+// RUN: %clang_cc1 -triple riscv64 -target-feature +xtheadvdot -disable-O0-optnone -emit-llvm %s -o - | opt -S -passes=mem2reg | FileCheck %s
+
+#include <riscv_vector.h>
+
+// CHECK-LABEL: @test_th_vmaqa_vv_i32mf2(
+// CHECK-NEXT:  entry:
+// CHECK-NEXT:    [[TMP0:%.*]] = call <vscale x 1 x i32> @llvm.riscv.th.vmaqa.nxv1i32.nxv4i8.nxv4i8.i64(<vscale x 1 x i32> [[ACC:%.*]], <vscale x 4 x i8> [[OP1:%.*]], <vscale x 4 x i8> [[OP2:%.*]], i64 [[VL:%.*]], i64 0)
+// CHECK-NEXT:    ret <vscale x 1 x i32> [[TMP0]]
+//
+vint32mf2_t test_th_vmaqa_vv_i32mf2(vint32mf2_t acc, vint8mf2_t op1, vint8mf2_t op2,
+                                size_t vl) {
+  return th_vmaqa(acc, op1, op2, vl);
+}
+
+// CHECK-LABEL: @test_th_vmaqa_vx_i32mf2(
+// CHECK-NEXT:  entry:
+// CHECK-NEXT:    [[TMP0:%.*]] = call <vscale x 1 x i32> @llvm.riscv.th.vmaqa.nxv1i32.i8.nxv4i8.i64(<vscale x 1 x i32> [[ACC:%.*]], i8 [[OP1:%.*]], <vscale x 4 x i8> [[OP2:%.*]], i64 [[VL:%.*]], i64 0)
+// CHECK-NEXT:    ret <vscale x 1 x i32> [[TMP0]]
+//
+vint32mf2_t test_th_vmaqa_vx_i32mf2(vint32mf2_t acc, int8_t op1, vint8mf2_t op2,
+                                size_t vl) {
+  return th_vmaqa(acc, op1, op2, vl);
+}
+
+// CHECK-LABEL: @test_th_vmaqa_vv_i32m1(
+// CHECK-NEXT:  entry:
+// CHECK-NEXT:    [[TMP0:%.*]] = call <vscale x 2 x i32> @llvm.riscv.th.vmaqa.nxv2i32.nxv8i8.nxv8i8.i64(<vscale x 2 x i32> [[ACC:%.*]], <vscale x 8 x i8> [[OP1:%.*]], <vscale x 8 x i8> [[OP2:%.*]], i64 [[VL:%.*]], i64 0)
+// CHECK-NEXT:    ret <vscale x 2 x i32> [[TMP0]]
+//
+vint32m1_t test_th_vmaqa_vv_i32m1(vint32m1_t acc, vint8m1_t op1, vint8m1_t op2,
+                                size_t vl) {
+  return th_vmaqa(acc, op1, op2, vl);
+}
+
+// CHECK-LABEL: @test_th_vmaqa_vx_i32m1(
+// CHECK-NEXT:  entry:
+// CHECK-NEXT:    [[TMP0:%.*]] = call <vscale x 2 x i32> @llvm.riscv.th.vmaqa.nxv2i32.i8.nxv8i8.i64(<vscale x 2 x i32> [[ACC:%.*]], i8 [[OP1:%.*]], <vscale x 8 x i8> [[OP2:%.*]], i64 [[VL:%.*]], i64 0)
+// CHECK-NEXT:    ret <vscale x 2 x i32> [[TMP0]]
+//
+vint32m1_t test_th_vmaqa_vx_i32m1(vint32m1_t acc, int8_t op1, vint8m1_t op2,
+                                size_t vl) {
+  return th_vmaqa(acc, op1, op2, vl);
+}
+
+// CHECK-LABEL: @test_th_vmaqa_vv_i32m2(
+// CHECK-NEXT:  entry:
+// CHECK-NEXT:    [[TMP0:%.*]] = call <vscale x 4 x i32> @llvm.riscv.th.vmaqa.nxv4i32.nxv16i8.nxv16i8.i64(<vscale x 4 x i32> [[ACC:%.*]], <vscale x 16 x i8> [[OP1:%.*]], <vscale x 16 x i8> [[OP2:%.*]], i64 [[VL:%.*]], i64 0)
+// CHECK-NEXT:    ret <vscale x 4 x i32> [[TMP0]]
+//
+vint32m2_t test_th_vmaqa_vv_i32m2(vint32m2_t acc, vint8m2_t op1, vint8m2_t op2,
+                                size_t vl) {
+  return th_vmaqa(acc, op1, op2, vl);
+}
+
+// CHECK-LABEL: @test_th_vmaqa_vx_i32m2(
+// CHECK-NEXT:  entry:
+// CHECK-NEXT:    [[TMP0:%.*]] = call <vscale x 4 x i32> @llvm.riscv.th.vmaqa.nxv4i32.i8.nxv16i8.i64(<vscale x 4 x i32> [[ACC:%.*]], i8 [[OP1:%.*]], <vscale x 16 x i8> [[OP2:%.*]], i64 [[VL:%.*]], i64 0)
+// CHECK-NEXT:    ret <vscale x 4 x i32> [[TMP0]]
+//
+vint32m2_t test_th_vmaqa_vx_i32m2(vint32m2_t acc, int8_t op1, vint8m2_t op2,
+                                size_t vl) {
+  return th_vmaqa(acc, op1, op2, vl);
+}
+
+// CHECK-LABEL: @test_th_vmaqa_vv_i32m4(
+// CHECK-NEXT:  entry:
+// CHECK-NEXT:    [[TMP0:%.*]] = call <vscale x 8 x i32> @llvm.riscv.th.vmaqa.nxv8i32.nxv32i8.nxv32i8.i64(<vscale x 8 x i32> [[ACC:%.*]], <vscale x 32 x i8> [[OP1:%.*]], <vscale x 32 x i8> [[OP2:%.*]], i64 [[VL:%.*]], i64 0)
+// CHECK-NEXT:    ret <vscale x 8 x i32> [[TMP0]]
+//
+vint32m4_t test_th_vmaqa_vv_i32m4(vint32m4_t acc, vint8m4_t op1, vint8m4_t op2,
+                                size_t vl) {
+  return th_vmaqa(acc, op1, op2, vl);
+}
+
+// CHECK-LABEL: @test_th_vmaqa_vx_i32m4(
+// CHECK-NEXT:  entry:
+// CHECK-NEXT:    [[TMP0:%.*]] = call <vscale x 8 x i32> @llvm.riscv.th.vmaqa.nxv8i32.i8.nxv32i8.i64(<vscale x 8 x i32> [[ACC:%.*]], i8 [[OP1:%.*]], <vscale x 32 x i8> [[OP2:%.*]], i64 [[VL:%.*]], i64 0)
+// CHECK-NEXT:    ret <vscale x 8 x i32> [[TMP0]]
+//
+vint32m4_t test_th_vmaqa_vx_i32m4(vint32m4_t acc, int8_t op1, vint8m4_t op2,
+                                size_t vl) {
+  return th_vmaqa(acc, op1, op2, vl);
+}
+
+
+// CHECK-LABEL: @test_th_vmaqau_vv_u32mf2(
+// CHECK-NEXT:  entry:
+// CHECK-NEXT:    [[TMP0:%.*]] = call <vscale x 1 x i32> @llvm.riscv.th.vmaqau.nxv1i32.nxv4i8.nxv4i8.i64(<vscale x 1 x i32> [[ACC:%.*]], <vscale x 4 x i8> [[OP1:%.*]], <vscale x 4 x i8> [[OP2:%.*]], i64 [[VL:%.*]], i64 0)
+// CHECK-NEXT:    ret <vscale x 1 x i32> [[TMP0]]
+//
+vuint32mf2_t test_th_vmaqau_vv_u32mf2(vuint32mf2_t acc, vuint8mf2_t op1,
+                                  vuint8mf2_t op2, size_t vl) {
+  return th_vmaqau(acc, op1, op2, vl);
+}
+
+// CHECK-LABEL: @test_th_vmaqau_vx_u32mf2(
+// CHECK-NEXT:  entry:
+// CHECK-NEXT:    [[TMP0:%.*]] = call <vscale x 1 x i32> @llvm.riscv.th.vmaqau.nxv1i32.i8.nxv4i8.i64(<vscale x 1 x i32> [[ACC:%.*]], i8 [[OP1:%.*]], <vscale x 4 x i8> [[OP2:%.*]], i64 [[VL:%.*]], i64 0)
+// CHECK-NEXT:    ret <vscale x 1 x i32> [[TMP0]]
+//
+vuint32mf2_t test_th_vmaqau_vx_u32mf2(vuint32mf2_t acc, uint8_t op1, vuint8mf2_t op2,
+                                  size_t vl) {
+  return th_vmaqau(acc, op1, op2, vl);
+}
+
+// CHECK-LABEL: @test_th_vmaqau_vv_u32m1(
+// CHECK-NEXT:  entry:
+// CHECK-NEXT:    [[TMP0:%.*]] = call <vscale x 2 x i32> @llvm.riscv.th.vmaqau.nxv2i32.nxv8i8.nxv8i8.i64(<vscale x 2 x i32> [[ACC:%.*]], <vscale x 8 x i8> [[OP1:%.*]], <vscale x 8 x i8> [[OP2:%.*]], i64 [[VL:%.*]], i64 0)
+// CHECK-NEXT:    ret <vscale x 2 x i32> [[TMP0]]
+//
+vuint32m1_t test_th_vmaqau_vv_u32m1(vuint32m1_t acc, vuint8m1_t op1,
+                                  vuint8m1_t op2, size_t vl) {
+  return th_vmaqau(acc, op1, op2, vl);
+}
+
+// CHECK-LABEL: @test_th_vmaqau_vx_u32m1(
+// CHECK-NEXT:  entry:
+// CHECK-NEXT:    [[TMP0:%.*]] = call <vscale x 2 x i32> @llvm.riscv.th.vmaqau.nxv2i32.i8.nxv8i8.i64(<vscale x 2 x i32> [[ACC:%.*]], i8 [[OP1:%.*]], <vscale x 8 x i8> [[OP2:%.*]], i64 [[VL:%.*]], i64 0)
+// CHECK-NEXT:    ret <vscale x 2 x i32> [[TMP0]]
+//
+vuint32m1_t test_th_vmaqau_vx_u32m1(vuint32m1_t acc, uint8_t op1, vuint8m1_t op2,
+                                  size_t vl) {
+  return th_vmaqau(acc, op1, op2, vl);
+}
+
+// CHECK-LABEL: @test_th_vmaqau_vv_u32m2(
+// CHECK-NEXT:  entry:
+// CHECK-NEXT:    [[TMP0:%.*]] = call <vscale x 4 x i32> @llvm.riscv.th.vmaqau.nxv4i32.nxv16i8.nxv16i8.i64(<vscale x 4 x i32> [[ACC:%.*]], <vscale x 16 x i8> [[OP1:%.*]], <vscale x 16 x i8> [[OP2:%.*]], i64 [[VL:%.*]], i64 0)
+// CHECK-NEXT:    ret <vscale x 4 x i32> [[TMP0]]
+//
+vuint32m2_t test_th_vmaqau_vv_u32m2(vuint32m2_t acc, vuint8m2_t op1,
+                                  vuint8m2_t op2, size_t vl) {
+  return th_vmaqau(acc, op1, op2, vl);
+}
+
+// CHECK-LABEL: @test_th_vmaqau_vx_u32m2(
+// CHECK-NEXT:  entry:
+// CHECK-NEXT:    [[TMP0:%.*]] = call <vscale x 4 x i32> @llvm.riscv.th.vmaqau.nxv4i32.i8.nxv16i8.i64(<vscale x 4 x i32> [[ACC:%.*]], i8 [[OP1:%.*]], <vscale x 16 x i8> [[OP2:%.*]], i64 [[VL:%.*]], i64 0)
+// CHECK-NEXT:    ret <vscale x 4 x i32> [[TMP0]]
+//
+vuint32m2_t test_th_vmaqau_vx_u32m2(vuint32m2_t acc, uint8_t op1, vuint8m2_t op2,
+                                  size_t vl) {
+  return th_vmaqau(acc, op1, op2, vl);
+}
+
+// CHECK-LABEL: @test_th_vmaqau_vv_u32m4(
+// CHECK-NEXT:  entry:
+// CHECK-NEXT:    [[TMP0:%.*]] = call <vscale x 8 x i32> @llvm.riscv.th.vmaqau.nxv8i32.nxv32i8.nxv32i8.i64(<vscale x 8 x i32> [[ACC:%.*]], <vscale x 32 x i8> [[OP1:%.*]], <vscale x 32 x i8> [[OP2:%.*]], i64 [[VL:%.*]], i64 0)
+// CHECK-NEXT:    ret <vscale x 8 x i32> [[TMP0]]
+//
+vuint32m4_t test_th_vmaqau_vv_u32m4(vuint32m4_t acc, vuint8m4_t op1,
+                                  vuint8m4_t op2, size_t vl) {
+  return th_vmaqau(acc, op1, op2, vl);
+}
+
+// CHECK-LABEL: @test_th_vmaqau_vx_u32m4(
+// CHECK-NEXT:  entry:
+// CHECK-NEXT:    [[TMP0:%.*]] = call <vscale x 8 x i32> @llvm.riscv.th.vmaqau.nxv8i32.i8.nxv32i8.i64(<vscale x 8 x i32> [[ACC:%.*]], i8 [[OP1:%.*]], <vscale x 32 x i8> [[OP2:%.*]], i64 [[VL:%.*]], i64 0)
+// CHECK-NEXT:    ret <vscale x 8 x i32> [[TMP0]]
+//
+vuint32m4_t test_th_vmaqau_vx_u32m4(vuint32m4_t acc, uint8_t op1, vuint8m4_t op2,
+                                  size_t vl) {
+  return th_vmaqau(acc, op1, op2, vl);
+}
+
+
+// CHECK-LABEL: @test_th_vmaqasu_vv_i32mf2(
+// CHECK-NEXT:  entry:
+// CHECK-NEXT:    [[TMP0:%.*]] = call <vscale x 1 x i32> @llvm.riscv.th.vmaqasu.nxv1i32.nxv4i8.nxv4i8.i64(<vscale x 1 x i32> [[ACC:%.*]], <vscale x 4 x i8> [[OP1:%.*]], <vscale x 4 x i8> [[OP2:%.*]], i64 [[VL:%.*]], i64 0)
+// CHECK-NEXT:    ret <vscale x 1 x i32> [[TMP0]]
+//
+vint32mf2_t test_th_vmaqasu_vv_i32mf2(vint32mf2_t acc, vint8mf2_t op1,
+                                  vuint8mf2_t op2, size_t vl) {
+  return th_vmaqasu(acc, op1, op2, vl);
+}
+
+// CHECK-LABEL: @test_th_vmaqasu_vx_i32mf2(
+// CHECK-NEXT:  entry:
+// CHECK-NEXT:    [[TMP0:%.*]] = call <vscale x 1 x i32> @llvm.riscv.th.vmaqasu.nxv1i32.i8.nxv4i8.i64(<vscale x 1 x i32> [[ACC:%.*]], i8 [[OP1:%.*]], <vscale x 4 x i8> [[OP2:%.*]], i64 [[VL:%.*]], i64 0)
+// CHECK-NEXT:    ret <vscale x 1 x i32> [[TMP0]]
+//
+vint32mf2_t test_th_vmaqasu_vx_i32mf2(vint32mf2_t acc, int8_t op1, vuint8mf2_t op2,
+                                  size_t vl) {
+  return th_vmaqasu(acc, op1, op2, vl);
+}
+
+// CHECK-LABEL: @test_th_vmaqasu_vv_i32m1(
+// CHECK-NEXT:  entry:
+// CHECK-NEXT:    [[TMP0:%.*]] = call <vscale x 2 x i32> @llvm.riscv.th.vmaqasu.nxv2i32.nxv8i8.nxv8i8.i64(<vscale x 2 x i32> [[ACC:%.*]], <vscale x 8 x i8> [[OP1:%.*]], <vscale x 8 x i8> [[OP2:%.*]], i64 [[VL:%.*]], i64 0)
+// CHECK-NEXT:    ret <vscale x 2 x i32> [[TMP0]]
+//
+vint32m1_t test_th_vmaqasu_vv_i32m1(vint32m1_t acc, vint8m1_t op1, vuint8m1_t op2,
+                                  size_t vl) {
+  return th_vmaqasu(acc, op1, op2, vl);
+}
+
+// CHECK-LABEL: @test_th_vmaqasu_vx_i32m1(
+// CHECK-NEXT:  entry:
+// CHECK-NEXT:    [[TMP0:%.*]] = call <vscale x 2 x i32> @llvm.riscv.th.vmaqasu.nxv2i32.i8.nxv8i8.i64(<vscale x 2 x i32> [[ACC:%.*]], i8 [[OP1:%.*]], <vscale x 8 x i8> [[OP2:%.*]], i64 [[VL:%.*]], i64 0)
+// CHECK-NEXT:    ret <vscale x 2 x i32> [[TMP0]]
+//
+vint32m1_t test_th_vmaqasu_vx_i32m1(vint32m1_t acc, int8_t op1, vuint8m1_t op2,
+                                  size_t vl) {
+  return th_vmaqasu(acc, op1, op2, vl);
+}
+
+// CHECK-LABEL: @test_th_vmaqasu_vv_i32m2(
+// CHECK-NEXT:  entry:
+// CHECK-NEXT:    [[TMP0:%.*]] = call <vscale x 4 x i32> @llvm.riscv.th.vmaqasu.nxv4i32.nxv16i8.nxv16i8.i64(<vscale x 4 x i32> [[ACC:%.*]], <vscale x 16 x i8> [[OP1:%.*]], <vscale x 16 x i8> [[OP2:%.*]], i64 [[VL:%.*]], i64 0)
+// CHECK-NEXT:    ret <vscale x 4 x i32> [[TMP0]]
+//
+vint32m2_t test_th_vmaqasu_vv_i32m2(vint32m2_t acc, vint8m2_t op1, vuint8m2_t op2,
+                                  size_t vl) {
+  return th_vmaqasu(acc, op1, op2, vl);
+}
+
+// CHECK-LABEL: @test_th_vmaqasu_vx_i32m2(
+// CHECK-NEXT:  entry:
+// CHECK-NEXT:    [[TMP0:%.*]] = call <vscale x 4 x i32> @llvm.riscv.th.vmaqasu.nxv4i32.i8.nxv16i8.i64(<vscale x 4 x i32> [[ACC:%.*]], i8 [[OP1:%.*]], <vscale x 16 x i8> [[OP2:%.*]], i64 [[VL:%.*]], i64 0)
+// CHECK-NEXT:    ret <vscale x 4 x i32> [[TMP0]]
+//
+vint32m2_t test_th_vmaqasu_vx_i32m2(vint32m2_t acc, int8_t op1, vuint8m2_t op2,
+                                  size_t vl) {
+  return th_vmaqasu(acc, op1, op2, vl);
+}
+
+// CHECK-LABEL: @test_th_vmaqasu_vv_i32m4(
+// CHECK-NEXT:  entry:
+// CHECK-NEXT:    [[TMP0:%.*]] = call <vscale x 8 x i32> @llvm.riscv.th.vmaqasu.nxv8i32.nxv32i8.nxv32i8.i64(<vscale x 8 x i32> [[ACC:%.*]], <vscale x 32 x i8> [[OP1:%.*]], <vscale x 32 x i8> [[OP2:%.*]], i64 [[VL:%.*]], i64 0)
+// CHECK-NEXT:    ret <vscale x 8 x i32> [[TMP0]]
+//
+vint32m4_t test_th_vmaqasu_vv_i32m4(vint32m4_t acc, vint8m4_t op1, vuint8m4_t op2,
+                                  size_t vl) {
+  return th_vmaqasu(acc, op1, op2, vl);
+}
+
+// CHECK-LABEL: @test_th_vmaqasu_vx_i32m4(
+// CHECK-NEXT:  entry:
+// CHECK-NEXT:    [[TMP0:%.*]] = call <vscale x 8 x i32> @llvm.riscv.th.vmaqasu.nxv8i32.i8.nxv32i8.i64(<vscale x 8 x i32> [[ACC:%.*]], i8 [[OP1:%.*]], <vscale x 32 x i8> [[OP2:%.*]], i64 [[VL:%.*]], i64 0)
+// CHECK-NEXT:    ret <vscale x 8 x i32> [[TMP0]]
+//
+vint32m4_t test_th_vmaqasu_vx_i32m4(vint32m4_t acc, int8_t op1, vuint8m4_t op2,
+                                  size_t vl) {
+  return th_vmaqasu(acc, op1, op2, vl);
+}
+
+
+// CHECK-LABEL: @test_th_vmaqaus_vx_i32mf2(
+// CHECK-NEXT:  entry:
+// CHECK-NEXT:    [[TMP0:%.*]] = call <vscale x 1 x i32> @llvm.riscv.th.vmaqaus.nxv1i32.i8.nxv4i8.i64(<vscale x 1 x i32> [[ACC:%.*]], i8 [[OP1:%.*]], <vscale x 4 x i8> [[OP2:%.*]], i64 [[VL:%.*]], i64 0)
+// CHECK-NEXT:    ret <vscale x 1 x i32> [[TMP0]]
+//
+vint32mf2_t test_th_vmaqaus_vx_i32mf2(vint32mf2_t acc, uint8_t op1, vint8mf2_t op2,
+                                  size_t vl) {
+  return th_vmaqaus(acc, op1, op2, vl);
+}
+
+// CHECK-LABEL: @test_th_vmaqaus_vx_i32m1(
+// CHECK-NEXT:  entry:
+// CHECK-NEXT:    [[TMP0:%.*]] = call <vscale x 2 x i32> @llvm.riscv.th.vmaqaus.nxv2i32.i8.nxv8i8.i64(<vscale x 2 x i32> [[ACC:%.*]], i8 [[OP1:%.*]], <vscale x 8 x i8> [[OP2:%.*]], i64 [[VL:%.*]], i64 0)
+// CHECK-NEXT:    ret <vscale x 2 x i32> [[TMP0]]
+//
+vint32m1_t test_th_vmaqaus_vx_i32m1(vint32m1_t acc, uint8_t op1, vint8m1_t op2,
+                                  size_t vl) {
+  return th_vmaqaus(acc, op1, op2, vl);
+}
+
+// CHECK-LABEL: @test_th_vmaqaus_vx_i32m2(
+// CHECK-NEXT:  entry:
+// CHECK-NEXT:    [[TMP0:%.*]] = call <vscale x 4 x i32> @llvm.riscv.th.vmaqaus.nxv4i32.i8.nxv16i8.i64(<vscale x 4 x i32> [[ACC:%.*]], i8 [[OP1:%.*]], <vscale x 16 x i8> [[OP2:%.*]], i64 [[VL:%.*]], i64 0)
+// CHECK-NEXT:    ret <vscale x 4 x i32> [[TMP0]]
+//
+vint32m2_t test_th_vmaqaus_vx_i32m2(vint32m2_t acc, uint8_t op1, vint8m2_t op2,
+                                  size_t vl) {
+  return th_vmaqaus(acc, op1, op2, vl);
+}
+
+// CHECK-LABEL: @test_th_vmaqaus_vx_i32m4(
+// CHECK-NEXT:  entry:
+// CHECK-NEXT:    [[TMP0:%.*]] = call <vscale x 8 x i32> @llvm.riscv.th.vmaqaus.nxv8i32.i8.nxv32i8.i64(<vscale x 8 x i32> [[ACC:%.*]], i8 [[OP1:%.*]], <vscale x 32 x i8> [[OP2:%.*]], i64 [[VL:%.*]], i64 0)
+// CHECK-NEXT:    ret <vscale x 8 x i32> [[TMP0]]
+//
+vint32m4_t test_th_vmaqaus_vx_i32m4(vint32m4_t acc, uint8_t op1, vint8m4_t op2,
+                                  size_t vl) {
+  return th_vmaqaus(acc, op1, op2, vl);
+}
+
+
+// CHECK-LABEL: @test_th_vmaqa_vv_i32mf2_m(
+// CHECK-NEXT:  entry:
+// CHECK-NEXT:    [[TMP0:%.*]] = call <vscale x 1 x i32> @llvm.riscv.th.vmaqa.mask.nxv1i32.nxv4i8.nxv4i8.i64(<vscale x 1 x i32> [[ACC:%.*]], <vscale x 4 x i8> [[OP1:%.*]], <vscale x 4 x i8> [[OP2:%.*]], <vscale x 4 x i1> [[MASK:%.*]], i64 [[VL:%.*]], i64 0)
+// CHECK-NEXT:    ret <vscale x 1 x i32> [[TMP0]]
+//
+vint32mf2_t test_th_vmaqa_vv_i32mf2_m(vbool16_t mask, vint32mf2_t acc,
+                                  vint8mf2_t op1, vint8mf2_t op2, size_t vl) {
+  return th_vmaqa(mask, acc, op1, op2, vl);
+}
+
+// CHECK-LABEL: @test_th_vmaqa_vx_i32mf2_m(
+// CHECK-NEXT:  entry:
+// CHECK-NEXT:    [[TMP0:%.*]] = call <vscale x 1 x i32> @llvm.riscv.th.vmaqa.mask.nxv1i32.i8.nxv4i8.i64(<vscale x 1 x i32> [[ACC:%.*]], i8 [[OP1:%.*]], <vscale x 4 x i8> [[OP2:%.*]], <vscale x 4 x i1> [[MASK:%.*]], i64 [[VL:%.*]], i64 0)
+// CHECK-NEXT:    ret <vscale x 1 x i32> [[TMP0]]
+//
+vint32mf2_t test_th_vmaqa_vx_i32mf2_m(vbool16_t mask, vint32mf2_t acc, int8_t op1,
+                                  vint8mf2_t op2, size_t vl) {
+  return th_vmaqa(mask, acc, op1, op2, vl);
+}
+
+// CHECK-LABEL: @test_th_vmaqa_vv_i32m1_m(
+// CHECK-NEXT:  entry:
+// CHECK-NEXT:    [[TMP0:%.*]] = call <vscale x 2 x i32> @llvm.riscv.th.vmaqa.mask.nxv2i32.nxv8i8.nxv8i8.i64(<vscale x 2 x i32> [[ACC:%.*]], <vscale x 8 x i8> [[OP1:%.*]], <vscale x 8 x i8> [[OP2:%.*]], <vscale x 8 x i1> [[MASK:%.*]], i64 [[VL:%.*]], i64 0)
+// CHECK-NEXT:    ret <vscale x 2 x i32> [[TMP0]]
+//
+vint32m1_t test_th_vmaqa_vv_i32m1_m(vbool8_t mask, vint32m1_t acc, vint8m1_t op1,
+                                  vint8m1_t op2, size_t vl) {
+  return th_vmaqa(mask, acc, op1, op2, vl);
+}
+
+// CHECK-LABEL: @test_th_vmaqa_vx_i32m1_m(
+// CHECK-NEXT:  entry:
+// CHECK-NEXT:    [[TMP0:%.*]] = call <vscale x 2 x i32> @llvm.riscv.th.vmaqa.mask.nxv2i32.i8.nxv8i8.i64(<vscale x 2 x i32> [[ACC:%.*]], i8 [[OP1:%.*]], <vscale x 8 x i8> [[OP2:%.*]], <vscale x 8 x i1> [[MASK:%.*]], i64 [[VL:%.*]], i64 0)
+// CHECK-NEXT:    ret <vscale x 2 x i32> [[TMP0]]
+//
+vint32m1_t test_th_vmaqa_vx_i32m1_m(vbool8_t mask, vint32m1_t acc, int8_t op1,
+                                  vint8m1_t op2, size_t vl) {
+  return th_vmaqa(mask, acc, op1, op2, vl);
+}
+
+// CHECK-LABEL: @test_th_vmaqa_vv_i32m2_m(
+// CHECK-NEXT:  entry:
+// CHECK-NEXT:    [[TMP0:%.*]] = call <vscale x 4 x i32> @llvm.riscv.th.vmaqa.mask.nxv4i32.nxv16i8.nxv16i8.i64(<vscale x 4 x i32> [[ACC:%.*]], <vscale x 16 x i8> [[OP1:%.*]], <vscale x 16 x i8> [[OP2:%.*]], <vscale x 16 x i1> [[MASK:%.*]], i64 [[VL:%.*]], i64 0)
+// CHECK-NEXT:    ret <vscale x 4 x i32> [[TMP0]]
+//
+vint32m2_t test_th_vmaqa_vv_i32m2_m(vbool4_t mask, vint32m2_t acc, vint8m2_t op1,
+                                  vint8m2_t op2, size_t vl) {
+  return th_vmaqa(mask, acc, op1, op2, vl);
+}
+
+// CHECK-LABEL: @test_th_vmaqa_vx_i32m2_m(
+// CHECK-NEXT:  entry:
+// CHECK-NEXT:    [[TMP0:%.*]] = call <vscale x 4 x i32> @llvm.riscv.th.vmaqa.mask.nxv4i32.i8.nxv16i8.i64(<vscale x 4 x i32> [[ACC:%.*]], i8 [[OP1:%.*]], <vscale x 16 x i8> [[OP2:%.*]], <vscale x 16 x i1> [[MASK:%.*]], i64 [[VL:%.*]], i64 0)
+// CHECK-NEXT:    ret <vscale x 4 x i32> [[TMP0]]
+//
+vint32m2_t test_th_vmaqa_vx_i32m2_m(vbool4_t mask, vint32m2_t acc, int8_t op1,
+                                  vint8m2_t op2, size_t vl) {
+  return th_vmaqa(mask, acc, op1, op2, vl);
+}
+
+// CHECK-LABEL: @test_th_vmaqa_vv_i32m4_m(
+// CHECK-NEXT:  entry:
+// CHECK-NEXT:    [[TMP0:%.*]] = call <vscale x 8 x i32> @llvm.riscv.th.vmaqa.mask.nxv8i32.nxv32i8.nxv32i8.i64(<vscale x 8 x i32> [[ACC:%.*]], <vscale x 32 x i8> [[OP1:%.*]], <vscale x 32 x i8> [[OP2:%.*]], <vscale x 32 x i1> [[MASK:%.*]], i64 [[VL:%.*]], i64 0)
+// CHECK-NEXT:    ret <vscale x 8 x i32> [[TMP0]]
+//
+vint32m4_t test_th_vmaqa_vv_i32m4_m(vbool2_t mask, vint32m4_t acc, vint8m4_t op1,
+                                  vint8m4_t op2, size_t vl) {
+  return th_vmaqa(mask, acc, op1, op2, vl);
+}
+
+// CHECK-LABEL: @test_th_vmaqa_vx_i32m4_m(
+// CHECK-NEXT:  entry:
+// CHECK-NEXT:    [[TMP0:%.*]] = call <vscale x 8 x i32> @llvm.riscv.th.vmaqa.mask.nxv8i32.i8.nxv32i8.i64(<vscale x 8 x i32> [[ACC:%.*]], i8 [[OP1:%.*]], <vscale x 32 x i8> [[OP2:%.*]], <vscale x 32 x i1> [[MASK:%.*]], i64 [[VL:%.*]], i64 0)
+// CHECK-NEXT:    ret <vscale x 8 x i32> [[TMP0]]
+//
+vint32m4_t test_th_vmaqa_vx_i32m4_m(vbool2_t mask, vint32m4_t acc, int8_t op1,
+                                  vint8m4_t op2, size_t vl) {
+  return th_vmaqa(mask, acc, op1, op2, vl);
+}
+
+
+// CHECK-LABEL: @test_th_vmaqau_vv_u32mf2_m(
+// CHECK-NEXT:  entry:
+// CHECK-NEXT:    [[TMP0:%.*]] = call <vscale x 1 x i32> @llvm.riscv.th.vmaqau.mask.nxv1i32.nxv4i8.nxv4i8.i64(<vscale x 1 x i32> [[ACC:%.*]], <vscale x 4 x i8> [[OP1:%.*]], <vscale x 4 x i8> [[OP2:%.*]], <vscale x 4 x i1> [[MASK:%.*]], i64 [[VL:%.*]], i64 0)
+// CHECK-NEXT:    ret <vscale x 1 x i32> [[TMP0]]
+//
+vuint32mf2_t test_th_vmaqau_vv_u32mf2_m(vbool16_t mask, vuint32mf2_t acc,
+                                    vuint8mf2_t op1, vuint8mf2_t op2,
+                                    size_t vl) {
+  return th_vmaqau(mask, acc, op1, op2, vl);
+}
+
+// CHECK-LABEL: @test_th_vmaqau_vx_u32mf2_m(
+// CHECK-NEXT:  entry:
+// CHECK-NEXT:    [[TMP0:%.*]] = call <vscale x 1 x i32> @llvm.riscv.th.vmaqau.mask.nxv1i32.i8.nxv4i8.i64(<vscale x 1 x i32> [[ACC:%.*]], i8 [[OP1:%.*]], <vscale x 4 x i8> [[OP2:%.*]], <vscale x 4 x i1> [[MASK:%.*]], i64 [[VL:%.*]], i64 0)
+// CHECK-NEXT:    ret <vscale x 1 x i32> [[TMP0]]
+//
+vuint32mf2_t test_th_vmaqau_vx_u32mf2_m(vbool16_t mask, vuint32mf2_t acc,
+                                    uint8_t op1, vuint8mf2_t op2, size_t vl) {
+  return th_vmaqau(mask, acc, op1, op2, vl);
+}
+
+// CHECK-LABEL: @test_th_vmaqau_vv_u32m1_m(
+// CHECK-NEXT:  entry:
+// CHECK-NEXT:    [[TMP0:%.*]] = call <vscale x 2 x i32> @llvm.riscv.th.vmaqau.mask.nxv2i32.nxv8i8.nxv8i8.i64(<vscale x 2 x i32> [[ACC:%.*]], <vscale x 8 x i8> [[OP1:%.*]], <vscale x 8 x i8> [[OP2:%.*]], <vscale x 8 x i1> [[MASK:%.*]], i64 [[VL:%.*]], i64 0)
+// CHECK-NEXT:    ret <vscale x 2 x i32> [[TMP0]]
+//
+vuint32m1_t test_th_vmaqau_vv_u32m1_m(vbool8_t mask, vuint32m1_t acc,
+                                    vuint8m1_t op1, vuint8m1_t op2, size_t vl) {
+  return th_vmaqau(mask, acc, op1, op2, vl);
+}
+
+// CHECK-LABEL: @test_th_vmaqau_vx_u32m1_m(
+// CHECK-NEXT:  entry:
+// CHECK-NEXT:    [[TMP0:%.*]] = call <vscale x 2 x i32> @llvm.riscv.th.vmaqau.mask.nxv2i32.i8.nxv8i8.i64(<vscale x 2 x i32> [[ACC:%.*]], i8 [[OP1:%.*]], <vscale x 8 x i8> [[OP2:%.*]], <vscale x 8 x i1> [[MASK:%.*]], i64 [[VL:%.*]], i64 0)
+// CHECK-NEXT:    ret <vscale x 2 x i32> [[TMP0]]
+//
+vuint32m1_t test_th_vmaqau_vx_u32m1_m(vbool8_t mask, vuint32m1_t acc, uint8_t op1,
+                                    vuint8m1_t op2, size_t vl) {
+  return th_vmaqau(mask, acc, op1, op2, vl);
+}
+
+// CHECK-LABEL: @test_th_vmaqau_vv_u32m2_m(
+// CHECK-NEXT:  entry:
+// CHECK-NEXT:    [[TMP0:%.*]] = call <vscale x 4 x i32> @llvm.riscv.th.vmaqau.mask.nxv4i32.nxv16i8.nxv16i8.i64(<vscale x 4 x i32> [[ACC:%.*]], <vscale x 16 x i8> [[OP1:%.*]], <vscale x 16 x i8> [[OP2:%.*]], <vscale x 16 x i1> [[MASK:%.*]], i64 [[VL:%.*]], i64 0)
+// CHECK-NEXT:    ret <vscale x 4 x i32> [[TMP0]]
+//
+vuint32m2_t test_th_vmaqau_vv_u32m2_m(vbool4_t mask, vuint32m2_t acc,
+                                    vuint8m2_t op1, vuint8m2_t op2, size_t vl) {
+  return th_vmaqau(mask, acc, op1, op2, vl);
+}
+
+// CHECK-LABEL: @test_th_vmaqau_vx_u32m2_m(
+// CHECK-NEXT:  entry:
+// CHECK-NEXT:    [[TMP0:%.*]] = call <vscale x 4 x i32> @llvm.riscv.th.vmaqau.mask.nxv4i32.i8.nxv16i8.i64(<vscale x 4 x i32> [[ACC:%.*]], i8 [[OP1:%.*]], <vscale x 16 x i8> [[OP2:%.*]], <vscale x 16 x i1> [[MASK:%.*]], i64 [[VL:%.*]], i64 0)
+// CHECK-NEXT:    ret <vscale x 4 x i32> [[TMP0]]
+//
+vuint32m2_t test_th_vmaqau_vx_u32m2_m(vbool4_t mask, vuint32m2_t acc, uint8_t op1,
+                                    vuint8m2_t op2, size_t vl) {
+  return th_vmaqau(mask, acc, op1, op2, vl);
+}
+
+// CHECK-LABEL: @test_th_vmaqau_vv_u32m4_m(
+// CHECK-NEXT:  entry:
+// CHECK-NEXT:    [[TMP0:%.*]] = call <vscale x 8 x i32> @llvm.riscv.th.vmaqau.mask.nxv8i32.nxv32i8.nxv32i8.i64(<vscale x 8 x i32> [[ACC:%.*]], <vscale x 32 x i8> [[OP1:%.*]], <vscale x 32 x i8> [[OP2:%.*]], <vscale x 32 x i1> [[MASK:%.*]], i64 [[VL:%.*]], i64 0)
+// CHECK-NEXT:    ret <vscale x 8 x i32> [[TMP0]]
+//
+vuint32m4_t test_th_vmaqau_vv_u32m4_m(vbool2_t mask, vuint32m4_t acc,
+                                    vuint8m4_t op1, vuint8m4_t op2, size_t vl) {
+  return th_vmaqau(mask, acc, op1, op2, vl);
+}
+
+// CHECK-LABEL: @test_th_vmaqau_vx_u32m4_m(
+// CHECK-NEXT:  entry:
+// CHECK-NEXT:    [[TMP0:%.*]] = call <vscale x 8 x i32> @llvm.riscv.th.vmaqau.mask.nxv8i32.i8.nxv32i8.i64(<vscale x 8 x i32> [[ACC:%.*]], i8 [[OP1:%.*]], <vscale x 32 x i8> [[OP2:%.*]], <vscale x 32 x i1> [[MASK:%.*]], i64 [[VL:%.*]], i64 0)
+// CHECK-NEXT:    ret <vscale x 8 x i32> [[TMP0]]
+//
+vuint32m4_t test_th_vmaqau_vx_u32m4_m(vbool2_t mask, vuint32m4_t acc, uint8_t op1,
+                                    vuint8m4_t op2, size_t vl) {
+  return th_vmaqau(mask, acc, op1, op2, vl);
+}
+
+
+// CHECK-LABEL: @test_th_vmaqasu_vv_i32mf2_m(
+// CHECK-NEXT:  entry:
+// CHECK-NEXT:    [[TMP0:%.*]] = call <vscale x 1 x i32> @llvm.riscv.th.vmaqasu.mask.nxv1i32.nxv4i8.nxv4i8.i64(<vscale x 1 x i32> [[ACC:%.*]], <vscale x 4 x i8> [[OP1:%.*]], <vscale x 4 x i8> [[OP2:%.*]], <vscale x 4 x i1> [[MASK:%.*]], i64 [[VL:%.*]], i64 0)
+// CHECK-NEXT:    ret <vscale x 1 x i32> [[TMP0]]
+//
+vint32mf2_t test_th_vmaqasu_vv_i32mf2_m(vbool16_t mask, vint32mf2_t acc,
+                                    vint8mf2_t op1, vuint8mf2_t op2,
+                                    size_t vl) {
+  return th_vmaqasu(mask, acc, op1, op2, vl);
+}
+
+// CHECK-LABEL: @test_th_vmaqasu_vx_i32mf2_m(
+// CHECK-NEXT:  entry:
+// CHECK-NEXT:    [[TMP0:%.*]] = call <vscale x 1 x i32> @llvm.riscv.th.vmaqasu.mask.nxv1i32.i8.nxv4i8.i64(<vscale x 1 x i32> [[ACC:%.*]], i8 [[OP1:%.*]], <vscale x 4 x i8> [[OP2:%.*]], <vscale x 4 x i1> [[MASK:%.*]], i64 [[VL:%.*]], i64 0)
+// CHECK-NEXT:    ret <vscale x 1 x i32> [[TMP0]]
+//
+vint32mf2_t test_th_vmaqasu_vx_i32mf2_m(vbool16_t mask, vint32mf2_t acc, int8_t op1,
+                                    vuint8mf2_t op2, size_t vl) {
+  return th_vmaqasu(mask, acc, op1, op2, vl);
+}
+
+// CHECK-LABEL: @test_th_vmaqasu_vv_i32m1_m(
+// CHECK-NEXT:  entry:
+// CHECK-NEXT:    [[TMP0:%.*]] = call <vscale x 2 x i32> @llvm.riscv.th.vmaqasu.mask.nxv2i32.nxv8i8.nxv8i8.i64(<vscale x 2 x i32> [[ACC:%.*]], <vscale x 8 x i8> [[OP1:%.*]], <vscale x 8 x i8> [[OP2:%.*]], <vscale x 8 x i1> [[MASK:%.*]], i64 [[VL:%.*]], i64 0)
+// CHECK-NEXT:    ret <vscale x 2 x i32> [[TMP0]]
+//
+vint32m1_t test_th_vmaqasu_vv_i32m1_m(vbool8_t mask, vint32m1_t acc,
+                                    vint8m1_t op1, vuint8m1_t op2, size_t vl) {
+  return th_vmaqasu(mask, acc, op1, op2, vl);
+}
+
+// CHECK-LABEL: @test_th_vmaqasu_vx_i32m1_m(
+// CHECK-NEXT:  entry:
+// CHECK-NEXT:    [[TMP0:%.*]] = call <vscale x 2 x i32> @llvm.riscv.th.vmaqasu.mask.nxv2i32.i8.nxv8i8.i64(<vscale x 2 x i32> [[ACC:%.*]], i8 [[OP1:%.*]], <vscale x 8 x i8> [[OP2:%.*]], <vscale x 8 x i1> [[MASK:%.*]], i64 [[VL:%.*]], i64 0)
+// CHECK-NEXT:    ret <vscale x 2 x i32> [[TMP0]]
+//
+vint32m1_t test_th_vmaqasu_vx_i32m1_m(vbool8_t mask, vint32m1_t acc, int8_t op1,
+                                    vuint8m1_t op2, size_t vl) {
+  return th_vmaqasu(mask, acc, op1, op2, vl);
+}
+
+// CHECK-LABEL: @test_th_vmaqasu_vv_i32m2_m(
+// CHECK-NEXT:  entry:
+// CHECK-NEXT:    [[TMP0:%.*]] = call <vscale x 4 x i32> @llvm.riscv.th.vmaqasu.mask.nxv4i32.nxv16i8.nxv16i8.i64(<vscale x 4 x i32> [[ACC:%.*]], <vscale x 16 x i8> [[OP1:%.*]], <vscale x 16 x i8> [[OP2:%.*]], <vscale x 16 x i1> [[MASK:%.*]], i64 [[VL:%.*]], i64 0)
+// CHECK-NEXT:    ret <vscale x 4 x i32> [[TMP0]]
+//
+vint32m2_t test_th_vmaqasu_vv_i32m2_m(vbool4_t mask, vint32m2_t acc,
+                                    vint8m2_t op1, vuint8m2_t op2, size_t vl) {
+  return th_vmaqasu(mask, acc, op1, op2, vl);
+}
+
+// CHECK-LABEL: @test_th_vmaqasu_vx_i32m2_m(
+// CHECK-NEXT:  entry:
+// CHECK-NEXT:    [[TMP0:%.*]] = call <vscale x 4 x i32> @llvm.riscv.th.vmaqasu.mask.nxv4i32.i8.nxv16i8.i64(<vscale x 4 x i32> [[ACC:%.*]], i8 [[OP1:%.*]], <vscale x 16 x i8> [[OP2:%.*]], <vscale x 16 x i1> [[MASK:%.*]], i64 [[VL:%.*]], i64 0)
+// CHECK-NEXT:    ret <vscale x 4 x i32> [[TMP0]]
+//
+vint32m2_t test_th_vmaqasu_vx_i32m2_m(vbool4_t mask, vint32m2_t acc, int8_t op1,
+                                    vuint8m2_t op2, size_t vl) {
+  return th_vmaqasu(mask, acc, op1, op2, vl);
+}
+
+// CHECK-LABEL: @test_th_vmaqasu_vv_i32m4_m(
+// CHECK-NEXT:  entry:
+// CHECK-NEXT:    [[TMP0:%.*]] = call <vscale x 8 x i32> @llvm.riscv.th.vmaqasu.mask.nxv8i32.nxv32i8.nxv32i8.i64(<vscale x 8 x i32> [[ACC:%.*]], <vscale x 32 x i8> [[OP1:%.*]], <vscale x 32 x i8> [[OP2:%.*]], <vscale x 32 x i1> [[MASK:%.*]], i64 [[VL:%.*]], i64 0)
+// CHECK-NEXT:    ret <vscale x 8 x i32> [[TMP0]]
+//
+vint32m4_t test_th_vmaqasu_vv_i32m4_m(vbool2_t mask, vint32m4_t acc,
+                                    vint8m4_t op1, vuint8m4_t op2, size_t vl) {
+  return th_vmaqasu(mask, acc, op1, op2, vl);
+}
+
+// CHECK-LABEL: @test_th_vmaqasu_vx_i32m4_m(
+// CHECK-NEXT:  entry:
+// CHECK-NEXT:    [[TMP0:%.*]] = call <vscale x 8 x i32> @llvm.riscv.th.vmaqasu.mask.nxv8i32.i8.nxv32i8.i64(<vscale x 8 x i32> [[ACC:%.*]], i8 [[OP1:%.*]], <vscale x 32 x i8> [[OP2:%.*]], <vscale x 32 x i1> [[MASK:%.*]], i64 [[VL:%.*]], i64 0)
+// CHECK-NEXT:    ret <vscale x 8 x i32> [[TMP0]]
+//
+vint32m4_t test_th_vmaqasu_vx_i32m4_m(vbool2_t mask, vint32m4_t acc, int8_t op1,
+                                    vuint8m4_t op2, size_t vl) {
+  return th_vmaqasu(mask, acc, op1, op2, vl);
+}
+
+
+// CHECK-LABEL: @test_th_vmaqaus_vx_i32mf2_m(
+// CHECK-NEXT:  entry:
+// CHECK-NEXT:    [[TMP0:%.*]] = call <vscale x 1 x i32> @llvm.riscv.th.vmaqaus.mask.nxv1i32.i8.nxv4i8.i64(<vscale x 1 x i32> [[ACC:%.*]], i8 [[OP1:%.*]], <vscale x 4 x i8> [[OP2:%.*]], <vscale x 4 x i1> [[MASK:%.*]], i64 [[VL:%.*]], i64 0)
+// CHECK-NEXT:    ret <vscale x 1 x i32> [[TMP0]]
+//
+vint32mf2_t test_th_vmaqaus_vx_i32mf2_m(vbool16_t mask, vint32mf2_t acc, uint8_t op1,
+                                    vint8mf2_t op2, size_t vl) {
+  return th_vmaqaus(mask, acc, op1, op2, vl);
+}
+
+// CHECK-LABEL: @test_th_vmaqaus_vx_i32m1_m(
+// CHECK-NEXT:  entry:
+// CHECK-NEXT:    [[TMP0:%.*]] = call <vscale x 2 x i32> @llvm.riscv.th.vmaqaus.mask.nxv2i32.i8.nxv8i8.i64(<vscale x 2 x i32> [[ACC:%.*]], i8 [[OP1:%.*]], <vscale x 8 x i8> [[OP2:%.*]], <vscale x 8 x i1> [[MASK:%.*]], i64 [[VL:%.*]], i64 0)
+// CHECK-NEXT:    ret <vscale x 2 x i32> [[TMP0]]
+//
+vint32m1_t test_th_vmaqaus_vx_i32m1_m(vbool8_t mask, vint32m1_t acc, uint8_t op1,
+                                    vint8m1_t op2, size_t vl) {
+  return th_vmaqaus(mask, acc, op1, op2, vl);
+}
+
+// CHECK-LABEL: @test_th_vmaqaus_vx_i32m2_m(
+// CHECK-NEXT:  entry:
+// CHECK-NEXT:    [[TMP0:%.*]] = call <vscale x 4 x i32> @llvm.riscv.th.vmaqaus.mask.nxv4i32.i8.nxv16i8.i64(<vscale x 4 x i32> [[ACC:%.*]], i8 [[OP1:%.*]], <vscale x 16 x i8> [[OP2:%.*]], <vscale x 16 x i1> [[MASK:%.*]], i64 [[VL:%.*]], i64 0)
+// CHECK-NEXT:    ret <vscale x 4 x i32> [[TMP0]]
+//
+vint32m2_t test_th_vmaqaus_vx_i32m2_m(vbool4_t mask, vint32m2_t acc, uint8_t op1,
+                                    vint8m2_t op2, size_t vl) {
+  return th_vmaqaus(mask, acc, op1, op2, vl);
+}
+
+// CHECK-LABEL: @test_th_vmaqaus_vx_i32m4_m(
+// CHECK-NEXT:  entry:
+// CHECK-NEXT:    [[TMP0:%.*]] = call <vscale x 8 x i32> @llvm.riscv.th.vmaqaus.mask.nxv8i32.i8.nxv32i8.i64(<vscale x 8 x i32> [[ACC:%.*]], i8 [[OP1:%.*]], <vscale x 32 x i8> [[OP2:%.*]], <vscale x 32 x i1> [[MASK:%.*]], i64 [[VL:%.*]], i64 0)
+// CHECK-NEXT:    ret <vscale x 8 x i32> [[TMP0]]
+//
+vint32m4_t test_th_vmaqaus_vx_i32m4_m(vbool2_t mask, vint32m4_t acc, uint8_t op1,
+                                    vint8m4_t op2, size_t vl) {
+  return th_vmaqaus(mask, acc, op1, op2, vl);
+}
Index: clang/test/CodeGen/RISCV/rvv-intrinsics/xtheadvdot-vmaqa.c
===================================================================
--- /dev/null
+++ clang/test/CodeGen/RISCV/rvv-intrinsics/xtheadvdot-vmaqa.c
@@ -0,0 +1,574 @@
+// NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py
+// REQUIRES: riscv-registered-target
+// RUN: %clang_cc1 -triple riscv64 -target-feature +xtheadvdot -disable-O0-optnone -emit-llvm %s -o - | opt -S -passes=mem2reg | FileCheck %s
+
+#include <riscv_vector.h>
+
+// CHECK-LABEL: @test_th_vmaqa_vv_i32mf2(
+// CHECK-NEXT:  entry:
+// CHECK-NEXT:    [[TMP0:%.*]] = call <vscale x 1 x i32> @llvm.riscv.th.vmaqa.nxv1i32.nxv4i8.nxv4i8.i64(<vscale x 1 x i32> [[ACC:%.*]], <vscale x 4 x i8> [[OP1:%.*]], <vscale x 4 x i8> [[OP2:%.*]], i64 [[VL:%.*]], i64 0)
+// CHECK-NEXT:    ret <vscale x 1 x i32> [[TMP0]]
+//
+vint32mf2_t test_th_vmaqa_vv_i32mf2(vint32mf2_t acc, vint8mf2_t op1, vint8mf2_t op2,
+                                size_t vl) {
+  return th_vmaqa_vv_i32mf2(acc, op1, op2, vl);
+}
+
+// CHECK-LABEL: @test_th_vmaqa_vx_i32mf2(
+// CHECK-NEXT:  entry:
+// CHECK-NEXT:    [[TMP0:%.*]] = call <vscale x 1 x i32> @llvm.riscv.th.vmaqa.nxv1i32.i8.nxv4i8.i64(<vscale x 1 x i32> [[ACC:%.*]], i8 [[OP1:%.*]], <vscale x 4 x i8> [[OP2:%.*]], i64 [[VL:%.*]], i64 0)
+// CHECK-NEXT:    ret <vscale x 1 x i32> [[TMP0]]
+//
+vint32mf2_t test_th_vmaqa_vx_i32mf2(vint32mf2_t acc, int8_t op1, vint8mf2_t op2,
+                                size_t vl) {
+  return th_vmaqa_vx_i32mf2(acc, op1, op2, vl);
+}
+
+// CHECK-LABEL: @test_th_vmaqa_vv_i32m1(
+// CHECK-NEXT:  entry:
+// CHECK-NEXT:    [[TMP0:%.*]] = call <vscale x 2 x i32> @llvm.riscv.th.vmaqa.nxv2i32.nxv8i8.nxv8i8.i64(<vscale x 2 x i32> [[ACC:%.*]], <vscale x 8 x i8> [[OP1:%.*]], <vscale x 8 x i8> [[OP2:%.*]], i64 [[VL:%.*]], i64 0)
+// CHECK-NEXT:    ret <vscale x 2 x i32> [[TMP0]]
+//
+vint32m1_t test_th_vmaqa_vv_i32m1(vint32m1_t acc, vint8m1_t op1, vint8m1_t op2,
+                                size_t vl) {
+  return th_vmaqa_vv_i32m1(acc, op1, op2, vl);
+}
+
+// CHECK-LABEL: @test_th_vmaqa_vx_i32m1(
+// CHECK-NEXT:  entry:
+// CHECK-NEXT:    [[TMP0:%.*]] = call <vscale x 2 x i32> @llvm.riscv.th.vmaqa.nxv2i32.i8.nxv8i8.i64(<vscale x 2 x i32> [[ACC:%.*]], i8 [[OP1:%.*]], <vscale x 8 x i8> [[OP2:%.*]], i64 [[VL:%.*]], i64 0)
+// CHECK-NEXT:    ret <vscale x 2 x i32> [[TMP0]]
+//
+vint32m1_t test_th_vmaqa_vx_i32m1(vint32m1_t acc, int8_t op1, vint8m1_t op2,
+                                size_t vl) {
+  return th_vmaqa_vx_i32m1(acc, op1, op2, vl);
+}
+
+// CHECK-LABEL: @test_th_vmaqa_vv_i32m2(
+// CHECK-NEXT:  entry:
+// CHECK-NEXT:    [[TMP0:%.*]] = call <vscale x 4 x i32> @llvm.riscv.th.vmaqa.nxv4i32.nxv16i8.nxv16i8.i64(<vscale x 4 x i32> [[ACC:%.*]], <vscale x 16 x i8> [[OP1:%.*]], <vscale x 16 x i8> [[OP2:%.*]], i64 [[VL:%.*]], i64 0)
+// CHECK-NEXT:    ret <vscale x 4 x i32> [[TMP0]]
+//
+vint32m2_t test_th_vmaqa_vv_i32m2(vint32m2_t acc, vint8m2_t op1, vint8m2_t op2,
+                                size_t vl) {
+  return th_vmaqa_vv_i32m2(acc, op1, op2, vl);
+}
+
+// CHECK-LABEL: @test_th_vmaqa_vx_i32m2(
+// CHECK-NEXT:  entry:
+// CHECK-NEXT:    [[TMP0:%.*]] = call <vscale x 4 x i32> @llvm.riscv.th.vmaqa.nxv4i32.i8.nxv16i8.i64(<vscale x 4 x i32> [[ACC:%.*]], i8 [[OP1:%.*]], <vscale x 16 x i8> [[OP2:%.*]], i64 [[VL:%.*]], i64 0)
+// CHECK-NEXT:    ret <vscale x 4 x i32> [[TMP0]]
+//
+vint32m2_t test_th_vmaqa_vx_i32m2(vint32m2_t acc, int8_t op1, vint8m2_t op2,
+                                size_t vl) {
+  return th_vmaqa_vx_i32m2(acc, op1, op2, vl);
+}
+
+// CHECK-LABEL: @test_th_vmaqa_vv_i32m4(
+// CHECK-NEXT:  entry:
+// CHECK-NEXT:    [[TMP0:%.*]] = call <vscale x 8 x i32> @llvm.riscv.th.vmaqa.nxv8i32.nxv32i8.nxv32i8.i64(<vscale x 8 x i32> [[ACC:%.*]], <vscale x 32 x i8> [[OP1:%.*]], <vscale x 32 x i8> [[OP2:%.*]], i64 [[VL:%.*]], i64 0)
+// CHECK-NEXT:    ret <vscale x 8 x i32> [[TMP0]]
+//
+vint32m4_t test_th_vmaqa_vv_i32m4(vint32m4_t acc, vint8m4_t op1, vint8m4_t op2,
+                                size_t vl) {
+  return th_vmaqa_vv_i32m4(acc, op1, op2, vl);
+}
+
+// CHECK-LABEL: @test_th_vmaqa_vx_i32m4(
+// CHECK-NEXT:  entry:
+// CHECK-NEXT:    [[TMP0:%.*]] = call <vscale x 8 x i32> @llvm.riscv.th.vmaqa.nxv8i32.i8.nxv32i8.i64(<vscale x 8 x i32> [[ACC:%.*]], i8 [[OP1:%.*]], <vscale x 32 x i8> [[OP2:%.*]], i64 [[VL:%.*]], i64 0)
+// CHECK-NEXT:    ret <vscale x 8 x i32> [[TMP0]]
+//
+vint32m4_t test_th_vmaqa_vx_i32m4(vint32m4_t acc, int8_t op1, vint8m4_t op2,
+                                size_t vl) {
+  return th_vmaqa_vx_i32m4(acc, op1, op2, vl);
+}
+
+
+// CHECK-LABEL: @test_th_vmaqau_vv_u32mf2(
+// CHECK-NEXT:  entry:
+// CHECK-NEXT:    [[TMP0:%.*]] = call <vscale x 1 x i32> @llvm.riscv.th.vmaqau.nxv1i32.nxv4i8.nxv4i8.i64(<vscale x 1 x i32> [[ACC:%.*]], <vscale x 4 x i8> [[OP1:%.*]], <vscale x 4 x i8> [[OP2:%.*]], i64 [[VL:%.*]], i64 0)
+// CHECK-NEXT:    ret <vscale x 1 x i32> [[TMP0]]
+//
+vuint32mf2_t test_th_vmaqau_vv_u32mf2(vuint32mf2_t acc, vuint8mf2_t op1,
+                                  vuint8mf2_t op2, size_t vl) {
+  return th_vmaqau_vv_u32mf2(acc, op1, op2, vl);
+}
+
+// CHECK-LABEL: @test_th_vmaqau_vx_u32mf2(
+// CHECK-NEXT:  entry:
+// CHECK-NEXT:    [[TMP0:%.*]] = call <vscale x 1 x i32> @llvm.riscv.th.vmaqau.nxv1i32.i8.nxv4i8.i64(<vscale x 1 x i32> [[ACC:%.*]], i8 [[OP1:%.*]], <vscale x 4 x i8> [[OP2:%.*]], i64 [[VL:%.*]], i64 0)
+// CHECK-NEXT:    ret <vscale x 1 x i32> [[TMP0]]
+//
+vuint32mf2_t test_th_vmaqau_vx_u32mf2(vuint32mf2_t acc, uint8_t op1, vuint8mf2_t op2,
+                                  size_t vl) {
+  return th_vmaqau_vx_u32mf2(acc, op1, op2, vl);
+}
+
+// CHECK-LABEL: @test_th_vmaqau_vv_u32m1(
+// CHECK-NEXT:  entry:
+// CHECK-NEXT:    [[TMP0:%.*]] = call <vscale x 2 x i32> @llvm.riscv.th.vmaqau.nxv2i32.nxv8i8.nxv8i8.i64(<vscale x 2 x i32> [[ACC:%.*]], <vscale x 8 x i8> [[OP1:%.*]], <vscale x 8 x i8> [[OP2:%.*]], i64 [[VL:%.*]], i64 0)
+// CHECK-NEXT:    ret <vscale x 2 x i32> [[TMP0]]
+//
+vuint32m1_t test_th_vmaqau_vv_u32m1(vuint32m1_t acc, vuint8m1_t op1,
+                                  vuint8m1_t op2, size_t vl) {
+  return th_vmaqau_vv_u32m1(acc, op1, op2, vl);
+}
+
+// CHECK-LABEL: @test_th_vmaqau_vx_u32m1(
+// CHECK-NEXT:  entry:
+// CHECK-NEXT:    [[TMP0:%.*]] = call <vscale x 2 x i32> @llvm.riscv.th.vmaqau.nxv2i32.i8.nxv8i8.i64(<vscale x 2 x i32> [[ACC:%.*]], i8 [[OP1:%.*]], <vscale x 8 x i8> [[OP2:%.*]], i64 [[VL:%.*]], i64 0)
+// CHECK-NEXT:    ret <vscale x 2 x i32> [[TMP0]]
+//
+vuint32m1_t test_th_vmaqau_vx_u32m1(vuint32m1_t acc, uint8_t op1, vuint8m1_t op2,
+                                  size_t vl) {
+  return th_vmaqau_vx_u32m1(acc, op1, op2, vl);
+}
+
+// CHECK-LABEL: @test_th_vmaqau_vv_u32m2(
+// CHECK-NEXT:  entry:
+// CHECK-NEXT:    [[TMP0:%.*]] = call <vscale x 4 x i32> @llvm.riscv.th.vmaqau.nxv4i32.nxv16i8.nxv16i8.i64(<vscale x 4 x i32> [[ACC:%.*]], <vscale x 16 x i8> [[OP1:%.*]], <vscale x 16 x i8> [[OP2:%.*]], i64 [[VL:%.*]], i64 0)
+// CHECK-NEXT:    ret <vscale x 4 x i32> [[TMP0]]
+//
+vuint32m2_t test_th_vmaqau_vv_u32m2(vuint32m2_t acc, vuint8m2_t op1,
+                                  vuint8m2_t op2, size_t vl) {
+  return th_vmaqau_vv_u32m2(acc, op1, op2, vl);
+}
+
+// CHECK-LABEL: @test_th_vmaqau_vx_u32m2(
+// CHECK-NEXT:  entry:
+// CHECK-NEXT:    [[TMP0:%.*]] = call <vscale x 4 x i32> @llvm.riscv.th.vmaqau.nxv4i32.i8.nxv16i8.i64(<vscale x 4 x i32> [[ACC:%.*]], i8 [[OP1:%.*]], <vscale x 16 x i8> [[OP2:%.*]], i64 [[VL:%.*]], i64 0)
+// CHECK-NEXT:    ret <vscale x 4 x i32> [[TMP0]]
+//
+vuint32m2_t test_th_vmaqau_vx_u32m2(vuint32m2_t acc, uint8_t op1, vuint8m2_t op2,
+                                  size_t vl) {
+  return th_vmaqau_vx_u32m2(acc, op1, op2, vl);
+}
+
+// CHECK-LABEL: @test_th_vmaqau_vv_u32m4(
+// CHECK-NEXT:  entry:
+// CHECK-NEXT:    [[TMP0:%.*]] = call <vscale x 8 x i32> @llvm.riscv.th.vmaqau.nxv8i32.nxv32i8.nxv32i8.i64(<vscale x 8 x i32> [[ACC:%.*]], <vscale x 32 x i8> [[OP1:%.*]], <vscale x 32 x i8> [[OP2:%.*]], i64 [[VL:%.*]], i64 0)
+// CHECK-NEXT:    ret <vscale x 8 x i32> [[TMP0]]
+//
+vuint32m4_t test_th_vmaqau_vv_u32m4(vuint32m4_t acc, vuint8m4_t op1,
+                                  vuint8m4_t op2, size_t vl) {
+  return th_vmaqau_vv_u32m4(acc, op1, op2, vl);
+}
+
+// CHECK-LABEL: @test_th_vmaqau_vx_u32m4(
+// CHECK-NEXT:  entry:
+// CHECK-NEXT:    [[TMP0:%.*]] = call <vscale x 8 x i32> @llvm.riscv.th.vmaqau.nxv8i32.i8.nxv32i8.i64(<vscale x 8 x i32> [[ACC:%.*]], i8 [[OP1:%.*]], <vscale x 32 x i8> [[OP2:%.*]], i64 [[VL:%.*]], i64 0)
+// CHECK-NEXT:    ret <vscale x 8 x i32> [[TMP0]]
+//
+vuint32m4_t test_th_vmaqau_vx_u32m4(vuint32m4_t acc, uint8_t op1, vuint8m4_t op2,
+                                  size_t vl) {
+  return th_vmaqau_vx_u32m4(acc, op1, op2, vl);
+}
+
+
+// CHECK-LABEL: @test_th_vmaqasu_vv_i32mf2(
+// CHECK-NEXT:  entry:
+// CHECK-NEXT:    [[TMP0:%.*]] = call <vscale x 1 x i32> @llvm.riscv.th.vmaqasu.nxv1i32.nxv4i8.nxv4i8.i64(<vscale x 1 x i32> [[ACC:%.*]], <vscale x 4 x i8> [[OP1:%.*]], <vscale x 4 x i8> [[OP2:%.*]], i64 [[VL:%.*]], i64 0)
+// CHECK-NEXT:    ret <vscale x 1 x i32> [[TMP0]]
+//
+vint32mf2_t test_th_vmaqasu_vv_i32mf2(vint32mf2_t acc, vint8mf2_t op1,
+                                  vuint8mf2_t op2, size_t vl) {
+  return th_vmaqasu_vv_i32mf2(acc, op1, op2, vl);
+}
+
+// CHECK-LABEL: @test_th_vmaqasu_vx_i32mf2(
+// CHECK-NEXT:  entry:
+// CHECK-NEXT:    [[TMP0:%.*]] = call <vscale x 1 x i32> @llvm.riscv.th.vmaqasu.nxv1i32.i8.nxv4i8.i64(<vscale x 1 x i32> [[ACC:%.*]], i8 [[OP1:%.*]], <vscale x 4 x i8> [[OP2:%.*]], i64 [[VL:%.*]], i64 0)
+// CHECK-NEXT:    ret <vscale x 1 x i32> [[TMP0]]
+//
+vint32mf2_t test_th_vmaqasu_vx_i32mf2(vint32mf2_t acc, int8_t op1, vuint8mf2_t op2,
+                                  size_t vl) {
+  return th_vmaqasu_vx_i32mf2(acc, op1, op2, vl);
+}
+
+// CHECK-LABEL: @test_th_vmaqasu_vv_i32m1(
+// CHECK-NEXT:  entry:
+// CHECK-NEXT:    [[TMP0:%.*]] = call <vscale x 2 x i32> @llvm.riscv.th.vmaqasu.nxv2i32.nxv8i8.nxv8i8.i64(<vscale x 2 x i32> [[ACC:%.*]], <vscale x 8 x i8> [[OP1:%.*]], <vscale x 8 x i8> [[OP2:%.*]], i64 [[VL:%.*]], i64 0)
+// CHECK-NEXT:    ret <vscale x 2 x i32> [[TMP0]]
+//
+vint32m1_t test_th_vmaqasu_vv_i32m1(vint32m1_t acc, vint8m1_t op1, vuint8m1_t op2,
+                                  size_t vl) {
+  return th_vmaqasu_vv_i32m1(acc, op1, op2, vl);
+}
+
+// CHECK-LABEL: @test_th_vmaqasu_vx_i32m1(
+// CHECK-NEXT:  entry:
+// CHECK-NEXT:    [[TMP0:%.*]] = call <vscale x 2 x i32> @llvm.riscv.th.vmaqasu.nxv2i32.i8.nxv8i8.i64(<vscale x 2 x i32> [[ACC:%.*]], i8 [[OP1:%.*]], <vscale x 8 x i8> [[OP2:%.*]], i64 [[VL:%.*]], i64 0)
+// CHECK-NEXT:    ret <vscale x 2 x i32> [[TMP0]]
+//
+vint32m1_t test_th_vmaqasu_vx_i32m1(vint32m1_t acc, int8_t op1, vuint8m1_t op2,
+                                  size_t vl) {
+  return th_vmaqasu_vx_i32m1(acc, op1, op2, vl);
+}
+
+// CHECK-LABEL: @test_th_vmaqasu_vv_i32m2(
+// CHECK-NEXT:  entry:
+// CHECK-NEXT:    [[TMP0:%.*]] = call <vscale x 4 x i32> @llvm.riscv.th.vmaqasu.nxv4i32.nxv16i8.nxv16i8.i64(<vscale x 4 x i32> [[ACC:%.*]], <vscale x 16 x i8> [[OP1:%.*]], <vscale x 16 x i8> [[OP2:%.*]], i64 [[VL:%.*]], i64 0)
+// CHECK-NEXT:    ret <vscale x 4 x i32> [[TMP0]]
+//
+vint32m2_t test_th_vmaqasu_vv_i32m2(vint32m2_t acc, vint8m2_t op1, vuint8m2_t op2,
+                                  size_t vl) {
+  return th_vmaqasu_vv_i32m2(acc, op1, op2, vl);
+}
+
+// CHECK-LABEL: @test_th_vmaqasu_vx_i32m2(
+// CHECK-NEXT:  entry:
+// CHECK-NEXT:    [[TMP0:%.*]] = call <vscale x 4 x i32> @llvm.riscv.th.vmaqasu.nxv4i32.i8.nxv16i8.i64(<vscale x 4 x i32> [[ACC:%.*]], i8 [[OP1:%.*]], <vscale x 16 x i8> [[OP2:%.*]], i64 [[VL:%.*]], i64 0)
+// CHECK-NEXT:    ret <vscale x 4 x i32> [[TMP0]]
+//
+vint32m2_t test_th_vmaqasu_vx_i32m2(vint32m2_t acc, int8_t op1, vuint8m2_t op2,
+                                  size_t vl) {
+  return th_vmaqasu_vx_i32m2(acc, op1, op2, vl);
+}
+
+// CHECK-LABEL: @test_th_vmaqasu_vv_i32m4(
+// CHECK-NEXT:  entry:
+// CHECK-NEXT:    [[TMP0:%.*]] = call <vscale x 8 x i32> @llvm.riscv.th.vmaqasu.nxv8i32.nxv32i8.nxv32i8.i64(<vscale x 8 x i32> [[ACC:%.*]], <vscale x 32 x i8> [[OP1:%.*]], <vscale x 32 x i8> [[OP2:%.*]], i64 [[VL:%.*]], i64 0)
+// CHECK-NEXT:    ret <vscale x 8 x i32> [[TMP0]]
+//
+vint32m4_t test_th_vmaqasu_vv_i32m4(vint32m4_t acc, vint8m4_t op1, vuint8m4_t op2,
+                                  size_t vl) {
+  return th_vmaqasu_vv_i32m4(acc, op1, op2, vl);
+}
+
+// CHECK-LABEL: @test_th_vmaqasu_vx_i32m4(
+// CHECK-NEXT:  entry:
+// CHECK-NEXT:    [[TMP0:%.*]] = call <vscale x 8 x i32> @llvm.riscv.th.vmaqasu.nxv8i32.i8.nxv32i8.i64(<vscale x 8 x i32> [[ACC:%.*]], i8 [[OP1:%.*]], <vscale x 32 x i8> [[OP2:%.*]], i64 [[VL:%.*]], i64 0)
+// CHECK-NEXT:    ret <vscale x 8 x i32> [[TMP0]]
+//
+vint32m4_t test_th_vmaqasu_vx_i32m4(vint32m4_t acc, int8_t op1, vuint8m4_t op2,
+                                  size_t vl) {
+  return th_vmaqasu_vx_i32m4(acc, op1, op2, vl);
+}
+
+
+// CHECK-LABEL: @test_th_vmaqaus_vx_i32mf2(
+// CHECK-NEXT:  entry:
+// CHECK-NEXT:    [[TMP0:%.*]] = call <vscale x 1 x i32> @llvm.riscv.th.vmaqaus.nxv1i32.i8.nxv4i8.i64(<vscale x 1 x i32> [[ACC:%.*]], i8 [[OP1:%.*]], <vscale x 4 x i8> [[OP2:%.*]], i64 [[VL:%.*]], i64 0)
+// CHECK-NEXT:    ret <vscale x 1 x i32> [[TMP0]]
+//
+vint32mf2_t test_th_vmaqaus_vx_i32mf2(vint32mf2_t acc, uint8_t op1, vint8mf2_t op2,
+                                  size_t vl) {
+  return th_vmaqaus_vx_i32mf2(acc, op1, op2, vl);
+}
+
+// CHECK-LABEL: @test_th_vmaqaus_vx_i32m1(
+// CHECK-NEXT:  entry:
+// CHECK-NEXT:    [[TMP0:%.*]] = call <vscale x 2 x i32> @llvm.riscv.th.vmaqaus.nxv2i32.i8.nxv8i8.i64(<vscale x 2 x i32> [[ACC:%.*]], i8 [[OP1:%.*]], <vscale x 8 x i8> [[OP2:%.*]], i64 [[VL:%.*]], i64 0)
+// CHECK-NEXT:    ret <vscale x 2 x i32> [[TMP0]]
+//
+vint32m1_t test_th_vmaqaus_vx_i32m1(vint32m1_t acc, uint8_t op1, vint8m1_t op2,
+                                  size_t vl) {
+  return th_vmaqaus_vx_i32m1(acc, op1, op2, vl);
+}
+
+// CHECK-LABEL: @test_th_vmaqaus_vx_i32m2(
+// CHECK-NEXT:  entry:
+// CHECK-NEXT:    [[TMP0:%.*]] = call <vscale x 4 x i32> @llvm.riscv.th.vmaqaus.nxv4i32.i8.nxv16i8.i64(<vscale x 4 x i32> [[ACC:%.*]], i8 [[OP1:%.*]], <vscale x 16 x i8> [[OP2:%.*]], i64 [[VL:%.*]], i64 0)
+// CHECK-NEXT:    ret <vscale x 4 x i32> [[TMP0]]
+//
+vint32m2_t test_th_vmaqaus_vx_i32m2(vint32m2_t acc, uint8_t op1, vint8m2_t op2,
+                                  size_t vl) {
+  return th_vmaqaus_vx_i32m2(acc, op1, op2, vl);
+}
+
+// CHECK-LABEL: @test_th_vmaqaus_vx_i32m4(
+// CHECK-NEXT:  entry:
+// CHECK-NEXT:    [[TMP0:%.*]] = call <vscale x 8 x i32> @llvm.riscv.th.vmaqaus.nxv8i32.i8.nxv32i8.i64(<vscale x 8 x i32> [[ACC:%.*]], i8 [[OP1:%.*]], <vscale x 32 x i8> [[OP2:%.*]], i64 [[VL:%.*]], i64 0)
+// CHECK-NEXT:    ret <vscale x 8 x i32> [[TMP0]]
+//
+vint32m4_t test_th_vmaqaus_vx_i32m4(vint32m4_t acc, uint8_t op1, vint8m4_t op2,
+                                  size_t vl) {
+  return th_vmaqaus_vx_i32m4(acc, op1, op2, vl);
+}
+
+
+// CHECK-LABEL: @test_th_vmaqa_vv_i32mf2_m(
+// CHECK-NEXT:  entry:
+// CHECK-NEXT:    [[TMP0:%.*]] = call <vscale x 1 x i32> @llvm.riscv.th.vmaqa.mask.nxv1i32.nxv4i8.nxv4i8.i64(<vscale x 1 x i32> [[ACC:%.*]], <vscale x 4 x i8> [[OP1:%.*]], <vscale x 4 x i8> [[OP2:%.*]], <vscale x 4 x i1> [[MASK:%.*]], i64 [[VL:%.*]], i64 0)
+// CHECK-NEXT:    ret <vscale x 1 x i32> [[TMP0]]
+//
+vint32mf2_t test_th_vmaqa_vv_i32mf2_m(vbool16_t mask, vint32mf2_t acc,
+                                  vint8mf2_t op1, vint8mf2_t op2, size_t vl) {
+  return th_vmaqa_vv_i32mf2_m(mask, acc, op1, op2, vl);
+}
+
+// CHECK-LABEL: @test_th_vmaqa_vx_i32mf2_m(
+// CHECK-NEXT:  entry:
+// CHECK-NEXT:    [[TMP0:%.*]] = call <vscale x 1 x i32> @llvm.riscv.th.vmaqa.mask.nxv1i32.i8.nxv4i8.i64(<vscale x 1 x i32> [[ACC:%.*]], i8 [[OP1:%.*]], <vscale x 4 x i8> [[OP2:%.*]], <vscale x 4 x i1> [[MASK:%.*]], i64 [[VL:%.*]], i64 0)
+// CHECK-NEXT:    ret <vscale x 1 x i32> [[TMP0]]
+//
+vint32mf2_t test_th_vmaqa_vx_i32mf2_m(vbool16_t mask, vint32mf2_t acc, int8_t op1,
+                                  vint8mf2_t op2, size_t vl) {
+  return th_vmaqa_vx_i32mf2_m(mask, acc, op1, op2, vl);
+}
+
+// CHECK-LABEL: @test_th_vmaqa_vv_i32m1_m(
+// CHECK-NEXT:  entry:
+// CHECK-NEXT:    [[TMP0:%.*]] = call <vscale x 2 x i32> @llvm.riscv.th.vmaqa.mask.nxv2i32.nxv8i8.nxv8i8.i64(<vscale x 2 x i32> [[ACC:%.*]], <vscale x 8 x i8> [[OP1:%.*]], <vscale x 8 x i8> [[OP2:%.*]], <vscale x 8 x i1> [[MASK:%.*]], i64 [[VL:%.*]], i64 0)
+// CHECK-NEXT:    ret <vscale x 2 x i32> [[TMP0]]
+//
+vint32m1_t test_th_vmaqa_vv_i32m1_m(vbool8_t mask, vint32m1_t acc, vint8m1_t op1,
+                                  vint8m1_t op2, size_t vl) {
+  return th_vmaqa_vv_i32m1_m(mask, acc, op1, op2, vl);
+}
+
+// CHECK-LABEL: @test_th_vmaqa_vx_i32m1_m(
+// CHECK-NEXT:  entry:
+// CHECK-NEXT:    [[TMP0:%.*]] = call <vscale x 2 x i32> @llvm.riscv.th.vmaqa.mask.nxv2i32.i8.nxv8i8.i64(<vscale x 2 x i32> [[ACC:%.*]], i8 [[OP1:%.*]], <vscale x 8 x i8> [[OP2:%.*]], <vscale x 8 x i1> [[MASK:%.*]], i64 [[VL:%.*]], i64 0)
+// CHECK-NEXT:    ret <vscale x 2 x i32> [[TMP0]]
+//
+vint32m1_t test_th_vmaqa_vx_i32m1_m(vbool8_t mask, vint32m1_t acc, int8_t op1,
+                                  vint8m1_t op2, size_t vl) {
+  return th_vmaqa_vx_i32m1_m(mask, acc, op1, op2, vl);
+}
+
+// CHECK-LABEL: @test_th_vmaqa_vv_i32m2_m(
+// CHECK-NEXT:  entry:
+// CHECK-NEXT:    [[TMP0:%.*]] = call <vscale x 4 x i32> @llvm.riscv.th.vmaqa.mask.nxv4i32.nxv16i8.nxv16i8.i64(<vscale x 4 x i32> [[ACC:%.*]], <vscale x 16 x i8> [[OP1:%.*]], <vscale x 16 x i8> [[OP2:%.*]], <vscale x 16 x i1> [[MASK:%.*]], i64 [[VL:%.*]], i64 0)
+// CHECK-NEXT:    ret <vscale x 4 x i32> [[TMP0]]
+//
+vint32m2_t test_th_vmaqa_vv_i32m2_m(vbool4_t mask, vint32m2_t acc, vint8m2_t op1,
+                                  vint8m2_t op2, size_t vl) {
+  return th_vmaqa_vv_i32m2_m(mask, acc, op1, op2, vl);
+}
+
+// CHECK-LABEL: @test_th_vmaqa_vx_i32m2_m(
+// CHECK-NEXT:  entry:
+// CHECK-NEXT:    [[TMP0:%.*]] = call <vscale x 4 x i32> @llvm.riscv.th.vmaqa.mask.nxv4i32.i8.nxv16i8.i64(<vscale x 4 x i32> [[ACC:%.*]], i8 [[OP1:%.*]], <vscale x 16 x i8> [[OP2:%.*]], <vscale x 16 x i1> [[MASK:%.*]], i64 [[VL:%.*]], i64 0)
+// CHECK-NEXT:    ret <vscale x 4 x i32> [[TMP0]]
+//
+vint32m2_t test_th_vmaqa_vx_i32m2_m(vbool4_t mask, vint32m2_t acc, int8_t op1,
+                                  vint8m2_t op2, size_t vl) {
+  return th_vmaqa_vx_i32m2_m(mask, acc, op1, op2, vl);
+}
+
+// CHECK-LABEL: @test_th_vmaqa_vv_i32m4_m(
+// CHECK-NEXT:  entry:
+// CHECK-NEXT:    [[TMP0:%.*]] = call <vscale x 8 x i32> @llvm.riscv.th.vmaqa.mask.nxv8i32.nxv32i8.nxv32i8.i64(<vscale x 8 x i32> [[ACC:%.*]], <vscale x 32 x i8> [[OP1:%.*]], <vscale x 32 x i8> [[OP2:%.*]], <vscale x 32 x i1> [[MASK:%.*]], i64 [[VL:%.*]], i64 0)
+// CHECK-NEXT:    ret <vscale x 8 x i32> [[TMP0]]
+//
+vint32m4_t test_th_vmaqa_vv_i32m4_m(vbool2_t mask, vint32m4_t acc, vint8m4_t op1,
+                                  vint8m4_t op2, size_t vl) {
+  return th_vmaqa_vv_i32m4_m(mask, acc, op1, op2, vl);
+}
+
+// CHECK-LABEL: @test_th_vmaqa_vx_i32m4_m(
+// CHECK-NEXT:  entry:
+// CHECK-NEXT:    [[TMP0:%.*]] = call <vscale x 8 x i32> @llvm.riscv.th.vmaqa.mask.nxv8i32.i8.nxv32i8.i64(<vscale x 8 x i32> [[ACC:%.*]], i8 [[OP1:%.*]], <vscale x 32 x i8> [[OP2:%.*]], <vscale x 32 x i1> [[MASK:%.*]], i64 [[VL:%.*]], i64 0)
+// CHECK-NEXT:    ret <vscale x 8 x i32> [[TMP0]]
+//
+vint32m4_t test_th_vmaqa_vx_i32m4_m(vbool2_t mask, vint32m4_t acc, int8_t op1,
+                                  vint8m4_t op2, size_t vl) {
+  return th_vmaqa_vx_i32m4_m(mask, acc, op1, op2, vl);
+}
+
+
+// CHECK-LABEL: @test_th_vmaqau_vv_u32mf2_m(
+// CHECK-NEXT:  entry:
+// CHECK-NEXT:    [[TMP0:%.*]] = call <vscale x 1 x i32> @llvm.riscv.th.vmaqau.mask.nxv1i32.nxv4i8.nxv4i8.i64(<vscale x 1 x i32> [[ACC:%.*]], <vscale x 4 x i8> [[OP1:%.*]], <vscale x 4 x i8> [[OP2:%.*]], <vscale x 4 x i1> [[MASK:%.*]], i64 [[VL:%.*]], i64 0)
+// CHECK-NEXT:    ret <vscale x 1 x i32> [[TMP0]]
+//
+vuint32mf2_t test_th_vmaqau_vv_u32mf2_m(vbool16_t mask, vuint32mf2_t acc,
+                                    vuint8mf2_t op1, vuint8mf2_t op2,
+                                    size_t vl) {
+  return th_vmaqau_vv_u32mf2_m(mask, acc, op1, op2, vl);
+}
+
+// CHECK-LABEL: @test_th_vmaqau_vx_u32mf2_m(
+// CHECK-NEXT:  entry:
+// CHECK-NEXT:    [[TMP0:%.*]] = call <vscale x 1 x i32> @llvm.riscv.th.vmaqau.mask.nxv1i32.i8.nxv4i8.i64(<vscale x 1 x i32> [[ACC:%.*]], i8 [[OP1:%.*]], <vscale x 4 x i8> [[OP2:%.*]], <vscale x 4 x i1> [[MASK:%.*]], i64 [[VL:%.*]], i64 0)
+// CHECK-NEXT:    ret <vscale x 1 x i32> [[TMP0]]
+//
+vuint32mf2_t test_th_vmaqau_vx_u32mf2_m(vbool16_t mask, vuint32mf2_t acc,
+                                    uint8_t op1, vuint8mf2_t op2, size_t vl) {
+  return th_vmaqau_vx_u32mf2_m(mask, acc, op1, op2, vl);
+}
+
+// CHECK-LABEL: @test_th_vmaqau_vv_u32m1_m(
+// CHECK-NEXT:  entry:
+// CHECK-NEXT:    [[TMP0:%.*]] = call <vscale x 2 x i32> @llvm.riscv.th.vmaqau.mask.nxv2i32.nxv8i8.nxv8i8.i64(<vscale x 2 x i32> [[ACC:%.*]], <vscale x 8 x i8> [[OP1:%.*]], <vscale x 8 x i8> [[OP2:%.*]], <vscale x 8 x i1> [[MASK:%.*]], i64 [[VL:%.*]], i64 0)
+// CHECK-NEXT:    ret <vscale x 2 x i32> [[TMP0]]
+//
+vuint32m1_t test_th_vmaqau_vv_u32m1_m(vbool8_t mask, vuint32m1_t acc,
+                                    vuint8m1_t op1, vuint8m1_t op2, size_t vl) {
+  return th_vmaqau_vv_u32m1_m(mask, acc, op1, op2, vl);
+}
+
+// CHECK-LABEL: @test_th_vmaqau_vx_u32m1_m(
+// CHECK-NEXT:  entry:
+// CHECK-NEXT:    [[TMP0:%.*]] = call <vscale x 2 x i32> @llvm.riscv.th.vmaqau.mask.nxv2i32.i8.nxv8i8.i64(<vscale x 2 x i32> [[ACC:%.*]], i8 [[OP1:%.*]], <vscale x 8 x i8> [[OP2:%.*]], <vscale x 8 x i1> [[MASK:%.*]], i64 [[VL:%.*]], i64 0)
+// CHECK-NEXT:    ret <vscale x 2 x i32> [[TMP0]]
+//
+vuint32m1_t test_th_vmaqau_vx_u32m1_m(vbool8_t mask, vuint32m1_t acc, uint8_t op1,
+                                    vuint8m1_t op2, size_t vl) {
+  return th_vmaqau_vx_u32m1_m(mask, acc, op1, op2, vl);
+}
+
+// CHECK-LABEL: @test_th_vmaqau_vv_u32m2_m(
+// CHECK-NEXT:  entry:
+// CHECK-NEXT:    [[TMP0:%.*]] = call <vscale x 4 x i32> @llvm.riscv.th.vmaqau.mask.nxv4i32.nxv16i8.nxv16i8.i64(<vscale x 4 x i32> [[ACC:%.*]], <vscale x 16 x i8> [[OP1:%.*]], <vscale x 16 x i8> [[OP2:%.*]], <vscale x 16 x i1> [[MASK:%.*]], i64 [[VL:%.*]], i64 0)
+// CHECK-NEXT:    ret <vscale x 4 x i32> [[TMP0]]
+//
+vuint32m2_t test_th_vmaqau_vv_u32m2_m(vbool4_t mask, vuint32m2_t acc,
+                                    vuint8m2_t op1, vuint8m2_t op2, size_t vl) {
+  return th_vmaqau_vv_u32m2_m(mask, acc, op1, op2, vl);
+}
+
+// CHECK-LABEL: @test_th_vmaqau_vx_u32m2_m(
+// CHECK-NEXT:  entry:
+// CHECK-NEXT:    [[TMP0:%.*]] = call <vscale x 4 x i32> @llvm.riscv.th.vmaqau.mask.nxv4i32.i8.nxv16i8.i64(<vscale x 4 x i32> [[ACC:%.*]], i8 [[OP1:%.*]], <vscale x 16 x i8> [[OP2:%.*]], <vscale x 16 x i1> [[MASK:%.*]], i64 [[VL:%.*]], i64 0)
+// CHECK-NEXT:    ret <vscale x 4 x i32> [[TMP0]]
+//
+vuint32m2_t test_th_vmaqau_vx_u32m2_m(vbool4_t mask, vuint32m2_t acc, uint8_t op1,
+                                    vuint8m2_t op2, size_t vl) {
+  return th_vmaqau_vx_u32m2_m(mask, acc, op1, op2, vl);
+}
+
+// CHECK-LABEL: @test_th_vmaqau_vv_u32m4_m(
+// CHECK-NEXT:  entry:
+// CHECK-NEXT:    [[TMP0:%.*]] = call <vscale x 8 x i32> @llvm.riscv.th.vmaqau.mask.nxv8i32.nxv32i8.nxv32i8.i64(<vscale x 8 x i32> [[ACC:%.*]], <vscale x 32 x i8> [[OP1:%.*]], <vscale x 32 x i8> [[OP2:%.*]], <vscale x 32 x i1> [[MASK:%.*]], i64 [[VL:%.*]], i64 0)
+// CHECK-NEXT:    ret <vscale x 8 x i32> [[TMP0]]
+//
+vuint32m4_t test_th_vmaqau_vv_u32m4_m(vbool2_t mask, vuint32m4_t acc,
+                                    vuint8m4_t op1, vuint8m4_t op2, size_t vl) {
+  return th_vmaqau_vv_u32m4_m(mask, acc, op1, op2, vl);
+}
+
+// CHECK-LABEL: @test_th_vmaqau_vx_u32m4_m(
+// CHECK-NEXT:  entry:
+// CHECK-NEXT:    [[TMP0:%.*]] = call <vscale x 8 x i32> @llvm.riscv.th.vmaqau.mask.nxv8i32.i8.nxv32i8.i64(<vscale x 8 x i32> [[ACC:%.*]], i8 [[OP1:%.*]], <vscale x 32 x i8> [[OP2:%.*]], <vscale x 32 x i1> [[MASK:%.*]], i64 [[VL:%.*]], i64 0)
+// CHECK-NEXT:    ret <vscale x 8 x i32> [[TMP0]]
+//
+vuint32m4_t test_th_vmaqau_vx_u32m4_m(vbool2_t mask, vuint32m4_t acc, uint8_t op1,
+                                    vuint8m4_t op2, size_t vl) {
+  return th_vmaqau_vx_u32m4_m(mask, acc, op1, op2, vl);
+}
+
+
+// CHECK-LABEL: @test_th_vmaqasu_vv_i32mf2_m(
+// CHECK-NEXT:  entry:
+// CHECK-NEXT:    [[TMP0:%.*]] = call <vscale x 1 x i32> @llvm.riscv.th.vmaqasu.mask.nxv1i32.nxv4i8.nxv4i8.i64(<vscale x 1 x i32> [[ACC:%.*]], <vscale x 4 x i8> [[OP1:%.*]], <vscale x 4 x i8> [[OP2:%.*]], <vscale x 4 x i1> [[MASK:%.*]], i64 [[VL:%.*]], i64 0)
+// CHECK-NEXT:    ret <vscale x 1 x i32> [[TMP0]]
+//
+vint32mf2_t test_th_vmaqasu_vv_i32mf2_m(vbool16_t mask, vint32mf2_t acc,
+                                    vint8mf2_t op1, vuint8mf2_t op2,
+                                    size_t vl) {
+  return th_vmaqasu_vv_i32mf2_m(mask, acc, op1, op2, vl);
+}
+
+// CHECK-LABEL: @test_th_vmaqasu_vx_i32mf2_m(
+// CHECK-NEXT:  entry:
+// CHECK-NEXT:    [[TMP0:%.*]] = call <vscale x 1 x i32> @llvm.riscv.th.vmaqasu.mask.nxv1i32.i8.nxv4i8.i64(<vscale x 1 x i32> [[ACC:%.*]], i8 [[OP1:%.*]], <vscale x 4 x i8> [[OP2:%.*]], <vscale x 4 x i1> [[MASK:%.*]], i64 [[VL:%.*]], i64 0)
+// CHECK-NEXT:    ret <vscale x 1 x i32> [[TMP0]]
+//
+vint32mf2_t test_th_vmaqasu_vx_i32mf2_m(vbool16_t mask, vint32mf2_t acc, int8_t op1,
+                                    vuint8mf2_t op2, size_t vl) {
+  return th_vmaqasu_vx_i32mf2_m(mask, acc, op1, op2, vl);
+}
+
+// CHECK-LABEL: @test_th_vmaqasu_vv_i32m1_m(
+// CHECK-NEXT:  entry:
+// CHECK-NEXT:    [[TMP0:%.*]] = call <vscale x 2 x i32> @llvm.riscv.th.vmaqasu.mask.nxv2i32.nxv8i8.nxv8i8.i64(<vscale x 2 x i32> [[ACC:%.*]], <vscale x 8 x i8> [[OP1:%.*]], <vscale x 8 x i8> [[OP2:%.*]], <vscale x 8 x i1> [[MASK:%.*]], i64 [[VL:%.*]], i64 0)
+// CHECK-NEXT:    ret <vscale x 2 x i32> [[TMP0]]
+//
+vint32m1_t test_th_vmaqasu_vv_i32m1_m(vbool8_t mask, vint32m1_t acc,
+                                    vint8m1_t op1, vuint8m1_t op2, size_t vl) {
+  return th_vmaqasu_vv_i32m1_m(mask, acc, op1, op2, vl);
+}
+
+// CHECK-LABEL: @test_th_vmaqasu_vx_i32m1_m(
+// CHECK-NEXT:  entry:
+// CHECK-NEXT:    [[TMP0:%.*]] = call <vscale x 2 x i32> @llvm.riscv.th.vmaqasu.mask.nxv2i32.i8.nxv8i8.i64(<vscale x 2 x i32> [[ACC:%.*]], i8 [[OP1:%.*]], <vscale x 8 x i8> [[OP2:%.*]], <vscale x 8 x i1> [[MASK:%.*]], i64 [[VL:%.*]], i64 0)
+// CHECK-NEXT:    ret <vscale x 2 x i32> [[TMP0]]
+//
+vint32m1_t test_th_vmaqasu_vx_i32m1_m(vbool8_t mask, vint32m1_t acc, int8_t op1,
+                                    vuint8m1_t op2, size_t vl) {
+  return th_vmaqasu_vx_i32m1_m(mask, acc, op1, op2, vl);
+}
+
+// CHECK-LABEL: @test_th_vmaqasu_vv_i32m2_m(
+// CHECK-NEXT:  entry:
+// CHECK-NEXT:    [[TMP0:%.*]] = call <vscale x 4 x i32> @llvm.riscv.th.vmaqasu.mask.nxv4i32.nxv16i8.nxv16i8.i64(<vscale x 4 x i32> [[ACC:%.*]], <vscale x 16 x i8> [[OP1:%.*]], <vscale x 16 x i8> [[OP2:%.*]], <vscale x 16 x i1> [[MASK:%.*]], i64 [[VL:%.*]], i64 0)
+// CHECK-NEXT:    ret <vscale x 4 x i32> [[TMP0]]
+//
+vint32m2_t test_th_vmaqasu_vv_i32m2_m(vbool4_t mask, vint32m2_t acc,
+                                    vint8m2_t op1, vuint8m2_t op2, size_t vl) {
+  return th_vmaqasu_vv_i32m2_m(mask, acc, op1, op2, vl);
+}
+
+// CHECK-LABEL: @test_th_vmaqasu_vx_i32m2_m(
+// CHECK-NEXT:  entry:
+// CHECK-NEXT:    [[TMP0:%.*]] = call <vscale x 4 x i32> @llvm.riscv.th.vmaqasu.mask.nxv4i32.i8.nxv16i8.i64(<vscale x 4 x i32> [[ACC:%.*]], i8 [[OP1:%.*]], <vscale x 16 x i8> [[OP2:%.*]], <vscale x 16 x i1> [[MASK:%.*]], i64 [[VL:%.*]], i64 0)
+// CHECK-NEXT:    ret <vscale x 4 x i32> [[TMP0]]
+//
+vint32m2_t test_th_vmaqasu_vx_i32m2_m(vbool4_t mask, vint32m2_t acc, int8_t op1,
+                                    vuint8m2_t op2, size_t vl) {
+  return th_vmaqasu_vx_i32m2_m(mask, acc, op1, op2, vl);
+}
+
+// CHECK-LABEL: @test_th_vmaqasu_vv_i32m4_m(
+// CHECK-NEXT:  entry:
+// CHECK-NEXT:    [[TMP0:%.*]] = call <vscale x 8 x i32> @llvm.riscv.th.vmaqasu.mask.nxv8i32.nxv32i8.nxv32i8.i64(<vscale x 8 x i32> [[ACC:%.*]], <vscale x 32 x i8> [[OP1:%.*]], <vscale x 32 x i8> [[OP2:%.*]], <vscale x 32 x i1> [[MASK:%.*]], i64 [[VL:%.*]], i64 0)
+// CHECK-NEXT:    ret <vscale x 8 x i32> [[TMP0]]
+//
+vint32m4_t test_th_vmaqasu_vv_i32m4_m(vbool2_t mask, vint32m4_t acc,
+                                    vint8m4_t op1, vuint8m4_t op2, size_t vl) {
+  return th_vmaqasu_vv_i32m4_m(mask, acc, op1, op2, vl);
+}
+
+// CHECK-LABEL: @test_th_vmaqasu_vx_i32m4_m(
+// CHECK-NEXT:  entry:
+// CHECK-NEXT:    [[TMP0:%.*]] = call <vscale x 8 x i32> @llvm.riscv.th.vmaqasu.mask.nxv8i32.i8.nxv32i8.i64(<vscale x 8 x i32> [[ACC:%.*]], i8 [[OP1:%.*]], <vscale x 32 x i8> [[OP2:%.*]], <vscale x 32 x i1> [[MASK:%.*]], i64 [[VL:%.*]], i64 0)
+// CHECK-NEXT:    ret <vscale x 8 x i32> [[TMP0]]
+//
+vint32m4_t test_th_vmaqasu_vx_i32m4_m(vbool2_t mask, vint32m4_t acc, int8_t op1,
+                                    vuint8m4_t op2, size_t vl) {
+  return th_vmaqasu_vx_i32m4_m(mask, acc, op1, op2, vl);
+}
+
+
+// CHECK-LABEL: @test_th_vmaqaus_vx_i32mf2_m(
+// CHECK-NEXT:  entry:
+// CHECK-NEXT:    [[TMP0:%.*]] = call <vscale x 1 x i32> @llvm.riscv.th.vmaqaus.mask.nxv1i32.i8.nxv4i8.i64(<vscale x 1 x i32> [[ACC:%.*]], i8 [[OP1:%.*]], <vscale x 4 x i8> [[OP2:%.*]], <vscale x 4 x i1> [[MASK:%.*]], i64 [[VL:%.*]], i64 0)
+// CHECK-NEXT:    ret <vscale x 1 x i32> [[TMP0]]
+//
+vint32mf2_t test_th_vmaqaus_vx_i32mf2_m(vbool16_t mask, vint32mf2_t acc, uint8_t op1,
+                                    vint8mf2_t op2, size_t vl) {
+  return th_vmaqaus_vx_i32mf2_m(mask, acc, op1, op2, vl);
+}
+
+// CHECK-LABEL: @test_th_vmaqaus_vx_i32m1_m(
+// CHECK-NEXT:  entry:
+// CHECK-NEXT:    [[TMP0:%.*]] = call <vscale x 2 x i32> @llvm.riscv.th.vmaqaus.mask.nxv2i32.i8.nxv8i8.i64(<vscale x 2 x i32> [[ACC:%.*]], i8 [[OP1:%.*]], <vscale x 8 x i8> [[OP2:%.*]], <vscale x 8 x i1> [[MASK:%.*]], i64 [[VL:%.*]], i64 0)
+// CHECK-NEXT:    ret <vscale x 2 x i32> [[TMP0]]
+//
+vint32m1_t test_th_vmaqaus_vx_i32m1_m(vbool8_t mask, vint32m1_t acc, uint8_t op1,
+                                    vint8m1_t op2, size_t vl) {
+  return th_vmaqaus_vx_i32m1_m(mask, acc, op1, op2, vl);
+}
+
+// CHECK-LABEL: @test_th_vmaqaus_vx_i32m2_m(
+// CHECK-NEXT:  entry:
+// CHECK-NEXT:    [[TMP0:%.*]] = call <vscale x 4 x i32> @llvm.riscv.th.vmaqaus.mask.nxv4i32.i8.nxv16i8.i64(<vscale x 4 x i32> [[ACC:%.*]], i8 [[OP1:%.*]], <vscale x 16 x i8> [[OP2:%.*]], <vscale x 16 x i1> [[MASK:%.*]], i64 [[VL:%.*]], i64 0)
+// CHECK-NEXT:    ret <vscale x 4 x i32> [[TMP0]]
+//
+vint32m2_t test_th_vmaqaus_vx_i32m2_m(vbool4_t mask, vint32m2_t acc, uint8_t op1,
+                                    vint8m2_t op2, size_t vl) {
+  return th_vmaqaus_vx_i32m2_m(mask, acc, op1, op2, vl);
+}
+
+// CHECK-LABEL: @test_th_vmaqaus_vx_i32m4_m(
+// CHECK-NEXT:  entry:
+// CHECK-NEXT:    [[TMP0:%.*]] = call <vscale x 8 x i32> @llvm.riscv.th.vmaqaus.mask.nxv8i32.i8.nxv32i8.i64(<vscale x 8 x i32> [[ACC:%.*]], i8 [[OP1:%.*]], <vscale x 32 x i8> [[OP2:%.*]], <vscale x 32 x i1> [[MASK:%.*]], i64 [[VL:%.*]], i64 0)
+// CHECK-NEXT:    ret <vscale x 8 x i32> [[TMP0]]
+//
+vint32m4_t test_th_vmaqaus_vx_i32m4_m(vbool2_t mask, vint32m4_t acc, uint8_t op1,
+                                    vint8m4_t op2, size_t vl) {
+  return th_vmaqaus_vx_i32m4_m(mask, acc, op1, op2, vl);
+}