diff --git a/llvm/lib/Target/AMDGPU/AsmParser/AMDGPUAsmParser.cpp b/llvm/lib/Target/AMDGPU/AsmParser/AMDGPUAsmParser.cpp --- a/llvm/lib/Target/AMDGPU/AsmParser/AMDGPUAsmParser.cpp +++ b/llvm/lib/Target/AMDGPU/AsmParser/AMDGPUAsmParser.cpp @@ -381,7 +381,7 @@ bool isFORMAT() const { return isImmTy(ImmTyFORMAT) && isUInt<7>(getImm()); } bool isBankMask() const { return isImmTy(ImmTyDppBankMask); } bool isRowMask() const { return isImmTy(ImmTyDppRowMask); } - bool isBoundCtrl() const { return isImmTy(ImmTyDppBoundCtrl); } + bool isDppBoundCtrl() const { return isImmTy(ImmTyDppBoundCtrl); } bool isFI() const { return isImmTy(ImmTyDppFi); } bool isSDWADstSel() const { return isImmTy(ImmTySdwaDstSel); } bool isSDWASrc0Sel() const { return isImmTy(ImmTySdwaSrc0Sel); } @@ -1579,6 +1579,7 @@ OperandMatchResultTy parseSymbolicOrNumericFormat(int64_t &Format); OperandMatchResultTy parseNumericFormat(int64_t &Format); OperandMatchResultTy parseFlatOffset(OperandVector &Operands); + OperandMatchResultTy parseR128A16(OperandVector &Operands); bool tryParseFmt(const char *Pref, int64_t MaxVal, int64_t &Val); bool matchDfmtNfmt(int64_t &Dfmt, int64_t &Nfmt, StringRef FormatStr, SMLoc Loc); @@ -1779,7 +1780,7 @@ int64_t parseDPPCtrlPerm(); AMDGPUOperand::Ptr defaultRowMask() const; AMDGPUOperand::Ptr defaultBankMask() const; - AMDGPUOperand::Ptr defaultBoundCtrl() const; + AMDGPUOperand::Ptr defaultDppBoundCtrl() const; AMDGPUOperand::Ptr defaultFI() const; void cvtDPP(MCInst &Inst, const OperandVector &Operands, bool IsDPP8 = false); void cvtDPP8(MCInst &Inst, const OperandVector &Operands) { @@ -6370,6 +6371,14 @@ return Res; } +OperandMatchResultTy AMDGPUAsmParser::parseR128A16(OperandVector &Operands) { + OperandMatchResultTy Res = + parseNamedBit("r128", Operands, AMDGPUOperand::ImmTyR128A16); + if (Res == MatchOperand_NoMatch) + Res = parseNamedBit("a16", Operands, AMDGPUOperand::ImmTyA16); + return Res; +} + //===----------------------------------------------------------------------===// // ds //===----------------------------------------------------------------------===// @@ -7992,7 +8001,7 @@ // Both bound_ctrl:0 and bound_ctrl:1 are encoded as 1. // This is intentional and ensures compatibility with sp3. // See bug 35397 for details. -static bool ConvertBoundCtrl(int64_t &BoundCtrl) { +static bool ConvertDppBoundCtrl(int64_t &BoundCtrl) { if (BoundCtrl == 0 || BoundCtrl == 1) { BoundCtrl = 1; return true; @@ -8683,7 +8692,7 @@ return AMDGPUOperand::CreateImm(this, 0xf, SMLoc(), AMDGPUOperand::ImmTyDppBankMask); } -AMDGPUOperand::Ptr AMDGPUAsmParser::defaultBoundCtrl() const { +AMDGPUOperand::Ptr AMDGPUAsmParser::defaultDppBoundCtrl() const { return AMDGPUOperand::CreateImm(this, 0, SMLoc(), AMDGPUOperand::ImmTyDppBoundCtrl); } @@ -9104,35 +9113,14 @@ } return Res; } - case MCK_ImmBoundCtrl: - return parseIntWithPrefix("bound_ctrl", Operands, - AMDGPUOperand::ImmTyDppBoundCtrl, - ConvertBoundCtrl); case MCK_ImmCBSZ: return parseIntWithPrefix("cbsz", Operands, AMDGPUOperand::ImmTyCBSZ); - case MCK_ImmClampSI: - return parseNamedBit("clamp", Operands, AMDGPUOperand::ImmTyClampSI); case MCK_ImmCPol: return parseCPol(Operands); - case MCK_ImmD16: - return parseNamedBit("d16", Operands, AMDGPUOperand::ImmTyD16); - case MCK_ImmDA: - return parseNamedBit("da", Operands, AMDGPUOperand::ImmTyDA); - case MCK_ImmExpCompr: - return parseNamedBit("compr", Operands, AMDGPUOperand::ImmTyExpCompr); - case MCK_ImmExpVM: - return parseNamedBit("vm", Operands, AMDGPUOperand::ImmTyExpVM); case MCK_ImmFI: return parseIntWithPrefix("fi", Operands, AMDGPUOperand::ImmTyDppFi); case MCK_gds: - case MCK_ImmGDS: return parseNamedBit("gds", Operands, AMDGPUOperand::ImmTyGDS); - case MCK_ImmA16: - return parseNamedBit("a16", Operands, AMDGPUOperand::ImmTyA16); - case MCK_ImmHigh: - return parseNamedBit("high", Operands, AMDGPUOperand::ImmTyHigh); - case MCK_ImmLWE: - return parseNamedBit("lwe", Operands, AMDGPUOperand::ImmTyLWE); case MCK_ImmNegHi: return parseOperandArrayWithPrefix("neg_hi", Operands, AMDGPUOperand::ImmTyNegHi); @@ -9149,13 +9137,6 @@ case MCK_ImmOpSelHi: return parseOperandArrayWithPrefix("op_sel_hi", Operands, AMDGPUOperand::ImmTyOpSelHi); - case MCK_ImmR128A16: { - OperandMatchResultTy Res = - parseNamedBit("r128", Operands, AMDGPUOperand::ImmTyR128A16); - if (Res == MatchOperand_NoMatch) - Res = parseNamedBit("a16", Operands, AMDGPUOperand::ImmTyA16); - return Res; - } case MCK_ImmRowMask: return parseIntWithPrefix("row_mask", Operands, AMDGPUOperand::ImmTyDppRowMask); @@ -9167,13 +9148,8 @@ return parseSDWASel(Operands, "src0_sel", AMDGPUOperand::ImmTySdwaSrc0Sel); case MCK_ImmSDWASrc1Sel: return parseSDWASel(Operands, "src1_sel", AMDGPUOperand::ImmTySdwaSrc1Sel); - case MCK_ImmSWZ: - return parseNamedBit("swz", Operands, AMDGPUOperand::ImmTySWZ); case MCK_tfe: - case MCK_ImmTFE: return parseNamedBit("tfe", Operands, AMDGPUOperand::ImmTyTFE); - case MCK_ImmUNorm: - return parseNamedBit("unorm", Operands, AMDGPUOperand::ImmTyUNorm); } return tryCustomParseOperand(Operands, MCK); } @@ -9199,7 +9175,6 @@ case MCK_offen: return Operand.isOffen() ? Match_Success : Match_InvalidOperand; case MCK_tfe: - case MCK_ImmTFE: return Operand.isTFE() ? Match_Success : Match_InvalidOperand; case MCK_SSrcB32: // When operands have expression values, they will return true for isToken, diff --git a/llvm/lib/Target/AMDGPU/MCTargetDesc/AMDGPUInstPrinter.h b/llvm/lib/Target/AMDGPU/MCTargetDesc/AMDGPUInstPrinter.h --- a/llvm/lib/Target/AMDGPU/MCTargetDesc/AMDGPUInstPrinter.h +++ b/llvm/lib/Target/AMDGPU/MCTargetDesc/AMDGPUInstPrinter.h @@ -136,8 +136,8 @@ raw_ostream &O); void printBankMask(const MCInst *MI, unsigned OpNo, const MCSubtargetInfo &STI, raw_ostream &O); - void printBoundCtrl(const MCInst *MI, unsigned OpNo, - const MCSubtargetInfo &STI, raw_ostream &O); + void printDppBoundCtrl(const MCInst *MI, unsigned OpNo, + const MCSubtargetInfo &STI, raw_ostream &O); void printFI(const MCInst *MI, unsigned OpNo, const MCSubtargetInfo &STI, raw_ostream &O); void printSDWASel(const MCInst *MI, unsigned OpNo, raw_ostream &O); diff --git a/llvm/lib/Target/AMDGPU/MCTargetDesc/AMDGPUInstPrinter.cpp b/llvm/lib/Target/AMDGPU/MCTargetDesc/AMDGPUInstPrinter.cpp --- a/llvm/lib/Target/AMDGPU/MCTargetDesc/AMDGPUInstPrinter.cpp +++ b/llvm/lib/Target/AMDGPU/MCTargetDesc/AMDGPUInstPrinter.cpp @@ -1026,9 +1026,9 @@ printU4ImmOperand(MI, OpNo, STI, O); } -void AMDGPUInstPrinter::printBoundCtrl(const MCInst *MI, unsigned OpNo, - const MCSubtargetInfo &STI, - raw_ostream &O) { +void AMDGPUInstPrinter::printDppBoundCtrl(const MCInst *MI, unsigned OpNo, + const MCSubtargetInfo &STI, + raw_ostream &O) { unsigned Imm = MI->getOperand(OpNo).getImm(); if (Imm) { O << " bound_ctrl:1"; diff --git a/llvm/lib/Target/AMDGPU/SIInstrInfo.td b/llvm/lib/Target/AMDGPU/SIInstrInfo.td --- a/llvm/lib/Target/AMDGPU/SIInstrInfo.td +++ b/llvm/lib/Target/AMDGPU/SIInstrInfo.td @@ -1157,23 +1157,6 @@ let DefaultMethod = !if(Optional, "default"#CName, ?); } -class NamedOperandBit : Operand { - let PrintMethod = "print"#Name; - let ParserMatchClass = MatchClass; -} - -class NamedOperandBit_0 : - OperandWithDefaultOps { - let PrintMethod = "print"#Name; - let ParserMatchClass = MatchClass; -} - -class NamedOperandBit_1 : - OperandWithDefaultOps { - let PrintMethod = "print"#Name; - let ParserMatchClass = MatchClass; -} - class CustomOperandClass : AsmOperandClass { let Name = CName; let PredicateMethod = "is"#CName; @@ -1183,23 +1166,43 @@ let DefaultMethod = "default"#CName; } +class CustomOperandProps> { + string PrintMethod = "print"#Name; + AsmOperandClass ParserMatchClass = Class; +} + class CustomOperand> - : Operand { - let PrintMethod = "print"#Name; - let ParserMatchClass = Class; + : Operand, CustomOperandProps; + +class NamedIntOperandClass + : CustomOperandClass { + string ImmTy = "AMDGPUOperand::ImmTy"#Name; + let ParserMethod = + "[this](OperandVector &Operands) -> OperandMatchResultTy { "# + "return parseIntWithPrefix(\""#Prefix#"\", Operands, "#ImmTy#", "# + ConvertMethod#"); }"; } -class NamedIntOperandClass +class NamedIntOperand + : CustomOperand>; + +class BitOperandClass : CustomOperandClass { string ImmTy = "AMDGPUOperand::ImmTy"#Name; let ParserMethod = "[this](OperandVector &Operands) -> OperandMatchResultTy { "# - "return parseIntWithPrefix(\""#Prefix#"\", Operands, "#ImmTy#"); }"; + "return parseNamedBit(\""#Id#"\", Operands, "#ImmTy#"); }"; } -class NamedIntOperand - : CustomOperand>; +class NamedBitOperand + : CustomOperand>; + +class DefaultOperand_0 + : OperandWithDefaultOps, + CustomOperandProps<1, Op.ParserMatchClass.Name, Op.ParserMatchClass>; class NamedOperandU32 : Operand { let PrintMethod = "print"#Name; @@ -1231,7 +1234,7 @@ def offset0 : NamedIntOperand; def offset1 : NamedIntOperand; -def gds : NamedOperandBit<"GDS", NamedMatchClass<"GDS">>; +def gds : NamedBitOperand<"gds", "GDS">; def omod : NamedOperandU32<"OModSI", NamedMatchClass<"OModSI">>; def omod0 : NamedOperandU32_0<"OModSI", NamedMatchClass<"OModSI">>; @@ -1239,25 +1242,25 @@ // We need to make the cases with a default of 0 distinct from no // default to help deal with some cases where the operand appears // before a mandatory operand. -def clampmod : NamedOperandBit<"ClampSI", NamedMatchClass<"ClampSI">>; -def clampmod0 : NamedOperandBit_0<"ClampSI", NamedMatchClass<"ClampSI">>; -def highmod : NamedOperandBit<"High", NamedMatchClass<"High">>; +def clampmod : NamedBitOperand<"clamp", "ClampSI">; +def clampmod0 : DefaultOperand_0; +def highmod : NamedBitOperand<"high", "High">; def CPol : NamedOperandU32<"CPol", NamedMatchClass<"CPol">>; def CPol_0 : NamedOperandU32Default0<"CPol", NamedMatchClass<"CPol">>; def CPol_GLC1 : NamedOperandU32Default1<"CPol", NamedMatchClass<"CPol">>; -def TFE : NamedOperandBit<"TFE", NamedMatchClass<"TFE">>; -def SWZ : NamedOperandBit<"SWZ", NamedMatchClass<"SWZ">>; -def SWZ_0 : NamedOperandBit_0<"SWZ", NamedMatchClass<"SWZ">>; -def UNorm : NamedOperandBit<"UNorm", NamedMatchClass<"UNorm">>; -def DA : NamedOperandBit<"DA", NamedMatchClass<"DA">>; -def R128A16 : NamedOperandBit<"R128A16", NamedMatchClass<"R128A16">>; -def A16 : NamedOperandBit<"A16", NamedMatchClass<"A16">>; -def D16 : NamedOperandBit<"D16", NamedMatchClass<"D16">>; -def LWE : NamedOperandBit<"LWE", NamedMatchClass<"LWE">>; -def exp_compr : NamedOperandBit<"ExpCompr", NamedMatchClass<"ExpCompr">>; -def exp_vm : NamedOperandBit<"ExpVM", NamedMatchClass<"ExpVM">>; +def TFE : NamedBitOperand<"tfe">; +def SWZ : NamedBitOperand<"swz">; +def SWZ_0 : DefaultOperand_0; +def UNorm : NamedBitOperand<"unorm">; +def DA : NamedBitOperand<"da">; +def R128A16 : CustomOperand; +def A16 : NamedBitOperand<"a16">; +def D16 : NamedBitOperand<"d16">; +def LWE : NamedBitOperand<"lwe">; +def exp_compr : NamedBitOperand<"compr", "ExpCompr">; +def exp_vm : NamedBitOperand<"vm", "ExpVM">; def FORMAT : CustomOperand; @@ -1279,7 +1282,7 @@ def row_mask : NamedOperandU32<"RowMask", NamedMatchClass<"RowMask">>; def bank_mask : NamedOperandU32<"BankMask", NamedMatchClass<"BankMask">>; -def bound_ctrl : NamedOperandBit<"BoundCtrl", NamedMatchClass<"BoundCtrl">>; +def bound_ctrl : NamedIntOperand; def FI : NamedOperandU32<"FI", NamedMatchClass<"FI">>; def blgp : NamedOperandU32<"BLGP", NamedMatchClass<"BLGP">>;