Index: llvm/lib/Target/AArch64/AArch64ExpandImm.cpp
===================================================================
--- llvm/lib/Target/AArch64/AArch64ExpandImm.cpp
+++ llvm/lib/Target/AArch64/AArch64ExpandImm.cpp
@@ -303,6 +303,8 @@
 void AArch64_IMM::expandMOVImm(uint64_t Imm, unsigned BitSize,
                                SmallVectorImpl<ImmInsnModel> &Insn) {
   const unsigned Mask = 0xFFFF;
+  // Adapt to the width of a register.
+  BitSize = BitSize <= 32 ? 32 : 64;
 
   // Scan the immediate and count the number of 16-bit chunks which are either
   // all ones or all zeros.
Index: llvm/test/CodeGen/AArch64/const-isel.ll
===================================================================
--- /dev/null
+++ llvm/test/CodeGen/AArch64/const-isel.ll
@@ -0,0 +1,16 @@
+; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
+; RUN: llc -mtriple=aarch64-none-linux-gnu -fast-isel -verify-machineinstrs < %s | FileCheck %s --check-prefix=FISEL
+
+define i53 @PR59892 () {
+; FISEL-LABEL: PR59892:
+; FISEL:       // %bb.0:
+; FISEL-NEXT:    mov x8, #47668
+; FISEL-NEXT:    movk x8, #4645, lsl #16
+; FISEL-NEXT:    movk x8, #58741, lsl #32
+; FISEL-NEXT:    movk x8, #1, lsl #48
+; FISEL-NEXT:    orr x9, x8, #0x2
+; FISEL-NEXT:    mul x0, x9, x8
+; FISEL-NEXT:    ret
+  %a = mul nsw i53 533765955107380, 533765955107382
+  ret i53 %a
+}