diff --git a/llvm/lib/Target/PowerPC/PPCISelLowering.cpp b/llvm/lib/Target/PowerPC/PPCISelLowering.cpp --- a/llvm/lib/Target/PowerPC/PPCISelLowering.cpp +++ b/llvm/lib/Target/PowerPC/PPCISelLowering.cpp @@ -14835,15 +14835,16 @@ // Handle DAG combine for STORE (FP_TO_INT F). SDValue PPCTargetLowering::combineStoreFPToInt(SDNode *N, DAGCombinerInfo &DCI) const { - SelectionDAG &DAG = DCI.DAG; SDLoc dl(N); unsigned Opcode = N->getOperand(1).getOpcode(); + bool Strict = N->getOperand(1)->isStrictFPOpcode(); - assert((Opcode == ISD::FP_TO_SINT || Opcode == ISD::FP_TO_UINT) + assert((Opcode == ISD::FP_TO_SINT || Opcode == ISD::FP_TO_UINT || + Opcode == ISD::STRICT_FP_TO_SINT || Opcode == ISD::STRICT_FP_TO_UINT) && "Not a FP_TO_INT Instruction!"); - SDValue Val = N->getOperand(1).getOperand(0); + SDValue Val = N->getOperand(1).getOperand(Strict ? 1 : 0); EVT Op1VT = N->getOperand(1).getValueType(); EVT ResVT = Val.getValueType(); @@ -14866,9 +14867,9 @@ // Set number of bytes being converted. unsigned ByteSize = Op1VT.getScalarSizeInBits() / 8; - SDValue Ops[] = { N->getOperand(0), Val, N->getOperand(2), - DAG.getIntPtrConstant(ByteSize, dl, false), - DAG.getValueType(Op1VT) }; + SDValue Ops[] = {N->getOperand(0), Val, N->getOperand(2), + DAG.getIntPtrConstant(ByteSize, dl, false), + DAG.getValueType(Op1VT)}; Val = DAG.getMemIntrinsicNode(PPCISD::ST_VSR_SCAL_INT, dl, DAG.getVTList(MVT::Other), Ops, @@ -15309,7 +15310,8 @@ EVT Op1VT = N->getOperand(1).getValueType(); unsigned Opcode = N->getOperand(1).getOpcode(); - if (Opcode == ISD::FP_TO_SINT || Opcode == ISD::FP_TO_UINT) { + if (Opcode == ISD::FP_TO_SINT || Opcode == ISD::FP_TO_UINT || + Opcode == ISD::STRICT_FP_TO_SINT || Opcode == ISD::STRICT_FP_TO_UINT) { SDValue Val= combineStoreFPToInt(N, DCI); if (Val) return Val; diff --git a/llvm/test/CodeGen/PowerPC/fp-strict-conv.ll b/llvm/test/CodeGen/PowerPC/fp-strict-conv.ll --- a/llvm/test/CodeGen/PowerPC/fp-strict-conv.ll +++ b/llvm/test/CodeGen/PowerPC/fp-strict-conv.ll @@ -1,8 +1,10 @@ ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py ; RUN: llc -verify-machineinstrs -ppc-asm-full-reg-names -ppc-vsr-nums-as-vr \ -; RUN: < %s -mtriple=powerpc64-unknown-linux -mcpu=pwr8 | FileCheck %s +; RUN: < %s -mtriple=powerpc64-unknown-linux -mcpu=pwr8 | FileCheck %s \ +; RUN: --check-prefixes=CHECK,P8 ; RUN: llc -verify-machineinstrs -ppc-asm-full-reg-names -ppc-vsr-nums-as-vr \ -; RUN: < %s -mtriple=powerpc64le-unknown-linux -mcpu=pwr9 | FileCheck %s +; RUN: < %s -mtriple=powerpc64le-unknown-linux -mcpu=pwr9 | FileCheck %s \ +; RUN: --check-prefixes=CHECK,P9 ; RUN: llc -verify-machineinstrs -ppc-asm-full-reg-names -ppc-vsr-nums-as-vr \ ; RUN: < %s -mtriple=powerpc64le-unknown-linux -mcpu=pwr8 -mattr=-vsx | \ ; RUN: FileCheck %s -check-prefix=NOVSX @@ -330,8 +332,7 @@ ; CHECK-LABEL: d_to_i32_store: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: xscvdpsxws f0, f1 -; CHECK-NEXT: mffprwz r3, f0 -; CHECK-NEXT: stw r3, 0(r4) +; CHECK-NEXT: stfiwx f0, 0, r4 ; CHECK-NEXT: blr ; ; NOVSX-LABEL: d_to_i32_store: @@ -349,12 +350,17 @@ } define void @d_to_i64_store(double %m, ptr %addr) #0 { -; CHECK-LABEL: d_to_i64_store: -; CHECK: # %bb.0: # %entry -; CHECK-NEXT: xscvdpsxds f0, f1 -; CHECK-NEXT: mffprd r3, f0 -; CHECK-NEXT: std r3, 0(r4) -; CHECK-NEXT: blr +; P8-LABEL: d_to_i64_store: +; P8: # %bb.0: # %entry +; P8-NEXT: xscvdpsxds f0, f1 +; P8-NEXT: stxsdx f0, 0, r4 +; P8-NEXT: blr +; +; P9-LABEL: d_to_i64_store: +; P9: # %bb.0: # %entry +; P9-NEXT: xscvdpsxds v2, f1 +; P9-NEXT: stxsd v2, 0(r4) +; P9-NEXT: blr ; ; NOVSX-LABEL: d_to_i64_store: ; NOVSX: # %bb.0: # %entry @@ -370,12 +376,17 @@ } define void @d_to_u64_store(double %m, ptr %addr) #0 { -; CHECK-LABEL: d_to_u64_store: -; CHECK: # %bb.0: # %entry -; CHECK-NEXT: xscvdpuxds f0, f1 -; CHECK-NEXT: mffprd r3, f0 -; CHECK-NEXT: std r3, 0(r4) -; CHECK-NEXT: blr +; P8-LABEL: d_to_u64_store: +; P8: # %bb.0: # %entry +; P8-NEXT: xscvdpuxds f0, f1 +; P8-NEXT: stxsdx f0, 0, r4 +; P8-NEXT: blr +; +; P9-LABEL: d_to_u64_store: +; P9: # %bb.0: # %entry +; P9-NEXT: xscvdpuxds v2, f1 +; P9-NEXT: stxsd v2, 0(r4) +; P9-NEXT: blr ; ; NOVSX-LABEL: d_to_u64_store: ; NOVSX: # %bb.0: # %entry @@ -394,8 +405,7 @@ ; CHECK-LABEL: d_to_u32_store: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: xscvdpuxws f0, f1 -; CHECK-NEXT: mffprwz r3, f0 -; CHECK-NEXT: stw r3, 0(r4) +; CHECK-NEXT: stfiwx f0, 0, r4 ; CHECK-NEXT: blr ; ; NOVSX-LABEL: d_to_u32_store: @@ -416,8 +426,7 @@ ; CHECK-LABEL: f_to_i32_store: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: xscvdpsxws f0, f1 -; CHECK-NEXT: mffprwz r3, f0 -; CHECK-NEXT: stw r3, 0(r4) +; CHECK-NEXT: stfiwx f0, 0, r4 ; CHECK-NEXT: blr ; ; NOVSX-LABEL: f_to_i32_store: @@ -435,12 +444,17 @@ } define void @f_to_i64_store(float %m, ptr %addr) #0 { -; CHECK-LABEL: f_to_i64_store: -; CHECK: # %bb.0: # %entry -; CHECK-NEXT: xscvdpsxds f0, f1 -; CHECK-NEXT: mffprd r3, f0 -; CHECK-NEXT: std r3, 0(r4) -; CHECK-NEXT: blr +; P8-LABEL: f_to_i64_store: +; P8: # %bb.0: # %entry +; P8-NEXT: xscvdpsxds f0, f1 +; P8-NEXT: stxsdx f0, 0, r4 +; P8-NEXT: blr +; +; P9-LABEL: f_to_i64_store: +; P9: # %bb.0: # %entry +; P9-NEXT: xscvdpsxds v2, f1 +; P9-NEXT: stxsd v2, 0(r4) +; P9-NEXT: blr ; ; NOVSX-LABEL: f_to_i64_store: ; NOVSX: # %bb.0: # %entry @@ -456,12 +470,17 @@ } define void @f_to_u64_store(float %m, ptr %addr) #0 { -; CHECK-LABEL: f_to_u64_store: -; CHECK: # %bb.0: # %entry -; CHECK-NEXT: xscvdpuxds f0, f1 -; CHECK-NEXT: mffprd r3, f0 -; CHECK-NEXT: std r3, 0(r4) -; CHECK-NEXT: blr +; P8-LABEL: f_to_u64_store: +; P8: # %bb.0: # %entry +; P8-NEXT: xscvdpuxds f0, f1 +; P8-NEXT: stxsdx f0, 0, r4 +; P8-NEXT: blr +; +; P9-LABEL: f_to_u64_store: +; P9: # %bb.0: # %entry +; P9-NEXT: xscvdpuxds v2, f1 +; P9-NEXT: stxsd v2, 0(r4) +; P9-NEXT: blr ; ; NOVSX-LABEL: f_to_u64_store: ; NOVSX: # %bb.0: # %entry @@ -480,8 +499,7 @@ ; CHECK-LABEL: f_to_u32_store: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: xscvdpuxws f0, f1 -; CHECK-NEXT: mffprwz r3, f0 -; CHECK-NEXT: stw r3, 0(r4) +; CHECK-NEXT: stfiwx f0, 0, r4 ; CHECK-NEXT: blr ; ; NOVSX-LABEL: f_to_u32_store: @@ -646,8 +664,8 @@ ; MIR-LABEL: name: fptoint_nofpexcept_f64 ; MIR: renamable $f{{[0-9]+}} = nofpexcept XSCVDPSXWS ; MIR: renamable $f{{[0-9]+}} = nofpexcept XSCVDPUXWS -; MIR: renamable $f{{[0-9]+}} = nofpexcept XSCVDPSXDS -; MIR: renamable $f{{[0-9]+}} = nofpexcept XSCVDPUXDS +; MIR: renamable $vf{{[0-9]+}} = nofpexcept XSCVDPSXDS +; MIR: renamable $vf{{[0-9]+}} = nofpexcept XSCVDPUXDS entry: %conv1 = tail call i32 @llvm.experimental.constrained.fptosi.i32.f64(double %m, metadata !"fpexcept.ignore") #0 %conv2 = tail call i32 @llvm.experimental.constrained.fptoui.i32.f64(double %m, metadata !"fpexcept.ignore") #0 @@ -664,8 +682,8 @@ ; MIR-LABEL: name: fptoint_nofpexcept_f32 ; MIR: renamable $f{{[0-9]+}} = nofpexcept XSCVDPSXWS ; MIR: renamable $f{{[0-9]+}} = nofpexcept XSCVDPUXWS -; MIR: renamable $f{{[0-9]+}} = nofpexcept XSCVDPSXDS -; MIR: renamable $f{{[0-9]+}} = nofpexcept XSCVDPUXDS +; MIR: renamable $vf{{[0-9]+}} = nofpexcept XSCVDPSXDS +; MIR: renamable $vf{{[0-9]+}} = nofpexcept XSCVDPUXDS entry: %conv1 = tail call i32 @llvm.experimental.constrained.fptosi.i32.f32(float %m, metadata !"fpexcept.ignore") #0 %conv2 = tail call i32 @llvm.experimental.constrained.fptoui.i32.f32(float %m, metadata !"fpexcept.ignore") #0 diff --git a/llvm/test/CodeGen/PowerPC/nofpexcept.ll b/llvm/test/CodeGen/PowerPC/nofpexcept.ll --- a/llvm/test/CodeGen/PowerPC/nofpexcept.ll +++ b/llvm/test/CodeGen/PowerPC/nofpexcept.ll @@ -82,28 +82,31 @@ ; CHECK-NEXT: [[COPY4:%[0-9]+]]:f8rc = COPY $f1 ; CHECK-NEXT: %5:vrrc = nofpexcept XSCVQPSWZ [[COPY2]] ; CHECK-NEXT: [[COPY5:%[0-9]+]]:vslrc = COPY %5 - ; CHECK-NEXT: [[COPY6:%[0-9]+]]:vfrc = COPY [[COPY5]].sub_64 - ; CHECK-NEXT: [[MFVSRWZ:%[0-9]+]]:gprc = MFVSRWZ killed [[COPY6]] - ; CHECK-NEXT: STW killed [[MFVSRWZ]], 0, [[COPY1]] :: (volatile store (s32) into %ir.addr1) - ; CHECK-NEXT: %8:vrrc = nofpexcept XSCVQPUWZ [[COPY2]] - ; CHECK-NEXT: [[COPY7:%[0-9]+]]:vslrc = COPY %8 - ; CHECK-NEXT: [[COPY8:%[0-9]+]]:vfrc = COPY [[COPY7]].sub_64 - ; CHECK-NEXT: [[MFVSRWZ1:%[0-9]+]]:gprc = MFVSRWZ killed [[COPY8]] - ; CHECK-NEXT: STW killed [[MFVSRWZ1]], 0, [[COPY1]] :: (volatile store (s32) into %ir.addr1) + ; CHECK-NEXT: [[COPY6:%[0-9]+]]:vsfrc = COPY [[COPY5]].sub_64 + ; CHECK-NEXT: STIWX killed [[COPY6]], $zero8, [[COPY1]] + ; CHECK-NEXT: %7:vrrc = nofpexcept XSCVQPUWZ [[COPY2]] + ; CHECK-NEXT: [[COPY7:%[0-9]+]]:vslrc = COPY %7 + ; CHECK-NEXT: [[COPY8:%[0-9]+]]:vsfrc = COPY [[COPY7]].sub_64 + ; CHECK-NEXT: STIWX killed [[COPY8]], $zero8, [[COPY1]] + ; CHECK-NEXT: %9:vrrc = nofpexcept XSCVQPSDZ [[COPY2]] + ; CHECK-NEXT: %10:g8rc = nofpexcept MFVRD killed %9 ; CHECK-NEXT: %11:vrrc = nofpexcept XSCVQPSDZ [[COPY2]] - ; CHECK-NEXT: %12:g8rc = nofpexcept MFVRD killed %11 - ; CHECK-NEXT: STD killed %12, 0, [[COPY]] :: (volatile store (s64) into %ir.addr2) - ; CHECK-NEXT: %13:vrrc = nofpexcept XSCVQPUDZ [[COPY2]] + ; CHECK-NEXT: %44:vslrc = COPY %11 + ; CHECK-NEXT: %12:vfrc = COPY %44.sub_64 + ; CHECK-NEXT: STXSD killed %12, 0, %4 + ; CHECK-NEXT: %13:vrrc = nofpexcept XSCVQPUDZ %2 ; CHECK-NEXT: %14:g8rc = nofpexcept MFVRD killed %13 - ; CHECK-NEXT: STD killed %14, 0, [[COPY]] :: (volatile store (s64) into %ir.addr2) + ; CHECK-NEXT: %15:vrrc = nofpexcept XSCVQPUDZ %2 + ; CHECK-NEXT: %45:vslrc = COPY %15 + ; CHECK-NEXT: %16:vfrc = COPY %45.sub_64 + ; CHECK-NEXT: STXSD killed %16, 0, [[COPY]] ; CHECK-NEXT: [[MFFS:%[0-9]+]]:f8rc = MFFS implicit $rm ; CHECK-NEXT: MTFSB1 31, implicit-def $rm, implicit-def $rm ; CHECK-NEXT: MTFSB0 30, implicit-def $rm, implicit-def $rm - ; CHECK-NEXT: %15:f8rc = nofpexcept FADD [[COPY3]], [[COPY4]], implicit $rm + ; CHECK-NEXT: %17:f8rc = nofpexcept FADD [[COPY3]], [[COPY4]], implicit $rm ; CHECK-NEXT: MTFSFb 1, [[MFFS]], implicit-def $rm - ; CHECK-NEXT: %16:vsfrc = nofpexcept XSCVDPSXWS killed %15, implicit $rm - ; CHECK-NEXT: [[MFVSRWZ2:%[0-9]+]]:gprc = MFVSRWZ killed %16 - ; CHECK-NEXT: STW killed [[MFVSRWZ2]], 0, [[COPY1]] :: (volatile store (s32) into %ir.addr1) + ; CHECK-NEXT: [[MFVSRWZ2:%[0-9]+]]:vsfrc = nofpexcept XSCVDPSXWS killed %17, implicit $rm + ; CHECK-NEXT: STIWX killed [[MFVSRWZ2]], $zero8, [[COPY1]] ; CHECK-NEXT: [[ADDIStocHA8_:%[0-9]+]]:g8rc_and_g8rc_nox0 = ADDIStocHA8 $x2, %const.0 ; CHECK-NEXT: [[DFLOADf32_:%[0-9]+]]:vssrc = DFLOADf32 target-flags(ppc-toc-lo) %const.0, killed [[ADDIStocHA8_]] :: (load (s32) from constant-pool) ; CHECK-NEXT: [[COPY9:%[0-9]+]]:f8rc = COPY [[DFLOADf32_]] @@ -136,14 +139,14 @@ ; CHECK-NEXT: BL8_NOP &__gcc_qsub, csr_ppc64_altivec, implicit-def dead $lr8, implicit $rm, implicit $f1, implicit $f2, implicit $f3, implicit $f4, implicit $x2, implicit-def $r1, implicit-def $f1, implicit-def $f2 ; CHECK-NEXT: ADJCALLSTACKUP 32, 0, implicit-def dead $r1, implicit $r1 ; CHECK-NEXT: [[COPY14:%[0-9]+]]:f8rc = COPY $f1 - ; CHECK-NEXT: [[COPY14:%[0-9]+]]:f8rc = COPY $f2 + ; CHECK-NEXT: [[COPY15:%[0-9]+]]:f8rc = COPY $f2 ; CHECK-NEXT: [[MFFS1:%[0-9]+]]:f8rc = MFFS implicit $rm ; CHECK-NEXT: MTFSB1 31, implicit-def $rm, implicit-def $rm ; CHECK-NEXT: MTFSB0 30, implicit-def $rm, implicit-def $rm - ; CHECK-NEXT: %37:f8rc = nofpexcept FADD [[COPY15]], [[COPY14]], implicit $rm + ; CHECK-NEXT: %38:f8rc = nofpexcept FADD [[COPY15]], [[COPY14]], implicit $rm ; CHECK-NEXT: MTFSFb 1, [[MFFS1]], implicit-def $rm - ; CHECK-NEXT: %38:vsfrc = nofpexcept XSCVDPSXWS killed %37, implicit $rm - ; CHECK-NEXT: [[MFVSRWZ3:%[0-9]+]]:gprc = MFVSRWZ killed %38 + ; CHECK-NEXT: %39:vsfrc = nofpexcept XSCVDPSXWS killed %38, implicit $rm + ; CHECK-NEXT: [[MFVSRWZ3:%[0-9]+]]:gprc = MFVSRWZ killed %39 ; CHECK-NEXT: [[XOR:%[0-9]+]]:gprc = XOR killed [[MFVSRWZ3]], killed [[ISEL]] ; CHECK-NEXT: STW killed [[XOR]], 0, [[COPY1]] :: (volatile store (s32) into %ir.addr1) ; CHECK-NEXT: BLR8 implicit $lr8, implicit $rm