Index: llvm/lib/Target/X86/X86ISelLowering.cpp
===================================================================
--- llvm/lib/Target/X86/X86ISelLowering.cpp
+++ llvm/lib/Target/X86/X86ISelLowering.cpp
@@ -21368,6 +21368,10 @@
   if (VT == MVT::f128 || !Subtarget.hasX87())
     return SDValue();
 
+  // On Windows, the default precision control on x87 is only 53-bit.
+  if (SrcVT == MVT::i64 && Subtarget.isOSWindows())
+    return SDValue();
+
   SDValue ValueToStore = Src;
   if (SrcVT == MVT::i64 && Subtarget.hasSSE2() && !Subtarget.is64Bit())
     // Bitcasting to f64 here allows us to do a single 64-bit store from
@@ -21859,6 +21863,9 @@
       (DstVT == MVT::f32 || DstVT == MVT::f64))
     return SDValue();
 
+  if (!Subtarget.hasX87())
+    return SDValue();
+
   // Make a 64-bit buffer, and use it to build an FILD.
   SDValue StackSlot = DAG.CreateStackTemporary(MVT::i64, 8);
   int SSFI = cast<FrameIndexSDNode>(StackSlot)->getIndex();
@@ -21880,6 +21887,11 @@
   }
 
   assert(SrcVT == MVT::i64 && "Unexpected type in UINT_TO_FP");
+
+  // On Windows, the default precision control on x87 is only 53-bit.
+  if (Subtarget.isOSWindows())
+    return SDValue();
+
   SDValue ValueToStore = Src;
   if (isScalarFPTypeInSSEReg(Op.getValueType()) && !Subtarget.is64Bit()) {
     // Bitcasting to f64 here allows us to do a single 64-bit store from