diff --git a/clang/include/clang/Basic/riscv_vector.td b/clang/include/clang/Basic/riscv_vector.td
--- a/clang/include/clang/Basic/riscv_vector.td
+++ b/clang/include/clang/Basic/riscv_vector.td
@@ -1557,6 +1557,17 @@
 }
 }] in
 def vread_vwrite_csr: RVVHeader;
+let HeaderCode =
+[{
+static __inline__ __attribute__((__always_inline__, __nodebug__))
+unsigned long vlenb() {
+  unsigned long __rv = 0;
+  __asm__ __volatile__ ("csrr\t%0, vlenb" : "=r"(__rv) : : "memory");
+  return __rv;
+}
+}] in
+def vlenb: RVVHeader;
+
 
 // 6. Configuration-Setting Instructions
 // 6.1. vsetvli/vsetvl instructions
diff --git a/clang/test/CodeGen/RISCV/rvv-intrinsics/vlenb.c b/clang/test/CodeGen/RISCV/rvv-intrinsics/vlenb.c
new file mode 100644
--- /dev/null
+++ b/clang/test/CodeGen/RISCV/rvv-intrinsics/vlenb.c
@@ -0,0 +1,15 @@
+// NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py
+// REQUIRES: riscv-registered-target
+// RUN: %clang_cc1 -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm %s -o - \
+// RUN:     | opt -S -O2 | FileCheck  %s
+
+#include <riscv_vector.h>
+
+// CHECK-LABEL: @test_vlenb(
+// CHECK-NEXT:  entry:
+// CHECK-NEXT:    [[TMP0:%.*]] = tail call i64 asm sideeffect "csrr\09$0, vlenb", "=r,~{memory}"() #[[ATTR1:[0-9]+]], !srcloc !4
+// CHECK-NEXT:    ret i64 [[TMP0]]
+//
+unsigned long test_vlenb(void) {
+  return vlenb();
+}