diff --git a/llvm/lib/Target/BPF/BPFInstrInfo.td b/llvm/lib/Target/BPF/BPFInstrInfo.td --- a/llvm/lib/Target/BPF/BPFInstrInfo.td +++ b/llvm/lib/Target/BPF/BPFInstrInfo.td @@ -59,6 +59,7 @@ def BPFHasSdivSmod : Predicate<"Subtarget->hasSdivSmod()">; def BPFNoMovsx : Predicate<"!Subtarget->hasMovsx()">; def BPFNoBswap : Predicate<"!Subtarget->hasBswap()">; +def BPFHasStoreImm : Predicate<"Subtarget->hasStoreImm()">; def brtarget : Operand { let PrintMethod = "printBrTargetOperand"; @@ -73,6 +74,12 @@ [{return isInt<32>(N->getSExtValue()); }]>; def i32immSExt32 : PatLeaf<(i32 imm), [{return isInt<32>(N->getSExtValue()); }]>; +def i64immZExt32 : PatLeaf<(i64 imm), + [{return isUInt<32>(N->getZExtValue()); }]>; + +def imm_to_i64 : SDNodeXFormgetTargetConstant(N->getZExtValue(), SDLoc(N), MVT::i64); +}]>; // Addressing modes. def ADDRri : ComplexPattern; @@ -447,7 +454,7 @@ } class STOREi64 - : STORE; + : STORE; let Predicates = [BPFNoALU32] in { def STW : STOREi64; @@ -456,6 +463,38 @@ } def STD : STOREi64; +class STORE_imm + : TYPE_LD_ST { + bits<20> addr; + bits<32> imm; + + let Inst{51-48} = addr{19-16}; // base reg + let Inst{47-32} = addr{15-0}; // offset + let Inst{31-0} = imm; + let BPFClass = BPF_ST; +} + +let Predicates = [BPFHasStoreImm] in { + def STD_imm : STORE_imm; + def STW_imm : STORE_imm; + def STH_imm : STORE_imm; + def STB_imm : STORE_imm; +} + +let Predicates = [BPFHasALU32, BPFHasStoreImm] in { + def : Pat<(store (i32 imm:$src), ADDRri:$dst), + (STW_imm (imm_to_i64 $src), ADDRri:$dst)>; + def : Pat<(truncstorei16 (i32 imm:$src), ADDRri:$dst), + (STH_imm (imm_to_i64 imm:$src), ADDRri:$dst)>; + def : Pat<(truncstorei8 (i32 imm:$src), ADDRri:$dst), + (STB_imm (imm_to_i64 imm:$src), ADDRri:$dst)>; +} + // LOAD instructions class LOAD Pattern> : TYPE_LD_ST - : STORE32; + : STORE32; let Predicates = [BPFHasALU32], DecoderNamespace = "BPFALU32" in { def STW32 : STOREi32; diff --git a/llvm/lib/Target/BPF/BPFSubtarget.h b/llvm/lib/Target/BPF/BPFSubtarget.h --- a/llvm/lib/Target/BPF/BPFSubtarget.h +++ b/llvm/lib/Target/BPF/BPFSubtarget.h @@ -57,7 +57,7 @@ bool UseDwarfRIS; // whether cpu v4 insns are enabled. - bool HasLdsx, HasMovsx, HasBswap, HasSdivSmod, HasGotol; + bool HasLdsx, HasMovsx, HasBswap, HasSdivSmod, HasGotol, HasStoreImm; public: // This constructor initializes the data members to match that @@ -79,6 +79,7 @@ bool hasBswap() const { return HasBswap; } bool hasSdivSmod() const { return HasSdivSmod; } bool hasGotol() const { return HasGotol; } + bool hasStoreImm() const { return HasStoreImm; } const BPFInstrInfo *getInstrInfo() const override { return &InstrInfo; } const BPFFrameLowering *getFrameLowering() const override { diff --git a/llvm/lib/Target/BPF/BPFSubtarget.cpp b/llvm/lib/Target/BPF/BPFSubtarget.cpp --- a/llvm/lib/Target/BPF/BPFSubtarget.cpp +++ b/llvm/lib/Target/BPF/BPFSubtarget.cpp @@ -33,6 +33,9 @@ cl::init(false), cl::desc("Disable sdiv/smod insns")); static cl::opt Disable_gotol("disable-gotol", cl::Hidden, cl::init(false), cl::desc("Disable gotol insn")); +static cl::opt + Disable_StoreImm("disable-storeimm", cl::Hidden, cl::init(false), + cl::desc("Disable BPF_ST (immediate store) insn")); void BPFSubtarget::anchor() {} @@ -54,6 +57,7 @@ HasBswap = false; HasSdivSmod = false; HasGotol = false; + HasStoreImm = false; } void BPFSubtarget::initSubtargetFeatures(StringRef CPU, StringRef FS) { @@ -80,6 +84,7 @@ HasBswap = !Disable_bswap; HasSdivSmod = !Disable_sdiv_smod; HasGotol = !Disable_gotol; + HasStoreImm = !Disable_StoreImm; return; } } diff --git a/llvm/test/CodeGen/BPF/store_imm.ll b/llvm/test/CodeGen/BPF/store_imm.ll new file mode 100644 --- /dev/null +++ b/llvm/test/CodeGen/BPF/store_imm.ll @@ -0,0 +1,104 @@ +; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py +; RUN: llc < %s -march=bpfel -mcpu=v4 -show-mc-encoding | FileCheck %s + +target triple = "bpf" + +define void @byte(ptr %p0) { +; CHECK-LABEL: byte: +; CHECK: # %bb.0: +; CHECK-NEXT: *(u8 *)(r1 + 0) = 1 # encoding: [0x72,0x01,0x00,0x00,0x01,0x00,0x00,0x00] +; CHECK-NEXT: *(u8 *)(r1 + 1) = 255 # encoding: [0x72,0x01,0x01,0x00,0xff,0x00,0x00,0x00] + %p1 = getelementptr i8, ptr %p0, i32 1 + + store volatile i8 1, ptr %p0, align 1 + store volatile i8 -1, ptr %p1, align 1 + + unreachable +} + +define void @half(ptr, ptr %p0) { +; CHECK-LABEL: half: +; CHECK: # %bb.0: +; CHECK-NEXT: *(u16 *)(r2 + 0) = 1 # encoding: [0x6a,0x02,0x00,0x00,0x01,0x00,0x00,0x00] +; CHECK-NEXT: *(u16 *)(r2 + 2) = 65535 # encoding: [0x6a,0x02,0x02,0x00,0xff,0xff,0x00,0x00] + %p1 = getelementptr i8, ptr %p0, i32 2 + + store volatile i16 1, ptr %p0, align 2 + store volatile i16 -1, ptr %p1, align 2 + + unreachable +} + +define void @word(ptr, ptr, ptr %p0) { +; CHECK-LABEL: word: +; CHECK: # %bb.0: +; CHECK-NEXT: *(u32 *)(r3 + 0) = 1 # encoding: [0x62,0x03,0x00,0x00,0x01,0x00,0x00,0x00] +; CHECK-NEXT: *(u32 *)(r3 + 4) = -1 # encoding: [0x62,0x03,0x04,0x00,0xff,0xff,0xff,0xff] +; CHECK-NEXT: *(u32 *)(r3 + 8) = -2000000000 # encoding: [0x62,0x03,0x08,0x00,0x00,0x6c,0xca,0x88] +; CHECK-NEXT: *(u32 *)(r3 + 12) = -1 # encoding: [0x62,0x03,0x0c,0x00,0xff,0xff,0xff,0xff] +; CHECK-NEXT: *(u32 *)(r3 + 12) = 0 # encoding: [0x62,0x03,0x0c,0x00,0x00,0x00,0x00,0x00] + %p1 = getelementptr i8, ptr %p0, i32 4 + %p2 = getelementptr i8, ptr %p0, i32 8 + %p3 = getelementptr i8, ptr %p0, i32 12 + + store volatile i32 1, ptr %p0, align 4 + store volatile i32 -1, ptr %p1, align 4 + store volatile i32 -2000000000, ptr %p2, align 4 + store volatile i32 4294967295, ptr %p3, align 4 + store volatile i32 4294967296, ptr %p3, align 4 + + unreachable +} + +define void @dword(ptr, ptr, ptr, ptr %p0) { +; CHECK-LABEL: dword: +; CHECK: # %bb.0: +; CHECK-NEXT: *(u64 *)(r4 + 0) = 1 # encoding: [0x7a,0x04,0x00,0x00,0x01,0x00,0x00,0x00] +; CHECK-NEXT: *(u64 *)(r4 + 8) = -1 # encoding: [0x7a,0x04,0x08,0x00,0xff,0xff,0xff,0xff] +; CHECK-NEXT: *(u64 *)(r4 + 16) = 2000000000 # encoding: [0x7a,0x04,0x10,0x00,0x00,0x94,0x35,0x77] +; CHECK-NEXT: *(u64 *)(r4 + 16) = -2000000000 # encoding: [0x7a,0x04,0x10,0x00,0x00,0x6c,0xca,0x88] +; CHECK-NEXT: r1 = 4294967295 ll # encoding: [0x18,0x01,0x00,0x00,0xff,0xff,0xff,0xff,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00] +; CHECK-NEXT: *(u64 *)(r4 + 24) = r1 # encoding: [0x7b,0x14,0x18,0x00,0x00,0x00,0x00,0x00] + %p1 = getelementptr i8, ptr %p0, i32 8 + %p2 = getelementptr i8, ptr %p0, i32 16 + %p3 = getelementptr i8, ptr %p0, i32 24 + + store volatile i64 1, ptr %p0, align 8 + store volatile i64 -1, ptr %p1, align 8 + store volatile i64 2000000000, ptr %p2, align 8 + store volatile i64 -2000000000, ptr %p2, align 8 + store volatile i64 4294967295, ptr %p3, align 8 + + unreachable +} + +define void @unaligned(ptr %p0) { +; CHECK-LABEL: unaligned: +; CHECK: # %bb.0: +; CHECK-NEXT: *(u8 *)(r1 + 1) = 255 # encoding: [0x72,0x01,0x01,0x00,0xff,0x00,0x00,0x00] +; CHECK-NEXT: *(u8 *)(r1 + 0) = 254 # encoding: [0x72,0x01,0x00,0x00,0xfe,0x00,0x00,0x00] +; CHECK-NEXT: *(u16 *)(r1 + 10) = 65535 # encoding: [0x6a,0x01,0x0a,0x00,0xff,0xff,0x00,0x00] +; CHECK-NEXT: *(u16 *)(r1 + 8) = 65534 # encoding: [0x6a,0x01,0x08,0x00,0xfe,0xff,0x00,0x00] +; CHECK-NEXT: *(u32 *)(r1 + 20) = -1 # encoding: [0x62,0x01,0x14,0x00,0xff,0xff,0xff,0xff] +; CHECK-NEXT: *(u32 *)(r1 + 16) = -2 # encoding: [0x62,0x01,0x10,0x00,0xfe,0xff,0xff,0xff] + %p1 = getelementptr i8, ptr %p0, i32 8 + %p2 = getelementptr i8, ptr %p0, i32 16 + + store volatile i16 -2, ptr %p0, align 1 + store volatile i32 -2, ptr %p1, align 2 + store volatile i64 -2, ptr %p2, align 4 + + unreachable +} + +define void @inline_asm(ptr %p0) { +; CHECK-LABEL: inline_asm: +; CHECK: # %bb.0: +; CHECK-NEXT: #APP +; CHECK-NEXT: *(u32 *)(r0 + 42) = 7 # encoding: [0x62,0x00,0x2a,0x00,0x07,0x00,0x00,0x00] +; CHECK-EMPTY: +; CHECK-NEXT: #NO_APP + call void asm "*(u32 *)(r0 + 42) = 7;", "~{r0},~{mem}"() + + unreachable +}