diff --git a/llvm/lib/Target/PowerPC/PPCSubtarget.cpp b/llvm/lib/Target/PowerPC/PPCSubtarget.cpp
--- a/llvm/lib/Target/PowerPC/PPCSubtarget.cpp
+++ b/llvm/lib/Target/PowerPC/PPCSubtarget.cpp
@@ -151,6 +151,8 @@
   // Spilling is generally expensive on all PPC cores, so always enable
   // register-pressure tracking.
   Policy.ShouldTrackPressure = true;
+  if (UseSubRegLiveness)
+    Policy.ShouldTrackLaneMasks = true;
 }
 
 bool PPCSubtarget::useAA() const {
diff --git a/llvm/test/CodeGen/PowerPC/mma-intrinsics.ll b/llvm/test/CodeGen/PowerPC/mma-intrinsics.ll
--- a/llvm/test/CodeGen/PowerPC/mma-intrinsics.ll
+++ b/llvm/test/CodeGen/PowerPC/mma-intrinsics.ll
@@ -11,10 +11,10 @@
 define void @ass_acc(ptr %ptr, <16 x i8> %vc) {
 ; CHECK-LABEL: ass_acc:
 ; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    xxlor vs3, v2, v2
-; CHECK-NEXT:    xxlor vs2, v2, v2
-; CHECK-NEXT:    xxlor vs0, vs2, vs2
-; CHECK-NEXT:    xxlor vs1, vs3, vs3
+; CHECK-NEXT:    xxlor vs1, v2, v2
+; CHECK-NEXT:    xxlor vs0, v2, v2
+; CHECK-NEXT:    xxlor vs2, vs0, vs0
+; CHECK-NEXT:    xxlor vs3, vs1, vs1
 ; CHECK-NEXT:    stxv vs0, 48(r3)
 ; CHECK-NEXT:    stxv vs1, 32(r3)
 ; CHECK-NEXT:    stxv vs2, 16(r3)
@@ -23,10 +23,10 @@
 ;
 ; CHECK-BE-LABEL: ass_acc:
 ; CHECK-BE:       # %bb.0: # %entry
-; CHECK-BE-NEXT:    xxlor vs3, v2, v2
-; CHECK-BE-NEXT:    xxlor vs2, v2, v2
-; CHECK-BE-NEXT:    xxlor vs0, vs2, vs2
-; CHECK-BE-NEXT:    xxlor vs1, vs3, vs3
+; CHECK-BE-NEXT:    xxlor vs1, v2, v2
+; CHECK-BE-NEXT:    xxlor vs0, v2, v2
+; CHECK-BE-NEXT:    xxlor vs2, vs0, vs0
+; CHECK-BE-NEXT:    xxlor vs3, vs1, vs1
 ; CHECK-BE-NEXT:    stxv vs1, 16(r3)
 ; CHECK-BE-NEXT:    stxv vs0, 0(r3)
 ; CHECK-BE-NEXT:    stxv vs3, 48(r3)
@@ -43,10 +43,10 @@
 define void @int_xxmtacc(ptr %ptr, <16 x i8> %vc) {
 ; CHECK-LABEL: int_xxmtacc:
 ; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    xxlor vs3, v2, v2
-; CHECK-NEXT:    xxlor vs2, v2, v2
-; CHECK-NEXT:    xxlor vs0, vs2, vs2
-; CHECK-NEXT:    xxlor vs1, vs3, vs3
+; CHECK-NEXT:    xxlor vs1, v2, v2
+; CHECK-NEXT:    xxlor vs0, v2, v2
+; CHECK-NEXT:    xxlor vs2, vs0, vs0
+; CHECK-NEXT:    xxlor vs3, vs1, vs1
 ; CHECK-NEXT:    xxmtacc acc0
 ; CHECK-NEXT:    stxv vs0, 48(r3)
 ; CHECK-NEXT:    stxv vs1, 32(r3)
@@ -56,10 +56,10 @@
 ;
 ; CHECK-BE-LABEL: int_xxmtacc:
 ; CHECK-BE:       # %bb.0: # %entry
-; CHECK-BE-NEXT:    xxlor vs3, v2, v2
-; CHECK-BE-NEXT:    xxlor vs2, v2, v2
-; CHECK-BE-NEXT:    xxlor vs0, vs2, vs2
-; CHECK-BE-NEXT:    xxlor vs1, vs3, vs3
+; CHECK-BE-NEXT:    xxlor vs1, v2, v2
+; CHECK-BE-NEXT:    xxlor vs0, v2, v2
+; CHECK-BE-NEXT:    xxlor vs2, vs0, vs0
+; CHECK-BE-NEXT:    xxlor vs3, vs1, vs1
 ; CHECK-BE-NEXT:    xxmtacc acc0
 ; CHECK-BE-NEXT:    stxv vs1, 16(r3)
 ; CHECK-BE-NEXT:    stxv vs0, 0(r3)
@@ -80,10 +80,10 @@
 define void @int_xxmfacc(ptr %ptr, <16 x i8> %vc) {
 ; CHECK-LABEL: int_xxmfacc:
 ; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    xxlor vs3, v2, v2
-; CHECK-NEXT:    xxlor vs2, v2, v2
-; CHECK-NEXT:    xxlor vs0, vs2, vs2
-; CHECK-NEXT:    xxlor vs1, vs3, vs3
+; CHECK-NEXT:    xxlor vs1, v2, v2
+; CHECK-NEXT:    xxlor vs0, v2, v2
+; CHECK-NEXT:    xxlor vs2, vs0, vs0
+; CHECK-NEXT:    xxlor vs3, vs1, vs1
 ; CHECK-NEXT:    stxv vs0, 48(r3)
 ; CHECK-NEXT:    stxv vs1, 32(r3)
 ; CHECK-NEXT:    stxv vs2, 16(r3)
@@ -92,10 +92,10 @@
 ;
 ; CHECK-BE-LABEL: int_xxmfacc:
 ; CHECK-BE:       # %bb.0: # %entry
-; CHECK-BE-NEXT:    xxlor vs3, v2, v2
-; CHECK-BE-NEXT:    xxlor vs2, v2, v2
-; CHECK-BE-NEXT:    xxlor vs0, vs2, vs2
-; CHECK-BE-NEXT:    xxlor vs1, vs3, vs3
+; CHECK-BE-NEXT:    xxlor vs1, v2, v2
+; CHECK-BE-NEXT:    xxlor vs0, v2, v2
+; CHECK-BE-NEXT:    xxlor vs2, vs0, vs0
+; CHECK-BE-NEXT:    xxlor vs3, vs1, vs1
 ; CHECK-BE-NEXT:    stxv vs1, 16(r3)
 ; CHECK-BE-NEXT:    stxv vs0, 0(r3)
 ; CHECK-BE-NEXT:    stxv vs3, 48(r3)
diff --git a/llvm/test/CodeGen/PowerPC/mma-outer-product.ll b/llvm/test/CodeGen/PowerPC/mma-outer-product.ll
--- a/llvm/test/CodeGen/PowerPC/mma-outer-product.ll
+++ b/llvm/test/CodeGen/PowerPC/mma-outer-product.ll
@@ -78,13 +78,13 @@
 ; CHECK-NEXT:    xxlor vs1, v3, v3
 ; CHECK-NEXT:    xxlor vs2, v4, v4
 ; CHECK-NEXT:    xxlor vs3, v5, v5
-; CHECK-NEXT:    vmr v1, v2
-; CHECK-NEXT:    vmr v0, v5
 ; CHECK-NEXT:    xxmtacc acc0
 ; CHECK-NEXT:    xvi8ger4pp acc0, v2, v3
 ; CHECK-NEXT:    xvf16ger2pn acc0, v2, v4
+; CHECK-NEXT:    vmr v4, v5
 ; CHECK-NEXT:    pmxvf32gernn acc0, v3, v5, 0, 0
-; CHECK-NEXT:    pmxvf64gernn acc0, vsp32, v2, 0, 0
+; CHECK-NEXT:    vmr v5, v2
+; CHECK-NEXT:    pmxvf64gernn acc0, vsp36, v2, 0, 0
 ; CHECK-NEXT:    xxmfacc acc0
 ; CHECK-NEXT:    stxv vs3, 0(r3)
 ; CHECK-NEXT:    stxv vs2, 0(r4)
@@ -102,13 +102,13 @@
 ; CHECK-BE-NEXT:    xxlor vs1, v3, v3
 ; CHECK-BE-NEXT:    xxlor vs2, v4, v4
 ; CHECK-BE-NEXT:    xxlor vs3, v5, v5
-; CHECK-BE-NEXT:    vmr v1, v2
-; CHECK-BE-NEXT:    vmr v0, v5
 ; CHECK-BE-NEXT:    xxmtacc acc0
 ; CHECK-BE-NEXT:    xvi8ger4pp acc0, v2, v3
 ; CHECK-BE-NEXT:    xvf16ger2pn acc0, v2, v4
+; CHECK-BE-NEXT:    vmr v4, v5
 ; CHECK-BE-NEXT:    pmxvf32gernn acc0, v3, v5, 0, 0
-; CHECK-BE-NEXT:    pmxvf64gernn acc0, vsp32, v2, 0, 0
+; CHECK-BE-NEXT:    vmr v5, v2
+; CHECK-BE-NEXT:    pmxvf64gernn acc0, vsp36, v2, 0, 0
 ; CHECK-BE-NEXT:    xxmfacc acc0
 ; CHECK-BE-NEXT:    stxv vs0, 0(r3)
 ; CHECK-BE-NEXT:    stxv vs1, 0(r4)
diff --git a/llvm/test/CodeGen/PowerPC/mmaplus-acc-spill.ll b/llvm/test/CodeGen/PowerPC/mmaplus-acc-spill.ll
--- a/llvm/test/CodeGen/PowerPC/mmaplus-acc-spill.ll
+++ b/llvm/test/CodeGen/PowerPC/mmaplus-acc-spill.ll
@@ -30,8 +30,8 @@
 ; CHECK-NEXT:    stxv v30, 128(r1) # 16-byte Folded Spill
 ; CHECK-NEXT:    stxv v31, 144(r1) # 16-byte Folded Spill
 ; CHECK-NEXT:    vmr v31, v5
-; CHECK-NEXT:    vmr v29, v3
 ; CHECK-NEXT:    vmr v30, v4
+; CHECK-NEXT:    vmr v29, v3
 ; CHECK-NEXT:    vmr v28, v2
 ; CHECK-NEXT:    std r30, 160(r1) # 8-byte Folded Spill
 ; CHECK-NEXT:    ld r30, 272(r1)
@@ -77,8 +77,8 @@
 ; CHECK-BE-NEXT:    stxv v30, 208(r1) # 16-byte Folded Spill
 ; CHECK-BE-NEXT:    stxv v31, 224(r1) # 16-byte Folded Spill
 ; CHECK-BE-NEXT:    vmr v31, v5
-; CHECK-BE-NEXT:    vmr v29, v3
 ; CHECK-BE-NEXT:    vmr v30, v4
+; CHECK-BE-NEXT:    vmr v29, v3
 ; CHECK-BE-NEXT:    vmr v28, v2
 ; CHECK-BE-NEXT:    std r30, 240(r1) # 8-byte Folded Spill
 ; CHECK-BE-NEXT:    ld r30, 368(r1)
diff --git a/llvm/test/CodeGen/PowerPC/ppc64-acc-regalloc.ll b/llvm/test/CodeGen/PowerPC/ppc64-acc-regalloc.ll
--- a/llvm/test/CodeGen/PowerPC/ppc64-acc-regalloc.ll
+++ b/llvm/test/CodeGen/PowerPC/ppc64-acc-regalloc.ll
@@ -29,34 +29,34 @@
 ; CHECK-NEXT:  .LBB0_1: # %bb9
 ; CHECK-NEXT:    #
 ; CHECK-NEXT:    addi r6, r6, 2
-; CHECK-NEXT:    lxv vs0, 16(0)
 ; CHECK-NEXT:    lxv vs1, -64(r5)
+; CHECK-NEXT:    lxv vs0, 16(0)
 ; CHECK-NEXT:    xxlxor vs7, vs7, vs7
 ; CHECK-NEXT:    xxlor vs3, v0, v0
 ; CHECK-NEXT:    xxlxor vs2, vs2, vs2
 ; CHECK-NEXT:    xxlxor vs12, vs12, vs12
-; CHECK-NEXT:    mulld r6, r6, r3
+; CHECK-NEXT:    lxv vs4, -16(r5)
 ; CHECK-NEXT:    xxlor vs10, v2, v2
-; CHECK-NEXT:    xxlor vs4, v2, v2
 ; CHECK-NEXT:    xxlor vs8, vs10, vs10
 ; CHECK-NEXT:    xxlor vs10, v1, v1
+; CHECK-NEXT:    mulld r6, r6, r3
 ; CHECK-NEXT:    xvmaddadp vs7, vs0, v5
 ; CHECK-NEXT:    xvmuldp vs6, vs0, v2
-; CHECK-NEXT:    lxv vs0, -16(r5)
 ; CHECK-NEXT:    xvmaddadp vs3, vs1, v2
 ; CHECK-NEXT:    xvmaddadp vs2, vs1, vs2
+; CHECK-NEXT:    xvmaddadp vs12, vs4, vs12
+; CHECK-NEXT:    xxlor vs0, v2, v2
 ; CHECK-NEXT:    lxvdsx v6, r6, r4
 ; CHECK-NEXT:    li r6, 0
 ; CHECK-NEXT:    xvmaddadp vs7, v2, v2
 ; CHECK-NEXT:    xvmaddadp vs6, v2, v2
-; CHECK-NEXT:    xvmaddadp vs12, vs0, vs12
+; CHECK-NEXT:    xxlor vs14, vs12, vs12
+; CHECK-NEXT:    xxlor vs12, v2, v2
 ; CHECK-NEXT:    xvmuldp v3, vs1, v6
 ; CHECK-NEXT:    xvmuldp vs11, v4, v6
-; CHECK-NEXT:    xvmuldp vs13, vs0, v6
+; CHECK-NEXT:    xvmuldp vs13, vs4, v6
 ; CHECK-NEXT:    xvmuldp vs5, v6, v2
-; CHECK-NEXT:    xxlor vs0, v2, v2
-; CHECK-NEXT:    xxlor vs14, vs12, vs12
-; CHECK-NEXT:    xxlor vs12, v2, v2
+; CHECK-NEXT:    xxlor vs4, v2, v2
 ; CHECK-NEXT:    xxlor vs1, v3, v3
 ; CHECK-NEXT:    xxlor vs9, vs11, vs11
 ; CHECK-NEXT:    xxlor vs15, vs13, vs13
@@ -121,34 +121,34 @@
 ; TRACKLIVE-NEXT:  .LBB0_1: # %bb9
 ; TRACKLIVE-NEXT:    #
 ; TRACKLIVE-NEXT:    addi r6, r6, 2
-; TRACKLIVE-NEXT:    lxv vs0, 16(0)
 ; TRACKLIVE-NEXT:    lxv vs1, -64(r5)
+; TRACKLIVE-NEXT:    lxv vs0, 16(0)
 ; TRACKLIVE-NEXT:    xxlxor vs7, vs7, vs7
 ; TRACKLIVE-NEXT:    xxlor vs3, v0, v0
 ; TRACKLIVE-NEXT:    xxlxor vs2, vs2, vs2
 ; TRACKLIVE-NEXT:    xxlxor vs12, vs12, vs12
-; TRACKLIVE-NEXT:    mulld r6, r6, r3
+; TRACKLIVE-NEXT:    lxv vs4, -16(r5)
 ; TRACKLIVE-NEXT:    xxlor vs10, v2, v2
-; TRACKLIVE-NEXT:    xxlor vs4, v2, v2
 ; TRACKLIVE-NEXT:    xxlor vs8, vs10, vs10
 ; TRACKLIVE-NEXT:    xxlor vs10, v1, v1
+; TRACKLIVE-NEXT:    mulld r6, r6, r3
 ; TRACKLIVE-NEXT:    xvmaddadp vs7, vs0, v5
 ; TRACKLIVE-NEXT:    xvmuldp vs6, vs0, v2
-; TRACKLIVE-NEXT:    lxv vs0, -16(r5)
 ; TRACKLIVE-NEXT:    xvmaddadp vs3, vs1, v2
 ; TRACKLIVE-NEXT:    xvmaddadp vs2, vs1, vs2
+; TRACKLIVE-NEXT:    xvmaddadp vs12, vs4, vs12
+; TRACKLIVE-NEXT:    xxlor vs0, v2, v2
 ; TRACKLIVE-NEXT:    lxvdsx v6, r6, r4
 ; TRACKLIVE-NEXT:    li r6, 0
 ; TRACKLIVE-NEXT:    xvmaddadp vs7, v2, v2
 ; TRACKLIVE-NEXT:    xvmaddadp vs6, v2, v2
-; TRACKLIVE-NEXT:    xvmaddadp vs12, vs0, vs12
+; TRACKLIVE-NEXT:    xxlor vs14, vs12, vs12
+; TRACKLIVE-NEXT:    xxlor vs12, v2, v2
 ; TRACKLIVE-NEXT:    xvmuldp v3, vs1, v6
 ; TRACKLIVE-NEXT:    xvmuldp vs11, v4, v6
-; TRACKLIVE-NEXT:    xvmuldp vs13, vs0, v6
+; TRACKLIVE-NEXT:    xvmuldp vs13, vs4, v6
 ; TRACKLIVE-NEXT:    xvmuldp vs5, v6, v2
-; TRACKLIVE-NEXT:    xxlor vs0, v2, v2
-; TRACKLIVE-NEXT:    xxlor vs14, vs12, vs12
-; TRACKLIVE-NEXT:    xxlor vs12, v2, v2
+; TRACKLIVE-NEXT:    xxlor vs4, v2, v2
 ; TRACKLIVE-NEXT:    xxlor vs1, v3, v3
 ; TRACKLIVE-NEXT:    xxlor vs9, vs11, vs11
 ; TRACKLIVE-NEXT:    xxlor vs15, vs13, vs13