Index: lib/Target/Mips/MicroMipsDSPInstrInfo.td
===================================================================
--- lib/Target/Mips/MicroMipsDSPInstrInfo.td
+++ lib/Target/Mips/MicroMipsDSPInstrInfo.td
@@ -55,6 +55,14 @@
 class SHLL_S_W_MM_ENC : POOL32A_2RSA5B0_FMT<"shll_s.w", 0b1111110101>;
 class SHRA_QB_MMR2_ENC : POOL32A_2RSA3_FMT<"shra.qb", 0b0000111>;
 class SHRA_R_QB_MMR2_ENC : POOL32A_2RSA3_FMT<"shra_r.qb", 0b1000111>;
+class DPS_W_PH_MMR2_ENC : POOL32A_2RAC_FMT<"dps.w.ph", 0b00010010>;
+class DPSQ_S_W_PH_MM_ENC : POOL32A_2RAC_FMT<"dpsq_s.w.ph", 0b00011010>;
+class DPSQ_SA_L_W_MM_ENC : POOL32A_2RAC_FMT<"dpsq_sa.l.w", 0b01011010>;
+class DPSQX_S_W_PH_MMR2_ENC : POOL32A_2RAC_FMT<"dpsqx_s.w.ph", 0b10011010>;
+class DPSQX_SA_W_PH_MMR2_ENC : POOL32A_2RAC_FMT<"dpsqx_sa.w.ph", 0b11011010>;
+class DPSU_H_QBL_MM_ENC : POOL32A_2RAC_FMT<"dpsu.h.qbl", 0b10010010>;
+class DPSU_H_QBR_MM_ENC : POOL32A_2RAC_FMT<"dpsu.h.qbr", 0b11010010>;
+class DPSX_W_PH_MMR2_ENC : POOL32A_2RAC_FMT<"dpsx.w.ph", 0b01010010>;
 
 // Instruction desc.
 class ABSQ_S_PH_MM_R2_DESC_BASE<string opstr, SDPatternOperator OpNode,
@@ -148,6 +156,10 @@
 def SHLLV_QB_MM : DspMMRel, SHLLV_QB_MM_ENC, SHLLV_QB_MM_DESC;
 def SHLLV_S_W_MM : DspMMRel, SHLLV_S_W_MM_ENC, SHLLV_S_W_MM_DESC;
 def SHLL_S_W_MM : DspMMRel, SHLL_S_W_MM_ENC, SHLL_S_W_MM_DESC;
+def DPSQ_S_W_PH_MM : DspMMRel, DPSQ_S_W_PH_MM_ENC, DPSQ_S_W_PH_DESC;
+def DPSQ_SA_L_W_MM : DspMMRel, DPSQ_SA_L_W_MM_ENC, DPSQ_SA_L_W_DESC;
+def DPSU_H_QBL_MM : DspMMRel, DPSU_H_QBL_MM_ENC, DPSU_H_QBL_DESC;
+def DPSU_H_QBR_MM : DspMMRel, DPSU_H_QBR_MM_ENC, DPSU_H_QBR_DESC;
 // microMIPS DSP Rev 2
 def ABSQ_S_QB_MMR2 : DspMMRel, ABSQ_S_QB_MMR2_ENC, ABSQ_S_QB_MMR2_DESC,
                      ISA_DSPR2;
@@ -168,3 +180,9 @@
 def SHRA_QB_MMR2 : DspMMRel, SHRA_QB_MMR2_ENC, SHRA_QB_MMR2_DESC, ISA_DSPR2;
 def SHRA_R_QB_MMR2 : DspMMRel, SHRA_R_QB_MMR2_ENC, SHRA_R_QB_MMR2_DESC,
                      ISA_DSPR2;
+def DPS_W_PH_MMR2 : DspMMRel, DPS_W_PH_MMR2_ENC, DPS_W_PH_DESC, ISA_DSPR2;
+def DPSQX_S_W_PH_MMR2 : DspMMRel, DPSQX_S_W_PH_MMR2_ENC, DPSQX_S_W_PH_DESC,
+                        ISA_DSPR2;
+def DPSQX_SA_W_PH_MMR2 : DspMMRel, DPSQX_SA_W_PH_MMR2_ENC, DPSQX_SA_W_PH_DESC,
+                         ISA_DSPR2;
+def DPSX_W_PH_MMR2 : DspMMRel, DPSX_W_PH_MMR2_ENC, DPSX_W_PH_DESC, ISA_DSPR2;
Index: lib/Target/Mips/MipsDSPInstrInfo.td
===================================================================
--- lib/Target/Mips/MipsDSPInstrInfo.td
+++ lib/Target/Mips/MipsDSPInstrInfo.td
@@ -1144,12 +1144,12 @@
 def MTLO_DSP : MTLO_ENC, MTLO_DESC;
 def DPAU_H_QBL : DspMMRel, DPAU_H_QBL_ENC, DPAU_H_QBL_DESC;
 def DPAU_H_QBR : DspMMRel, DPAU_H_QBR_ENC, DPAU_H_QBR_DESC;
-def DPSU_H_QBL : DPSU_H_QBL_ENC, DPSU_H_QBL_DESC;
-def DPSU_H_QBR : DPSU_H_QBR_ENC, DPSU_H_QBR_DESC;
+def DPSU_H_QBL : DspMMRel, DPSU_H_QBL_ENC, DPSU_H_QBL_DESC;
+def DPSU_H_QBR : DspMMRel, DPSU_H_QBR_ENC, DPSU_H_QBR_DESC;
 def DPAQ_S_W_PH : DspMMRel, DPAQ_S_W_PH_ENC, DPAQ_S_W_PH_DESC;
-def DPSQ_S_W_PH : DPSQ_S_W_PH_ENC, DPSQ_S_W_PH_DESC;
+def DPSQ_S_W_PH : DspMMRel, DPSQ_S_W_PH_ENC, DPSQ_S_W_PH_DESC;
 def DPAQ_SA_L_W : DspMMRel, DPAQ_SA_L_W_ENC, DPAQ_SA_L_W_DESC;
-def DPSQ_SA_L_W : DPSQ_SA_L_W_ENC, DPSQ_SA_L_W_DESC;
+def DPSQ_SA_L_W : DspMMRel, DPSQ_SA_L_W_ENC, DPSQ_SA_L_W_DESC;
 def MULT_DSP : DspMMRel, MULT_DSP_ENC, MULT_DSP_DESC;
 def MULTU_DSP : DspMMRel, MULTU_DSP_ENC, MULTU_DSP_DESC;
 def MADD_DSP : DspMMRel, MADD_DSP_ENC, MADD_DSP_DESC;
@@ -1225,13 +1225,13 @@
 def MULQ_RS_W : MULQ_RS_W_ENC, MULQ_RS_W_DESC;
 def MULQ_S_PH : MULQ_S_PH_ENC, MULQ_S_PH_DESC;
 def DPA_W_PH : DspMMRel, DPA_W_PH_ENC, DPA_W_PH_DESC;
-def DPS_W_PH : DPS_W_PH_ENC, DPS_W_PH_DESC;
+def DPS_W_PH : DspMMRel, DPS_W_PH_ENC, DPS_W_PH_DESC;
 def DPAQX_S_W_PH : DspMMRel, DPAQX_S_W_PH_ENC, DPAQX_S_W_PH_DESC;
 def DPAQX_SA_W_PH : DspMMRel, DPAQX_SA_W_PH_ENC, DPAQX_SA_W_PH_DESC;
 def DPAX_W_PH : DspMMRel, DPAX_W_PH_ENC, DPAX_W_PH_DESC;
-def DPSX_W_PH : DPSX_W_PH_ENC, DPSX_W_PH_DESC;
-def DPSQX_S_W_PH : DPSQX_S_W_PH_ENC, DPSQX_S_W_PH_DESC;
-def DPSQX_SA_W_PH : DPSQX_SA_W_PH_ENC, DPSQX_SA_W_PH_DESC;
+def DPSX_W_PH : DspMMRel, DPSX_W_PH_ENC, DPSX_W_PH_DESC;
+def DPSQX_S_W_PH : DspMMRel, DPSQX_S_W_PH_ENC, DPSQX_S_W_PH_DESC;
+def DPSQX_SA_W_PH : DspMMRel, DPSQX_SA_W_PH_ENC, DPSQX_SA_W_PH_DESC;
 def MULSA_W_PH : MULSA_W_PH_ENC, MULSA_W_PH_DESC;
 def PRECR_QB_PH : PRECR_QB_PH_ENC, PRECR_QB_PH_DESC;
 def PRECR_SRA_PH_W : PRECR_SRA_PH_W_ENC, PRECR_SRA_PH_W_DESC;
Index: test/MC/Disassembler/Mips/micromips-dsp/valid.txt
===================================================================
--- test/MC/Disassembler/Mips/micromips-dsp/valid.txt
+++ test/MC/Disassembler/Mips/micromips-dsp/valid.txt
@@ -28,3 +28,7 @@
 0x00 0x85 0x1b 0x95 # CHECK: shllv.qb $3, $4, $5
 0x00 0x85 0x1b 0xd5 # CHECK: shllv_s.w $3, $4, $5
 0x00 0x64 0x2b 0xf5 # CHECK: shll_s.w $3, $4, 5
+0x00 0xc4 0x46 0xbc # CHECK: dpsq_s.w.ph $ac1, $4, $6
+0x00 0xc4 0x56 0xbc # CHECK: dpsq_sa.l.w $ac1, $4, $6
+0x00 0xc4 0x64 0xbc # CHECK: dpsu.h.qbl $ac1, $4, $6
+0x00 0xc4 0x74 0xbc # CHECK: dpsu.h.qbr $ac1, $4, $6
Index: test/MC/Disassembler/Mips/micromips-dspr2/valid.txt
===================================================================
--- test/MC/Disassembler/Mips/micromips-dspr2/valid.txt
+++ test/MC/Disassembler/Mips/micromips-dspr2/valid.txt
@@ -15,3 +15,7 @@
 0x00 0x22 0xd0 0xbc # CHECK: dpax.w.ph $ac3, $2, $1
 0x00 0x64 0xa1 0xfc # CHECK: shra.qb $3, $4, 5
 0x00 0x64 0xb1 0xfc # CHECK: shra_r.qb $3, $4, 5
+0x00 0xc4 0x44 0xbc # CHECK: dps.w.ph $ac1, $4, $6
+0x00 0xc4 0x66 0xbc # CHECK: dpsqx_s.w.ph $ac1, $4, $6
+0x00 0xc4 0x76 0xbc # CHECK: dpsqx_sa.w.ph $ac1, $4, $6
+0x00 0xc4 0x54 0xbc # CHECK: dpsx.w.ph $ac1, $4, $6
Index: test/MC/Mips/micromips-dsp/valid.s
===================================================================
--- test/MC/Mips/micromips-dsp/valid.s
+++ test/MC/Mips/micromips-dsp/valid.s
@@ -29,3 +29,7 @@
   shllv.qb $3, $4, $5          # CHECK: shllv.qb $3, $4, $5     # encoding: [0x00,0x85,0x1b,0x95]
   shllv_s.w $3, $4, $5         # CHECK: shllv_s.w $3, $4, $5    # encoding: [0x00,0x85,0x1b,0xd5]
   shll_s.w $3, $4, 5           # CHECK: shll_s.w $3, $4, 5      # encoding: [0x00,0x64,0x2b,0xf5]
+  dpsq_s.w.ph $ac1, $4, $6     # CHECK: dpsq_s.w.ph $ac1, $4, $6   # encoding: [0x00,0xc4,0x46,0xbc]
+  dpsq_sa.l.w $ac1, $4, $6     # CHECK: dpsq_sa.l.w $ac1, $4, $6   # encoding: [0x00,0xc4,0x56,0xbc]
+  dpsu.h.qbl $ac1, $4, $6      # CHECK: dpsu.h.qbl $ac1, $4, $6    # encoding: [0x00,0xc4,0x64,0xbc]
+  dpsu.h.qbr $ac1, $4, $6      # CHECK: dpsu.h.qbr $ac1, $4, $6    # encoding: [0x00,0xc4,0x74,0xbc]
Index: test/MC/Mips/micromips-dspr2/valid.s
===================================================================
--- test/MC/Mips/micromips-dspr2/valid.s
+++ test/MC/Mips/micromips-dspr2/valid.s
@@ -16,3 +16,7 @@
   dpax.w.ph $ac3, $2, $1       # CHECK: dpax.w.ph $ac3, $2, $1     # encoding: [0x00,0x22,0xd0,0xbc]
   shra.qb $3, $4, 5            # CHECK: shra.qb $3, $4, 5       # encoding: [0x00,0x64,0xa1,0xfc]
   shra_r.qb $3, $4, 5          # CHECK: shra_r.qb $3, $4, 5     # encoding: [0x00,0x64,0xb1,0xfc]
+  dps.w.ph $ac1, $4, $6        # CHECK: dps.w.ph $ac1, $4, $6      # encoding: [0x00,0xc4,0x44,0xbc]
+  dpsqx_s.w.ph $ac1, $4, $6    # CHECK: dpsqx_s.w.ph $ac1, $4, $6  # encoding: [0x00,0xc4,0x66,0xbc]
+  dpsqx_sa.w.ph $ac1, $4, $6   # CHECK: dpsqx_sa.w.ph $ac1, $4, $6 # encoding: [0x00,0xc4,0x76,0xbc]
+  dpsx.w.ph $ac1, $4, $6       # CHECK: dpsx.w.ph $ac1, $4, $6     # encoding: [0x00,0xc4,0x54,0xbc]