diff --git a/llvm/lib/Target/AMDGPU/VOP3Instructions.td b/llvm/lib/Target/AMDGPU/VOP3Instructions.td
--- a/llvm/lib/Target/AMDGPU/VOP3Instructions.td
+++ b/llvm/lib/Target/AMDGPU/VOP3Instructions.td
@@ -681,31 +681,6 @@
         SCSrc_b32:$src1, 0, SCSrc_b32:$src2, VGPR_32:$vdst_in)
 >;
 
-// Permlane intrinsic that has either fetch invalid or bound control
-// fields enabled.
-class BoundControlOrFetchInvalidPermlane<SDPatternOperator permlane> :
-  PatFrag<(ops node:$vdst_in, node:$src0, node:$src1, node:$src2,
-               node:$fi, node:$bc),
-          (permlane node:$vdst_in, node:$src0, node:
-                    $src1, node:$src2, node:$fi, node:$bc)> {
-  let PredicateCode = [{ return N->getConstantOperandVal(5) != 0 ||
-                                N->getConstantOperandVal(6) != 0; }];
-  let GISelPredicateCode = [{
-    return MI.getOperand(6).getImm() != 0 ||
-           MI.getOperand(7).getImm() != 0;
-  }];
-}
-
-// Drop the input value if it won't be read.
-class PermlaneDiscardVDstIn<SDPatternOperator permlane,
-                            Instruction inst> : GCNPat<
-  (permlane srcvalue, i32:$src0, i32:$src1, i32:$src2,
-            timm:$fi, timm:$bc),
-  (inst (as_i1timm $fi), VGPR_32:$src0, (as_i1timm $bc),
-        SCSrc_b32:$src1, 0, SCSrc_b32:$src2,
-        (IMPLICIT_DEF))
->;
-
 
 let SubtargetPredicate = isGFX10Plus in {
   let isCommutable = 1, isReMaterializable = 1 in {
@@ -721,13 +696,6 @@
   def : PermlanePat<int_amdgcn_permlane16, V_PERMLANE16_B32_e64>;
   def : PermlanePat<int_amdgcn_permlanex16, V_PERMLANEX16_B32_e64>;
 
-  def : PermlaneDiscardVDstIn<
-    BoundControlOrFetchInvalidPermlane<int_amdgcn_permlane16>,
-    V_PERMLANE16_B32_e64>;
-  def : PermlaneDiscardVDstIn<
-    BoundControlOrFetchInvalidPermlane<int_amdgcn_permlanex16>,
-    V_PERMLANEX16_B32_e64>;
-
   defm V_ADD_NC_U16 : VOP3Inst <"v_add_nc_u16", VOP3_Profile<VOP_I16_I16_I16, VOP3_OPSEL>, add>;
   defm V_SUB_NC_U16 : VOP3Inst <"v_sub_nc_u16", VOP3_Profile<VOP_I16_I16_I16, VOP3_OPSEL>, sub>;
 
diff --git a/llvm/test/CodeGen/AMDGPU/llvm.amdgcn.permlane.ll b/llvm/test/CodeGen/AMDGPU/llvm.amdgcn.permlane.ll
--- a/llvm/test/CodeGen/AMDGPU/llvm.amdgcn.permlane.ll
+++ b/llvm/test/CodeGen/AMDGPU/llvm.amdgcn.permlane.ll
@@ -850,7 +850,7 @@
 ; GFX11-NEXT:    s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
 ; GFX11-NEXT:    s_endpgm
   %tidx = call i32 @llvm.amdgcn.workitem.id.x()
-  %v = call i32 @llvm.amdgcn.permlane16(i32 12345, i32 %tidx, i32 %src1, i32 %src2, i1 1, i1 0)
+  %v = call i32 @llvm.amdgcn.permlane16(i32 undef, i32 %tidx, i32 %src1, i32 %src2, i1 1, i1 0)
   store i32 %v, ptr addrspace(1) %out
   ret void
 }
@@ -879,7 +879,7 @@
 ; GFX11-NEXT:    s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
 ; GFX11-NEXT:    s_endpgm
   %tidx = call i32 @llvm.amdgcn.workitem.id.x()
-  %v = call i32 @llvm.amdgcn.permlane16(i32 12345, i32 %tidx, i32 %src1, i32 %src2, i1 0, i1 1)
+  %v = call i32 @llvm.amdgcn.permlane16(i32 undef, i32 %tidx, i32 %src1, i32 %src2, i1 0, i1 1)
   store i32 %v, ptr addrspace(1) %out
   ret void
 }
@@ -908,7 +908,7 @@
 ; GFX11-NEXT:    s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
 ; GFX11-NEXT:    s_endpgm
   %tidx = call i32 @llvm.amdgcn.workitem.id.x()
-  %v = call i32 @llvm.amdgcn.permlane16(i32 12345, i32 %tidx, i32 %src1, i32 %src2, i1 1, i1 1)
+  %v = call i32 @llvm.amdgcn.permlane16(i32 undef, i32 %tidx, i32 %src1, i32 %src2, i1 1, i1 1)
   store i32 %v, ptr addrspace(1) %out
   ret void
 }
@@ -1052,7 +1052,7 @@
 ; GFX11-NEXT:    s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
 ; GFX11-NEXT:    s_endpgm
   %tidx = call i32 @llvm.amdgcn.workitem.id.x()
-  %v = call i32 @llvm.amdgcn.permlanex16(i32 12345, i32 %tidx, i32 %src1, i32 %src2, i1 1, i1 0)
+  %v = call i32 @llvm.amdgcn.permlanex16(i32 undef, i32 %tidx, i32 %src1, i32 %src2, i1 1, i1 0)
   store i32 %v, ptr addrspace(1) %out
   ret void
 }
@@ -1081,7 +1081,7 @@
 ; GFX11-NEXT:    s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
 ; GFX11-NEXT:    s_endpgm
   %tidx = call i32 @llvm.amdgcn.workitem.id.x()
-  %v = call i32 @llvm.amdgcn.permlanex16(i32 12345, i32 %tidx, i32 %src1, i32 %src2, i1 0, i1 1)
+  %v = call i32 @llvm.amdgcn.permlanex16(i32 undef, i32 %tidx, i32 %src1, i32 %src2, i1 0, i1 1)
   store i32 %v, ptr addrspace(1) %out
   ret void
 }
@@ -1110,7 +1110,7 @@
 ; GFX11-NEXT:    s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
 ; GFX11-NEXT:    s_endpgm
   %tidx = call i32 @llvm.amdgcn.workitem.id.x()
-  %v = call i32 @llvm.amdgcn.permlanex16(i32 12345, i32 %tidx, i32 %src1, i32 %src2, i1 1, i1 1)
+  %v = call i32 @llvm.amdgcn.permlanex16(i32 undef, i32 %tidx, i32 %src1, i32 %src2, i1 1, i1 1)
   store i32 %v, ptr addrspace(1) %out
   ret void
 }