diff --git a/llvm/lib/CodeGen/TailDuplicator.cpp b/llvm/lib/CodeGen/TailDuplicator.cpp --- a/llvm/lib/CodeGen/TailDuplicator.cpp +++ b/llvm/lib/CodeGen/TailDuplicator.cpp @@ -436,16 +436,13 @@ MO.setReg(VI->second.Reg); // We have Reg -> VI.Reg:VI.SubReg, so if Reg is used with a // sub-register, we need to compose the sub-register indices. - MO.setSubReg(TRI->composeSubRegIndices(MO.getSubReg(), - VI->second.SubReg)); + MO.setSubReg( + TRI->composeSubRegIndices(VI->second.SubReg, MO.getSubReg())); } else { // The direct replacement is not possible, due to failing register // class constraints. An explicit COPY is necessary. Create one - // that can be reused - auto *NewRC = MI->getRegClassConstraint(i, TII, TRI); - if (NewRC == nullptr) - NewRC = OrigRC; - Register NewReg = MRI->createVirtualRegister(NewRC); + // that can be reused. + Register NewReg = MRI->createVirtualRegister(OrigRC); BuildMI(*PredBB, NewMI, NewMI.getDebugLoc(), TII->get(TargetOpcode::COPY), NewReg) .addReg(VI->second.Reg, 0, VI->second.SubReg); diff --git a/llvm/test/CodeGen/AArch64/taildup-subreg-compose.mir b/llvm/test/CodeGen/AArch64/taildup-subreg-compose.mir --- a/llvm/test/CodeGen/AArch64/taildup-subreg-compose.mir +++ b/llvm/test/CodeGen/AArch64/taildup-subreg-compose.mir @@ -23,7 +23,7 @@ ; CHECK-NEXT: liveins: $q1 ; CHECK-NEXT: {{ $}} ; CHECK-NEXT: [[COPY:%[0-9]+]]:fpr128 = COPY $q1 - ; CHECK-NEXT: $s1 = COPY [[COPY]].dsub + ; CHECK-NEXT: $s1 = COPY [[COPY]].ssub ; CHECK-NEXT: [[COPY1:%[0-9]+]]:fpr64 = COPY [[COPY]].dsub ; CHECK-NEXT: B %bb.4 ; CHECK-NEXT: {{ $}} @@ -31,7 +31,7 @@ ; CHECK-NEXT: successors: %bb.4(0x80000000) ; CHECK-NEXT: {{ $}} ; CHECK-NEXT: [[DEF:%[0-9]+]]:fpr128 = IMPLICIT_DEF - ; CHECK-NEXT: $s1 = COPY [[DEF]].dsub + ; CHECK-NEXT: $s1 = COPY [[DEF]].ssub ; CHECK-NEXT: [[COPY2:%[0-9]+]]:fpr64 = COPY [[DEF]].dsub ; CHECK-NEXT: B %bb.4 ; CHECK-NEXT: {{ $}}