diff --git a/llvm/lib/Target/RISCV/RISCVInstrInfoXVentana.td b/llvm/lib/Target/RISCV/RISCVInstrInfoXVentana.td
--- a/llvm/lib/Target/RISCV/RISCVInstrInfoXVentana.td
+++ b/llvm/lib/Target/RISCV/RISCVInstrInfoXVentana.td
@@ -35,6 +35,42 @@
 def : Pat<(select GPR:$rc, (i64 0), GPR:$rs1),
           (VT_MASKCN $rs1, $rc)>;
 
+def : Pat<(select (i64 (setne GPR:$rc, (i64 0))), GPR:$rs1, (i64 0)),
+          (VT_MASKC GPR:$rs1, GPR:$rc)>;
+def : Pat<(select (i64 (seteq GPR:$rc, (i64 0))), GPR:$rs1, (i64 0)),
+          (VT_MASKCN GPR:$rs1, GPR:$rc)>;
+def : Pat<(select (i64 (setne GPR:$rc, (i64 0))), (i64 0), GPR:$rs1),
+          (VT_MASKCN GPR:$rs1, GPR:$rc)>;
+def : Pat<(select (i64 (seteq GPR:$rc, (i64 0))), (i64 0), GPR:$rs1),
+          (VT_MASKC GPR:$rs1, GPR:$rc)>;
+
+def : Pat<(select (i64 (setne GPR:$x, simm12_plus1:$y)), GPR:$rs1, (i64 0)),
+          (VT_MASKC GPR:$rs1, (ADDI GPR:$x, (NegImm simm12_plus1:$y)))>;
+def : Pat<(select (i64 (seteq GPR:$x, simm12_plus1:$y)), GPR:$rs1, (i64 0)),
+          (VT_MASKCN GPR:$rs1, (ADDI GPR:$x, (NegImm simm12_plus1:$y)))>;
+def : Pat<(select (i64 (setne GPR:$x, simm12_plus1:$y)), (i64 0), GPR:$rs1),
+          (VT_MASKCN GPR:$rs1, (ADDI GPR:$x, (NegImm simm12_plus1:$y)))>;
+def : Pat<(select (i64 (seteq GPR:$x, simm12_plus1:$y)), (i64 0), GPR:$rs1),
+          (VT_MASKC GPR:$rs1, (ADDI GPR:$x, (NegImm simm12_plus1:$y)))>;
+
+def : Pat<(select (i64 (setne GPR:$x, (i64 -2048))), GPR:$rs1, (i64 0)),
+          (VT_MASKC GPR:$rs1, (XORI GPR:$x, -2048))>;
+def : Pat<(select (i64 (seteq GPR:$x, (i64 -2048))), GPR:$rs1, (i64 0)),
+          (VT_MASKCN GPR:$rs1, (XORI GPR:$x, -2048))>;
+def : Pat<(select (i64 (setne GPR:$x, (i64 -2048))), (i64 0), GPR:$rs1),
+          (VT_MASKCN GPR:$rs1, (XORI GPR:$x, -2048))>;
+def : Pat<(select (i64 (seteq GPR:$x, (i64 -2048))), (i64 0), GPR:$rs1),
+          (VT_MASKC GPR:$rs1, (XORI GPR:$x, -2048))>;
+
+def : Pat<(select (i64 (setne GPR:$x, GPR:$y)), GPR:$rs1, (i64 0)),
+          (VT_MASKC GPR:$rs1, (XOR GPR:$x, GPR:$y))>;
+def : Pat<(select (i64 (seteq GPR:$x, GPR:$y)), GPR:$rs1, (i64 0)),
+          (VT_MASKCN GPR:$rs1, (XOR GPR:$x, GPR:$y))>;
+def : Pat<(select (i64 (setne GPR:$x, GPR:$y)), (i64 0), GPR:$rs1),
+          (VT_MASKCN GPR:$rs1, (XOR GPR:$x, GPR:$y))>;
+def : Pat<(select (i64 (seteq GPR:$x, GPR:$y)), (i64 0), GPR:$rs1),
+          (VT_MASKC GPR:$rs1, (XOR GPR:$x, GPR:$y))>;
+
 // Conditional AND operation patterns.
 def : Pat<(i64 (select GPR:$rc, (and GPR:$rs1, GPR:$rs2), GPR:$rs1)),
           (OR (AND $rs1, $rs2), (VT_MASKCN $rs1, $rc))>;
@@ -44,4 +80,31 @@
 // Basic select pattern that selects between 2 registers.
 def : Pat<(i64 (select GPR:$rc, GPR:$rs1, GPR:$rs2)),
           (OR (VT_MASKC $rs1, $rc), (VT_MASKCN $rs2, $rc))>;
+
+def : Pat<(i64 (select (i64 (setne GPR:$rc, (i64 0))), GPR:$rs1, GPR:$rs2)),
+          (OR (VT_MASKC GPR:$rs1, GPR:$rc), (VT_MASKCN GPR:$rs2, GPR:$rc))>;
+def : Pat<(i64 (select (i64 (seteq GPR:$rc, (i64 0))), GPR:$rs2, GPR:$rs1)),
+          (OR (VT_MASKC GPR:$rs1, GPR:$rc), (VT_MASKCN GPR:$rs2, GPR:$rc))>;
+
+def : Pat<(i64 (select (i64 (setne GPR:$x, simm12_plus1:$y)), GPR:$rs1, GPR:$rs2)),
+          (OR (VT_MASKC GPR:$rs1, (ADDI GPR:$x, (NegImm simm12_plus1:$y))),
+              (VT_MASKCN GPR:$rs2, (ADDI GPR:$x, (NegImm simm12_plus1:$y))))>;
+def : Pat<(i64 (select (i64 (seteq GPR:$x, simm12_plus1:$y)), GPR:$rs2, GPR:$rs1)),
+          (OR (VT_MASKC GPR:$rs1, (ADDI GPR:$x, (NegImm simm12_plus1:$y))),
+              (VT_MASKCN GPR:$rs2, (ADDI GPR:$x, (NegImm simm12_plus1:$y))))>;
+
+def : Pat<(i64 (select (i64 (setne GPR:$x, (i64 -2048))), GPR:$rs1, GPR:$rs2)),
+          (OR (VT_MASKC GPR:$rs1, (XORI GPR:$x, -2048)),
+              (VT_MASKCN GPR:$rs2, (XORI GPR:$x, -2048)))>;
+def : Pat<(i64 (select (i64 (seteq GPR:$x, (i64 -2048))), GPR:$rs2, GPR:$rs1)),
+          (OR (VT_MASKC GPR:$rs1, (XORI GPR:$x, -2048)),
+              (VT_MASKCN GPR:$rs2, (XORI GPR:$x, -2048)))>;
+
+def : Pat<(i64 (select (i64 (setne GPR:$x, GPR:$y)), GPR:$rs1, GPR:$rs2)),
+          (OR (VT_MASKC GPR:$rs1, (XOR GPR:$x, GPR:$y)),
+              (VT_MASKCN GPR:$rs2, (XOR GPR:$x, GPR:$y)))>;
+def : Pat<(i64 (select (i64 (seteq GPR:$x, GPR:$y)), GPR:$rs2, GPR:$rs1)),
+          (OR (VT_MASKC GPR:$rs1, (XOR GPR:$x, GPR:$y)),
+              (VT_MASKCN GPR:$rs2, (XOR GPR:$x, GPR:$y)))>;
+
 } // Predicates = [IsRV64, HasVendorXVentanaCondOps]
diff --git a/llvm/test/CodeGen/RISCV/select.ll b/llvm/test/CodeGen/RISCV/select.ll
--- a/llvm/test/CodeGen/RISCV/select.ll
+++ b/llvm/test/CodeGen/RISCV/select.ll
@@ -138,9 +138,8 @@
 ; CONDOPS-LABEL: select_xor_3:
 ; CONDOPS:       # %bb.0: # %entry
 ; CONDOPS-NEXT:    andi a1, a1, 1
-; CONDOPS-NEXT:    seqz a1, a1
 ; CONDOPS-NEXT:    li a2, 43
-; CONDOPS-NEXT:    vt.maskc a1, a2, a1
+; CONDOPS-NEXT:    vt.maskcn a1, a2, a1
 ; CONDOPS-NEXT:    xor a0, a0, a1
 ; CONDOPS-NEXT:    ret
 entry:
@@ -205,8 +204,7 @@
 ; CONDOPS-LABEL: select_xor_4:
 ; CONDOPS:       # %bb.0: # %entry
 ; CONDOPS-NEXT:    andi a2, a2, 1
-; CONDOPS-NEXT:    seqz a2, a2
-; CONDOPS-NEXT:    vt.maskc a1, a1, a2
+; CONDOPS-NEXT:    vt.maskcn a1, a1, a2
 ; CONDOPS-NEXT:    xor a0, a0, a1
 ; CONDOPS-NEXT:    ret
 entry:
@@ -384,8 +382,7 @@
 ; CONDOPS-LABEL: select_or_2:
 ; CONDOPS:       # %bb.0: # %entry
 ; CONDOPS-NEXT:    andi a2, a2, 1
-; CONDOPS-NEXT:    seqz a2, a2
-; CONDOPS-NEXT:    vt.maskc a1, a1, a2
+; CONDOPS-NEXT:    vt.maskcn a1, a1, a2
 ; CONDOPS-NEXT:    or a0, a0, a1
 ; CONDOPS-NEXT:    ret
 entry:
@@ -449,8 +446,7 @@
 ; CONDOPS-LABEL: select_or_3:
 ; CONDOPS:       # %bb.0: # %entry
 ; CONDOPS-NEXT:    andi a2, a2, 1
-; CONDOPS-NEXT:    seqz a2, a2
-; CONDOPS-NEXT:    vt.maskc a1, a1, a2
+; CONDOPS-NEXT:    vt.maskcn a1, a1, a2
 ; CONDOPS-NEXT:    or a0, a0, a1
 ; CONDOPS-NEXT:    ret
 entry:
diff --git a/llvm/test/CodeGen/RISCV/xventanacondops.ll b/llvm/test/CodeGen/RISCV/xventanacondops.ll
--- a/llvm/test/CodeGen/RISCV/xventanacondops.ll
+++ b/llvm/test/CodeGen/RISCV/xventanacondops.ll
@@ -236,9 +236,8 @@
 ; CHECK-LABEL: seteq:
 ; CHECK:       # %bb.0:
 ; CHECK-NEXT:    xor a0, a0, a1
-; CHECK-NEXT:    seqz a0, a0
-; CHECK-NEXT:    vt.maskcn a1, a3, a0
-; CHECK-NEXT:    vt.maskc a0, a2, a0
+; CHECK-NEXT:    vt.maskcn a1, a2, a0
+; CHECK-NEXT:    vt.maskc a0, a3, a0
 ; CHECK-NEXT:    or a0, a0, a1
 ; CHECK-NEXT:    ret
   %rc = icmp eq i64 %a, %b
@@ -250,7 +249,6 @@
 ; CHECK-LABEL: setne:
 ; CHECK:       # %bb.0:
 ; CHECK-NEXT:    xor a0, a0, a1
-; CHECK-NEXT:    snez a0, a0
 ; CHECK-NEXT:    vt.maskcn a1, a3, a0
 ; CHECK-NEXT:    vt.maskc a0, a2, a0
 ; CHECK-NEXT:    or a0, a0, a1
@@ -367,10 +365,9 @@
 define i64 @seteq_zero(i64 %a, i64 %rs1, i64 %rs2) {
 ; CHECK-LABEL: seteq_zero:
 ; CHECK:       # %bb.0:
-; CHECK-NEXT:    seqz a0, a0
-; CHECK-NEXT:    vt.maskcn a2, a2, a0
-; CHECK-NEXT:    vt.maskc a0, a1, a0
-; CHECK-NEXT:    or a0, a0, a2
+; CHECK-NEXT:    vt.maskcn a1, a1, a0
+; CHECK-NEXT:    vt.maskc a0, a2, a0
+; CHECK-NEXT:    or a0, a0, a1
 ; CHECK-NEXT:    ret
   %rc = icmp eq i64 %a, 0
   %sel = select i1 %rc, i64 %rs1, i64 %rs2
@@ -380,7 +377,6 @@
 define i64 @setne_zero(i64 %a, i64 %rs1, i64 %rs2) {
 ; CHECK-LABEL: setne_zero:
 ; CHECK:       # %bb.0:
-; CHECK-NEXT:    snez a0, a0
 ; CHECK-NEXT:    vt.maskcn a2, a2, a0
 ; CHECK-NEXT:    vt.maskc a0, a1, a0
 ; CHECK-NEXT:    or a0, a0, a2
@@ -394,10 +390,9 @@
 ; CHECK-LABEL: seteq_constant:
 ; CHECK:       # %bb.0:
 ; CHECK-NEXT:    addi a0, a0, -123
-; CHECK-NEXT:    seqz a0, a0
-; CHECK-NEXT:    vt.maskcn a2, a2, a0
-; CHECK-NEXT:    vt.maskc a0, a1, a0
-; CHECK-NEXT:    or a0, a0, a2
+; CHECK-NEXT:    vt.maskcn a1, a1, a0
+; CHECK-NEXT:    vt.maskc a0, a2, a0
+; CHECK-NEXT:    or a0, a0, a1
 ; CHECK-NEXT:    ret
   %rc = icmp eq i64 %a, 123
   %sel = select i1 %rc, i64 %rs1, i64 %rs2
@@ -408,7 +403,6 @@
 ; CHECK-LABEL: setne_constant:
 ; CHECK:       # %bb.0:
 ; CHECK-NEXT:    addi a0, a0, -456
-; CHECK-NEXT:    snez a0, a0
 ; CHECK-NEXT:    vt.maskcn a2, a2, a0
 ; CHECK-NEXT:    vt.maskc a0, a1, a0
 ; CHECK-NEXT:    or a0, a0, a2
@@ -422,10 +416,9 @@
 ; CHECK-LABEL: seteq_neg2048:
 ; CHECK:       # %bb.0:
 ; CHECK-NEXT:    xori a0, a0, -2048
-; CHECK-NEXT:    seqz a0, a0
-; CHECK-NEXT:    vt.maskcn a2, a2, a0
-; CHECK-NEXT:    vt.maskc a0, a1, a0
-; CHECK-NEXT:    or a0, a0, a2
+; CHECK-NEXT:    vt.maskcn a1, a1, a0
+; CHECK-NEXT:    vt.maskc a0, a2, a0
+; CHECK-NEXT:    or a0, a0, a1
 ; CHECK-NEXT:    ret
   %rc = icmp eq i64 %a, -2048
   %sel = select i1 %rc, i64 %rs1, i64 %rs2
@@ -436,7 +429,6 @@
 ; CHECK-LABEL: setne_neg2048:
 ; CHECK:       # %bb.0:
 ; CHECK-NEXT:    xori a0, a0, -2048
-; CHECK-NEXT:    snez a0, a0
 ; CHECK-NEXT:    vt.maskcn a2, a2, a0
 ; CHECK-NEXT:    vt.maskc a0, a1, a0
 ; CHECK-NEXT:    or a0, a0, a2
@@ -450,8 +442,7 @@
 ; CHECK-LABEL: zero1_seteq:
 ; CHECK:       # %bb.0:
 ; CHECK-NEXT:    xor a0, a0, a1
-; CHECK-NEXT:    seqz a0, a0
-; CHECK-NEXT:    vt.maskc a0, a2, a0
+; CHECK-NEXT:    vt.maskcn a0, a2, a0
 ; CHECK-NEXT:    ret
   %rc = icmp eq i64 %a, %b
   %sel = select i1 %rc, i64 %rs1, i64 0
@@ -462,8 +453,7 @@
 ; CHECK-LABEL: zero2_seteq:
 ; CHECK:       # %bb.0:
 ; CHECK-NEXT:    xor a0, a0, a1
-; CHECK-NEXT:    seqz a0, a0
-; CHECK-NEXT:    vt.maskcn a0, a2, a0
+; CHECK-NEXT:    vt.maskc a0, a2, a0
 ; CHECK-NEXT:    ret
   %rc = icmp eq i64 %a, %b
   %sel = select i1 %rc, i64 0, i64 %rs1
@@ -474,7 +464,6 @@
 ; CHECK-LABEL: zero1_setne:
 ; CHECK:       # %bb.0:
 ; CHECK-NEXT:    xor a0, a0, a1
-; CHECK-NEXT:    snez a0, a0
 ; CHECK-NEXT:    vt.maskc a0, a2, a0
 ; CHECK-NEXT:    ret
   %rc = icmp ne i64 %a, %b
@@ -486,7 +475,6 @@
 ; CHECK-LABEL: zero2_setne:
 ; CHECK:       # %bb.0:
 ; CHECK-NEXT:    xor a0, a0, a1
-; CHECK-NEXT:    snez a0, a0
 ; CHECK-NEXT:    vt.maskcn a0, a2, a0
 ; CHECK-NEXT:    ret
   %rc = icmp ne i64 %a, %b
@@ -497,8 +485,7 @@
 define i64 @zero1_seteq_zero(i64 %a, i64 %rs1) {
 ; CHECK-LABEL: zero1_seteq_zero:
 ; CHECK:       # %bb.0:
-; CHECK-NEXT:    seqz a0, a0
-; CHECK-NEXT:    vt.maskc a0, a1, a0
+; CHECK-NEXT:    vt.maskcn a0, a1, a0
 ; CHECK-NEXT:    ret
   %rc = icmp eq i64 %a, 0
   %sel = select i1 %rc, i64 %rs1, i64 0
@@ -508,8 +495,7 @@
 define i64 @zero2_seteq_zero(i64 %a, i64 %rs1) {
 ; CHECK-LABEL: zero2_seteq_zero:
 ; CHECK:       # %bb.0:
-; CHECK-NEXT:    seqz a0, a0
-; CHECK-NEXT:    vt.maskcn a0, a1, a0
+; CHECK-NEXT:    vt.maskc a0, a1, a0
 ; CHECK-NEXT:    ret
   %rc = icmp eq i64 %a, 0
   %sel = select i1 %rc, i64 0, i64 %rs1
@@ -519,7 +505,6 @@
 define i64 @zero1_setne_zero(i64 %a, i64 %rs1) {
 ; CHECK-LABEL: zero1_setne_zero:
 ; CHECK:       # %bb.0:
-; CHECK-NEXT:    snez a0, a0
 ; CHECK-NEXT:    vt.maskc a0, a1, a0
 ; CHECK-NEXT:    ret
   %rc = icmp ne i64 %a, 0
@@ -530,7 +515,6 @@
 define i64 @zero2_setne_zero(i64 %a, i64 %rs1) {
 ; CHECK-LABEL: zero2_setne_zero:
 ; CHECK:       # %bb.0:
-; CHECK-NEXT:    snez a0, a0
 ; CHECK-NEXT:    vt.maskcn a0, a1, a0
 ; CHECK-NEXT:    ret
   %rc = icmp ne i64 %a, 0
@@ -542,8 +526,7 @@
 ; CHECK-LABEL: zero1_seteq_constant:
 ; CHECK:       # %bb.0:
 ; CHECK-NEXT:    addi a0, a0, 231
-; CHECK-NEXT:    seqz a0, a0
-; CHECK-NEXT:    vt.maskc a0, a1, a0
+; CHECK-NEXT:    vt.maskcn a0, a1, a0
 ; CHECK-NEXT:    ret
   %rc = icmp eq i64 %a, -231
   %sel = select i1 %rc, i64 %rs1, i64 0
@@ -554,8 +537,7 @@
 ; CHECK-LABEL: zero2_seteq_constant:
 ; CHECK:       # %bb.0:
 ; CHECK-NEXT:    addi a0, a0, -546
-; CHECK-NEXT:    seqz a0, a0
-; CHECK-NEXT:    vt.maskcn a0, a1, a0
+; CHECK-NEXT:    vt.maskc a0, a1, a0
 ; CHECK-NEXT:    ret
   %rc = icmp eq i64 %a, 546
   %sel = select i1 %rc, i64 0, i64 %rs1
@@ -566,7 +548,6 @@
 ; CHECK-LABEL: zero1_setne_constant:
 ; CHECK:       # %bb.0:
 ; CHECK-NEXT:    addi a0, a0, -321
-; CHECK-NEXT:    snez a0, a0
 ; CHECK-NEXT:    vt.maskc a0, a1, a0
 ; CHECK-NEXT:    ret
   %rc = icmp ne i64 %a, 321
@@ -578,7 +559,6 @@
 ; CHECK-LABEL: zero2_setne_constant:
 ; CHECK:       # %bb.0:
 ; CHECK-NEXT:    addi a0, a0, 654
-; CHECK-NEXT:    snez a0, a0
 ; CHECK-NEXT:    vt.maskcn a0, a1, a0
 ; CHECK-NEXT:    ret
   %rc = icmp ne i64 %a, -654
@@ -590,8 +570,7 @@
 ; CHECK-LABEL: zero1_seteq_neg2048:
 ; CHECK:       # %bb.0:
 ; CHECK-NEXT:    xori a0, a0, -2048
-; CHECK-NEXT:    seqz a0, a0
-; CHECK-NEXT:    vt.maskc a0, a1, a0
+; CHECK-NEXT:    vt.maskcn a0, a1, a0
 ; CHECK-NEXT:    ret
   %rc = icmp eq i64 %a, -2048
   %sel = select i1 %rc, i64 %rs1, i64 0
@@ -602,8 +581,7 @@
 ; CHECK-LABEL: zero2_seteq_neg2048:
 ; CHECK:       # %bb.0:
 ; CHECK-NEXT:    xori a0, a0, -2048
-; CHECK-NEXT:    seqz a0, a0
-; CHECK-NEXT:    vt.maskcn a0, a1, a0
+; CHECK-NEXT:    vt.maskc a0, a1, a0
 ; CHECK-NEXT:    ret
   %rc = icmp eq i64 %a, -2048
   %sel = select i1 %rc, i64 0, i64 %rs1
@@ -614,7 +592,6 @@
 ; CHECK-LABEL: zero1_setne_neg2048:
 ; CHECK:       # %bb.0:
 ; CHECK-NEXT:    xori a0, a0, -2048
-; CHECK-NEXT:    snez a0, a0
 ; CHECK-NEXT:    vt.maskc a0, a1, a0
 ; CHECK-NEXT:    ret
   %rc = icmp ne i64 %a, -2048
@@ -626,7 +603,6 @@
 ; CHECK-LABEL: zero2_setne_neg2048:
 ; CHECK:       # %bb.0:
 ; CHECK-NEXT:    xori a0, a0, -2048
-; CHECK-NEXT:    snez a0, a0
 ; CHECK-NEXT:    vt.maskcn a0, a1, a0
 ; CHECK-NEXT:    ret
   %rc = icmp ne i64 %a, -2048