diff --git a/llvm/lib/Target/ARC/ARC.h b/llvm/lib/Target/ARC/ARC.h
--- a/llvm/lib/Target/ARC/ARC.h
+++ b/llvm/lib/Target/ARC/ARC.h
@@ -19,14 +19,16 @@
 
 namespace llvm {
 
-class FunctionPass;
 class ARCTargetMachine;
+class FunctionPass;
+class PassRegistry;
 
 FunctionPass *createARCISelDag(ARCTargetMachine &TM,
                                CodeGenOpt::Level OptLevel);
 FunctionPass *createARCExpandPseudosPass();
 FunctionPass *createARCOptAddrMode();
 FunctionPass *createARCBranchFinalizePass();
+void initializeARCDAGToDAGISelPass(PassRegistry &);
 
 } // end namespace llvm
 
diff --git a/llvm/lib/Target/ARC/ARCISelDAGToDAG.cpp b/llvm/lib/Target/ARC/ARCISelDAGToDAG.cpp
--- a/llvm/lib/Target/ARC/ARCISelDAGToDAG.cpp
+++ b/llvm/lib/Target/ARC/ARCISelDAGToDAG.cpp
@@ -32,6 +32,9 @@
 
 using namespace llvm;
 
+#define DEBUG_TYPE "arc-isel"
+#define PASS_NAME "ARC DAG->DAG Pattern Instruction Selection"
+
 /// ARCDAGToDAGISel - ARC specific code to select ARC machine
 /// instructions for SelectionDAG operations.
 namespace {
@@ -40,6 +43,8 @@
 public:
   static char ID;
 
+  ARCDAGToDAGISel() = delete;
+
   ARCDAGToDAGISel(ARCTargetMachine &TM, CodeGenOpt::Level OptLevel)
       : SelectionDAGISel(ID, TM, OptLevel) {}
 
@@ -51,16 +56,14 @@
   bool SelectAddrModeImm(SDValue Addr, SDValue &Base, SDValue &Offset);
   bool SelectAddrModeFar(SDValue Addr, SDValue &Base, SDValue &Offset);
 
-  StringRef getPassName() const override {
-    return "ARC DAG->DAG Pattern Instruction Selection";
-  }
-
 // Include the pieces autogenerated from the target description.
 #include "ARCGenDAGISel.inc"
 };
 
 char ARCDAGToDAGISel::ID;
 
+INITIALIZE_PASS(ARCDAGToDAGISel, DEBUG_TYPE, PASS_NAME, false, false)
+
 } // end anonymous namespace
 
 /// This pass converts a legalized DAG into a ARC-specific DAG, ready for
diff --git a/llvm/lib/Target/ARC/ARCTargetMachine.cpp b/llvm/lib/Target/ARC/ARCTargetMachine.cpp
--- a/llvm/lib/Target/ARC/ARCTargetMachine.cpp
+++ b/llvm/lib/Target/ARC/ARCTargetMachine.cpp
@@ -82,6 +82,8 @@
 // Force static initialization.
 extern "C" LLVM_EXTERNAL_VISIBILITY void LLVMInitializeARCTarget() {
   RegisterTargetMachine<ARCTargetMachine> X(getTheARCTarget());
+  PassRegistry &PR = *PassRegistry::getPassRegistry();
+  initializeARCDAGToDAGISelPass(PR);
 }
 
 TargetTransformInfo
diff --git a/llvm/lib/Target/ARM/ARM.h b/llvm/lib/Target/ARM/ARM.h
--- a/llvm/lib/Target/ARM/ARM.h
+++ b/llvm/lib/Target/ARM/ARM.h
@@ -28,8 +28,8 @@
 class Function;
 class FunctionPass;
 class InstructionSelector;
-class MachineInstr;
 class MCInst;
+class MachineInstr;
 class PassRegistry;
 
 Pass *createMVETailPredicationPass();
@@ -62,23 +62,24 @@
 void LowerARMMachineInstrToMCInst(const MachineInstr *MI, MCInst &OutMI,
                                   ARMAsmPrinter &AP);
 
-void initializeARMParallelDSPPass(PassRegistry &);
-void initializeARMLoadStoreOptPass(PassRegistry &);
-void initializeARMPreAllocLoadStoreOptPass(PassRegistry &);
+void initializeARMBlockPlacementPass(PassRegistry &);
 void initializeARMBranchTargetsPass(PassRegistry &);
 void initializeARMConstantIslandsPass(PassRegistry &);
+void initializeARMDAGToDAGISelPass(PassRegistry &);
 void initializeARMExpandPseudoPass(PassRegistry &);
-void initializeThumb2SizeReducePass(PassRegistry &);
-void initializeThumb2ITBlockPass(PassRegistry &);
-void initializeMVEVPTBlockPass(PassRegistry &);
-void initializeMVETPAndVPTOptimisationsPass(PassRegistry &);
+void initializeARMFixCortexA57AES1742098Pass(PassRegistry &);
+void initializeARMLoadStoreOptPass(PassRegistry &);
 void initializeARMLowOverheadLoopsPass(PassRegistry &);
-void initializeARMBlockPlacementPass(PassRegistry &);
-void initializeMVETailPredicationPass(PassRegistry &);
-void initializeMVEGatherScatterLoweringPass(PassRegistry &);
+void initializeARMParallelDSPPass(PassRegistry &);
+void initializeARMPreAllocLoadStoreOptPass(PassRegistry &);
 void initializeARMSLSHardeningPass(PassRegistry &);
+void initializeMVEGatherScatterLoweringPass(PassRegistry &);
 void initializeMVELaneInterleavingPass(PassRegistry &);
-void initializeARMFixCortexA57AES1742098Pass(PassRegistry &);
+void initializeMVETPAndVPTOptimisationsPass(PassRegistry &);
+void initializeMVETailPredicationPass(PassRegistry &);
+void initializeMVEVPTBlockPass(PassRegistry &);
+void initializeThumb2ITBlockPass(PassRegistry &);
+void initializeThumb2SizeReducePass(PassRegistry &);
 
 } // end namespace llvm
 
diff --git a/llvm/lib/Target/ARM/ARMISelDAGToDAG.cpp b/llvm/lib/Target/ARM/ARMISelDAGToDAG.cpp
--- a/llvm/lib/Target/ARM/ARMISelDAGToDAG.cpp
+++ b/llvm/lib/Target/ARM/ARMISelDAGToDAG.cpp
@@ -40,6 +40,7 @@
 using namespace llvm;
 
 #define DEBUG_TYPE "arm-isel"
+#define PASS_NAME "ARM Instruction Selection"
 
 static cl::opt<bool>
 DisableShifterOp("disable-shifter-op", cl::Hidden,
@@ -60,6 +61,8 @@
 public:
   static char ID;
 
+  ARMDAGToDAGISel() = delete;
+
   explicit ARMDAGToDAGISel(ARMBaseTargetMachine &tm, CodeGenOpt::Level OptLevel)
       : SelectionDAGISel(ID, tm, OptLevel) {}
 
@@ -70,8 +73,6 @@
     return true;
   }
 
-  StringRef getPassName() const override { return "ARM Instruction Selection"; }
-
   void PreprocessISelDAG() override;
 
   /// getI32Imm - Return a target constant of type i32 with the specified
@@ -364,6 +365,8 @@
 
 char ARMDAGToDAGISel::ID = 0;
 
+INITIALIZE_PASS(ARMDAGToDAGISel, DEBUG_TYPE, PASS_NAME, false, false)
+
 /// isInt32Immediate - This method tests to see if the node is a 32-bit constant
 /// operand. If so Imm will receive the 32-bit value.
 static bool isInt32Immediate(SDNode *N, unsigned &Imm) {
diff --git a/llvm/lib/Target/ARM/ARMTargetMachine.cpp b/llvm/lib/Target/ARM/ARMTargetMachine.cpp
--- a/llvm/lib/Target/ARM/ARMTargetMachine.cpp
+++ b/llvm/lib/Target/ARM/ARMTargetMachine.cpp
@@ -108,6 +108,7 @@
   initializeARMSLSHardeningPass(Registry);
   initializeMVELaneInterleavingPass(Registry);
   initializeARMFixCortexA57AES1742098Pass(Registry);
+  initializeARMDAGToDAGISelPass(Registry);
 }
 
 static std::unique_ptr<TargetLoweringObjectFile> createTLOF(const Triple &TT) {
diff --git a/llvm/lib/Target/AVR/AVR.h b/llvm/lib/Target/AVR/AVR.h
--- a/llvm/lib/Target/AVR/AVR.h
+++ b/llvm/lib/Target/AVR/AVR.h
@@ -23,6 +23,7 @@
 
 class AVRTargetMachine;
 class FunctionPass;
+class PassRegistry;
 
 Pass *createAVRShiftExpandPass();
 FunctionPass *createAVRISelDag(AVRTargetMachine &TM,
@@ -31,8 +32,9 @@
 FunctionPass *createAVRFrameAnalyzerPass();
 FunctionPass *createAVRBranchSelectionPass();
 
-void initializeAVRShiftExpandPass(PassRegistry &);
+void initializeAVRDAGToDAGISelPass(PassRegistry &);
 void initializeAVRExpandPseudoPass(PassRegistry &);
+void initializeAVRShiftExpandPass(PassRegistry &);
 
 /// Contains the AVR backend.
 namespace AVR {
diff --git a/llvm/lib/Target/AVR/AVRISelDAGToDAG.cpp b/llvm/lib/Target/AVR/AVRISelDAGToDAG.cpp
--- a/llvm/lib/Target/AVR/AVRISelDAGToDAG.cpp
+++ b/llvm/lib/Target/AVR/AVRISelDAGToDAG.cpp
@@ -20,6 +20,7 @@
 #include "llvm/Support/raw_ostream.h"
 
 #define DEBUG_TYPE "avr-isel"
+#define PASS_NAME "AVR DAG->DAG Instruction Selection"
 
 namespace llvm {
 
@@ -28,13 +29,11 @@
 public:
   static char ID;
 
+  AVRDAGToDAGISel() = delete;
+
   AVRDAGToDAGISel(AVRTargetMachine &TM, CodeGenOpt::Level OptLevel)
       : SelectionDAGISel(ID, TM, OptLevel), Subtarget(nullptr) {}
 
-  StringRef getPassName() const override {
-    return "AVR DAG->DAG Instruction Selection";
-  }
-
   bool runOnMachineFunction(MachineFunction &MF) override;
 
   bool SelectAddr(SDNode *Op, SDValue N, SDValue &Base, SDValue &Disp);
@@ -60,6 +59,8 @@
 
 char AVRDAGToDAGISel::ID = 0;
 
+INITIALIZE_PASS(AVRDAGToDAGISel, DEBUG_TYPE, PASS_NAME, false, false)
+
 bool AVRDAGToDAGISel::runOnMachineFunction(MachineFunction &MF) {
   Subtarget = &MF.getSubtarget<AVRSubtarget>();
   return SelectionDAGISel::runOnMachineFunction(MF);
diff --git a/llvm/lib/Target/AVR/AVRTargetMachine.cpp b/llvm/lib/Target/AVR/AVRTargetMachine.cpp
--- a/llvm/lib/Target/AVR/AVRTargetMachine.cpp
+++ b/llvm/lib/Target/AVR/AVRTargetMachine.cpp
@@ -95,6 +95,7 @@
   auto &PR = *PassRegistry::getPassRegistry();
   initializeAVRExpandPseudoPass(PR);
   initializeAVRShiftExpandPass(PR);
+  initializeAVRDAGToDAGISelPass(PR);
 }
 
 const AVRSubtarget *AVRTargetMachine::getSubtargetImpl() const {
diff --git a/llvm/lib/Target/BPF/BPF.h b/llvm/lib/Target/BPF/BPF.h
--- a/llvm/lib/Target/BPF/BPF.h
+++ b/llvm/lib/Target/BPF/BPF.h
@@ -12,11 +12,11 @@
 #include "MCTargetDesc/BPFMCTargetDesc.h"
 #include "llvm/IR/PassManager.h"
 #include "llvm/Pass.h"
-#include "llvm/PassRegistry.h"
 #include "llvm/Target/TargetMachine.h"
 
 namespace llvm {
 class BPFTargetMachine;
+class PassRegistry;
 
 ModulePass *createBPFAdjustOpt();
 ModulePass *createBPFCheckAndAdjustIR();
@@ -31,17 +31,17 @@
 FunctionPass *createBPFMIPreEmitPeepholePass();
 FunctionPass *createBPFMIPreEmitCheckingPass();
 
+void initializeBPFAbstractMemberAccessLegacyPassPass(PassRegistry &);
 void initializeBPFAdjustOptPass(PassRegistry&);
 void initializeBPFCheckAndAdjustIRPass(PassRegistry&);
-
-void initializeBPFAbstractMemberAccessLegacyPassPass(PassRegistry &);
-void initializeBPFPreserveDITypePass(PassRegistry&);
-void initializeBPFIRPeepholePass(PassRegistry&);
-void initializeBPFMISimplifyPatchablePass(PassRegistry&);
+void initializeBPFDAGToDAGISelPass(PassRegistry &);
+void initializeBPFIRPeepholePass(PassRegistry &);
 void initializeBPFMIPeepholePass(PassRegistry&);
-void initializeBPFMIPeepholeTruncElimPass(PassRegistry&);
-void initializeBPFMIPreEmitPeepholePass(PassRegistry&);
+void initializeBPFMIPeepholeTruncElimPass(PassRegistry &);
 void initializeBPFMIPreEmitCheckingPass(PassRegistry&);
+void initializeBPFMIPreEmitPeepholePass(PassRegistry &);
+void initializeBPFMISimplifyPatchablePass(PassRegistry &);
+void initializeBPFPreserveDITypePass(PassRegistry &);
 
 class BPFAbstractMemberAccessPass
     : public PassInfoMixin<BPFAbstractMemberAccessPass> {
diff --git a/llvm/lib/Target/BPF/BPFISelDAGToDAG.cpp b/llvm/lib/Target/BPF/BPFISelDAGToDAG.cpp
--- a/llvm/lib/Target/BPF/BPFISelDAGToDAG.cpp
+++ b/llvm/lib/Target/BPF/BPFISelDAGToDAG.cpp
@@ -34,6 +34,7 @@
 using namespace llvm;
 
 #define DEBUG_TYPE "bpf-isel"
+#define PASS_NAME "BPF DAG->DAG Pattern Instruction Selection"
 
 // Instruction Selector Implementation
 namespace {
@@ -47,13 +48,11 @@
 public:
   static char ID;
 
+  BPFDAGToDAGISel() = delete;
+
   explicit BPFDAGToDAGISel(BPFTargetMachine &TM)
       : SelectionDAGISel(ID, TM), Subtarget(nullptr) {}
 
-  StringRef getPassName() const override {
-    return "BPF DAG->DAG Pattern Instruction Selection";
-  }
-
   bool runOnMachineFunction(MachineFunction &MF) override {
     // Reset the subtarget each time through.
     Subtarget = &MF.getSubtarget<BPFSubtarget>();
@@ -100,6 +99,8 @@
 
 char BPFDAGToDAGISel::ID = 0;
 
+INITIALIZE_PASS(BPFDAGToDAGISel, DEBUG_TYPE, PASS_NAME, false, false)
+
 // ComplexPattern used on BPF Load/Store instructions
 bool BPFDAGToDAGISel::SelectAddr(SDValue Addr, SDValue &Base, SDValue &Offset) {
   // if Address is FI, get the TargetFrameIndex.
diff --git a/llvm/lib/Target/BPF/BPFTargetMachine.cpp b/llvm/lib/Target/BPF/BPFTargetMachine.cpp
--- a/llvm/lib/Target/BPF/BPFTargetMachine.cpp
+++ b/llvm/lib/Target/BPF/BPFTargetMachine.cpp
@@ -48,6 +48,7 @@
   initializeBPFCheckAndAdjustIRPass(PR);
   initializeBPFMIPeepholePass(PR);
   initializeBPFMIPeepholeTruncElimPass(PR);
+  initializeBPFDAGToDAGISelPass(PR);
 }
 
 // DataLayout: little or big endian
diff --git a/llvm/lib/Target/CSKY/CSKY.h b/llvm/lib/Target/CSKY/CSKY.h
--- a/llvm/lib/Target/CSKY/CSKY.h
+++ b/llvm/lib/Target/CSKY/CSKY.h
@@ -26,6 +26,7 @@
 FunctionPass *createCSKYConstantIslandPass();
 
 void initializeCSKYConstantIslandsPass(PassRegistry &);
+void initializeCSKYDAGToDAGISelPass(PassRegistry &);
 
 } // namespace llvm
 
diff --git a/llvm/lib/Target/CSKY/CSKYISelDAGToDAG.cpp b/llvm/lib/Target/CSKY/CSKYISelDAGToDAG.cpp
--- a/llvm/lib/Target/CSKY/CSKYISelDAGToDAG.cpp
+++ b/llvm/lib/Target/CSKY/CSKYISelDAGToDAG.cpp
@@ -21,6 +21,7 @@
 using namespace llvm;
 
 #define DEBUG_TYPE "csky-isel"
+#define PASS_NAME "CSKY DAG->DAG Pattern Instruction Selection"
 
 namespace {
 class CSKYDAGToDAGISel : public SelectionDAGISel {
@@ -29,10 +30,6 @@
 public:
   explicit CSKYDAGToDAGISel(CSKYTargetMachine &TM) : SelectionDAGISel(TM) {}
 
-  StringRef getPassName() const override {
-    return "CSKY DAG->DAG Pattern Instruction Selection";
-  }
-
   bool runOnMachineFunction(MachineFunction &MF) override {
     // Reset the subtarget each time through.
     Subtarget = &MF.getSubtarget<CSKYSubtarget>();
@@ -55,6 +52,8 @@
 };
 } // namespace
 
+INITIALIZE_PASS(CSKYDAGToDAGISel, DEBUG_TYPE, PASS_NAME, false, false)
+
 void CSKYDAGToDAGISel::Select(SDNode *N) {
   // If we have a custom node, we have already selected
   if (N->isMachineOpcode()) {
diff --git a/llvm/lib/Target/CSKY/CSKYTargetMachine.cpp b/llvm/lib/Target/CSKY/CSKYTargetMachine.cpp
--- a/llvm/lib/Target/CSKY/CSKYTargetMachine.cpp
+++ b/llvm/lib/Target/CSKY/CSKYTargetMachine.cpp
@@ -29,6 +29,7 @@
 
   PassRegistry *Registry = PassRegistry::getPassRegistry();
   initializeCSKYConstantIslandsPass(*Registry);
+  initializeCSKYDAGToDAGISelPass(*Registry);
 }
 
 static std::string computeDataLayout(const Triple &TT) {
diff --git a/llvm/lib/Target/Hexagon/Hexagon.h b/llvm/lib/Target/Hexagon/Hexagon.h
--- a/llvm/lib/Target/Hexagon/Hexagon.h
+++ b/llvm/lib/Target/Hexagon/Hexagon.h
@@ -17,9 +17,12 @@
 namespace llvm {
   class HexagonTargetMachine;
   class ImmutablePass;
+  class PassRegistry;
 
   /// Creates a Hexagon-specific Target Transformation Info pass.
   ImmutablePass *createHexagonTargetTransformInfoPass(const HexagonTargetMachine *TM);
+
+  void initializeHexagonDAGToDAGISelPass(PassRegistry &);
 } // end namespace llvm;
 
 #endif
diff --git a/llvm/lib/Target/Hexagon/HexagonISelDAGToDAG.h b/llvm/lib/Target/Hexagon/HexagonISelDAGToDAG.h
--- a/llvm/lib/Target/Hexagon/HexagonISelDAGToDAG.h
+++ b/llvm/lib/Target/Hexagon/HexagonISelDAGToDAG.h
@@ -33,6 +33,8 @@
 public:
   static char ID;
 
+  HexagonDAGToDAGISel() = delete;
+
   explicit HexagonDAGToDAGISel(HexagonTargetMachine &tm,
                                CodeGenOpt::Level OptLevel)
       : SelectionDAGISel(ID, tm, OptLevel), HST(nullptr), HII(nullptr),
@@ -71,10 +73,6 @@
   inline bool SelectAnyImm2(SDValue &N, SDValue &R);
   inline bool SelectAnyImm3(SDValue &N, SDValue &R);
 
-  StringRef getPassName() const override {
-    return "Hexagon DAG->DAG Pattern Instruction Selection";
-  }
-
   // Generate a machine instruction node corresponding to the circ/brev
   // load intrinsic.
   MachineSDNode *LoadInstrForLoadIntrinsic(SDNode *IntN);
diff --git a/llvm/lib/Target/Hexagon/HexagonISelDAGToDAG.cpp b/llvm/lib/Target/Hexagon/HexagonISelDAGToDAG.cpp
--- a/llvm/lib/Target/Hexagon/HexagonISelDAGToDAG.cpp
+++ b/llvm/lib/Target/Hexagon/HexagonISelDAGToDAG.cpp
@@ -25,6 +25,7 @@
 using namespace llvm;
 
 #define DEBUG_TYPE "hexagon-isel"
+#define PASS_NAME "Hexagon DAG->DAG Pattern Instruction Selection"
 
 static
 cl::opt<bool>
@@ -65,6 +66,8 @@
 
 char HexagonDAGToDAGISel::ID = 0;
 
+INITIALIZE_PASS(HexagonDAGToDAGISel, DEBUG_TYPE, PASS_NAME, false, false)
+
 void HexagonDAGToDAGISel::SelectIndexedLoad(LoadSDNode *LD, const SDLoc &dl) {
   SDValue Chain = LD->getChain();
   SDValue Base = LD->getBasePtr();
diff --git a/llvm/lib/Target/Hexagon/HexagonTargetMachine.cpp b/llvm/lib/Target/Hexagon/HexagonTargetMachine.cpp
--- a/llvm/lib/Target/Hexagon/HexagonTargetMachine.cpp
+++ b/llvm/lib/Target/Hexagon/HexagonTargetMachine.cpp
@@ -155,9 +155,9 @@
   void initializeHexagonPacketizerPass(PassRegistry&);
   void initializeHexagonRDFOptPass(PassRegistry&);
   void initializeHexagonSplitDoubleRegsPass(PassRegistry&);
+  void initializeHexagonVExtractPass(PassRegistry &);
   void initializeHexagonVectorCombineLegacyPass(PassRegistry&);
   void initializeHexagonVectorLoopCarriedReuseLegacyPassPass(PassRegistry &);
-  void initializeHexagonVExtractPass(PassRegistry&);
   Pass *createHexagonLoopIdiomPass();
   Pass *createHexagonVectorLoopCarriedReuseLegacyPass();
 
@@ -218,6 +218,7 @@
   initializeHexagonVectorCombineLegacyPass(PR);
   initializeHexagonVectorLoopCarriedReuseLegacyPassPass(PR);
   initializeHexagonVExtractPass(PR);
+  initializeHexagonDAGToDAGISelPass(PR);
 }
 
 HexagonTargetMachine::HexagonTargetMachine(const Target &T, const Triple &TT,
diff --git a/llvm/lib/Target/Lanai/Lanai.h b/llvm/lib/Target/Lanai/Lanai.h
--- a/llvm/lib/Target/Lanai/Lanai.h
+++ b/llvm/lib/Target/Lanai/Lanai.h
@@ -19,6 +19,7 @@
 namespace llvm {
 class FunctionPass;
 class LanaiTargetMachine;
+class PassRegistry;
 
 // createLanaiISelDag - This pass converts a legalized DAG into a
 // Lanai-specific DAG, ready for instruction scheduling.
@@ -36,6 +37,8 @@
 // operations.
 FunctionPass *createLanaiSetflagAluCombinerPass();
 
+void initializeLanaiDAGToDAGISelPass(PassRegistry &);
+
 } // namespace llvm
 
 #endif // LLVM_LIB_TARGET_LANAI_LANAI_H
diff --git a/llvm/lib/Target/Lanai/LanaiISelDAGToDAG.cpp b/llvm/lib/Target/Lanai/LanaiISelDAGToDAG.cpp
--- a/llvm/lib/Target/Lanai/LanaiISelDAGToDAG.cpp
+++ b/llvm/lib/Target/Lanai/LanaiISelDAGToDAG.cpp
@@ -34,6 +34,7 @@
 using namespace llvm;
 
 #define DEBUG_TYPE "lanai-isel"
+#define PASS_NAME "Lanai DAG->DAG Pattern Instruction Selection"
 
 //===----------------------------------------------------------------------===//
 // Instruction Selector Implementation
@@ -49,6 +50,8 @@
 public:
   static char ID;
 
+  LanaiDAGToDAGISel() = delete;
+
   explicit LanaiDAGToDAGISel(LanaiTargetMachine &TargetMachine)
       : SelectionDAGISel(ID, TargetMachine) {}
 
@@ -56,11 +59,6 @@
     return SelectionDAGISel::runOnMachineFunction(MF);
   }
 
-  // Pass Name
-  StringRef getPassName() const override {
-    return "Lanai DAG->DAG Pattern Instruction Selection";
-  }
-
   bool SelectInlineAsmMemoryOperand(const SDValue &Op, unsigned ConstraintCode,
                                     std::vector<SDValue> &OutOps) override;
 
@@ -102,6 +100,8 @@
 
 char LanaiDAGToDAGISel::ID = 0;
 
+INITIALIZE_PASS(LanaiDAGToDAGISel, DEBUG_TYPE, PASS_NAME, false, false)
+
 // Helper functions for ComplexPattern used on LanaiInstrInfo
 // Used on Lanai Load/Store instructions.
 bool LanaiDAGToDAGISel::selectAddrSls(SDValue Addr, SDValue &Offset) {
diff --git a/llvm/lib/Target/Lanai/LanaiTargetMachine.cpp b/llvm/lib/Target/Lanai/LanaiTargetMachine.cpp
--- a/llvm/lib/Target/Lanai/LanaiTargetMachine.cpp
+++ b/llvm/lib/Target/Lanai/LanaiTargetMachine.cpp
@@ -35,6 +35,8 @@
   // Register the target.
   RegisterTargetMachine<LanaiTargetMachine> registered_target(
       getTheLanaiTarget());
+  PassRegistry &PR = *PassRegistry::getPassRegistry();
+  initializeLanaiDAGToDAGISelPass(PR);
 }
 
 static std::string computeDataLayout() {
diff --git a/llvm/lib/Target/LoongArch/LoongArch.h b/llvm/lib/Target/LoongArch/LoongArch.h
--- a/llvm/lib/Target/LoongArch/LoongArch.h
+++ b/llvm/lib/Target/LoongArch/LoongArch.h
@@ -18,9 +18,9 @@
 #include "llvm/Target/TargetMachine.h"
 
 namespace llvm {
-class LoongArchTargetMachine;
 class AsmPrinter;
 class FunctionPass;
+class LoongArchTargetMachine;
 class MCInst;
 class MCOperand;
 class MachineInstr;
@@ -33,11 +33,11 @@
                                              MCOperand &MCOp,
                                              const AsmPrinter &AP);
 
-FunctionPass *createLoongArchISelDag(LoongArchTargetMachine &TM);
 FunctionPass *createLoongArchExpandAtomicPseudoPass();
-void initializeLoongArchExpandAtomicPseudoPass(PassRegistry &);
-
+FunctionPass *createLoongArchISelDag(LoongArchTargetMachine &TM);
 FunctionPass *createLoongArchPreRAExpandPseudoPass();
+void initializeLoongArchDAGToDAGISelPass(PassRegistry &);
+void initializeLoongArchExpandAtomicPseudoPass(PassRegistry &);
 void initializeLoongArchPreRAExpandPseudoPass(PassRegistry &);
 } // end namespace llvm
 
diff --git a/llvm/lib/Target/LoongArch/LoongArchISelDAGToDAG.h b/llvm/lib/Target/LoongArch/LoongArchISelDAGToDAG.h
--- a/llvm/lib/Target/LoongArch/LoongArchISelDAGToDAG.h
+++ b/llvm/lib/Target/LoongArch/LoongArchISelDAGToDAG.h
@@ -26,13 +26,11 @@
 public:
   static char ID;
 
+  LoongArchDAGToDAGISel() = delete;
+
   explicit LoongArchDAGToDAGISel(LoongArchTargetMachine &TM)
       : SelectionDAGISel(ID, TM) {}
 
-  StringRef getPassName() const override {
-    return "LoongArch DAG->DAG Pattern Instruction Selection";
-  }
-
   bool runOnMachineFunction(MachineFunction &MF) override {
     Subtarget = &MF.getSubtarget<LoongArchSubtarget>();
     return SelectionDAGISel::runOnMachineFunction(MF);
diff --git a/llvm/lib/Target/LoongArch/LoongArchISelDAGToDAG.cpp b/llvm/lib/Target/LoongArch/LoongArchISelDAGToDAG.cpp
--- a/llvm/lib/Target/LoongArch/LoongArchISelDAGToDAG.cpp
+++ b/llvm/lib/Target/LoongArch/LoongArchISelDAGToDAG.cpp
@@ -19,9 +19,12 @@
 using namespace llvm;
 
 #define DEBUG_TYPE "loongarch-isel"
+#define PASS_NAME "LoongArch DAG->DAG Pattern Instruction Selection"
 
 char LoongArchDAGToDAGISel::ID;
 
+INITIALIZE_PASS(LoongArchDAGToDAGISel, DEBUG_TYPE, PASS_NAME, false, false)
+
 void LoongArchDAGToDAGISel::Select(SDNode *Node) {
   // If we have a custom node, we have already selected.
   if (Node->isMachineOpcode()) {
diff --git a/llvm/lib/Target/LoongArch/LoongArchTargetMachine.cpp b/llvm/lib/Target/LoongArch/LoongArchTargetMachine.cpp
--- a/llvm/lib/Target/LoongArch/LoongArchTargetMachine.cpp
+++ b/llvm/lib/Target/LoongArch/LoongArchTargetMachine.cpp
@@ -30,6 +30,7 @@
   RegisterTargetMachine<LoongArchTargetMachine> Y(getTheLoongArch64Target());
   auto *PR = PassRegistry::getPassRegistry();
   initializeLoongArchPreRAExpandPseudoPass(*PR);
+  initializeLoongArchDAGToDAGISelPass(*PR);
 }
 
 static std::string computeDataLayout(const Triple &TT) {
diff --git a/llvm/lib/Target/M68k/M68k.h b/llvm/lib/Target/M68k/M68k.h
--- a/llvm/lib/Target/M68k/M68k.h
+++ b/llvm/lib/Target/M68k/M68k.h
@@ -22,6 +22,7 @@
 class M68kRegisterBankInfo;
 class M68kSubtarget;
 class M68kTargetMachine;
+class PassRegistry;
 
 /// This pass converts a legalized DAG into a M68k-specific DAG, ready for
 /// instruction scheduling.
@@ -52,6 +53,8 @@
 createM68kInstructionSelector(const M68kTargetMachine &, const M68kSubtarget &,
                               const M68kRegisterBankInfo &);
 
+void initializeM68kDAGToDAGISelPass(PassRegistry &);
+
 } // namespace llvm
 
 #endif // LLVM_LIB_TARGET_M68K_M68K_H
diff --git a/llvm/lib/Target/M68k/M68kISelDAGToDAG.cpp b/llvm/lib/Target/M68k/M68kISelDAGToDAG.cpp
--- a/llvm/lib/Target/M68k/M68kISelDAGToDAG.cpp
+++ b/llvm/lib/Target/M68k/M68kISelDAGToDAG.cpp
@@ -39,6 +39,7 @@
 using namespace llvm;
 
 #define DEBUG_TYPE "m68k-isel"
+#define PASS_NAME "M68k DAG->DAG Pattern Instruction Selection"
 
 namespace {
 
@@ -175,13 +176,11 @@
 public:
   static char ID;
 
+  M68kDAGToDAGISel() = delete;
+
   explicit M68kDAGToDAGISel(M68kTargetMachine &TM)
       : SelectionDAGISel(ID, TM), Subtarget(nullptr) {}
 
-  StringRef getPassName() const override {
-    return "M68k DAG->DAG Pattern Instruction Selection";
-  }
-
   bool runOnMachineFunction(MachineFunction &MF) override;
   bool IsProfitableToFold(SDValue N, SDNode *U, SDNode *Root) const override;
 
@@ -314,6 +313,9 @@
 };
 
 char M68kDAGToDAGISel::ID;
+
+INITIALIZE_PASS(M68kDAGToDAGISel, DEBUG_TYPE, PASS_NAME, false, false)
+
 } // namespace
 
 bool M68kDAGToDAGISel::IsProfitableToFold(SDValue N, SDNode *U,
diff --git a/llvm/lib/Target/M68k/M68kTargetMachine.cpp b/llvm/lib/Target/M68k/M68kTargetMachine.cpp
--- a/llvm/lib/Target/M68k/M68kTargetMachine.cpp
+++ b/llvm/lib/Target/M68k/M68kTargetMachine.cpp
@@ -37,6 +37,7 @@
   RegisterTargetMachine<M68kTargetMachine> X(getTheM68kTarget());
   auto *PR = PassRegistry::getPassRegistry();
   initializeGlobalISel(*PR);
+  initializeM68kDAGToDAGISelPass(*PR);
 }
 
 namespace {
diff --git a/llvm/lib/Target/MSP430/MSP430.h b/llvm/lib/Target/MSP430/MSP430.h
--- a/llvm/lib/Target/MSP430/MSP430.h
+++ b/llvm/lib/Target/MSP430/MSP430.h
@@ -34,14 +34,17 @@
 }
 
 namespace llvm {
-  class MSP430TargetMachine;
-  class FunctionPass;
+class FunctionPass;
+class MSP430TargetMachine;
+class PassRegistry;
 
-  FunctionPass *createMSP430ISelDag(MSP430TargetMachine &TM,
-                                    CodeGenOpt::Level OptLevel);
+FunctionPass *createMSP430ISelDag(MSP430TargetMachine &TM,
+                                  CodeGenOpt::Level OptLevel);
 
-  FunctionPass *createMSP430BranchSelectionPass();
+FunctionPass *createMSP430BranchSelectionPass();
 
-} // end namespace llvm;
+void initializeMSP430DAGToDAGISelPass(PassRegistry &);
+
+} // namespace llvm
 
 #endif
diff --git a/llvm/lib/Target/MSP430/MSP430ISelDAGToDAG.cpp b/llvm/lib/Target/MSP430/MSP430ISelDAGToDAG.cpp
--- a/llvm/lib/Target/MSP430/MSP430ISelDAGToDAG.cpp
+++ b/llvm/lib/Target/MSP430/MSP430ISelDAGToDAG.cpp
@@ -30,6 +30,7 @@
 using namespace llvm;
 
 #define DEBUG_TYPE "msp430-isel"
+#define PASS_NAME "MSP430 DAG->DAG Pattern Instruction Selection"
 
 namespace {
   struct MSP430ISelAddressMode {
@@ -92,14 +93,12 @@
   public:
     static char ID;
 
+    MSP430DAGToDAGISel() = delete;
+
     MSP430DAGToDAGISel(MSP430TargetMachine &TM, CodeGenOpt::Level OptLevel)
         : SelectionDAGISel(ID, TM, OptLevel) {}
 
   private:
-    StringRef getPassName() const override {
-      return "MSP430 DAG->DAG Pattern Instruction Selection";
-    }
-
     bool MatchAddress(SDValue N, MSP430ISelAddressMode &AM);
     bool MatchWrapper(SDValue N, MSP430ISelAddressMode &AM);
     bool MatchAddressBase(SDValue N, MSP430ISelAddressMode &AM);
@@ -123,6 +122,8 @@
 
 char MSP430DAGToDAGISel::ID;
 
+INITIALIZE_PASS(MSP430DAGToDAGISel, DEBUG_TYPE, PASS_NAME, false, false)
+
 /// createMSP430ISelDag - This pass converts a legalized DAG into a
 /// MSP430-specific DAG, ready for instruction scheduling.
 ///
diff --git a/llvm/lib/Target/MSP430/MSP430TargetMachine.cpp b/llvm/lib/Target/MSP430/MSP430TargetMachine.cpp
--- a/llvm/lib/Target/MSP430/MSP430TargetMachine.cpp
+++ b/llvm/lib/Target/MSP430/MSP430TargetMachine.cpp
@@ -25,6 +25,8 @@
 extern "C" LLVM_EXTERNAL_VISIBILITY void LLVMInitializeMSP430Target() {
   // Register the target.
   RegisterTargetMachine<MSP430TargetMachine> X(getTheMSP430Target());
+  PassRegistry &PR = *PassRegistry::getPassRegistry();
+  initializeMSP430DAGToDAGISelPass(PR);
 }
 
 static Reloc::Model getEffectiveRelocModel(std::optional<Reloc::Model> RM) {
diff --git a/llvm/lib/Target/Mips/Mips.h b/llvm/lib/Target/Mips/Mips.h
--- a/llvm/lib/Target/Mips/Mips.h
+++ b/llvm/lib/Target/Mips/Mips.h
@@ -18,39 +18,40 @@
 #include "llvm/Target/TargetMachine.h"
 
 namespace llvm {
-  class MipsTargetMachine;
-  class ModulePass;
-  class FunctionPass;
-  class MipsRegisterBankInfo;
-  class MipsSubtarget;
-  class MipsTargetMachine;
-  class InstructionSelector;
-  class PassRegistry;
-
-  ModulePass *createMipsOs16Pass();
-  ModulePass *createMips16HardFloatPass();
-
-  FunctionPass *createMipsModuleISelDagPass();
-  FunctionPass *createMipsOptimizePICCallPass();
-  FunctionPass *createMipsDelaySlotFillerPass();
-  FunctionPass *createMipsBranchExpansion();
-  FunctionPass *createMipsConstantIslandPass();
-  FunctionPass *createMicroMipsSizeReducePass();
-  FunctionPass *createMipsExpandPseudoPass();
-  FunctionPass *createMipsPreLegalizeCombiner();
-  FunctionPass *createMipsPostLegalizeCombiner(bool IsOptNone);
-  FunctionPass *createMipsMulMulBugPass();
-
-  InstructionSelector *createMipsInstructionSelector(const MipsTargetMachine &,
-                                                     MipsSubtarget &,
-                                                     MipsRegisterBankInfo &);
-
-  void initializeMipsDelaySlotFillerPass(PassRegistry &);
-  void initializeMipsBranchExpansionPass(PassRegistry &);
-  void initializeMicroMipsSizeReducePass(PassRegistry &);
-  void initializeMipsPreLegalizerCombinerPass(PassRegistry&);
-  void initializeMipsPostLegalizerCombinerPass(PassRegistry &);
-  void initializeMipsMulMulBugFixPass(PassRegistry&);
-} // end namespace llvm;
+class FunctionPass;
+class InstructionSelector;
+class MipsRegisterBankInfo;
+class MipsSubtarget;
+class MipsTargetMachine;
+class MipsTargetMachine;
+class ModulePass;
+class PassRegistry;
+
+ModulePass *createMipsOs16Pass();
+ModulePass *createMips16HardFloatPass();
+
+FunctionPass *createMipsModuleISelDagPass();
+FunctionPass *createMipsOptimizePICCallPass();
+FunctionPass *createMipsDelaySlotFillerPass();
+FunctionPass *createMipsBranchExpansion();
+FunctionPass *createMipsConstantIslandPass();
+FunctionPass *createMicroMipsSizeReducePass();
+FunctionPass *createMipsExpandPseudoPass();
+FunctionPass *createMipsPreLegalizeCombiner();
+FunctionPass *createMipsPostLegalizeCombiner(bool IsOptNone);
+FunctionPass *createMipsMulMulBugPass();
+
+InstructionSelector *createMipsInstructionSelector(const MipsTargetMachine &,
+                                                   MipsSubtarget &,
+                                                   MipsRegisterBankInfo &);
+
+void initializeMicroMipsSizeReducePass(PassRegistry &);
+void initializeMipsBranchExpansionPass(PassRegistry &);
+void initializeMipsDAGToDAGISelPass(PassRegistry &);
+void initializeMipsDelaySlotFillerPass(PassRegistry &);
+void initializeMipsMulMulBugFixPass(PassRegistry &);
+void initializeMipsPostLegalizerCombinerPass(PassRegistry &);
+void initializeMipsPreLegalizerCombinerPass(PassRegistry &);
+} // namespace llvm
 
 #endif
diff --git a/llvm/lib/Target/Mips/MipsISelDAGToDAG.h b/llvm/lib/Target/Mips/MipsISelDAGToDAG.h
--- a/llvm/lib/Target/Mips/MipsISelDAGToDAG.h
+++ b/llvm/lib/Target/Mips/MipsISelDAGToDAG.h
@@ -32,14 +32,11 @@
 public:
   static char ID;
 
+  MipsDAGToDAGISel() = delete;
+
   explicit MipsDAGToDAGISel(MipsTargetMachine &TM, CodeGenOpt::Level OL)
       : SelectionDAGISel(ID, TM, OL), Subtarget(nullptr) {}
 
-  // Pass Name
-  StringRef getPassName() const override {
-    return "MIPS DAG->DAG Pattern Instruction Selection";
-  }
-
   bool runOnMachineFunction(MachineFunction &MF) override;
 
   void getAnalysisUsage(AnalysisUsage &AU) const override;
diff --git a/llvm/lib/Target/Mips/MipsISelDAGToDAG.cpp b/llvm/lib/Target/Mips/MipsISelDAGToDAG.cpp
--- a/llvm/lib/Target/Mips/MipsISelDAGToDAG.cpp
+++ b/llvm/lib/Target/Mips/MipsISelDAGToDAG.cpp
@@ -36,6 +36,7 @@
 using namespace llvm;
 
 #define DEBUG_TYPE "mips-isel"
+#define PASS_NAME "MIPS DAG->DAG Pattern Instruction Selection"
 
 //===----------------------------------------------------------------------===//
 // Instruction Selector Implementation
@@ -324,3 +325,5 @@
 }
 
 char MipsDAGToDAGISel::ID = 0;
+
+INITIALIZE_PASS(MipsDAGToDAGISel, DEBUG_TYPE, PASS_NAME, false, false)
diff --git a/llvm/lib/Target/Mips/MipsTargetMachine.cpp b/llvm/lib/Target/Mips/MipsTargetMachine.cpp
--- a/llvm/lib/Target/Mips/MipsTargetMachine.cpp
+++ b/llvm/lib/Target/Mips/MipsTargetMachine.cpp
@@ -66,6 +66,7 @@
   initializeMipsPreLegalizerCombinerPass(*PR);
   initializeMipsPostLegalizerCombinerPass(*PR);
   initializeMipsMulMulBugFixPass(*PR);
+  initializeMipsDAGToDAGISelPass(*PR);
 }
 
 static std::string computeDataLayout(const Triple &TT, StringRef CPU,
diff --git a/llvm/lib/Target/NVPTX/NVPTX.h b/llvm/lib/Target/NVPTX/NVPTX.h
--- a/llvm/lib/Target/NVPTX/NVPTX.h
+++ b/llvm/lib/Target/NVPTX/NVPTX.h
@@ -19,9 +19,10 @@
 #include "llvm/Support/CodeGen.h"
 
 namespace llvm {
-class NVPTXTargetMachine;
 class FunctionPass;
 class MachineFunctionPass;
+class NVPTXTargetMachine;
+class PassRegistry;
 
 namespace NVPTXCC {
 enum CondCodes {
@@ -174,7 +175,8 @@
 };
 }
 }
-} // end namespace llvm;
+void initializeNVPTXDAGToDAGISelPass(PassRegistry &);
+} // namespace llvm
 
 // Defines symbolic names for NVPTX registers.  This defines a mapping from
 // register name to register number.
diff --git a/llvm/lib/Target/NVPTX/NVPTXISelDAGToDAG.h b/llvm/lib/Target/NVPTX/NVPTXISelDAGToDAG.h
--- a/llvm/lib/Target/NVPTX/NVPTXISelDAGToDAG.h
+++ b/llvm/lib/Target/NVPTX/NVPTXISelDAGToDAG.h
@@ -40,13 +40,11 @@
 public:
   static char ID;
 
+  NVPTXDAGToDAGISel() = delete;
+
   explicit NVPTXDAGToDAGISel(NVPTXTargetMachine &tm,
                              CodeGenOpt::Level   OptLevel);
 
-  // Pass Name
-  StringRef getPassName() const override {
-    return "NVPTX DAG->DAG Pattern Instruction Selection";
-  }
   bool runOnMachineFunction(MachineFunction &MF) override;
   const NVPTXSubtarget *Subtarget = nullptr;
 
diff --git a/llvm/lib/Target/NVPTX/NVPTXISelDAGToDAG.cpp b/llvm/lib/Target/NVPTX/NVPTXISelDAGToDAG.cpp
--- a/llvm/lib/Target/NVPTX/NVPTXISelDAGToDAG.cpp
+++ b/llvm/lib/Target/NVPTX/NVPTXISelDAGToDAG.cpp
@@ -27,6 +27,7 @@
 using namespace llvm;
 
 #define DEBUG_TYPE "nvptx-isel"
+#define PASS_NAME "NVPTX DAG->DAG Pattern Instruction Selection"
 
 /// createNVPTXISelDag - This pass converts a legalized DAG into a
 /// NVPTX-specific DAG, ready for instruction scheduling.
@@ -37,6 +38,8 @@
 
 char NVPTXDAGToDAGISel::ID = 0;
 
+INITIALIZE_PASS(NVPTXDAGToDAGISel, DEBUG_TYPE, PASS_NAME, false, false)
+
 NVPTXDAGToDAGISel::NVPTXDAGToDAGISel(NVPTXTargetMachine &tm,
                                      CodeGenOpt::Level OptLevel)
     : SelectionDAGISel(ID, tm, OptLevel), TM(tm) {
diff --git a/llvm/lib/Target/NVPTX/NVPTXTargetMachine.cpp b/llvm/lib/Target/NVPTX/NVPTXTargetMachine.cpp
--- a/llvm/lib/Target/NVPTX/NVPTXTargetMachine.cpp
+++ b/llvm/lib/Target/NVPTX/NVPTXTargetMachine.cpp
@@ -63,16 +63,16 @@
 
 namespace llvm {
 
-void initializeNVVMIntrRangePass(PassRegistry&);
-void initializeNVVMReflectPass(PassRegistry&);
 void initializeGenericToNVVMPass(PassRegistry&);
 void initializeNVPTXAllocaHoistingPass(PassRegistry &);
-void initializeNVPTXAtomicLowerPass(PassRegistry &);
 void initializeNVPTXAssignValidGlobalNamesPass(PassRegistry&);
+void initializeNVPTXAtomicLowerPass(PassRegistry &);
 void initializeNVPTXLowerAggrCopiesPass(PassRegistry &);
-void initializeNVPTXLowerArgsPass(PassRegistry &);
 void initializeNVPTXLowerAllocaPass(PassRegistry &);
+void initializeNVPTXLowerArgsPass(PassRegistry &);
 void initializeNVPTXProxyRegErasurePass(PassRegistry &);
+void initializeNVVMIntrRangePass(PassRegistry &);
+void initializeNVVMReflectPass(PassRegistry &);
 
 } // end namespace llvm
 
@@ -94,6 +94,7 @@
   initializeNVPTXLowerAllocaPass(PR);
   initializeNVPTXLowerAggrCopiesPass(PR);
   initializeNVPTXProxyRegErasurePass(PR);
+  initializeNVPTXDAGToDAGISelPass(PR);
 }
 
 static std::string computeDataLayout(bool is64Bit, bool UseShortPointers) {
diff --git a/llvm/lib/Target/PowerPC/PPC.h b/llvm/lib/Target/PowerPC/PPC.h
--- a/llvm/lib/Target/PowerPC/PPC.h
+++ b/llvm/lib/Target/PowerPC/PPC.h
@@ -77,6 +77,7 @@
   void initializePPCMIPeepholePass(PassRegistry&);
   void initializePPCExpandAtomicPseudoPass(PassRegistry &);
   void initializePPCCTRLoopsPass(PassRegistry &);
+  void initializePPCDAGToDAGISelPass(PassRegistry &);
 
   extern char &PPCVSXFMAMutateID;
 
diff --git a/llvm/lib/Target/PowerPC/PPCISelDAGToDAG.cpp b/llvm/lib/Target/PowerPC/PPCISelDAGToDAG.cpp
--- a/llvm/lib/Target/PowerPC/PPCISelDAGToDAG.cpp
+++ b/llvm/lib/Target/PowerPC/PPCISelDAGToDAG.cpp
@@ -69,6 +69,7 @@
 using namespace llvm;
 
 #define DEBUG_TYPE "ppc-codegen"
+#define PASS_NAME "PowerPC DAG->DAG Pattern Instruction Selection"
 
 STATISTIC(NumSextSetcc,
           "Number of (sext(setcc)) nodes expanded into GPR sequence.");
@@ -147,6 +148,8 @@
   public:
     static char ID;
 
+    PPCDAGToDAGISel() = delete;
+
     explicit PPCDAGToDAGISel(PPCTargetMachine &tm, CodeGenOpt::Level OptLevel)
         : SelectionDAGISel(ID, tm, OptLevel), TM(tm) {}
 
@@ -412,10 +415,6 @@
       return true;
     }
 
-    StringRef getPassName() const override {
-      return "PowerPC DAG->DAG Pattern Instruction Selection";
-    }
-
 // Include the pieces autogenerated from the target description.
 #include "PPCGenDAGISel.inc"
 
@@ -449,6 +448,8 @@
 
 char PPCDAGToDAGISel::ID = 0;
 
+INITIALIZE_PASS(PPCDAGToDAGISel, DEBUG_TYPE, PASS_NAME, false, false)
+
 /// getGlobalBaseReg - Output the instructions required to put the
 /// base address to use for accessing globals into a register.
 ///
diff --git a/llvm/lib/Target/PowerPC/PPCTargetMachine.cpp b/llvm/lib/Target/PowerPC/PPCTargetMachine.cpp
--- a/llvm/lib/Target/PowerPC/PPCTargetMachine.cpp
+++ b/llvm/lib/Target/PowerPC/PPCTargetMachine.cpp
@@ -135,6 +135,7 @@
   initializePPCExpandAtomicPseudoPass(PR);
   initializeGlobalISel(PR);
   initializePPCCTRLoopsPass(PR);
+  initializePPCDAGToDAGISelPass(PR);
 }
 
 static bool isLittleEndianTriple(const Triple &T) {
diff --git a/llvm/lib/Target/RISCV/RISCV.h b/llvm/lib/Target/RISCV/RISCV.h
--- a/llvm/lib/Target/RISCV/RISCV.h
+++ b/llvm/lib/Target/RISCV/RISCV.h
@@ -18,9 +18,6 @@
 #include "llvm/Target/TargetMachine.h"
 
 namespace llvm {
-class RISCVRegisterBankInfo;
-class RISCVSubtarget;
-class RISCVTargetMachine;
 class AsmPrinter;
 class FunctionPass;
 class InstructionSelector;
@@ -29,6 +26,9 @@
 class MachineInstr;
 class MachineOperand;
 class PassRegistry;
+class RISCVRegisterBankInfo;
+class RISCVSubtarget;
+class RISCVTargetMachine;
 
 FunctionPass *createRISCVCodeGenPreparePass();
 void initializeRISCVCodeGenPreparePass(PassRegistry &);
@@ -71,6 +71,7 @@
 InstructionSelector *createRISCVInstructionSelector(const RISCVTargetMachine &,
                                                     RISCVSubtarget &,
                                                     RISCVRegisterBankInfo &);
-}
+void initializeRISCVDAGToDAGISelPass(PassRegistry &);
+} // namespace llvm
 
 #endif
diff --git a/llvm/lib/Target/RISCV/RISCVISelDAGToDAG.h b/llvm/lib/Target/RISCV/RISCVISelDAGToDAG.h
--- a/llvm/lib/Target/RISCV/RISCVISelDAGToDAG.h
+++ b/llvm/lib/Target/RISCV/RISCVISelDAGToDAG.h
@@ -26,14 +26,12 @@
 public:
   static char ID;
 
+  RISCVDAGToDAGISel() = delete;
+
   explicit RISCVDAGToDAGISel(RISCVTargetMachine &TargetMachine,
                              CodeGenOpt::Level OptLevel)
       : SelectionDAGISel(ID, TargetMachine, OptLevel) {}
 
-  StringRef getPassName() const override {
-    return "RISCV DAG->DAG Pattern Instruction Selection";
-  }
-
   bool runOnMachineFunction(MachineFunction &MF) override {
     Subtarget = &MF.getSubtarget<RISCVSubtarget>();
     return SelectionDAGISel::runOnMachineFunction(MF);
diff --git a/llvm/lib/Target/RISCV/RISCVISelDAGToDAG.cpp b/llvm/lib/Target/RISCV/RISCVISelDAGToDAG.cpp
--- a/llvm/lib/Target/RISCV/RISCVISelDAGToDAG.cpp
+++ b/llvm/lib/Target/RISCV/RISCVISelDAGToDAG.cpp
@@ -27,6 +27,7 @@
 using namespace llvm;
 
 #define DEBUG_TYPE "riscv-isel"
+#define PASS_NAME "RISCV DAG->DAG Pattern Instruction Selection"
 
 namespace llvm::RISCV {
 #define GET_RISCVVSSEGTable_IMPL
@@ -2909,3 +2910,5 @@
 }
 
 char RISCVDAGToDAGISel::ID = 0;
+
+INITIALIZE_PASS(RISCVDAGToDAGISel, DEBUG_TYPE, PASS_NAME, false, false)
diff --git a/llvm/lib/Target/RISCV/RISCVTargetMachine.cpp b/llvm/lib/Target/RISCV/RISCVTargetMachine.cpp
--- a/llvm/lib/Target/RISCV/RISCVTargetMachine.cpp
+++ b/llvm/lib/Target/RISCV/RISCVTargetMachine.cpp
@@ -66,6 +66,7 @@
   initializeRISCVPreRAExpandPseudoPass(*PR);
   initializeRISCVExpandPseudoPass(*PR);
   initializeRISCVInsertVSETVLIPass(*PR);
+  initializeRISCVDAGToDAGISelPass(*PR);
 }
 
 static StringRef computeDataLayout(const Triple &TT) {
diff --git a/llvm/lib/Target/Sparc/Sparc.h b/llvm/lib/Target/Sparc/Sparc.h
--- a/llvm/lib/Target/Sparc/Sparc.h
+++ b/llvm/lib/Target/Sparc/Sparc.h
@@ -19,19 +19,20 @@
 #include "llvm/Target/TargetMachine.h"
 
 namespace llvm {
-  class FunctionPass;
-  class SparcTargetMachine;
-  class AsmPrinter;
-  class MCInst;
-  class MachineInstr;
+class AsmPrinter;
+class FunctionPass;
+class MCInst;
+class MachineInstr;
+class PassRegistry;
+class SparcTargetMachine;
 
-  FunctionPass *createSparcISelDag(SparcTargetMachine &TM);
-  FunctionPass *createSparcDelaySlotFillerPass();
+FunctionPass *createSparcISelDag(SparcTargetMachine &TM);
+FunctionPass *createSparcDelaySlotFillerPass();
 
-  void LowerSparcMachineInstrToMCInst(const MachineInstr *MI,
-                                      MCInst &OutMI,
-                                      AsmPrinter &AP);
-} // end namespace llvm;
+void LowerSparcMachineInstrToMCInst(const MachineInstr *MI, MCInst &OutMI,
+                                    AsmPrinter &AP);
+void initializeSparcDAGToDAGISelPass(PassRegistry &);
+} // namespace llvm
 
 namespace llvm {
   // Enums corresponding to Sparc condition codes, both icc's and fcc's.  These
diff --git a/llvm/lib/Target/Sparc/SparcISelDAGToDAG.cpp b/llvm/lib/Target/Sparc/SparcISelDAGToDAG.cpp
--- a/llvm/lib/Target/Sparc/SparcISelDAGToDAG.cpp
+++ b/llvm/lib/Target/Sparc/SparcISelDAGToDAG.cpp
@@ -19,6 +19,9 @@
 #include "llvm/Support/raw_ostream.h"
 using namespace llvm;
 
+#define DEBUG_TYPE "sparc-isel"
+#define PASS_NAME "SPARC DAG->DAG Pattern Instruction Selection"
+
 //===----------------------------------------------------------------------===//
 // Instruction Selector Implementation
 //===----------------------------------------------------------------------===//
@@ -35,6 +38,8 @@
 public:
   static char ID;
 
+  SparcDAGToDAGISel() = delete;
+
   explicit SparcDAGToDAGISel(SparcTargetMachine &tm) : SelectionDAGISel(ID, tm) {}
 
   bool runOnMachineFunction(MachineFunction &MF) override {
@@ -54,10 +59,6 @@
                                     unsigned ConstraintID,
                                     std::vector<SDValue> &OutOps) override;
 
-  StringRef getPassName() const override {
-    return "SPARC DAG->DAG Pattern Instruction Selection";
-  }
-
   // Include the pieces autogenerated from the target description.
 #include "SparcGenDAGISel.inc"
 
@@ -69,6 +70,8 @@
 
 char SparcDAGToDAGISel::ID = 0;
 
+INITIALIZE_PASS(SparcDAGToDAGISel, DEBUG_TYPE, PASS_NAME, false, false)
+
 SDNode* SparcDAGToDAGISel::getGlobalBaseReg() {
   Register GlobalBaseReg = Subtarget->getInstrInfo()->getGlobalBaseReg(MF);
   return CurDAG->getRegister(GlobalBaseReg,
diff --git a/llvm/lib/Target/Sparc/SparcTargetMachine.cpp b/llvm/lib/Target/Sparc/SparcTargetMachine.cpp
--- a/llvm/lib/Target/Sparc/SparcTargetMachine.cpp
+++ b/llvm/lib/Target/Sparc/SparcTargetMachine.cpp
@@ -26,6 +26,9 @@
   RegisterTargetMachine<SparcV8TargetMachine> X(getTheSparcTarget());
   RegisterTargetMachine<SparcV9TargetMachine> Y(getTheSparcV9Target());
   RegisterTargetMachine<SparcelTargetMachine> Z(getTheSparcelTarget());
+
+  PassRegistry &PR = *PassRegistry::getPassRegistry();
+  initializeSparcDAGToDAGISelPass(PR);
 }
 
 static std::string computeDataLayout(const Triple &T, bool is64Bit) {
diff --git a/llvm/lib/Target/SystemZ/SystemZ.h b/llvm/lib/Target/SystemZ/SystemZ.h
--- a/llvm/lib/Target/SystemZ/SystemZ.h
+++ b/llvm/lib/Target/SystemZ/SystemZ.h
@@ -18,9 +18,9 @@
 #include "llvm/Support/CodeGen.h"
 
 namespace llvm {
-class SystemZTargetMachine;
 class FunctionPass;
 class PassRegistry;
+class SystemZTargetMachine;
 
 namespace SystemZ {
 // Condition-code mask values.
@@ -198,12 +198,13 @@
 FunctionPass *createSystemZPostRewritePass(SystemZTargetMachine &TM);
 FunctionPass *createSystemZTDCPass();
 
+void initializeSystemZCopyPhysRegsPass(PassRegistry &);
+void initializeSystemZDAGToDAGISelPass(PassRegistry &);
 void initializeSystemZElimComparePass(PassRegistry &);
-void initializeSystemZShortenInstPass(PassRegistry &);
-void initializeSystemZLongBranchPass(PassRegistry &);
 void initializeSystemZLDCleanupPass(PassRegistry &);
-void initializeSystemZCopyPhysRegsPass(PassRegistry &);
+void initializeSystemZLongBranchPass(PassRegistry &);
 void initializeSystemZPostRewritePass(PassRegistry &);
+void initializeSystemZShortenInstPass(PassRegistry &);
 void initializeSystemZTDCPassPass(PassRegistry &);
 
 } // end namespace llvm
diff --git a/llvm/lib/Target/SystemZ/SystemZISelDAGToDAG.cpp b/llvm/lib/Target/SystemZ/SystemZISelDAGToDAG.cpp
--- a/llvm/lib/Target/SystemZ/SystemZISelDAGToDAG.cpp
+++ b/llvm/lib/Target/SystemZ/SystemZISelDAGToDAG.cpp
@@ -21,6 +21,7 @@
 using namespace llvm;
 
 #define DEBUG_TYPE "systemz-isel"
+#define PASS_NAME "SystemZ DAG->DAG Pattern Instruction Selection"
 
 namespace {
 // Used to build addressing modes.
@@ -347,6 +348,8 @@
 public:
   static char ID;
 
+  SystemZDAGToDAGISel() = delete;
+
   SystemZDAGToDAGISel(SystemZTargetMachine &TM, CodeGenOpt::Level OptLevel)
       : SelectionDAGISel(ID, TM, OptLevel) {}
 
@@ -363,11 +366,6 @@
     return SelectionDAGISel::runOnMachineFunction(MF);
   }
 
-  // Override MachineFunctionPass.
-  StringRef getPassName() const override {
-    return "SystemZ DAG->DAG Pattern Instruction Selection";
-  }
-
   // Override SelectionDAGISel.
   void Select(SDNode *Node) override;
   bool SelectInlineAsmMemoryOperand(const SDValue &Op, unsigned ConstraintID,
@@ -382,6 +380,8 @@
 
 char SystemZDAGToDAGISel::ID = 0;
 
+INITIALIZE_PASS(SystemZDAGToDAGISel, DEBUG_TYPE, PASS_NAME, false, false)
+
 FunctionPass *llvm::createSystemZISelDag(SystemZTargetMachine &TM,
                                          CodeGenOpt::Level OptLevel) {
   return new SystemZDAGToDAGISel(TM, OptLevel);
diff --git a/llvm/lib/Target/SystemZ/SystemZTargetMachine.cpp b/llvm/lib/Target/SystemZ/SystemZTargetMachine.cpp
--- a/llvm/lib/Target/SystemZ/SystemZTargetMachine.cpp
+++ b/llvm/lib/Target/SystemZ/SystemZTargetMachine.cpp
@@ -40,6 +40,7 @@
   initializeSystemZShortenInstPass(PR);
   initializeSystemZPostRewritePass(PR);
   initializeSystemZTDCPassPass(PR);
+  initializeSystemZDAGToDAGISelPass(PR);
 }
 
 static std::string computeDataLayout(const Triple &TT) {
diff --git a/llvm/lib/Target/VE/VE.h b/llvm/lib/Target/VE/VE.h
--- a/llvm/lib/Target/VE/VE.h
+++ b/llvm/lib/Target/VE/VE.h
@@ -22,14 +22,16 @@
 #include "llvm/Target/TargetMachine.h"
 
 namespace llvm {
-class FunctionPass;
-class VETargetMachine;
 class AsmPrinter;
+class FunctionPass;
 class MCInst;
 class MachineInstr;
+class PassRegistry;
+class VETargetMachine;
 
 FunctionPass *createVEISelDag(VETargetMachine &TM);
 FunctionPass *createLVLGenPass();
+void initializeVEDAGToDAGISelPass(PassRegistry &);
 
 void LowerVEMachineInstrToMCInst(const MachineInstr *MI, MCInst &OutMI,
                                  AsmPrinter &AP);
diff --git a/llvm/lib/Target/VE/VEISelDAGToDAG.cpp b/llvm/lib/Target/VE/VEISelDAGToDAG.cpp
--- a/llvm/lib/Target/VE/VEISelDAGToDAG.cpp
+++ b/llvm/lib/Target/VE/VEISelDAGToDAG.cpp
@@ -20,6 +20,9 @@
 #include "llvm/Support/raw_ostream.h"
 using namespace llvm;
 
+#define DEBUG_TYPE "ve-isel"
+#define PASS_NAME "VE DAG->DAG Pattern Instruction Selection"
+
 //===--------------------------------------------------------------------===//
 /// VEDAGToDAGISel - VE specific code to select VE machine
 /// instructions for SelectionDAG operations.
@@ -33,6 +36,8 @@
 public:
   static char ID;
 
+  VEDAGToDAGISel() = delete;
+
   explicit VEDAGToDAGISel(VETargetMachine &tm) : SelectionDAGISel(ID, tm) {}
 
   bool runOnMachineFunction(MachineFunction &MF) override {
@@ -56,10 +61,6 @@
                                     unsigned ConstraintID,
                                     std::vector<SDValue> &OutOps) override;
 
-  StringRef getPassName() const override {
-    return "VE DAG->DAG Pattern Instruction Selection";
-  }
-
   // Include the pieces autogenerated from the target description.
 #include "VEGenDAGISel.inc"
 
@@ -73,6 +74,8 @@
 
 char VEDAGToDAGISel::ID = 0;
 
+INITIALIZE_PASS(VEDAGToDAGISel, DEBUG_TYPE, PASS_NAME, false, false)
+
 bool VEDAGToDAGISel::selectADDRrri(SDValue Addr, SDValue &Base, SDValue &Index,
                                    SDValue &Offset) {
   if (Addr.getOpcode() == ISD::FrameIndex)
diff --git a/llvm/lib/Target/VE/VETargetMachine.cpp b/llvm/lib/Target/VE/VETargetMachine.cpp
--- a/llvm/lib/Target/VE/VETargetMachine.cpp
+++ b/llvm/lib/Target/VE/VETargetMachine.cpp
@@ -27,6 +27,9 @@
 extern "C" LLVM_EXTERNAL_VISIBILITY void LLVMInitializeVETarget() {
   // Register the target.
   RegisterTargetMachine<VETargetMachine> X(getTheVETarget());
+
+  PassRegistry &PR = *PassRegistry::getPassRegistry();
+  initializeVEDAGToDAGISelPass(PR);
 }
 
 static std::string computeDataLayout(const Triple &T) {
diff --git a/llvm/lib/Target/WebAssembly/WebAssembly.h b/llvm/lib/Target/WebAssembly/WebAssembly.h
--- a/llvm/lib/Target/WebAssembly/WebAssembly.h
+++ b/llvm/lib/Target/WebAssembly/WebAssembly.h
@@ -57,31 +57,32 @@
 ModulePass *createWebAssemblyMCLowerPrePass();
 
 // PassRegistry initialization declarations.
-void initializeWebAssemblyAddMissingPrototypesPass(PassRegistry &);
-void initializeWebAssemblyLowerEmscriptenEHSjLjPass(PassRegistry &);
 void initializeFixFunctionBitcastsPass(PassRegistry &);
 void initializeOptimizeReturnedPass(PassRegistry &);
+void initializeWebAssemblyAddMissingPrototypesPass(PassRegistry &);
 void initializeWebAssemblyArgumentMovePass(PassRegistry &);
-void initializeWebAssemblySetP2AlignOperandsPass(PassRegistry &);
-void initializeWebAssemblyReplacePhysRegsPass(PassRegistry &);
-void initializeWebAssemblyNullifyDebugValueListsPass(PassRegistry &);
-void initializeWebAssemblyOptimizeLiveIntervalsPass(PassRegistry &);
-void initializeWebAssemblyMemIntrinsicResultsPass(PassRegistry &);
-void initializeWebAssemblyRegStackifyPass(PassRegistry &);
-void initializeWebAssemblyRegColoringPass(PassRegistry &);
-void initializeWebAssemblyFixBrTableDefaultsPass(PassRegistry &);
-void initializeWebAssemblyFixIrreducibleControlFlowPass(PassRegistry &);
-void initializeWebAssemblyLateEHPreparePass(PassRegistry &);
-void initializeWebAssemblyExceptionInfoPass(PassRegistry &);
 void initializeWebAssemblyCFGSortPass(PassRegistry &);
 void initializeWebAssemblyCFGStackifyPass(PassRegistry &);
+void initializeWebAssemblyDAGToDAGISelPass(PassRegistry &);
+void initializeWebAssemblyDebugFixupPass(PassRegistry &);
+void initializeWebAssemblyExceptionInfoPass(PassRegistry &);
 void initializeWebAssemblyExplicitLocalsPass(PassRegistry &);
+void initializeWebAssemblyFixBrTableDefaultsPass(PassRegistry &);
+void initializeWebAssemblyFixIrreducibleControlFlowPass(PassRegistry &);
+void initializeWebAssemblyLateEHPreparePass(PassRegistry &);
 void initializeWebAssemblyLowerBrUnlessPass(PassRegistry &);
-void initializeWebAssemblyRegNumberingPass(PassRegistry &);
-void initializeWebAssemblyDebugFixupPass(PassRegistry &);
-void initializeWebAssemblyPeepholePass(PassRegistry &);
-void initializeWebAssemblyMCLowerPrePassPass(PassRegistry &);
+void initializeWebAssemblyLowerEmscriptenEHSjLjPass(PassRegistry &);
 void initializeWebAssemblyLowerRefTypesIntPtrConvPass(PassRegistry &);
+void initializeWebAssemblyMCLowerPrePassPass(PassRegistry &);
+void initializeWebAssemblyMemIntrinsicResultsPass(PassRegistry &);
+void initializeWebAssemblyNullifyDebugValueListsPass(PassRegistry &);
+void initializeWebAssemblyOptimizeLiveIntervalsPass(PassRegistry &);
+void initializeWebAssemblyPeepholePass(PassRegistry &);
+void initializeWebAssemblyRegColoringPass(PassRegistry &);
+void initializeWebAssemblyRegNumberingPass(PassRegistry &);
+void initializeWebAssemblyRegStackifyPass(PassRegistry &);
+void initializeWebAssemblyReplacePhysRegsPass(PassRegistry &);
+void initializeWebAssemblySetP2AlignOperandsPass(PassRegistry &);
 
 namespace WebAssembly {
 enum TargetIndex {
diff --git a/llvm/lib/Target/WebAssembly/WebAssemblyISelDAGToDAG.cpp b/llvm/lib/Target/WebAssembly/WebAssemblyISelDAGToDAG.cpp
--- a/llvm/lib/Target/WebAssembly/WebAssemblyISelDAGToDAG.cpp
+++ b/llvm/lib/Target/WebAssembly/WebAssemblyISelDAGToDAG.cpp
@@ -29,6 +29,7 @@
 using namespace llvm;
 
 #define DEBUG_TYPE "wasm-isel"
+#define PASS_NAME "WebAssembly Instruction Selection"
 
 //===--------------------------------------------------------------------===//
 /// WebAssembly-specific code to select WebAssembly machine instructions for
@@ -43,14 +44,12 @@
 public:
   static char ID;
 
+  WebAssemblyDAGToDAGISel() = delete;
+
   WebAssemblyDAGToDAGISel(WebAssemblyTargetMachine &TM,
                           CodeGenOpt::Level OptLevel)
       : SelectionDAGISel(ID, TM, OptLevel), Subtarget(nullptr) {}
 
-  StringRef getPassName() const override {
-    return "WebAssembly Instruction Selection";
-  }
-
   bool runOnMachineFunction(MachineFunction &MF) override {
     LLVM_DEBUG(dbgs() << "********** ISelDAGToDAG **********\n"
                          "********** Function: "
@@ -86,6 +85,8 @@
 
 char WebAssemblyDAGToDAGISel::ID;
 
+INITIALIZE_PASS(WebAssemblyDAGToDAGISel, DEBUG_TYPE, PASS_NAME, false, false)
+
 void WebAssemblyDAGToDAGISel::PreprocessISelDAG() {
   // Stack objects that should be allocated to locals are hoisted to WebAssembly
   // locals when they are first used.  However for those without uses, we hoist
diff --git a/llvm/lib/Target/WebAssembly/WebAssemblyTargetMachine.cpp b/llvm/lib/Target/WebAssembly/WebAssemblyTargetMachine.cpp
--- a/llvm/lib/Target/WebAssembly/WebAssemblyTargetMachine.cpp
+++ b/llvm/lib/Target/WebAssembly/WebAssemblyTargetMachine.cpp
@@ -82,6 +82,7 @@
   initializeWebAssemblyMCLowerPrePassPass(PR);
   initializeWebAssemblyLowerRefTypesIntPtrConvPass(PR);
   initializeWebAssemblyFixBrTableDefaultsPass(PR);
+  initializeWebAssemblyDAGToDAGISelPass(PR);
 }
 
 //===----------------------------------------------------------------------===//
diff --git a/llvm/lib/Target/XCore/XCore.h b/llvm/lib/Target/XCore/XCore.h
--- a/llvm/lib/Target/XCore/XCore.h
+++ b/llvm/lib/Target/XCore/XCore.h
@@ -21,6 +21,7 @@
 namespace llvm {
   class FunctionPass;
   class ModulePass;
+  class PassRegistry;
   class TargetMachine;
   class XCoreTargetMachine;
 
@@ -30,6 +31,7 @@
   FunctionPass *createXCoreISelDag(XCoreTargetMachine &TM,
                                    CodeGenOpt::Level OptLevel);
   ModulePass *createXCoreLowerThreadLocalPass();
+  void initializeXCoreDAGToDAGISelPass(PassRegistry &);
 
 } // end namespace llvm;
 
diff --git a/llvm/lib/Target/XCore/XCoreISelDAGToDAG.cpp b/llvm/lib/Target/XCore/XCoreISelDAGToDAG.cpp
--- a/llvm/lib/Target/XCore/XCoreISelDAGToDAG.cpp
+++ b/llvm/lib/Target/XCore/XCoreISelDAGToDAG.cpp
@@ -31,6 +31,9 @@
 #include "llvm/Support/raw_ostream.h"
 using namespace llvm;
 
+#define DEBUG_TYPE "xcore-isel"
+#define PASS_NAME "XCore DAG->DAG Pattern Instruction Selection"
+
 /// XCoreDAGToDAGISel - XCore specific code to select XCore machine
 /// instructions for SelectionDAG operations.
 ///
@@ -40,6 +43,8 @@
   public:
     static char ID;
 
+    XCoreDAGToDAGISel() = delete;
+
     XCoreDAGToDAGISel(XCoreTargetMachine &TM, CodeGenOpt::Level OptLevel)
       : SelectionDAGISel(ID, TM, OptLevel) {}
 
@@ -69,10 +74,6 @@
     bool SelectInlineAsmMemoryOperand(const SDValue &Op, unsigned ConstraintID,
                                       std::vector<SDValue> &OutOps) override;
 
-    StringRef getPassName() const override {
-      return "XCore DAG->DAG Pattern Instruction Selection";
-    }
-
     // Include the pieces autogenerated from the target description.
   #include "XCoreGenDAGISel.inc"
   };
@@ -80,6 +81,8 @@
 
 char XCoreDAGToDAGISel::ID = 0;
 
+INITIALIZE_PASS(XCoreDAGToDAGISel, DEBUG_TYPE, PASS_NAME, false, false)
+
 /// createXCoreISelDag - This pass converts a legalized DAG into a
 /// XCore-specific DAG, ready for instruction scheduling.
 ///
diff --git a/llvm/lib/Target/XCore/XCoreTargetMachine.cpp b/llvm/lib/Target/XCore/XCoreTargetMachine.cpp
--- a/llvm/lib/Target/XCore/XCoreTargetMachine.cpp
+++ b/llvm/lib/Target/XCore/XCoreTargetMachine.cpp
@@ -105,6 +105,8 @@
 // Force static initialization.
 extern "C" LLVM_EXTERNAL_VISIBILITY void LLVMInitializeXCoreTarget() {
   RegisterTargetMachine<XCoreTargetMachine> X(getTheXCoreTarget());
+  PassRegistry &PR = *PassRegistry::getPassRegistry();
+  initializeXCoreDAGToDAGISelPass(PR);
 }
 
 TargetTransformInfo