diff --git a/llvm/lib/Target/AArch64/AArch64.h b/llvm/lib/Target/AArch64/AArch64.h --- a/llvm/lib/Target/AArch64/AArch64.h +++ b/llvm/lib/Target/AArch64/AArch64.h @@ -76,35 +76,36 @@ void initializeAArch64AdvSIMDScalarPass(PassRegistry&); void initializeAArch64BranchTargetsPass(PassRegistry&); void initializeAArch64CFIFixupPass(PassRegistry&); -void initializeAArch64CollectLOHPass(PassRegistry&); -void initializeAArch64CondBrTuningPass(PassRegistry &); +void initializeAArch64CollectLOHPass(PassRegistry &); void initializeAArch64CompressJumpTablesPass(PassRegistry&); -void initializeAArch64ConditionalComparesPass(PassRegistry&); +void initializeAArch64CondBrTuningPass(PassRegistry &); void initializeAArch64ConditionOptimizerPass(PassRegistry&); +void initializeAArch64ConditionalComparesPass(PassRegistry &); +void initializeAArch64DAGToDAGISelPass(PassRegistry &); void initializeAArch64DeadRegisterDefinitionsPass(PassRegistry&); -void initializeAArch64ExpandPseudoPass(PassRegistry&); -void initializeAArch64SLSHardeningPass(PassRegistry&); -void initializeAArch64SpeculationHardeningPass(PassRegistry&); +void initializeAArch64ExpandPseudoPass(PassRegistry &); void initializeAArch64KCFIPass(PassRegistry &); void initializeAArch64LoadStoreOptPass(PassRegistry&); void initializeAArch64LowerHomogeneousPrologEpilogPass(PassRegistry &); void initializeAArch64MIPeepholeOptPass(PassRegistry &); -void initializeAArch64SIMDInstrOptPass(PassRegistry&); void initializeAArch64O0PreLegalizerCombinerPass(PassRegistry &); -void initializeAArch64PreLegalizerCombinerPass(PassRegistry&); void initializeAArch64PostLegalizerCombinerPass(PassRegistry &); void initializeAArch64PostLegalizerLoweringPass(PassRegistry &); void initializeAArch64PostSelectOptimizePass(PassRegistry &); +void initializeAArch64PreLegalizerCombinerPass(PassRegistry &); void initializeAArch64PromoteConstantPass(PassRegistry&); void initializeAArch64RedundantCopyEliminationPass(PassRegistry&); +void initializeAArch64SIMDInstrOptPass(PassRegistry &); +void initializeAArch64SLSHardeningPass(PassRegistry &); +void initializeAArch64SpeculationHardeningPass(PassRegistry &); +void initializeAArch64StackTaggingPass(PassRegistry &); +void initializeAArch64StackTaggingPreRAPass(PassRegistry &); void initializeAArch64StorePairSuppressPass(PassRegistry&); void initializeFalkorHWPFFixPass(PassRegistry&); void initializeFalkorMarkStridedAccessesLegacyPass(PassRegistry&); void initializeLDTLSCleanupPass(PassRegistry&); void initializeSMEABIPass(PassRegistry &); -void initializeSVEIntrinsicOptsPass(PassRegistry&); -void initializeAArch64StackTaggingPass(PassRegistry&); -void initializeAArch64StackTaggingPreRAPass(PassRegistry&); +void initializeSVEIntrinsicOptsPass(PassRegistry &); } // end namespace llvm #endif diff --git a/llvm/lib/Target/AArch64/AArch64ISelDAGToDAG.cpp b/llvm/lib/Target/AArch64/AArch64ISelDAGToDAG.cpp --- a/llvm/lib/Target/AArch64/AArch64ISelDAGToDAG.cpp +++ b/llvm/lib/Target/AArch64/AArch64ISelDAGToDAG.cpp @@ -29,6 +29,7 @@ using namespace llvm; #define DEBUG_TYPE "aarch64-isel" +#define PASS_NAME "AArch64 Instruction Selection" //===--------------------------------------------------------------------===// /// AArch64DAGToDAGISel - AArch64 specific code to select AArch64 machine @@ -51,9 +52,7 @@ CodeGenOpt::Level OptLevel) : SelectionDAGISel(ID, tm, OptLevel), Subtarget(nullptr) {} - StringRef getPassName() const override { - return "AArch64 Instruction Selection"; - } + StringRef getPassName() const override { return PASS_NAME; } bool runOnMachineFunction(MachineFunction &MF) override { Subtarget = &MF.getSubtarget(); @@ -425,6 +424,8 @@ char AArch64DAGToDAGISel::ID = 0; +INITIALIZE_PASS(AArch64DAGToDAGISel, DEBUG_TYPE, PASS_NAME, false, false) + /// isIntImmediate - This method tests to see if the node is a constant /// operand. If so Imm will receive the 32-bit value. static bool isIntImmediate(const SDNode *N, uint64_t &Imm) { @@ -5547,7 +5548,7 @@ /// AArch64-specific DAG, ready for instruction scheduling. FunctionPass *llvm::createAArch64ISelDag(AArch64TargetMachine &TM, CodeGenOpt::Level OptLevel) { - return new AArch64DAGToDAGISel(TM, OptLevel); + return new AArch64DAGToDAGISel(&TM, OptLevel); } /// When \p PredVT is a scalable vector predicate in the form diff --git a/llvm/lib/Target/AArch64/AArch64TargetMachine.cpp b/llvm/lib/Target/AArch64/AArch64TargetMachine.cpp --- a/llvm/lib/Target/AArch64/AArch64TargetMachine.cpp +++ b/llvm/lib/Target/AArch64/AArch64TargetMachine.cpp @@ -237,6 +237,7 @@ initializeAArch64StackTaggingPass(*PR); initializeAArch64StackTaggingPreRAPass(*PR); initializeAArch64LowerHomogeneousPrologEpilogPass(*PR); + initializeAArch64DAGToDAGISelPass(*PR); } //===----------------------------------------------------------------------===//