diff --git a/llvm/lib/Target/AArch64/SVEInstrFormats.td b/llvm/lib/Target/AArch64/SVEInstrFormats.td
--- a/llvm/lib/Target/AArch64/SVEInstrFormats.td
+++ b/llvm/lib/Target/AArch64/SVEInstrFormats.td
@@ -659,6 +659,8 @@
 multiclass sve_int_pfalse<bits<6> opc, string asm> {
   def NAME : sve_int_pfalse<opc, asm>;
 
+  def : InstAlias<"pfalse\t$Pd", (!cast<Instruction>(NAME) PNR8:$Pd), 0>;
+
   def : Pat<(nxv16i1 immAllZerosV), (!cast<Instruction>(NAME))>;
   def : Pat<(nxv8i1 immAllZerosV), (!cast<Instruction>(NAME))>;
   def : Pat<(nxv4i1 immAllZerosV), (!cast<Instruction>(NAME))>;
diff --git a/llvm/test/MC/AArch64/SVE/pfalse-diagnostics.s b/llvm/test/MC/AArch64/SVE/pfalse-diagnostics.s
--- a/llvm/test/MC/AArch64/SVE/pfalse-diagnostics.s
+++ b/llvm/test/MC/AArch64/SVE/pfalse-diagnostics.s
@@ -8,3 +8,10 @@
 // CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid predicate register
 // CHECK-NEXT: pfalse p15.h
 // CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
+
+// Support until pn15.b
+
+pfalse pn16.b
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand for instruction
+// CHECK-NEXT: pfalse pn16.b
+// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
diff --git a/llvm/test/MC/AArch64/SVE/pfalse.s b/llvm/test/MC/AArch64/SVE/pfalse.s
--- a/llvm/test/MC/AArch64/SVE/pfalse.s
+++ b/llvm/test/MC/AArch64/SVE/pfalse.s
@@ -14,3 +14,9 @@
 // CHECK-ENCODING: [0x0f,0xe4,0x18,0x25]
 // CHECK-ERROR: instruction requires: sve or sme
 // CHECK-UNKNOWN: 2518e40f <unknown>
+
+pfalse pn15.b
+// CHECK-INST: pfalse  p15.b
+// CHECK-ENCODING: [0x0f,0xe4,0x18,0x25]
+// CHECK-ERROR: instruction requires: sve or sme
+// CHECK-UNKNOWN: 2518e40f <unknown>