diff --git a/llvm/include/llvm/CodeGen/GlobalISel/Legalizer.h b/llvm/include/llvm/CodeGen/GlobalISel/Legalizer.h
--- a/llvm/include/llvm/CodeGen/GlobalISel/Legalizer.h
+++ b/llvm/include/llvm/CodeGen/GlobalISel/Legalizer.h
@@ -22,6 +22,7 @@
 
 #include "llvm/ADT/ArrayRef.h"
 #include "llvm/ADT/StringRef.h"
+#include "llvm/CodeGen/GlobalISel/GISelKnownBits.h"
 #include "llvm/CodeGen/MachineFunction.h"
 #include "llvm/CodeGen/MachineFunctionPass.h"
 
@@ -75,7 +76,7 @@
   legalizeMachineFunction(MachineFunction &MF, const LegalizerInfo &LI,
                           ArrayRef<GISelChangeObserver *> AuxObservers,
                           LostDebugLocObserver &LocObserver,
-                          MachineIRBuilder &MIRBuilder);
+                          MachineIRBuilder &MIRBuilder, GISelKnownBits *KB);
 };
 } // End namespace llvm.
 
diff --git a/llvm/include/llvm/CodeGen/GlobalISel/LegalizerHelper.h b/llvm/include/llvm/CodeGen/GlobalISel/LegalizerHelper.h
--- a/llvm/include/llvm/CodeGen/GlobalISel/LegalizerHelper.h
+++ b/llvm/include/llvm/CodeGen/GlobalISel/LegalizerHelper.h
@@ -21,6 +21,7 @@
 #define LLVM_CODEGEN_GLOBALISEL_LEGALIZERHELPER_H
 
 #include "llvm/CodeGen/GlobalISel/CallLowering.h"
+#include "llvm/CodeGen/GlobalISel/GISelKnownBits.h"
 #include "llvm/CodeGen/RuntimeLibcalls.h"
 #include "llvm/CodeGen/TargetOpcodes.h"
 
@@ -56,6 +57,7 @@
   MachineRegisterInfo &MRI;
   const LegalizerInfo &LI;
   const TargetLowering &TLI;
+  GISelKnownBits *KB;
 
 public:
   enum LegalizeResult {
@@ -74,11 +76,15 @@
   /// Expose LegalizerInfo so the clients can re-use.
   const LegalizerInfo &getLegalizerInfo() const { return LI; }
   const TargetLowering &getTargetLowering() const { return TLI; }
+  GISelKnownBits *getKnownBits() const { return KB; }
 
   LegalizerHelper(MachineFunction &MF, GISelChangeObserver &Observer,
                   MachineIRBuilder &B);
   LegalizerHelper(MachineFunction &MF, const LegalizerInfo &LI,
                   GISelChangeObserver &Observer, MachineIRBuilder &B);
+  LegalizerHelper(MachineFunction &MF, const LegalizerInfo &LI,
+                  GISelChangeObserver &Observer, MachineIRBuilder &B,
+                  GISelKnownBits *KB);
 
   /// Replace \p MI by a sequence of legal instructions that can implement the
   /// same operation. Note that this means \p MI may be deleted, so any iterator
diff --git a/llvm/lib/CodeGen/GlobalISel/Legalizer.cpp b/llvm/lib/CodeGen/GlobalISel/Legalizer.cpp
--- a/llvm/lib/CodeGen/GlobalISel/Legalizer.cpp
+++ b/llvm/lib/CodeGen/GlobalISel/Legalizer.cpp
@@ -18,6 +18,7 @@
 #include "llvm/CodeGen/GlobalISel/CSEInfo.h"
 #include "llvm/CodeGen/GlobalISel/CSEMIRBuilder.h"
 #include "llvm/CodeGen/GlobalISel/GISelChangeObserver.h"
+#include "llvm/CodeGen/GlobalISel/GISelKnownBits.h"
 #include "llvm/CodeGen/GlobalISel/GISelWorkList.h"
 #include "llvm/CodeGen/GlobalISel/LegalizationArtifactCombiner.h"
 #include "llvm/CodeGen/GlobalISel/LegalizerHelper.h"
@@ -75,6 +76,7 @@
                       false)
 INITIALIZE_PASS_DEPENDENCY(TargetPassConfig)
 INITIALIZE_PASS_DEPENDENCY(GISelCSEAnalysisWrapperPass)
+INITIALIZE_PASS_DEPENDENCY(GISelKnownBitsAnalysis)
 INITIALIZE_PASS_END(Legalizer, DEBUG_TYPE,
                     "Legalize the Machine IR a function's Machine IR", false,
                     false)
@@ -85,6 +87,8 @@
   AU.addRequired<TargetPassConfig>();
   AU.addRequired<GISelCSEAnalysisWrapperPass>();
   AU.addPreserved<GISelCSEAnalysisWrapperPass>();
+  AU.addRequired<GISelKnownBitsAnalysis>();
+  AU.addPreserved<GISelKnownBitsAnalysis>();
   getSelectionDAGFallbackAnalysisUsage(AU);
   MachineFunctionPass::getAnalysisUsage(AU);
 }
@@ -173,7 +177,8 @@
 Legalizer::legalizeMachineFunction(MachineFunction &MF, const LegalizerInfo &LI,
                                    ArrayRef<GISelChangeObserver *> AuxObservers,
                                    LostDebugLocObserver &LocObserver,
-                                   MachineIRBuilder &MIRBuilder) {
+                                   MachineIRBuilder &MIRBuilder,
+                                   GISelKnownBits *KB) {
   MIRBuilder.setMF(MF);
   MachineRegisterInfo &MRI = MF.getRegInfo();
 
@@ -212,7 +217,7 @@
   // Now install the observer as the delegate to MF.
   // This will keep all the observers notified about new insertions/deletions.
   RAIIMFObsDelInstaller Installer(MF, WrapperObserver);
-  LegalizerHelper Helper(MF, LI, WrapperObserver, MIRBuilder);
+  LegalizerHelper Helper(MF, LI, WrapperObserver, MIRBuilder, KB);
   LegalizationArtifactCombiner ArtCombiner(MIRBuilder, MRI, LI);
   bool Changed = false;
   SmallVector<MachineInstr *, 128> RetryList;
@@ -338,9 +343,12 @@
   if (VerifyDebugLocs > DebugLocVerifyLevel::None)
     AuxObservers.push_back(&LocObserver);
 
+  // This allows Known Bits Analysis in the legalizer.
+  GISelKnownBits *KB = &getAnalysis<GISelKnownBitsAnalysis>().get(MF);
+
   const LegalizerInfo &LI = *MF.getSubtarget().getLegalizerInfo();
-  MFResult Result =
-      legalizeMachineFunction(MF, LI, AuxObservers, LocObserver, *MIRBuilder);
+  MFResult Result = legalizeMachineFunction(MF, LI, AuxObservers, LocObserver,
+                                            *MIRBuilder, KB);
 
   if (Result.FailedOn) {
     reportGISelFailure(MF, TPC, MORE, "gisel-legalize",
diff --git a/llvm/lib/CodeGen/GlobalISel/LegalizerHelper.cpp b/llvm/lib/CodeGen/GlobalISel/LegalizerHelper.cpp
--- a/llvm/lib/CodeGen/GlobalISel/LegalizerHelper.cpp
+++ b/llvm/lib/CodeGen/GlobalISel/LegalizerHelper.cpp
@@ -15,6 +15,7 @@
 #include "llvm/CodeGen/GlobalISel/LegalizerHelper.h"
 #include "llvm/CodeGen/GlobalISel/CallLowering.h"
 #include "llvm/CodeGen/GlobalISel/GISelChangeObserver.h"
+#include "llvm/CodeGen/GlobalISel/GISelKnownBits.h"
 #include "llvm/CodeGen/GlobalISel/GenericMachineInstrs.h"
 #include "llvm/CodeGen/GlobalISel/LegalizerInfo.h"
 #include "llvm/CodeGen/GlobalISel/LostDebugLocObserver.h"
@@ -102,7 +103,7 @@
                                  MachineIRBuilder &Builder)
     : MIRBuilder(Builder), Observer(Observer), MRI(MF.getRegInfo()),
       LI(*MF.getSubtarget().getLegalizerInfo()),
-      TLI(*MF.getSubtarget().getTargetLowering()) { }
+      TLI(*MF.getSubtarget().getTargetLowering()), KB(nullptr) {}
 
 LegalizerHelper::LegalizerHelper(MachineFunction &MF, const LegalizerInfo &LI,
                                  GISelChangeObserver &Observer,
@@ -110,6 +111,13 @@
   : MIRBuilder(B), Observer(Observer), MRI(MF.getRegInfo()), LI(LI),
     TLI(*MF.getSubtarget().getTargetLowering()) { }
 
+LegalizerHelper::LegalizerHelper(MachineFunction &MF, const LegalizerInfo &LI,
+                                 GISelChangeObserver &Observer,
+                                 MachineIRBuilder &B,
+                                 GISelKnownBits *KB = nullptr)
+    : MIRBuilder(B), Observer(Observer), MRI(MF.getRegInfo()), LI(LI),
+      TLI(*MF.getSubtarget().getTargetLowering()), KB(KB) {}
+
 LegalizerHelper::LegalizeResult
 LegalizerHelper::legalizeInstrStep(MachineInstr &MI,
                                    LostDebugLocObserver &LocObserver) {
diff --git a/llvm/lib/Target/AMDGPU/AMDGPULegalizerInfo.cpp b/llvm/lib/Target/AMDGPU/AMDGPULegalizerInfo.cpp
--- a/llvm/lib/Target/AMDGPU/AMDGPULegalizerInfo.cpp
+++ b/llvm/lib/Target/AMDGPU/AMDGPULegalizerInfo.cpp
@@ -2907,6 +2907,7 @@
   using Carry = SmallVector<Register, 2>;
 
   MachineIRBuilder &B = Helper.MIRBuilder;
+  GISelKnownBits &KB = *Helper.getKnownBits();
 
   const LLT S1 = LLT::scalar(1);
   const LLT S32 = LLT::scalar(32);
@@ -2926,6 +2927,13 @@
     return Zero64;
   };
 
+  auto length = Src0.size();
+  SmallVector<KnownBits, 2> Src0KB, Src1KB;
+  for (unsigned i = 0; i < length; ++i) {
+      Src0KB.push_back(KB.getKnownBits(Src0[i]));
+      Src1KB.push_back(KB.getKnownBits(Src1[i]));
+  }
+
   // Merge the given carries into the 32-bit LocalAccum, which is modified
   // in-place.
   //
@@ -2988,9 +2996,15 @@
         if (LocalAccum.size() == 1 &&
             (!UsePartialMad64_32 || !CarryIn.empty())) {
           do {
+            // Skip multiplication if one of the operands is 0
             unsigned j1 = DstIndex - j0;
+            bool AtLeastOneArgIsZero = Src0KB[j0].isZero() || Src1KB[j1].isZero(); 
+            if (AtLeastOneArgIsZero) {
+              ++j0;
+              continue;
+            }
             auto Mul = B.buildMul(S32, Src0[j0], Src1[j1]);
-            if (!LocalAccum[0]) {
+            if (!LocalAccum[0] || KB.getKnownBits(LocalAccum[0]).isZero()) {
               LocalAccum[0] = Mul.getReg(0);
             } else {
               if (CarryIn.empty()) {
@@ -3030,12 +3044,15 @@
 
           do {
             unsigned j1 = DstIndex - j0;
+            bool AtLeastOneArgIsZero = Src0KB[j0].isZero() || Src1KB[j1].isZero(); 
+            if (!AtLeastOneArgIsZero) {
             auto Mad = B.buildInstr(AMDGPU::G_AMDGPU_MAD_U64_U32, {S64, S1},
                                     {Src0[j0], Src1[j1], Tmp});
             Tmp = Mad.getReg(0);
             if (!HaveSmallAccum)
               CarryOut.push_back(Mad.getReg(1));
             HaveSmallAccum = false;
+            }
             ++j0;
           } while (j0 <= DstIndex);
 
@@ -3162,6 +3179,12 @@
   // in an even-aligned VGPR.
   const bool SeparateOddAlignedProducts = ST.hasFullRate64Ops();
 
+  const bool Src0IsZero = Helper.getKnownBits()->getKnownBits(Src0).isZero();
+  const bool Src1IsZero = Helper.getKnownBits()->getKnownBits(Src1).isZero();
+  
+  if (Src0IsZero || Src1IsZero) {
+    B.buildConstant(DstReg, 0);
+  } else {
   LLT S32 = LLT::scalar(32);
   SmallVector<Register, 2> Src0Parts, Src1Parts;
   for (unsigned i = 0; i < NumParts; ++i) {
@@ -3176,6 +3199,7 @@
                 SeparateOddAlignedProducts);
 
   B.buildMerge(DstReg, AccumRegs);
+  }
   MI.eraseFromParent();
   return true;
 
diff --git a/llvm/test/CodeGen/AMDGPU/GlobalISel/mul-known-bits.i64.ll b/llvm/test/CodeGen/AMDGPU/GlobalISel/mul-known-bits.i64.ll
--- a/llvm/test/CodeGen/AMDGPU/GlobalISel/mul-known-bits.i64.ll
+++ b/llvm/test/CodeGen/AMDGPU/GlobalISel/mul-known-bits.i64.ll
@@ -74,9 +74,8 @@
 ; FUNC-NEXT:    global_load_dwordx2 v[0:1], v3, s[2:3]
 ; FUNC-NEXT:    s_waitcnt vmcnt(0)
 ; FUNC-NEXT:    v_mad_u64_u32 v[2:3], s0, v4, v0, 0
-; FUNC-NEXT:    v_mul_lo_u32 v1, v4, v1
-; FUNC-NEXT:    v_mul_lo_u32 v0, 0, v0
-; FUNC-NEXT:    v_add3_u32 v3, v3, v1, v0
+; FUNC-NEXT:    v_mul_lo_u32 v0, v4, v1
+; FUNC-NEXT:    v_add_nc_u32_e32 v3, v3, v0
 ; FUNC-NEXT:    v_mov_b32_e32 v0, 0
 ; FUNC-NEXT:    global_store_dwordx2 v0, v[2:3], s[4:5]
 ; FUNC-NEXT:    s_endpgm
@@ -105,8 +104,6 @@
 ; FUNC-NEXT:    global_load_dword v2, v0, s[2:3]
 ; FUNC-NEXT:    s_waitcnt vmcnt(0)
 ; FUNC-NEXT:    v_mad_u64_u32 v[0:1], s0, v1, v2, 0
-; FUNC-NEXT:    v_mul_lo_u32 v2, 0, v2
-; FUNC-NEXT:    v_add_nc_u32_e32 v1, v1, v2
 ; FUNC-NEXT:    v_mov_b32_e32 v2, 0
 ; FUNC-NEXT:    global_store_dwordx2 v2, v[0:1], s[4:5]
 ; FUNC-NEXT:    s_endpgm
@@ -136,9 +133,8 @@
 ; FUNC-NEXT:    global_load_dwordx2 v[0:1], v2, s[2:3]
 ; FUNC-NEXT:    s_waitcnt vmcnt(0)
 ; FUNC-NEXT:    v_mad_u64_u32 v[2:3], s0, v4, v0, 0
-; FUNC-NEXT:    v_mul_lo_u32 v1, v4, v1
-; FUNC-NEXT:    v_mul_lo_u32 v0, 0, v0
-; FUNC-NEXT:    v_add3_u32 v3, v3, v1, v0
+; FUNC-NEXT:    v_mul_lo_u32 v0, v4, v1
+; FUNC-NEXT:    v_add_nc_u32_e32 v3, v3, v0
 ; FUNC-NEXT:    v_mov_b32_e32 v0, 0
 ; FUNC-NEXT:    global_store_dwordx2 v0, v[2:3], s[4:5]
 ; FUNC-NEXT:    s_endpgm
@@ -158,21 +154,18 @@
 ; FUNC-LABEL: v_mul_i64_and_a_lo:
 ; FUNC:       ; %bb.0:
 ; FUNC-NEXT:    s_clause 0x1
-; FUNC-NEXT:    s_load_dwordx2 s[2:3], s[0:1], 0x34
 ; FUNC-NEXT:    s_load_dwordx4 s[4:7], s[0:1], 0x24
+; FUNC-NEXT:    s_load_dwordx2 s[2:3], s[0:1], 0x34
 ; FUNC-NEXT:    v_lshlrev_b32_e32 v4, 3, v0
 ; FUNC-NEXT:    s_waitcnt lgkmcnt(0)
 ; FUNC-NEXT:    s_clause 0x1
-; FUNC-NEXT:    global_load_dwordx2 v[0:1], v4, s[2:3]
-; FUNC-NEXT:    global_load_dwordx2 v[2:3], v4, s[6:7]
+; FUNC-NEXT:    global_load_dwordx2 v[0:1], v4, s[6:7]
+; FUNC-NEXT:    global_load_dwordx2 v[2:3], v4, s[2:3]
 ; FUNC-NEXT:    s_waitcnt vmcnt(1)
-; FUNC-NEXT:    v_mad_u64_u32 v[4:5], s0, 0, v0, 0
-; FUNC-NEXT:    v_mul_lo_u32 v1, 0, v1
-; FUNC-NEXT:    s_waitcnt vmcnt(0)
-; FUNC-NEXT:    v_mul_lo_u32 v0, v3, v0
-; FUNC-NEXT:    v_add3_u32 v5, v5, v1, v0
 ; FUNC-NEXT:    v_mov_b32_e32 v0, 0
-; FUNC-NEXT:    global_store_dwordx2 v0, v[4:5], s[4:5]
+; FUNC-NEXT:    s_waitcnt vmcnt(0)
+; FUNC-NEXT:    v_mul_lo_u32 v1, v1, v2
+; FUNC-NEXT:    global_store_dwordx2 v0, v[0:1], s[4:5]
 ; FUNC-NEXT:    s_endpgm
   %tid = call i32 @llvm.amdgcn.workitem.id.x()
   %gep.a = getelementptr inbounds i64, i64 addrspace(1)* %aptr, i32 %tid
@@ -192,19 +185,18 @@
 ; FUNC-NEXT:    s_clause 0x1
 ; FUNC-NEXT:    s_load_dwordx4 s[4:7], s[0:1], 0x24
 ; FUNC-NEXT:    s_load_dwordx2 s[2:3], s[0:1], 0x34
-; FUNC-NEXT:    v_lshlrev_b32_e32 v4, 3, v0
+; FUNC-NEXT:    v_lshlrev_b32_e32 v3, 3, v0
+; FUNC-NEXT:    ; kill: killed $vgpr3
+; FUNC-NEXT:    ; kill: killed $sgpr6_sgpr7
 ; FUNC-NEXT:    s_waitcnt lgkmcnt(0)
 ; FUNC-NEXT:    s_clause 0x1
-; FUNC-NEXT:    global_load_dwordx2 v[0:1], v4, s[6:7]
-; FUNC-NEXT:    global_load_dwordx2 v[2:3], v4, s[2:3]
-; FUNC-NEXT:    s_waitcnt vmcnt(1)
-; FUNC-NEXT:    v_mad_u64_u32 v[4:5], s0, v0, 0, 0
+; FUNC-NEXT:    global_load_dwordx2 v[0:1], v3, s[6:7]
+; FUNC-NEXT:    global_load_dwordx2 v[1:2], v3, s[2:3]
+; FUNC-NEXT:    ; kill: killed $sgpr2_sgpr3
 ; FUNC-NEXT:    s_waitcnt vmcnt(0)
-; FUNC-NEXT:    v_mul_lo_u32 v0, v0, v3
-; FUNC-NEXT:    v_mul_lo_u32 v1, v1, 0
-; FUNC-NEXT:    v_add3_u32 v5, v5, v0, v1
+; FUNC-NEXT:    v_mul_lo_u32 v1, v0, v2
 ; FUNC-NEXT:    v_mov_b32_e32 v0, 0
-; FUNC-NEXT:    global_store_dwordx2 v0, v[4:5], s[4:5]
+; FUNC-NEXT:    global_store_dwordx2 v0, v[0:1], s[4:5]
 ; FUNC-NEXT:    s_endpgm
   %tid = call i32 @llvm.amdgcn.workitem.id.x()
   %gep.a = getelementptr inbounds i64, i64 addrspace(1)* %aptr, i32 %tid
@@ -282,35 +274,27 @@
 ; FUNC-NEXT:    s_clause 0x1
 ; FUNC-NEXT:    s_load_dwordx4 s[4:7], s[0:1], 0x24
 ; FUNC-NEXT:    s_load_dwordx2 s[2:3], s[0:1], 0x34
-; FUNC-NEXT:    v_lshlrev_b32_e32 v0, 3, v0
+; FUNC-NEXT:    v_lshlrev_b32_e32 v4, 3, v0
 ; FUNC-NEXT:    s_waitcnt lgkmcnt(0)
 ; FUNC-NEXT:    s_clause 0x1
-; FUNC-NEXT:    global_load_dwordx2 v[2:3], v0, s[6:7]
-; FUNC-NEXT:    global_load_dwordx2 v[4:5], v0, s[2:3]
-; FUNC-NEXT:    ; implicit-def: $vgpr0_vgpr1
+; FUNC-NEXT:    global_load_dwordx2 v[2:3], v4, s[6:7]
+; FUNC-NEXT:    global_load_dwordx2 v[0:1], v4, s[2:3]
 ; FUNC-NEXT:    s_waitcnt vmcnt(1)
 ; FUNC-NEXT:    v_cmp_ge_u64_e32 vcc_lo, 0, v[2:3]
+; FUNC-NEXT:    s_waitcnt vmcnt(0)
+; FUNC-NEXT:    v_mul_lo_u32 v1, v2, v1
 ; FUNC-NEXT:    s_and_saveexec_b32 s0, vcc_lo
 ; FUNC-NEXT:    s_xor_b32 s0, exec_lo, s0
-; FUNC-NEXT:    s_cbranch_execz .LBB9_2
 ; FUNC-NEXT:  ; %bb.1: ; %else
-; FUNC-NEXT:    s_waitcnt vmcnt(0)
-; FUNC-NEXT:    v_mad_u64_u32 v[0:1], s1, v2, v4, 0
-; FUNC-NEXT:    v_mul_lo_u32 v2, v2, v5
-; FUNC-NEXT:    v_mul_lo_u32 v3, 0, v4
-; FUNC-NEXT:    ; implicit-def: $vgpr4_vgpr5
-; FUNC-NEXT:    v_add3_u32 v1, v1, v2, v3
-; FUNC-NEXT:    ; implicit-def: $vgpr2_vgpr3
-; FUNC-NEXT:  .LBB9_2: ; %Flow
+; FUNC-NEXT:    v_mad_u64_u32 v[2:3], s1, v2, v0, 0
+; FUNC-NEXT:    v_add_nc_u32_e32 v3, v3, v1
+; FUNC-NEXT:    v_mov_b32_e32 v0, v2
+; FUNC-NEXT:    v_mov_b32_e32 v1, v3
+; FUNC-NEXT:  ; %bb.2: ; %Flow
 ; FUNC-NEXT:    s_andn2_saveexec_b32 s0, s0
-; FUNC-NEXT:    s_cbranch_execz .LBB9_4
 ; FUNC-NEXT:  ; %bb.3: ; %if
-; FUNC-NEXT:    v_mad_u64_u32 v[0:1], s1, v2, 0, 0
-; FUNC-NEXT:    s_waitcnt vmcnt(0)
-; FUNC-NEXT:    v_mul_lo_u32 v2, v2, v5
-; FUNC-NEXT:    v_mul_lo_u32 v3, 0, 0
-; FUNC-NEXT:    v_add3_u32 v1, v1, v2, v3
-; FUNC-NEXT:  .LBB9_4: ; %endif
+; FUNC-NEXT:    v_mov_b32_e32 v0, 0
+; FUNC-NEXT:  ; %bb.4: ; %endif
 ; FUNC-NEXT:    s_or_b32 exec_lo, exec_lo, s0
 ; FUNC-NEXT:    v_mov_b32_e32 v2, 0
 ; FUNC-NEXT:    global_store_dwordx2 v2, v[0:1], s[4:5]
diff --git a/llvm/test/CodeGen/AMDGPU/GlobalISel/sdiv.i64.ll b/llvm/test/CodeGen/AMDGPU/GlobalISel/sdiv.i64.ll
--- a/llvm/test/CodeGen/AMDGPU/GlobalISel/sdiv.i64.ll
+++ b/llvm/test/CodeGen/AMDGPU/GlobalISel/sdiv.i64.ll
@@ -1035,89 +1035,88 @@
 ; CHECK-NEXT:    v_addc_u32_e32 v6, vcc, v6, v3, vcc
 ; CHECK-NEXT:    v_mad_u64_u32 v[2:3], s[4:5], s6, v5, 0
 ; CHECK-NEXT:    v_ashrrev_i32_e32 v7, 31, v1
-; CHECK-NEXT:    v_add_i32_e32 v0, vcc, v0, v7
+; CHECK-NEXT:    v_add_i32_e32 v8, vcc, v0, v7
 ; CHECK-NEXT:    v_mad_u64_u32 v[3:4], s[4:5], s6, v6, v[3:4]
-; CHECK-NEXT:    v_addc_u32_e32 v1, vcc, v1, v7, vcc
-; CHECK-NEXT:    v_mad_u64_u32 v[3:4], s[4:5], -1, v5, v[3:4]
-; CHECK-NEXT:    v_xor_b32_e32 v4, v0, v7
-; CHECK-NEXT:    v_mul_lo_u32 v0, v6, v2
-; CHECK-NEXT:    v_mul_lo_u32 v8, v5, v3
-; CHECK-NEXT:    v_xor_b32_e32 v9, v1, v7
-; CHECK-NEXT:    v_mul_hi_u32 v1, v5, v2
+; CHECK-NEXT:    v_addc_u32_e32 v9, vcc, v1, v7, vcc
+; CHECK-NEXT:    v_mad_u64_u32 v[0:1], s[4:5], -1, v5, v[3:4]
+; CHECK-NEXT:    v_xor_b32_e32 v3, v8, v7
+; CHECK-NEXT:    v_mul_lo_u32 v1, v6, v2
+; CHECK-NEXT:    v_mul_lo_u32 v8, v5, v0
+; CHECK-NEXT:    v_xor_b32_e32 v4, v9, v7
+; CHECK-NEXT:    v_mul_hi_u32 v9, v5, v2
 ; CHECK-NEXT:    v_mul_hi_u32 v2, v6, v2
-; CHECK-NEXT:    v_add_i32_e32 v0, vcc, v0, v8
-; CHECK-NEXT:    v_cndmask_b32_e64 v8, 0, 1, vcc
-; CHECK-NEXT:    v_add_i32_e32 v0, vcc, v0, v1
-; CHECK-NEXT:    v_cndmask_b32_e64 v0, 0, 1, vcc
-; CHECK-NEXT:    v_mul_lo_u32 v1, v6, v3
-; CHECK-NEXT:    v_add_i32_e32 v0, vcc, v8, v0
-; CHECK-NEXT:    v_mul_hi_u32 v8, v5, v3
-; CHECK-NEXT:    v_add_i32_e32 v1, vcc, v1, v2
-; CHECK-NEXT:    v_cndmask_b32_e64 v2, 0, 1, vcc
 ; CHECK-NEXT:    v_add_i32_e32 v1, vcc, v1, v8
 ; CHECK-NEXT:    v_cndmask_b32_e64 v8, 0, 1, vcc
-; CHECK-NEXT:    v_add_i32_e32 v2, vcc, v2, v8
-; CHECK-NEXT:    v_mul_hi_u32 v3, v6, v3
-; CHECK-NEXT:    v_add_i32_e32 v0, vcc, v1, v0
+; CHECK-NEXT:    v_add_i32_e32 v1, vcc, v1, v9
 ; CHECK-NEXT:    v_cndmask_b32_e64 v1, 0, 1, vcc
+; CHECK-NEXT:    v_mul_lo_u32 v9, v6, v0
+; CHECK-NEXT:    v_add_i32_e32 v1, vcc, v8, v1
+; CHECK-NEXT:    v_mul_hi_u32 v8, v5, v0
+; CHECK-NEXT:    v_add_i32_e32 v2, vcc, v9, v2
+; CHECK-NEXT:    v_cndmask_b32_e64 v9, 0, 1, vcc
+; CHECK-NEXT:    v_add_i32_e32 v2, vcc, v2, v8
+; CHECK-NEXT:    v_cndmask_b32_e64 v8, 0, 1, vcc
+; CHECK-NEXT:    v_add_i32_e32 v8, vcc, v9, v8
+; CHECK-NEXT:    v_mul_hi_u32 v0, v6, v0
 ; CHECK-NEXT:    v_add_i32_e32 v1, vcc, v2, v1
-; CHECK-NEXT:    v_add_i32_e32 v1, vcc, v3, v1
-; CHECK-NEXT:    v_add_i32_e32 v0, vcc, v5, v0
-; CHECK-NEXT:    v_addc_u32_e32 v1, vcc, v6, v1, vcc
-; CHECK-NEXT:    v_mul_lo_u32 v2, v9, v0
-; CHECK-NEXT:    v_mul_lo_u32 v3, v4, v1
-; CHECK-NEXT:    v_mul_hi_u32 v5, v4, v0
-; CHECK-NEXT:    v_mul_hi_u32 v0, v9, v0
+; CHECK-NEXT:    v_cndmask_b32_e64 v2, 0, 1, vcc
+; CHECK-NEXT:    v_add_i32_e32 v2, vcc, v8, v2
+; CHECK-NEXT:    v_add_i32_e32 v0, vcc, v0, v2
+; CHECK-NEXT:    v_add_i32_e32 v1, vcc, v5, v1
+; CHECK-NEXT:    v_addc_u32_e32 v0, vcc, v6, v0, vcc
+; CHECK-NEXT:    v_mul_lo_u32 v2, v4, v1
+; CHECK-NEXT:    v_mul_lo_u32 v5, v3, v0
+; CHECK-NEXT:    v_mul_hi_u32 v8, v3, v1
+; CHECK-NEXT:    v_mul_hi_u32 v1, v4, v1
 ; CHECK-NEXT:    s_movk_i32 s6, 0x1000
-; CHECK-NEXT:    v_add_i32_e32 v2, vcc, v2, v3
-; CHECK-NEXT:    v_cndmask_b32_e64 v3, 0, 1, vcc
 ; CHECK-NEXT:    v_add_i32_e32 v2, vcc, v2, v5
+; CHECK-NEXT:    v_cndmask_b32_e64 v5, 0, 1, vcc
+; CHECK-NEXT:    v_add_i32_e32 v2, vcc, v2, v8
 ; CHECK-NEXT:    v_cndmask_b32_e64 v2, 0, 1, vcc
-; CHECK-NEXT:    v_mul_lo_u32 v5, v9, v1
-; CHECK-NEXT:    v_add_i32_e32 v2, vcc, v3, v2
-; CHECK-NEXT:    v_mul_hi_u32 v3, v4, v1
-; CHECK-NEXT:    v_add_i32_e32 v0, vcc, v5, v0
+; CHECK-NEXT:    v_mul_lo_u32 v8, v4, v0
+; CHECK-NEXT:    v_add_i32_e32 v2, vcc, v5, v2
+; CHECK-NEXT:    v_mul_hi_u32 v5, v3, v0
+; CHECK-NEXT:    v_add_i32_e32 v1, vcc, v8, v1
+; CHECK-NEXT:    v_cndmask_b32_e64 v8, 0, 1, vcc
+; CHECK-NEXT:    v_add_i32_e32 v1, vcc, v1, v5
 ; CHECK-NEXT:    v_cndmask_b32_e64 v5, 0, 1, vcc
-; CHECK-NEXT:    v_add_i32_e32 v0, vcc, v0, v3
-; CHECK-NEXT:    v_cndmask_b32_e64 v3, 0, 1, vcc
-; CHECK-NEXT:    v_add_i32_e32 v3, vcc, v5, v3
-; CHECK-NEXT:    v_add_i32_e32 v5, vcc, v0, v2
-; CHECK-NEXT:    v_mul_hi_u32 v6, v9, v1
-; CHECK-NEXT:    v_mad_u64_u32 v[0:1], s[4:5], s6, v5, 0
+; CHECK-NEXT:    v_add_i32_e32 v5, vcc, v8, v5
+; CHECK-NEXT:    v_add_i32_e32 v8, vcc, v1, v2
+; CHECK-NEXT:    v_mul_hi_u32 v9, v4, v0
+; CHECK-NEXT:    v_mad_u64_u32 v[0:1], s[4:5], s6, v8, 0
 ; CHECK-NEXT:    v_cndmask_b32_e64 v2, 0, 1, vcc
-; CHECK-NEXT:    v_add_i32_e32 v2, vcc, v3, v2
-; CHECK-NEXT:    v_add_i32_e32 v3, vcc, v6, v2
-; CHECK-NEXT:    v_mad_u64_u32 v[1:2], s[4:5], s6, v3, v[1:2]
-; CHECK-NEXT:    v_sub_i32_e32 v0, vcc, v4, v0
-; CHECK-NEXT:    v_mad_u64_u32 v[1:2], s[4:5], 0, v5, v[1:2]
+; CHECK-NEXT:    v_add_i32_e32 v2, vcc, v5, v2
+; CHECK-NEXT:    v_add_i32_e32 v5, vcc, v9, v2
+; CHECK-NEXT:    v_mad_u64_u32 v[1:2], s[4:5], s6, v5, v[1:2]
+; CHECK-NEXT:    v_sub_i32_e32 v0, vcc, v3, v0
+; CHECK-NEXT:    v_subb_u32_e64 v2, s[4:5], v4, v1, vcc
+; CHECK-NEXT:    v_sub_i32_e64 v1, s[4:5], v4, v1
 ; CHECK-NEXT:    v_mov_b32_e32 v6, 0x1000
-; CHECK-NEXT:    s_bfe_i32 s6, -1, 0x10000
-; CHECK-NEXT:    v_subb_u32_e64 v2, s[4:5], v9, v1, vcc
-; CHECK-NEXT:    v_sub_i32_e64 v1, s[4:5], v9, v1
 ; CHECK-NEXT:    v_subbrev_u32_e32 v1, vcc, 0, v1, vcc
+; CHECK-NEXT:    s_bfe_i32 s6, -1, 0x10000
 ; CHECK-NEXT:    v_cmp_ge_u32_e64 s[4:5], v0, v6
 ; CHECK-NEXT:    v_sub_i32_e32 v0, vcc, v0, v6
-; CHECK-NEXT:    v_cndmask_b32_e64 v4, 0, -1, s[4:5]
-; CHECK-NEXT:    v_mov_b32_e32 v8, s6
+; CHECK-NEXT:    v_cndmask_b32_e64 v3, 0, -1, s[4:5]
+; CHECK-NEXT:    v_mov_b32_e32 v4, s6
 ; CHECK-NEXT:    v_cmp_eq_u32_e64 s[4:5], 0, v2
 ; CHECK-NEXT:    v_subbrev_u32_e32 v1, vcc, 0, v1, vcc
-; CHECK-NEXT:    v_cndmask_b32_e64 v2, v8, v4, s[4:5]
-; CHECK-NEXT:    v_add_i32_e32 v4, vcc, 1, v5
-; CHECK-NEXT:    v_addc_u32_e32 v8, vcc, 0, v3, vcc
+; CHECK-NEXT:    v_cndmask_b32_e64 v2, v4, v3, s[4:5]
+; CHECK-NEXT:    v_add_i32_e32 v3, vcc, 1, v8
+; CHECK-NEXT:    v_addc_u32_e32 v4, vcc, 0, v5, vcc
 ; CHECK-NEXT:    s_bfe_i32 s4, -1, 0x10000
 ; CHECK-NEXT:    v_cmp_ge_u32_e32 vcc, v0, v6
 ; CHECK-NEXT:    v_cndmask_b32_e64 v0, 0, -1, vcc
 ; CHECK-NEXT:    v_mov_b32_e32 v6, s4
 ; CHECK-NEXT:    v_cmp_eq_u32_e32 vcc, 0, v1
 ; CHECK-NEXT:    v_cndmask_b32_e32 v0, v6, v0, vcc
-; CHECK-NEXT:    v_add_i32_e32 v1, vcc, 1, v4
-; CHECK-NEXT:    v_addc_u32_e32 v6, vcc, 0, v8, vcc
+; CHECK-NEXT:    v_add_i32_e32 v1, vcc, 1, v3
+; CHECK-NEXT:    v_addc_u32_e32 v6, vcc, 0, v4, vcc
 ; CHECK-NEXT:    v_cmp_ne_u32_e32 vcc, 0, v0
-; CHECK-NEXT:    v_cndmask_b32_e32 v0, v4, v1, vcc
-; CHECK-NEXT:    v_cndmask_b32_e32 v1, v8, v6, vcc
+; CHECK-NEXT:    v_cndmask_b32_e32 v0, v3, v1, vcc
+; CHECK-NEXT:    v_cndmask_b32_e32 v1, v4, v6, vcc
 ; CHECK-NEXT:    v_cmp_ne_u32_e32 vcc, 0, v2
-; CHECK-NEXT:    v_cndmask_b32_e32 v0, v5, v0, vcc
-; CHECK-NEXT:    v_cndmask_b32_e32 v1, v3, v1, vcc
+; CHECK-NEXT:    v_cndmask_b32_e32 v0, v8, v0, vcc
+; CHECK-NEXT:    v_cndmask_b32_e32 v1, v5, v1, vcc
 ; CHECK-NEXT:    v_xor_b32_e32 v0, v0, v7
 ; CHECK-NEXT:    v_xor_b32_e32 v1, v1, v7
 ; CHECK-NEXT:    v_sub_i32_e32 v0, vcc, v0, v7
@@ -1437,88 +1436,87 @@
 ; CGP-NEXT:    v_add_i32_e32 v6, vcc, v9, v6
 ; CGP-NEXT:    v_add_i32_e32 v5, vcc, v5, v6
 ; CGP-NEXT:    v_add_i32_e32 v9, vcc, v7, v4
-; CGP-NEXT:    v_addc_u32_e32 v8, vcc, v8, v5, vcc
-; CGP-NEXT:    v_mad_u64_u32 v[5:6], s[4:5], s6, v9, 0
-; CGP-NEXT:    v_mov_b32_e32 v4, v6
-; CGP-NEXT:    v_mad_u64_u32 v[6:7], s[4:5], s6, v8, v[4:5]
-; CGP-NEXT:    v_ashrrev_i32_e32 v4, 31, v1
-; CGP-NEXT:    v_add_i32_e32 v0, vcc, v0, v4
-; CGP-NEXT:    v_mad_u64_u32 v[6:7], s[4:5], -1, v9, v[6:7]
-; CGP-NEXT:    v_addc_u32_e32 v1, vcc, v1, v4, vcc
-; CGP-NEXT:    v_xor_b32_e32 v10, v0, v4
-; CGP-NEXT:    v_mul_lo_u32 v0, v8, v5
-; CGP-NEXT:    v_mul_lo_u32 v7, v9, v6
-; CGP-NEXT:    v_xor_b32_e32 v11, v1, v4
-; CGP-NEXT:    v_mul_hi_u32 v1, v9, v5
-; CGP-NEXT:    v_mul_hi_u32 v5, v8, v5
-; CGP-NEXT:    v_add_i32_e32 v0, vcc, v0, v7
-; CGP-NEXT:    v_cndmask_b32_e64 v7, 0, 1, vcc
-; CGP-NEXT:    v_add_i32_e32 v0, vcc, v0, v1
-; CGP-NEXT:    v_cndmask_b32_e64 v0, 0, 1, vcc
-; CGP-NEXT:    v_mul_lo_u32 v1, v8, v6
-; CGP-NEXT:    v_add_i32_e32 v0, vcc, v7, v0
+; CGP-NEXT:    v_mad_u64_u32 v[6:7], s[4:5], s6, v9, 0
+; CGP-NEXT:    v_addc_u32_e32 v10, vcc, v8, v5, vcc
+; CGP-NEXT:    v_ashrrev_i32_e32 v5, 31, v1
+; CGP-NEXT:    v_mov_b32_e32 v4, v7
+; CGP-NEXT:    v_mad_u64_u32 v[7:8], s[4:5], s6, v10, v[4:5]
+; CGP-NEXT:    v_add_i32_e32 v4, vcc, v0, v5
+; CGP-NEXT:    v_addc_u32_e32 v11, vcc, v1, v5, vcc
+; CGP-NEXT:    v_mad_u64_u32 v[0:1], s[4:5], -1, v9, v[7:8]
+; CGP-NEXT:    v_xor_b32_e32 v8, v4, v5
+; CGP-NEXT:    v_mul_lo_u32 v1, v10, v6
+; CGP-NEXT:    v_mul_lo_u32 v4, v9, v0
 ; CGP-NEXT:    v_mul_hi_u32 v7, v9, v6
-; CGP-NEXT:    v_add_i32_e32 v1, vcc, v1, v5
-; CGP-NEXT:    v_cndmask_b32_e64 v5, 0, 1, vcc
+; CGP-NEXT:    v_mul_hi_u32 v6, v10, v6
+; CGP-NEXT:    v_xor_b32_e32 v11, v11, v5
+; CGP-NEXT:    v_add_i32_e32 v1, vcc, v1, v4
+; CGP-NEXT:    v_cndmask_b32_e64 v4, 0, 1, vcc
 ; CGP-NEXT:    v_add_i32_e32 v1, vcc, v1, v7
-; CGP-NEXT:    v_cndmask_b32_e64 v7, 0, 1, vcc
-; CGP-NEXT:    v_add_i32_e32 v5, vcc, v5, v7
-; CGP-NEXT:    v_mul_hi_u32 v6, v8, v6
-; CGP-NEXT:    v_add_i32_e32 v0, vcc, v1, v0
 ; CGP-NEXT:    v_cndmask_b32_e64 v1, 0, 1, vcc
-; CGP-NEXT:    v_add_i32_e32 v1, vcc, v5, v1
-; CGP-NEXT:    v_add_i32_e32 v1, vcc, v6, v1
-; CGP-NEXT:    v_add_i32_e32 v0, vcc, v9, v0
-; CGP-NEXT:    v_addc_u32_e32 v1, vcc, v8, v1, vcc
-; CGP-NEXT:    v_mul_lo_u32 v5, v11, v0
-; CGP-NEXT:    v_mul_lo_u32 v6, v10, v1
-; CGP-NEXT:    v_mul_hi_u32 v7, v10, v0
-; CGP-NEXT:    v_mul_hi_u32 v0, v11, v0
-; CGP-NEXT:    v_add_i32_e32 v5, vcc, v5, v6
+; CGP-NEXT:    v_mul_lo_u32 v7, v10, v0
+; CGP-NEXT:    v_add_i32_e32 v1, vcc, v4, v1
+; CGP-NEXT:    v_mul_hi_u32 v4, v9, v0
+; CGP-NEXT:    v_add_i32_e32 v6, vcc, v7, v6
+; CGP-NEXT:    v_cndmask_b32_e64 v7, 0, 1, vcc
+; CGP-NEXT:    v_add_i32_e32 v4, vcc, v6, v4
 ; CGP-NEXT:    v_cndmask_b32_e64 v6, 0, 1, vcc
-; CGP-NEXT:    v_add_i32_e32 v5, vcc, v5, v7
-; CGP-NEXT:    v_cndmask_b32_e64 v5, 0, 1, vcc
-; CGP-NEXT:    v_mul_lo_u32 v7, v11, v1
-; CGP-NEXT:    v_add_i32_e32 v5, vcc, v6, v5
-; CGP-NEXT:    v_mul_hi_u32 v6, v10, v1
-; CGP-NEXT:    v_add_i32_e32 v0, vcc, v7, v0
+; CGP-NEXT:    v_add_i32_e32 v6, vcc, v7, v6
+; CGP-NEXT:    v_mul_hi_u32 v0, v10, v0
+; CGP-NEXT:    v_add_i32_e32 v1, vcc, v4, v1
+; CGP-NEXT:    v_cndmask_b32_e64 v4, 0, 1, vcc
+; CGP-NEXT:    v_add_i32_e32 v4, vcc, v6, v4
+; CGP-NEXT:    v_add_i32_e32 v0, vcc, v0, v4
+; CGP-NEXT:    v_add_i32_e32 v1, vcc, v9, v1
+; CGP-NEXT:    v_addc_u32_e32 v0, vcc, v10, v0, vcc
+; CGP-NEXT:    v_mul_lo_u32 v6, v11, v1
+; CGP-NEXT:    v_mul_lo_u32 v7, v8, v0
+; CGP-NEXT:    v_mul_hi_u32 v9, v8, v1
+; CGP-NEXT:    v_mul_hi_u32 v1, v11, v1
+; CGP-NEXT:    v_mul_hi_u32 v10, v11, v0
+; CGP-NEXT:    v_add_i32_e32 v6, vcc, v6, v7
 ; CGP-NEXT:    v_cndmask_b32_e64 v7, 0, 1, vcc
-; CGP-NEXT:    v_add_i32_e32 v0, vcc, v0, v6
+; CGP-NEXT:    v_add_i32_e32 v6, vcc, v6, v9
 ; CGP-NEXT:    v_cndmask_b32_e64 v6, 0, 1, vcc
+; CGP-NEXT:    v_mul_lo_u32 v9, v11, v0
 ; CGP-NEXT:    v_add_i32_e32 v6, vcc, v7, v6
-; CGP-NEXT:    v_add_i32_e32 v8, vcc, v0, v5
-; CGP-NEXT:    v_mul_hi_u32 v7, v11, v1
-; CGP-NEXT:    v_mad_u64_u32 v[0:1], s[4:5], s7, v8, 0
-; CGP-NEXT:    v_cndmask_b32_e64 v5, 0, 1, vcc
-; CGP-NEXT:    v_add_i32_e32 v5, vcc, v6, v5
-; CGP-NEXT:    v_add_i32_e32 v9, vcc, v7, v5
-; CGP-NEXT:    v_mad_u64_u32 v[6:7], s[4:5], s7, v9, v[1:2]
-; CGP-NEXT:    v_sub_i32_e32 v0, vcc, v10, v0
-; CGP-NEXT:    v_mad_u64_u32 v[6:7], s[4:5], 0, v8, v[6:7]
-; CGP-NEXT:    v_mov_b32_e32 v5, 0x1000
-; CGP-NEXT:    v_mov_b32_e32 v10, s8
+; CGP-NEXT:    v_mul_hi_u32 v7, v8, v0
+; CGP-NEXT:    v_add_i32_e32 v1, vcc, v9, v1
+; CGP-NEXT:    v_cndmask_b32_e64 v9, 0, 1, vcc
+; CGP-NEXT:    v_add_i32_e32 v1, vcc, v1, v7
+; CGP-NEXT:    v_cndmask_b32_e64 v7, 0, 1, vcc
+; CGP-NEXT:    v_add_i32_e32 v7, vcc, v9, v7
+; CGP-NEXT:    v_add_i32_e32 v9, vcc, v1, v6
+; CGP-NEXT:    v_mad_u64_u32 v[0:1], s[4:5], s7, v9, 0
+; CGP-NEXT:    v_cndmask_b32_e64 v6, 0, 1, vcc
+; CGP-NEXT:    v_add_i32_e32 v6, vcc, v7, v6
+; CGP-NEXT:    v_add_i32_e32 v10, vcc, v10, v6
+; CGP-NEXT:    v_mad_u64_u32 v[6:7], s[4:5], s7, v10, v[1:2]
+; CGP-NEXT:    v_sub_i32_e32 v0, vcc, v8, v0
+; CGP-NEXT:    v_mov_b32_e32 v4, 0x1000
 ; CGP-NEXT:    v_subb_u32_e64 v1, s[4:5], v11, v6, vcc
 ; CGP-NEXT:    v_sub_i32_e64 v6, s[4:5], v11, v6
-; CGP-NEXT:    v_cmp_ge_u32_e64 s[4:5], v0, v5
+; CGP-NEXT:    v_cmp_ge_u32_e64 s[4:5], v0, v4
 ; CGP-NEXT:    v_cndmask_b32_e64 v7, 0, -1, s[4:5]
 ; CGP-NEXT:    v_cmp_eq_u32_e64 s[4:5], 0, v1
 ; CGP-NEXT:    v_subbrev_u32_e32 v1, vcc, 0, v6, vcc
 ; CGP-NEXT:    v_cvt_f32_u32_e32 v6, 0x1000
-; CGP-NEXT:    v_sub_i32_e32 v0, vcc, v0, v5
-; CGP-NEXT:    v_cndmask_b32_e64 v10, v10, v7, s[4:5]
+; CGP-NEXT:    v_mov_b32_e32 v8, s8
+; CGP-NEXT:    v_sub_i32_e32 v0, vcc, v0, v4
+; CGP-NEXT:    v_cndmask_b32_e64 v8, v8, v7, s[4:5]
 ; CGP-NEXT:    v_subbrev_u32_e32 v7, vcc, 0, v1, vcc
 ; CGP-NEXT:    v_cvt_f32_ubyte0_e32 v1, 0
 ; CGP-NEXT:    v_mac_f32_e32 v6, 0x4f800000, v1
 ; CGP-NEXT:    v_rcp_iflag_f32_e32 v1, v6
-; CGP-NEXT:    v_add_i32_e32 v11, vcc, 1, v8
-; CGP-NEXT:    v_addc_u32_e32 v12, vcc, 0, v9, vcc
+; CGP-NEXT:    v_add_i32_e32 v11, vcc, 1, v9
+; CGP-NEXT:    v_addc_u32_e32 v12, vcc, 0, v10, vcc
 ; CGP-NEXT:    v_mul_f32_e32 v1, 0x5f7ffffc, v1
 ; CGP-NEXT:    v_mul_f32_e32 v6, 0x2f800000, v1
 ; CGP-NEXT:    v_trunc_f32_e32 v6, v6
 ; CGP-NEXT:    v_mac_f32_e32 v1, 0xcf800000, v6
 ; CGP-NEXT:    v_cvt_u32_f32_e32 v13, v1
 ; CGP-NEXT:    s_bfe_i32 s4, -1, 0x10000
-; CGP-NEXT:    v_cmp_ge_u32_e32 vcc, v0, v5
+; CGP-NEXT:    v_cmp_ge_u32_e32 vcc, v0, v4
 ; CGP-NEXT:    v_mov_b32_e32 v15, s4
 ; CGP-NEXT:    v_mad_u64_u32 v[0:1], s[4:5], s6, v13, 0
 ; CGP-NEXT:    v_cvt_u32_f32_e32 v16, v6
@@ -1556,96 +1554,94 @@
 ; CGP-NEXT:    v_add_i32_e32 v11, vcc, v13, v0
 ; CGP-NEXT:    v_addc_u32_e32 v13, vcc, v16, v1, vcc
 ; CGP-NEXT:    v_mad_u64_u32 v[0:1], s[4:5], s6, v11, 0
-; CGP-NEXT:    v_cmp_ne_u32_e32 vcc, 0, v10
-; CGP-NEXT:    v_cndmask_b32_e32 v8, v8, v7, vcc
+; CGP-NEXT:    v_cmp_ne_u32_e32 vcc, 0, v8
+; CGP-NEXT:    v_cndmask_b32_e32 v6, v9, v7, vcc
+; CGP-NEXT:    v_xor_b32_e32 v9, v6, v5
 ; CGP-NEXT:    v_mad_u64_u32 v[6:7], s[4:5], s6, v13, v[1:2]
-; CGP-NEXT:    v_xor_b32_e32 v1, v8, v4
-; CGP-NEXT:    v_ashrrev_i32_e32 v8, 31, v3
+; CGP-NEXT:    v_cndmask_b32_e32 v8, v10, v12, vcc
+; CGP-NEXT:    v_xor_b32_e32 v1, v8, v5
 ; CGP-NEXT:    v_mad_u64_u32 v[6:7], s[4:5], -1, v11, v[6:7]
-; CGP-NEXT:    v_cndmask_b32_e32 v9, v9, v12, vcc
+; CGP-NEXT:    v_ashrrev_i32_e32 v8, 31, v3
 ; CGP-NEXT:    v_add_i32_e32 v2, vcc, v2, v8
 ; CGP-NEXT:    v_addc_u32_e32 v3, vcc, v3, v8, vcc
-; CGP-NEXT:    v_xor_b32_e32 v10, v2, v8
+; CGP-NEXT:    v_xor_b32_e32 v7, v2, v8
 ; CGP-NEXT:    v_mul_lo_u32 v2, v13, v0
-; CGP-NEXT:    v_mul_lo_u32 v7, v11, v6
+; CGP-NEXT:    v_mul_lo_u32 v10, v11, v6
 ; CGP-NEXT:    v_xor_b32_e32 v12, v3, v8
 ; CGP-NEXT:    v_mul_hi_u32 v3, v11, v0
 ; CGP-NEXT:    v_mul_hi_u32 v0, v13, v0
-; CGP-NEXT:    v_add_i32_e32 v2, vcc, v2, v7
-; CGP-NEXT:    v_cndmask_b32_e64 v7, 0, 1, vcc
+; CGP-NEXT:    v_add_i32_e32 v2, vcc, v2, v10
+; CGP-NEXT:    v_cndmask_b32_e64 v10, 0, 1, vcc
 ; CGP-NEXT:    v_add_i32_e32 v2, vcc, v2, v3
 ; CGP-NEXT:    v_cndmask_b32_e64 v2, 0, 1, vcc
 ; CGP-NEXT:    v_mul_lo_u32 v3, v13, v6
-; CGP-NEXT:    v_add_i32_e32 v2, vcc, v7, v2
-; CGP-NEXT:    v_mul_hi_u32 v7, v11, v6
+; CGP-NEXT:    v_add_i32_e32 v2, vcc, v10, v2
+; CGP-NEXT:    v_mul_hi_u32 v10, v11, v6
 ; CGP-NEXT:    v_add_i32_e32 v0, vcc, v3, v0
 ; CGP-NEXT:    v_cndmask_b32_e64 v3, 0, 1, vcc
-; CGP-NEXT:    v_add_i32_e32 v0, vcc, v0, v7
-; CGP-NEXT:    v_cndmask_b32_e64 v7, 0, 1, vcc
-; CGP-NEXT:    v_add_i32_e32 v3, vcc, v3, v7
+; CGP-NEXT:    v_add_i32_e32 v0, vcc, v0, v10
+; CGP-NEXT:    v_cndmask_b32_e64 v10, 0, 1, vcc
+; CGP-NEXT:    v_add_i32_e32 v3, vcc, v3, v10
 ; CGP-NEXT:    v_mul_hi_u32 v6, v13, v6
 ; CGP-NEXT:    v_add_i32_e32 v0, vcc, v0, v2
 ; CGP-NEXT:    v_cndmask_b32_e64 v2, 0, 1, vcc
 ; CGP-NEXT:    v_add_i32_e32 v2, vcc, v3, v2
 ; CGP-NEXT:    v_add_i32_e32 v2, vcc, v6, v2
-; CGP-NEXT:    v_add_i32_e32 v0, vcc, v11, v0
+; CGP-NEXT:    v_add_i32_e32 v3, vcc, v11, v0
 ; CGP-NEXT:    v_addc_u32_e32 v2, vcc, v13, v2, vcc
-; CGP-NEXT:    v_mul_lo_u32 v3, v12, v0
-; CGP-NEXT:    v_mul_lo_u32 v6, v10, v2
-; CGP-NEXT:    v_mul_hi_u32 v7, v10, v0
-; CGP-NEXT:    v_mul_hi_u32 v0, v12, v0
-; CGP-NEXT:    v_xor_b32_e32 v9, v9, v4
-; CGP-NEXT:    v_add_i32_e32 v3, vcc, v3, v6
-; CGP-NEXT:    v_cndmask_b32_e64 v6, 0, 1, vcc
-; CGP-NEXT:    v_add_i32_e32 v3, vcc, v3, v7
-; CGP-NEXT:    v_cndmask_b32_e64 v3, 0, 1, vcc
-; CGP-NEXT:    v_mul_lo_u32 v7, v12, v2
+; CGP-NEXT:    v_mul_lo_u32 v6, v12, v3
+; CGP-NEXT:    v_mul_lo_u32 v10, v7, v2
+; CGP-NEXT:    v_sub_i32_e32 v0, vcc, v9, v5
+; CGP-NEXT:    v_subb_u32_e32 v1, vcc, v1, v5, vcc
+; CGP-NEXT:    v_mul_hi_u32 v5, v7, v3
+; CGP-NEXT:    v_add_i32_e32 v6, vcc, v6, v10
+; CGP-NEXT:    v_cndmask_b32_e64 v9, 0, 1, vcc
+; CGP-NEXT:    v_add_i32_e32 v5, vcc, v6, v5
+; CGP-NEXT:    v_cndmask_b32_e64 v5, 0, 1, vcc
+; CGP-NEXT:    v_mul_lo_u32 v6, v12, v2
+; CGP-NEXT:    v_mul_hi_u32 v3, v12, v3
+; CGP-NEXT:    v_add_i32_e32 v5, vcc, v9, v5
+; CGP-NEXT:    v_mul_hi_u32 v9, v7, v2
 ; CGP-NEXT:    v_add_i32_e32 v3, vcc, v6, v3
-; CGP-NEXT:    v_mul_hi_u32 v6, v10, v2
-; CGP-NEXT:    v_add_i32_e32 v0, vcc, v7, v0
-; CGP-NEXT:    v_cndmask_b32_e64 v7, 0, 1, vcc
-; CGP-NEXT:    v_add_i32_e32 v0, vcc, v0, v6
 ; CGP-NEXT:    v_cndmask_b32_e64 v6, 0, 1, vcc
-; CGP-NEXT:    v_add_i32_e32 v6, vcc, v7, v6
-; CGP-NEXT:    v_add_i32_e32 v11, vcc, v0, v3
-; CGP-NEXT:    v_mul_hi_u32 v7, v12, v2
-; CGP-NEXT:    v_mad_u64_u32 v[2:3], s[4:5], s7, v11, 0
-; CGP-NEXT:    v_cndmask_b32_e64 v0, 0, 1, vcc
-; CGP-NEXT:    v_add_i32_e32 v0, vcc, v6, v0
-; CGP-NEXT:    v_add_i32_e32 v13, vcc, v7, v0
-; CGP-NEXT:    v_mov_b32_e32 v0, v3
-; CGP-NEXT:    v_mad_u64_u32 v[6:7], s[4:5], s7, v13, v[0:1]
-; CGP-NEXT:    v_sub_i32_e32 v0, vcc, v1, v4
-; CGP-NEXT:    v_subb_u32_e32 v1, vcc, v9, v4, vcc
-; CGP-NEXT:    v_mad_u64_u32 v[3:4], s[4:5], 0, v11, v[6:7]
-; CGP-NEXT:    v_sub_i32_e32 v2, vcc, v10, v2
-; CGP-NEXT:    v_subb_u32_e64 v4, s[4:5], v12, v3, vcc
-; CGP-NEXT:    v_sub_i32_e64 v3, s[4:5], v12, v3
-; CGP-NEXT:    v_subbrev_u32_e32 v3, vcc, 0, v3, vcc
+; CGP-NEXT:    v_add_i32_e32 v3, vcc, v3, v9
+; CGP-NEXT:    v_cndmask_b32_e64 v9, 0, 1, vcc
+; CGP-NEXT:    v_add_i32_e32 v6, vcc, v6, v9
+; CGP-NEXT:    v_add_i32_e32 v9, vcc, v3, v5
+; CGP-NEXT:    v_mul_hi_u32 v10, v12, v2
+; CGP-NEXT:    v_mad_u64_u32 v[2:3], s[4:5], s7, v9, 0
+; CGP-NEXT:    v_cndmask_b32_e64 v5, 0, 1, vcc
+; CGP-NEXT:    v_add_i32_e32 v5, vcc, v6, v5
+; CGP-NEXT:    v_add_i32_e32 v10, vcc, v10, v5
+; CGP-NEXT:    v_mad_u64_u32 v[5:6], s[4:5], s7, v10, v[3:4]
+; CGP-NEXT:    v_sub_i32_e32 v2, vcc, v7, v2
+; CGP-NEXT:    v_subb_u32_e64 v3, s[4:5], v12, v5, vcc
+; CGP-NEXT:    v_sub_i32_e64 v5, s[4:5], v12, v5
+; CGP-NEXT:    v_subbrev_u32_e32 v5, vcc, 0, v5, vcc
 ; CGP-NEXT:    s_bfe_i32 s6, -1, 0x10000
-; CGP-NEXT:    v_cmp_ge_u32_e64 s[4:5], v2, v5
-; CGP-NEXT:    v_sub_i32_e32 v2, vcc, v2, v5
+; CGP-NEXT:    v_cmp_ge_u32_e64 s[4:5], v2, v4
+; CGP-NEXT:    v_sub_i32_e32 v2, vcc, v2, v4
 ; CGP-NEXT:    v_cndmask_b32_e64 v6, 0, -1, s[4:5]
 ; CGP-NEXT:    v_mov_b32_e32 v7, s6
-; CGP-NEXT:    v_cmp_eq_u32_e64 s[4:5], 0, v4
-; CGP-NEXT:    v_subbrev_u32_e32 v3, vcc, 0, v3, vcc
-; CGP-NEXT:    v_cndmask_b32_e64 v4, v7, v6, s[4:5]
-; CGP-NEXT:    v_add_i32_e32 v6, vcc, 1, v11
-; CGP-NEXT:    v_addc_u32_e32 v7, vcc, 0, v13, vcc
+; CGP-NEXT:    v_cmp_eq_u32_e64 s[4:5], 0, v3
+; CGP-NEXT:    v_subbrev_u32_e32 v5, vcc, 0, v5, vcc
+; CGP-NEXT:    v_cndmask_b32_e64 v3, v7, v6, s[4:5]
+; CGP-NEXT:    v_add_i32_e32 v6, vcc, 1, v9
+; CGP-NEXT:    v_addc_u32_e32 v7, vcc, 0, v10, vcc
 ; CGP-NEXT:    s_bfe_i32 s4, -1, 0x10000
-; CGP-NEXT:    v_cmp_ge_u32_e32 vcc, v2, v5
+; CGP-NEXT:    v_cmp_ge_u32_e32 vcc, v2, v4
 ; CGP-NEXT:    v_cndmask_b32_e64 v2, 0, -1, vcc
-; CGP-NEXT:    v_mov_b32_e32 v5, s4
-; CGP-NEXT:    v_cmp_eq_u32_e32 vcc, 0, v3
-; CGP-NEXT:    v_cndmask_b32_e32 v2, v5, v2, vcc
-; CGP-NEXT:    v_add_i32_e32 v3, vcc, 1, v6
+; CGP-NEXT:    v_mov_b32_e32 v4, s4
+; CGP-NEXT:    v_cmp_eq_u32_e32 vcc, 0, v5
+; CGP-NEXT:    v_cndmask_b32_e32 v2, v4, v2, vcc
+; CGP-NEXT:    v_add_i32_e32 v4, vcc, 1, v6
 ; CGP-NEXT:    v_addc_u32_e32 v5, vcc, 0, v7, vcc
 ; CGP-NEXT:    v_cmp_ne_u32_e32 vcc, 0, v2
-; CGP-NEXT:    v_cndmask_b32_e32 v2, v6, v3, vcc
-; CGP-NEXT:    v_cndmask_b32_e32 v3, v7, v5, vcc
-; CGP-NEXT:    v_cmp_ne_u32_e32 vcc, 0, v4
-; CGP-NEXT:    v_cndmask_b32_e32 v2, v11, v2, vcc
-; CGP-NEXT:    v_cndmask_b32_e32 v3, v13, v3, vcc
+; CGP-NEXT:    v_cndmask_b32_e32 v2, v6, v4, vcc
+; CGP-NEXT:    v_cndmask_b32_e32 v4, v7, v5, vcc
+; CGP-NEXT:    v_cmp_ne_u32_e32 vcc, 0, v3
+; CGP-NEXT:    v_cndmask_b32_e32 v2, v9, v2, vcc
+; CGP-NEXT:    v_cndmask_b32_e32 v3, v10, v4, vcc
 ; CGP-NEXT:    v_xor_b32_e32 v2, v2, v8
 ; CGP-NEXT:    v_xor_b32_e32 v3, v3, v8
 ; CGP-NEXT:    v_sub_i32_e32 v2, vcc, v2, v8
@@ -1699,89 +1695,88 @@
 ; CHECK-NEXT:    v_addc_u32_e32 v6, vcc, v6, v3, vcc
 ; CHECK-NEXT:    v_mad_u64_u32 v[2:3], s[4:5], s6, v5, 0
 ; CHECK-NEXT:    v_ashrrev_i32_e32 v7, 31, v1
-; CHECK-NEXT:    v_add_i32_e32 v0, vcc, v0, v7
+; CHECK-NEXT:    v_add_i32_e32 v8, vcc, v0, v7
 ; CHECK-NEXT:    v_mad_u64_u32 v[3:4], s[4:5], s6, v6, v[3:4]
-; CHECK-NEXT:    v_addc_u32_e32 v1, vcc, v1, v7, vcc
-; CHECK-NEXT:    v_mad_u64_u32 v[3:4], s[4:5], -1, v5, v[3:4]
-; CHECK-NEXT:    v_xor_b32_e32 v4, v0, v7
-; CHECK-NEXT:    v_mul_lo_u32 v0, v6, v2
-; CHECK-NEXT:    v_mul_lo_u32 v8, v5, v3
-; CHECK-NEXT:    v_xor_b32_e32 v9, v1, v7
-; CHECK-NEXT:    v_mul_hi_u32 v1, v5, v2
+; CHECK-NEXT:    v_addc_u32_e32 v9, vcc, v1, v7, vcc
+; CHECK-NEXT:    v_mad_u64_u32 v[0:1], s[4:5], -1, v5, v[3:4]
+; CHECK-NEXT:    v_xor_b32_e32 v3, v8, v7
+; CHECK-NEXT:    v_mul_lo_u32 v1, v6, v2
+; CHECK-NEXT:    v_mul_lo_u32 v8, v5, v0
+; CHECK-NEXT:    v_xor_b32_e32 v4, v9, v7
+; CHECK-NEXT:    v_mul_hi_u32 v9, v5, v2
 ; CHECK-NEXT:    v_mul_hi_u32 v2, v6, v2
-; CHECK-NEXT:    v_add_i32_e32 v0, vcc, v0, v8
-; CHECK-NEXT:    v_cndmask_b32_e64 v8, 0, 1, vcc
-; CHECK-NEXT:    v_add_i32_e32 v0, vcc, v0, v1
-; CHECK-NEXT:    v_cndmask_b32_e64 v0, 0, 1, vcc
-; CHECK-NEXT:    v_mul_lo_u32 v1, v6, v3
-; CHECK-NEXT:    v_add_i32_e32 v0, vcc, v8, v0
-; CHECK-NEXT:    v_mul_hi_u32 v8, v5, v3
-; CHECK-NEXT:    v_add_i32_e32 v1, vcc, v1, v2
-; CHECK-NEXT:    v_cndmask_b32_e64 v2, 0, 1, vcc
 ; CHECK-NEXT:    v_add_i32_e32 v1, vcc, v1, v8
 ; CHECK-NEXT:    v_cndmask_b32_e64 v8, 0, 1, vcc
-; CHECK-NEXT:    v_add_i32_e32 v2, vcc, v2, v8
-; CHECK-NEXT:    v_mul_hi_u32 v3, v6, v3
-; CHECK-NEXT:    v_add_i32_e32 v0, vcc, v1, v0
+; CHECK-NEXT:    v_add_i32_e32 v1, vcc, v1, v9
 ; CHECK-NEXT:    v_cndmask_b32_e64 v1, 0, 1, vcc
+; CHECK-NEXT:    v_mul_lo_u32 v9, v6, v0
+; CHECK-NEXT:    v_add_i32_e32 v1, vcc, v8, v1
+; CHECK-NEXT:    v_mul_hi_u32 v8, v5, v0
+; CHECK-NEXT:    v_add_i32_e32 v2, vcc, v9, v2
+; CHECK-NEXT:    v_cndmask_b32_e64 v9, 0, 1, vcc
+; CHECK-NEXT:    v_add_i32_e32 v2, vcc, v2, v8
+; CHECK-NEXT:    v_cndmask_b32_e64 v8, 0, 1, vcc
+; CHECK-NEXT:    v_add_i32_e32 v8, vcc, v9, v8
+; CHECK-NEXT:    v_mul_hi_u32 v0, v6, v0
 ; CHECK-NEXT:    v_add_i32_e32 v1, vcc, v2, v1
-; CHECK-NEXT:    v_add_i32_e32 v1, vcc, v3, v1
-; CHECK-NEXT:    v_add_i32_e32 v0, vcc, v5, v0
-; CHECK-NEXT:    v_addc_u32_e32 v1, vcc, v6, v1, vcc
-; CHECK-NEXT:    v_mul_lo_u32 v2, v9, v0
-; CHECK-NEXT:    v_mul_lo_u32 v3, v4, v1
-; CHECK-NEXT:    v_mul_hi_u32 v5, v4, v0
-; CHECK-NEXT:    v_mul_hi_u32 v0, v9, v0
+; CHECK-NEXT:    v_cndmask_b32_e64 v2, 0, 1, vcc
+; CHECK-NEXT:    v_add_i32_e32 v2, vcc, v8, v2
+; CHECK-NEXT:    v_add_i32_e32 v0, vcc, v0, v2
+; CHECK-NEXT:    v_add_i32_e32 v1, vcc, v5, v1
+; CHECK-NEXT:    v_addc_u32_e32 v0, vcc, v6, v0, vcc
+; CHECK-NEXT:    v_mul_lo_u32 v2, v4, v1
+; CHECK-NEXT:    v_mul_lo_u32 v5, v3, v0
+; CHECK-NEXT:    v_mul_hi_u32 v8, v3, v1
+; CHECK-NEXT:    v_mul_hi_u32 v1, v4, v1
 ; CHECK-NEXT:    s_mov_b32 s6, 0x12d8fb
-; CHECK-NEXT:    v_add_i32_e32 v2, vcc, v2, v3
-; CHECK-NEXT:    v_cndmask_b32_e64 v3, 0, 1, vcc
 ; CHECK-NEXT:    v_add_i32_e32 v2, vcc, v2, v5
+; CHECK-NEXT:    v_cndmask_b32_e64 v5, 0, 1, vcc
+; CHECK-NEXT:    v_add_i32_e32 v2, vcc, v2, v8
 ; CHECK-NEXT:    v_cndmask_b32_e64 v2, 0, 1, vcc
-; CHECK-NEXT:    v_mul_lo_u32 v5, v9, v1
-; CHECK-NEXT:    v_add_i32_e32 v2, vcc, v3, v2
-; CHECK-NEXT:    v_mul_hi_u32 v3, v4, v1
-; CHECK-NEXT:    v_add_i32_e32 v0, vcc, v5, v0
+; CHECK-NEXT:    v_mul_lo_u32 v8, v4, v0
+; CHECK-NEXT:    v_add_i32_e32 v2, vcc, v5, v2
+; CHECK-NEXT:    v_mul_hi_u32 v5, v3, v0
+; CHECK-NEXT:    v_add_i32_e32 v1, vcc, v8, v1
+; CHECK-NEXT:    v_cndmask_b32_e64 v8, 0, 1, vcc
+; CHECK-NEXT:    v_add_i32_e32 v1, vcc, v1, v5
 ; CHECK-NEXT:    v_cndmask_b32_e64 v5, 0, 1, vcc
-; CHECK-NEXT:    v_add_i32_e32 v0, vcc, v0, v3
-; CHECK-NEXT:    v_cndmask_b32_e64 v3, 0, 1, vcc
-; CHECK-NEXT:    v_add_i32_e32 v3, vcc, v5, v3
-; CHECK-NEXT:    v_add_i32_e32 v5, vcc, v0, v2
-; CHECK-NEXT:    v_mul_hi_u32 v6, v9, v1
-; CHECK-NEXT:    v_mad_u64_u32 v[0:1], s[4:5], s6, v5, 0
+; CHECK-NEXT:    v_add_i32_e32 v5, vcc, v8, v5
+; CHECK-NEXT:    v_add_i32_e32 v8, vcc, v1, v2
+; CHECK-NEXT:    v_mul_hi_u32 v9, v4, v0
+; CHECK-NEXT:    v_mad_u64_u32 v[0:1], s[4:5], s6, v8, 0
 ; CHECK-NEXT:    v_cndmask_b32_e64 v2, 0, 1, vcc
-; CHECK-NEXT:    v_add_i32_e32 v2, vcc, v3, v2
-; CHECK-NEXT:    v_add_i32_e32 v3, vcc, v6, v2
-; CHECK-NEXT:    v_mad_u64_u32 v[1:2], s[4:5], s6, v3, v[1:2]
-; CHECK-NEXT:    v_sub_i32_e32 v0, vcc, v4, v0
-; CHECK-NEXT:    v_mad_u64_u32 v[1:2], s[4:5], 0, v5, v[1:2]
+; CHECK-NEXT:    v_add_i32_e32 v2, vcc, v5, v2
+; CHECK-NEXT:    v_add_i32_e32 v5, vcc, v9, v2
+; CHECK-NEXT:    v_mad_u64_u32 v[1:2], s[4:5], s6, v5, v[1:2]
+; CHECK-NEXT:    v_sub_i32_e32 v0, vcc, v3, v0
+; CHECK-NEXT:    v_subb_u32_e64 v2, s[4:5], v4, v1, vcc
+; CHECK-NEXT:    v_sub_i32_e64 v1, s[4:5], v4, v1
 ; CHECK-NEXT:    v_mov_b32_e32 v6, 0x12d8fb
-; CHECK-NEXT:    s_bfe_i32 s6, -1, 0x10000
-; CHECK-NEXT:    v_subb_u32_e64 v2, s[4:5], v9, v1, vcc
-; CHECK-NEXT:    v_sub_i32_e64 v1, s[4:5], v9, v1
 ; CHECK-NEXT:    v_subbrev_u32_e32 v1, vcc, 0, v1, vcc
+; CHECK-NEXT:    s_bfe_i32 s6, -1, 0x10000
 ; CHECK-NEXT:    v_cmp_ge_u32_e64 s[4:5], v0, v6
 ; CHECK-NEXT:    v_sub_i32_e32 v0, vcc, v0, v6
-; CHECK-NEXT:    v_cndmask_b32_e64 v4, 0, -1, s[4:5]
-; CHECK-NEXT:    v_mov_b32_e32 v8, s6
+; CHECK-NEXT:    v_cndmask_b32_e64 v3, 0, -1, s[4:5]
+; CHECK-NEXT:    v_mov_b32_e32 v4, s6
 ; CHECK-NEXT:    v_cmp_eq_u32_e64 s[4:5], 0, v2
 ; CHECK-NEXT:    v_subbrev_u32_e32 v1, vcc, 0, v1, vcc
-; CHECK-NEXT:    v_cndmask_b32_e64 v2, v8, v4, s[4:5]
-; CHECK-NEXT:    v_add_i32_e32 v4, vcc, 1, v5
-; CHECK-NEXT:    v_addc_u32_e32 v8, vcc, 0, v3, vcc
+; CHECK-NEXT:    v_cndmask_b32_e64 v2, v4, v3, s[4:5]
+; CHECK-NEXT:    v_add_i32_e32 v3, vcc, 1, v8
+; CHECK-NEXT:    v_addc_u32_e32 v4, vcc, 0, v5, vcc
 ; CHECK-NEXT:    s_bfe_i32 s4, -1, 0x10000
 ; CHECK-NEXT:    v_cmp_ge_u32_e32 vcc, v0, v6
 ; CHECK-NEXT:    v_cndmask_b32_e64 v0, 0, -1, vcc
 ; CHECK-NEXT:    v_mov_b32_e32 v6, s4
 ; CHECK-NEXT:    v_cmp_eq_u32_e32 vcc, 0, v1
 ; CHECK-NEXT:    v_cndmask_b32_e32 v0, v6, v0, vcc
-; CHECK-NEXT:    v_add_i32_e32 v1, vcc, 1, v4
-; CHECK-NEXT:    v_addc_u32_e32 v6, vcc, 0, v8, vcc
+; CHECK-NEXT:    v_add_i32_e32 v1, vcc, 1, v3
+; CHECK-NEXT:    v_addc_u32_e32 v6, vcc, 0, v4, vcc
 ; CHECK-NEXT:    v_cmp_ne_u32_e32 vcc, 0, v0
-; CHECK-NEXT:    v_cndmask_b32_e32 v0, v4, v1, vcc
-; CHECK-NEXT:    v_cndmask_b32_e32 v1, v8, v6, vcc
+; CHECK-NEXT:    v_cndmask_b32_e32 v0, v3, v1, vcc
+; CHECK-NEXT:    v_cndmask_b32_e32 v1, v4, v6, vcc
 ; CHECK-NEXT:    v_cmp_ne_u32_e32 vcc, 0, v2
-; CHECK-NEXT:    v_cndmask_b32_e32 v0, v5, v0, vcc
-; CHECK-NEXT:    v_cndmask_b32_e32 v1, v3, v1, vcc
+; CHECK-NEXT:    v_cndmask_b32_e32 v0, v8, v0, vcc
+; CHECK-NEXT:    v_cndmask_b32_e32 v1, v5, v1, vcc
 ; CHECK-NEXT:    v_xor_b32_e32 v0, v0, v7
 ; CHECK-NEXT:    v_xor_b32_e32 v1, v1, v7
 ; CHECK-NEXT:    v_sub_i32_e32 v0, vcc, v0, v7
@@ -2101,88 +2096,87 @@
 ; CGP-NEXT:    v_add_i32_e32 v6, vcc, v9, v6
 ; CGP-NEXT:    v_add_i32_e32 v5, vcc, v5, v6
 ; CGP-NEXT:    v_add_i32_e32 v9, vcc, v7, v4
-; CGP-NEXT:    v_addc_u32_e32 v8, vcc, v8, v5, vcc
-; CGP-NEXT:    v_mad_u64_u32 v[5:6], s[4:5], s6, v9, 0
-; CGP-NEXT:    v_mov_b32_e32 v4, v6
-; CGP-NEXT:    v_mad_u64_u32 v[6:7], s[4:5], s6, v8, v[4:5]
-; CGP-NEXT:    v_ashrrev_i32_e32 v4, 31, v1
-; CGP-NEXT:    v_add_i32_e32 v0, vcc, v0, v4
-; CGP-NEXT:    v_mad_u64_u32 v[6:7], s[4:5], -1, v9, v[6:7]
-; CGP-NEXT:    v_addc_u32_e32 v1, vcc, v1, v4, vcc
-; CGP-NEXT:    v_xor_b32_e32 v10, v0, v4
-; CGP-NEXT:    v_mul_lo_u32 v0, v8, v5
-; CGP-NEXT:    v_mul_lo_u32 v7, v9, v6
-; CGP-NEXT:    v_xor_b32_e32 v11, v1, v4
-; CGP-NEXT:    v_mul_hi_u32 v1, v9, v5
-; CGP-NEXT:    v_mul_hi_u32 v5, v8, v5
-; CGP-NEXT:    v_add_i32_e32 v0, vcc, v0, v7
-; CGP-NEXT:    v_cndmask_b32_e64 v7, 0, 1, vcc
-; CGP-NEXT:    v_add_i32_e32 v0, vcc, v0, v1
-; CGP-NEXT:    v_cndmask_b32_e64 v0, 0, 1, vcc
-; CGP-NEXT:    v_mul_lo_u32 v1, v8, v6
-; CGP-NEXT:    v_add_i32_e32 v0, vcc, v7, v0
+; CGP-NEXT:    v_mad_u64_u32 v[6:7], s[4:5], s6, v9, 0
+; CGP-NEXT:    v_addc_u32_e32 v10, vcc, v8, v5, vcc
+; CGP-NEXT:    v_ashrrev_i32_e32 v5, 31, v1
+; CGP-NEXT:    v_mov_b32_e32 v4, v7
+; CGP-NEXT:    v_mad_u64_u32 v[7:8], s[4:5], s6, v10, v[4:5]
+; CGP-NEXT:    v_add_i32_e32 v4, vcc, v0, v5
+; CGP-NEXT:    v_addc_u32_e32 v11, vcc, v1, v5, vcc
+; CGP-NEXT:    v_mad_u64_u32 v[0:1], s[4:5], -1, v9, v[7:8]
+; CGP-NEXT:    v_xor_b32_e32 v8, v4, v5
+; CGP-NEXT:    v_mul_lo_u32 v1, v10, v6
+; CGP-NEXT:    v_mul_lo_u32 v4, v9, v0
 ; CGP-NEXT:    v_mul_hi_u32 v7, v9, v6
-; CGP-NEXT:    v_add_i32_e32 v1, vcc, v1, v5
-; CGP-NEXT:    v_cndmask_b32_e64 v5, 0, 1, vcc
+; CGP-NEXT:    v_mul_hi_u32 v6, v10, v6
+; CGP-NEXT:    v_xor_b32_e32 v11, v11, v5
+; CGP-NEXT:    v_add_i32_e32 v1, vcc, v1, v4
+; CGP-NEXT:    v_cndmask_b32_e64 v4, 0, 1, vcc
 ; CGP-NEXT:    v_add_i32_e32 v1, vcc, v1, v7
-; CGP-NEXT:    v_cndmask_b32_e64 v7, 0, 1, vcc
-; CGP-NEXT:    v_add_i32_e32 v5, vcc, v5, v7
-; CGP-NEXT:    v_mul_hi_u32 v6, v8, v6
-; CGP-NEXT:    v_add_i32_e32 v0, vcc, v1, v0
 ; CGP-NEXT:    v_cndmask_b32_e64 v1, 0, 1, vcc
-; CGP-NEXT:    v_add_i32_e32 v1, vcc, v5, v1
-; CGP-NEXT:    v_add_i32_e32 v1, vcc, v6, v1
-; CGP-NEXT:    v_add_i32_e32 v0, vcc, v9, v0
-; CGP-NEXT:    v_addc_u32_e32 v1, vcc, v8, v1, vcc
-; CGP-NEXT:    v_mul_lo_u32 v5, v11, v0
-; CGP-NEXT:    v_mul_lo_u32 v6, v10, v1
-; CGP-NEXT:    v_mul_hi_u32 v7, v10, v0
-; CGP-NEXT:    v_mul_hi_u32 v0, v11, v0
-; CGP-NEXT:    v_add_i32_e32 v5, vcc, v5, v6
+; CGP-NEXT:    v_mul_lo_u32 v7, v10, v0
+; CGP-NEXT:    v_add_i32_e32 v1, vcc, v4, v1
+; CGP-NEXT:    v_mul_hi_u32 v4, v9, v0
+; CGP-NEXT:    v_add_i32_e32 v6, vcc, v7, v6
+; CGP-NEXT:    v_cndmask_b32_e64 v7, 0, 1, vcc
+; CGP-NEXT:    v_add_i32_e32 v4, vcc, v6, v4
 ; CGP-NEXT:    v_cndmask_b32_e64 v6, 0, 1, vcc
-; CGP-NEXT:    v_add_i32_e32 v5, vcc, v5, v7
-; CGP-NEXT:    v_cndmask_b32_e64 v5, 0, 1, vcc
-; CGP-NEXT:    v_mul_lo_u32 v7, v11, v1
-; CGP-NEXT:    v_add_i32_e32 v5, vcc, v6, v5
-; CGP-NEXT:    v_mul_hi_u32 v6, v10, v1
-; CGP-NEXT:    v_add_i32_e32 v0, vcc, v7, v0
+; CGP-NEXT:    v_add_i32_e32 v6, vcc, v7, v6
+; CGP-NEXT:    v_mul_hi_u32 v0, v10, v0
+; CGP-NEXT:    v_add_i32_e32 v1, vcc, v4, v1
+; CGP-NEXT:    v_cndmask_b32_e64 v4, 0, 1, vcc
+; CGP-NEXT:    v_add_i32_e32 v4, vcc, v6, v4
+; CGP-NEXT:    v_add_i32_e32 v0, vcc, v0, v4
+; CGP-NEXT:    v_add_i32_e32 v1, vcc, v9, v1
+; CGP-NEXT:    v_addc_u32_e32 v0, vcc, v10, v0, vcc
+; CGP-NEXT:    v_mul_lo_u32 v6, v11, v1
+; CGP-NEXT:    v_mul_lo_u32 v7, v8, v0
+; CGP-NEXT:    v_mul_hi_u32 v9, v8, v1
+; CGP-NEXT:    v_mul_hi_u32 v1, v11, v1
+; CGP-NEXT:    v_mul_hi_u32 v10, v11, v0
+; CGP-NEXT:    v_add_i32_e32 v6, vcc, v6, v7
 ; CGP-NEXT:    v_cndmask_b32_e64 v7, 0, 1, vcc
-; CGP-NEXT:    v_add_i32_e32 v0, vcc, v0, v6
+; CGP-NEXT:    v_add_i32_e32 v6, vcc, v6, v9
 ; CGP-NEXT:    v_cndmask_b32_e64 v6, 0, 1, vcc
+; CGP-NEXT:    v_mul_lo_u32 v9, v11, v0
 ; CGP-NEXT:    v_add_i32_e32 v6, vcc, v7, v6
-; CGP-NEXT:    v_add_i32_e32 v8, vcc, v0, v5
-; CGP-NEXT:    v_mul_hi_u32 v7, v11, v1
-; CGP-NEXT:    v_mad_u64_u32 v[0:1], s[4:5], s7, v8, 0
-; CGP-NEXT:    v_cndmask_b32_e64 v5, 0, 1, vcc
-; CGP-NEXT:    v_add_i32_e32 v5, vcc, v6, v5
-; CGP-NEXT:    v_add_i32_e32 v9, vcc, v7, v5
-; CGP-NEXT:    v_mad_u64_u32 v[6:7], s[4:5], s7, v9, v[1:2]
-; CGP-NEXT:    v_sub_i32_e32 v0, vcc, v10, v0
-; CGP-NEXT:    v_mad_u64_u32 v[6:7], s[4:5], 0, v8, v[6:7]
-; CGP-NEXT:    v_mov_b32_e32 v5, 0x12d8fb
-; CGP-NEXT:    v_mov_b32_e32 v10, s8
+; CGP-NEXT:    v_mul_hi_u32 v7, v8, v0
+; CGP-NEXT:    v_add_i32_e32 v1, vcc, v9, v1
+; CGP-NEXT:    v_cndmask_b32_e64 v9, 0, 1, vcc
+; CGP-NEXT:    v_add_i32_e32 v1, vcc, v1, v7
+; CGP-NEXT:    v_cndmask_b32_e64 v7, 0, 1, vcc
+; CGP-NEXT:    v_add_i32_e32 v7, vcc, v9, v7
+; CGP-NEXT:    v_add_i32_e32 v9, vcc, v1, v6
+; CGP-NEXT:    v_mad_u64_u32 v[0:1], s[4:5], s7, v9, 0
+; CGP-NEXT:    v_cndmask_b32_e64 v6, 0, 1, vcc
+; CGP-NEXT:    v_add_i32_e32 v6, vcc, v7, v6
+; CGP-NEXT:    v_add_i32_e32 v10, vcc, v10, v6
+; CGP-NEXT:    v_mad_u64_u32 v[6:7], s[4:5], s7, v10, v[1:2]
+; CGP-NEXT:    v_sub_i32_e32 v0, vcc, v8, v0
+; CGP-NEXT:    v_mov_b32_e32 v4, 0x12d8fb
 ; CGP-NEXT:    v_subb_u32_e64 v1, s[4:5], v11, v6, vcc
 ; CGP-NEXT:    v_sub_i32_e64 v6, s[4:5], v11, v6
-; CGP-NEXT:    v_cmp_ge_u32_e64 s[4:5], v0, v5
+; CGP-NEXT:    v_cmp_ge_u32_e64 s[4:5], v0, v4
 ; CGP-NEXT:    v_cndmask_b32_e64 v7, 0, -1, s[4:5]
 ; CGP-NEXT:    v_cmp_eq_u32_e64 s[4:5], 0, v1
 ; CGP-NEXT:    v_subbrev_u32_e32 v1, vcc, 0, v6, vcc
 ; CGP-NEXT:    v_cvt_f32_u32_e32 v6, 0x12d8fb
-; CGP-NEXT:    v_sub_i32_e32 v0, vcc, v0, v5
-; CGP-NEXT:    v_cndmask_b32_e64 v10, v10, v7, s[4:5]
+; CGP-NEXT:    v_mov_b32_e32 v8, s8
+; CGP-NEXT:    v_sub_i32_e32 v0, vcc, v0, v4
+; CGP-NEXT:    v_cndmask_b32_e64 v8, v8, v7, s[4:5]
 ; CGP-NEXT:    v_subbrev_u32_e32 v7, vcc, 0, v1, vcc
 ; CGP-NEXT:    v_cvt_f32_ubyte0_e32 v1, 0
 ; CGP-NEXT:    v_mac_f32_e32 v6, 0x4f800000, v1
 ; CGP-NEXT:    v_rcp_iflag_f32_e32 v1, v6
-; CGP-NEXT:    v_add_i32_e32 v11, vcc, 1, v8
-; CGP-NEXT:    v_addc_u32_e32 v12, vcc, 0, v9, vcc
+; CGP-NEXT:    v_add_i32_e32 v11, vcc, 1, v9
+; CGP-NEXT:    v_addc_u32_e32 v12, vcc, 0, v10, vcc
 ; CGP-NEXT:    v_mul_f32_e32 v1, 0x5f7ffffc, v1
 ; CGP-NEXT:    v_mul_f32_e32 v6, 0x2f800000, v1
 ; CGP-NEXT:    v_trunc_f32_e32 v6, v6
 ; CGP-NEXT:    v_mac_f32_e32 v1, 0xcf800000, v6
 ; CGP-NEXT:    v_cvt_u32_f32_e32 v13, v1
 ; CGP-NEXT:    s_bfe_i32 s4, -1, 0x10000
-; CGP-NEXT:    v_cmp_ge_u32_e32 vcc, v0, v5
+; CGP-NEXT:    v_cmp_ge_u32_e32 vcc, v0, v4
 ; CGP-NEXT:    v_mov_b32_e32 v15, s4
 ; CGP-NEXT:    v_mad_u64_u32 v[0:1], s[4:5], s6, v13, 0
 ; CGP-NEXT:    v_cvt_u32_f32_e32 v16, v6
@@ -2220,96 +2214,94 @@
 ; CGP-NEXT:    v_add_i32_e32 v11, vcc, v13, v0
 ; CGP-NEXT:    v_addc_u32_e32 v13, vcc, v16, v1, vcc
 ; CGP-NEXT:    v_mad_u64_u32 v[0:1], s[4:5], s6, v11, 0
-; CGP-NEXT:    v_cmp_ne_u32_e32 vcc, 0, v10
-; CGP-NEXT:    v_cndmask_b32_e32 v8, v8, v7, vcc
+; CGP-NEXT:    v_cmp_ne_u32_e32 vcc, 0, v8
+; CGP-NEXT:    v_cndmask_b32_e32 v6, v9, v7, vcc
+; CGP-NEXT:    v_xor_b32_e32 v9, v6, v5
 ; CGP-NEXT:    v_mad_u64_u32 v[6:7], s[4:5], s6, v13, v[1:2]
-; CGP-NEXT:    v_xor_b32_e32 v1, v8, v4
-; CGP-NEXT:    v_ashrrev_i32_e32 v8, 31, v3
+; CGP-NEXT:    v_cndmask_b32_e32 v8, v10, v12, vcc
+; CGP-NEXT:    v_xor_b32_e32 v1, v8, v5
 ; CGP-NEXT:    v_mad_u64_u32 v[6:7], s[4:5], -1, v11, v[6:7]
-; CGP-NEXT:    v_cndmask_b32_e32 v9, v9, v12, vcc
+; CGP-NEXT:    v_ashrrev_i32_e32 v8, 31, v3
 ; CGP-NEXT:    v_add_i32_e32 v2, vcc, v2, v8
 ; CGP-NEXT:    v_addc_u32_e32 v3, vcc, v3, v8, vcc
-; CGP-NEXT:    v_xor_b32_e32 v10, v2, v8
+; CGP-NEXT:    v_xor_b32_e32 v7, v2, v8
 ; CGP-NEXT:    v_mul_lo_u32 v2, v13, v0
-; CGP-NEXT:    v_mul_lo_u32 v7, v11, v6
+; CGP-NEXT:    v_mul_lo_u32 v10, v11, v6
 ; CGP-NEXT:    v_xor_b32_e32 v12, v3, v8
 ; CGP-NEXT:    v_mul_hi_u32 v3, v11, v0
 ; CGP-NEXT:    v_mul_hi_u32 v0, v13, v0
-; CGP-NEXT:    v_add_i32_e32 v2, vcc, v2, v7
-; CGP-NEXT:    v_cndmask_b32_e64 v7, 0, 1, vcc
+; CGP-NEXT:    v_add_i32_e32 v2, vcc, v2, v10
+; CGP-NEXT:    v_cndmask_b32_e64 v10, 0, 1, vcc
 ; CGP-NEXT:    v_add_i32_e32 v2, vcc, v2, v3
 ; CGP-NEXT:    v_cndmask_b32_e64 v2, 0, 1, vcc
 ; CGP-NEXT:    v_mul_lo_u32 v3, v13, v6
-; CGP-NEXT:    v_add_i32_e32 v2, vcc, v7, v2
-; CGP-NEXT:    v_mul_hi_u32 v7, v11, v6
+; CGP-NEXT:    v_add_i32_e32 v2, vcc, v10, v2
+; CGP-NEXT:    v_mul_hi_u32 v10, v11, v6
 ; CGP-NEXT:    v_add_i32_e32 v0, vcc, v3, v0
 ; CGP-NEXT:    v_cndmask_b32_e64 v3, 0, 1, vcc
-; CGP-NEXT:    v_add_i32_e32 v0, vcc, v0, v7
-; CGP-NEXT:    v_cndmask_b32_e64 v7, 0, 1, vcc
-; CGP-NEXT:    v_add_i32_e32 v3, vcc, v3, v7
+; CGP-NEXT:    v_add_i32_e32 v0, vcc, v0, v10
+; CGP-NEXT:    v_cndmask_b32_e64 v10, 0, 1, vcc
+; CGP-NEXT:    v_add_i32_e32 v3, vcc, v3, v10
 ; CGP-NEXT:    v_mul_hi_u32 v6, v13, v6
 ; CGP-NEXT:    v_add_i32_e32 v0, vcc, v0, v2
 ; CGP-NEXT:    v_cndmask_b32_e64 v2, 0, 1, vcc
 ; CGP-NEXT:    v_add_i32_e32 v2, vcc, v3, v2
 ; CGP-NEXT:    v_add_i32_e32 v2, vcc, v6, v2
-; CGP-NEXT:    v_add_i32_e32 v0, vcc, v11, v0
+; CGP-NEXT:    v_add_i32_e32 v3, vcc, v11, v0
 ; CGP-NEXT:    v_addc_u32_e32 v2, vcc, v13, v2, vcc
-; CGP-NEXT:    v_mul_lo_u32 v3, v12, v0
-; CGP-NEXT:    v_mul_lo_u32 v6, v10, v2
-; CGP-NEXT:    v_mul_hi_u32 v7, v10, v0
-; CGP-NEXT:    v_mul_hi_u32 v0, v12, v0
-; CGP-NEXT:    v_xor_b32_e32 v9, v9, v4
-; CGP-NEXT:    v_add_i32_e32 v3, vcc, v3, v6
-; CGP-NEXT:    v_cndmask_b32_e64 v6, 0, 1, vcc
-; CGP-NEXT:    v_add_i32_e32 v3, vcc, v3, v7
-; CGP-NEXT:    v_cndmask_b32_e64 v3, 0, 1, vcc
-; CGP-NEXT:    v_mul_lo_u32 v7, v12, v2
+; CGP-NEXT:    v_mul_lo_u32 v6, v12, v3
+; CGP-NEXT:    v_mul_lo_u32 v10, v7, v2
+; CGP-NEXT:    v_sub_i32_e32 v0, vcc, v9, v5
+; CGP-NEXT:    v_subb_u32_e32 v1, vcc, v1, v5, vcc
+; CGP-NEXT:    v_mul_hi_u32 v5, v7, v3
+; CGP-NEXT:    v_add_i32_e32 v6, vcc, v6, v10
+; CGP-NEXT:    v_cndmask_b32_e64 v9, 0, 1, vcc
+; CGP-NEXT:    v_add_i32_e32 v5, vcc, v6, v5
+; CGP-NEXT:    v_cndmask_b32_e64 v5, 0, 1, vcc
+; CGP-NEXT:    v_mul_lo_u32 v6, v12, v2
+; CGP-NEXT:    v_mul_hi_u32 v3, v12, v3
+; CGP-NEXT:    v_add_i32_e32 v5, vcc, v9, v5
+; CGP-NEXT:    v_mul_hi_u32 v9, v7, v2
 ; CGP-NEXT:    v_add_i32_e32 v3, vcc, v6, v3
-; CGP-NEXT:    v_mul_hi_u32 v6, v10, v2
-; CGP-NEXT:    v_add_i32_e32 v0, vcc, v7, v0
-; CGP-NEXT:    v_cndmask_b32_e64 v7, 0, 1, vcc
-; CGP-NEXT:    v_add_i32_e32 v0, vcc, v0, v6
 ; CGP-NEXT:    v_cndmask_b32_e64 v6, 0, 1, vcc
-; CGP-NEXT:    v_add_i32_e32 v6, vcc, v7, v6
-; CGP-NEXT:    v_add_i32_e32 v11, vcc, v0, v3
-; CGP-NEXT:    v_mul_hi_u32 v7, v12, v2
-; CGP-NEXT:    v_mad_u64_u32 v[2:3], s[4:5], s7, v11, 0
-; CGP-NEXT:    v_cndmask_b32_e64 v0, 0, 1, vcc
-; CGP-NEXT:    v_add_i32_e32 v0, vcc, v6, v0
-; CGP-NEXT:    v_add_i32_e32 v13, vcc, v7, v0
-; CGP-NEXT:    v_mov_b32_e32 v0, v3
-; CGP-NEXT:    v_mad_u64_u32 v[6:7], s[4:5], s7, v13, v[0:1]
-; CGP-NEXT:    v_sub_i32_e32 v0, vcc, v1, v4
-; CGP-NEXT:    v_subb_u32_e32 v1, vcc, v9, v4, vcc
-; CGP-NEXT:    v_mad_u64_u32 v[3:4], s[4:5], 0, v11, v[6:7]
-; CGP-NEXT:    v_sub_i32_e32 v2, vcc, v10, v2
-; CGP-NEXT:    v_subb_u32_e64 v4, s[4:5], v12, v3, vcc
-; CGP-NEXT:    v_sub_i32_e64 v3, s[4:5], v12, v3
-; CGP-NEXT:    v_subbrev_u32_e32 v3, vcc, 0, v3, vcc
+; CGP-NEXT:    v_add_i32_e32 v3, vcc, v3, v9
+; CGP-NEXT:    v_cndmask_b32_e64 v9, 0, 1, vcc
+; CGP-NEXT:    v_add_i32_e32 v6, vcc, v6, v9
+; CGP-NEXT:    v_add_i32_e32 v9, vcc, v3, v5
+; CGP-NEXT:    v_mul_hi_u32 v10, v12, v2
+; CGP-NEXT:    v_mad_u64_u32 v[2:3], s[4:5], s7, v9, 0
+; CGP-NEXT:    v_cndmask_b32_e64 v5, 0, 1, vcc
+; CGP-NEXT:    v_add_i32_e32 v5, vcc, v6, v5
+; CGP-NEXT:    v_add_i32_e32 v10, vcc, v10, v5
+; CGP-NEXT:    v_mad_u64_u32 v[5:6], s[4:5], s7, v10, v[3:4]
+; CGP-NEXT:    v_sub_i32_e32 v2, vcc, v7, v2
+; CGP-NEXT:    v_subb_u32_e64 v3, s[4:5], v12, v5, vcc
+; CGP-NEXT:    v_sub_i32_e64 v5, s[4:5], v12, v5
+; CGP-NEXT:    v_subbrev_u32_e32 v5, vcc, 0, v5, vcc
 ; CGP-NEXT:    s_bfe_i32 s6, -1, 0x10000
-; CGP-NEXT:    v_cmp_ge_u32_e64 s[4:5], v2, v5
-; CGP-NEXT:    v_sub_i32_e32 v2, vcc, v2, v5
+; CGP-NEXT:    v_cmp_ge_u32_e64 s[4:5], v2, v4
+; CGP-NEXT:    v_sub_i32_e32 v2, vcc, v2, v4
 ; CGP-NEXT:    v_cndmask_b32_e64 v6, 0, -1, s[4:5]
 ; CGP-NEXT:    v_mov_b32_e32 v7, s6
-; CGP-NEXT:    v_cmp_eq_u32_e64 s[4:5], 0, v4
-; CGP-NEXT:    v_subbrev_u32_e32 v3, vcc, 0, v3, vcc
-; CGP-NEXT:    v_cndmask_b32_e64 v4, v7, v6, s[4:5]
-; CGP-NEXT:    v_add_i32_e32 v6, vcc, 1, v11
-; CGP-NEXT:    v_addc_u32_e32 v7, vcc, 0, v13, vcc
+; CGP-NEXT:    v_cmp_eq_u32_e64 s[4:5], 0, v3
+; CGP-NEXT:    v_subbrev_u32_e32 v5, vcc, 0, v5, vcc
+; CGP-NEXT:    v_cndmask_b32_e64 v3, v7, v6, s[4:5]
+; CGP-NEXT:    v_add_i32_e32 v6, vcc, 1, v9
+; CGP-NEXT:    v_addc_u32_e32 v7, vcc, 0, v10, vcc
 ; CGP-NEXT:    s_bfe_i32 s4, -1, 0x10000
-; CGP-NEXT:    v_cmp_ge_u32_e32 vcc, v2, v5
+; CGP-NEXT:    v_cmp_ge_u32_e32 vcc, v2, v4
 ; CGP-NEXT:    v_cndmask_b32_e64 v2, 0, -1, vcc
-; CGP-NEXT:    v_mov_b32_e32 v5, s4
-; CGP-NEXT:    v_cmp_eq_u32_e32 vcc, 0, v3
-; CGP-NEXT:    v_cndmask_b32_e32 v2, v5, v2, vcc
-; CGP-NEXT:    v_add_i32_e32 v3, vcc, 1, v6
+; CGP-NEXT:    v_mov_b32_e32 v4, s4
+; CGP-NEXT:    v_cmp_eq_u32_e32 vcc, 0, v5
+; CGP-NEXT:    v_cndmask_b32_e32 v2, v4, v2, vcc
+; CGP-NEXT:    v_add_i32_e32 v4, vcc, 1, v6
 ; CGP-NEXT:    v_addc_u32_e32 v5, vcc, 0, v7, vcc
 ; CGP-NEXT:    v_cmp_ne_u32_e32 vcc, 0, v2
-; CGP-NEXT:    v_cndmask_b32_e32 v2, v6, v3, vcc
-; CGP-NEXT:    v_cndmask_b32_e32 v3, v7, v5, vcc
-; CGP-NEXT:    v_cmp_ne_u32_e32 vcc, 0, v4
-; CGP-NEXT:    v_cndmask_b32_e32 v2, v11, v2, vcc
-; CGP-NEXT:    v_cndmask_b32_e32 v3, v13, v3, vcc
+; CGP-NEXT:    v_cndmask_b32_e32 v2, v6, v4, vcc
+; CGP-NEXT:    v_cndmask_b32_e32 v4, v7, v5, vcc
+; CGP-NEXT:    v_cmp_ne_u32_e32 vcc, 0, v3
+; CGP-NEXT:    v_cndmask_b32_e32 v2, v9, v2, vcc
+; CGP-NEXT:    v_cndmask_b32_e32 v3, v10, v4, vcc
 ; CGP-NEXT:    v_xor_b32_e32 v2, v2, v8
 ; CGP-NEXT:    v_xor_b32_e32 v3, v3, v8
 ; CGP-NEXT:    v_sub_i32_e32 v2, vcc, v2, v8
diff --git a/llvm/test/CodeGen/AMDGPU/GlobalISel/srem.i64.ll b/llvm/test/CodeGen/AMDGPU/GlobalISel/srem.i64.ll
--- a/llvm/test/CodeGen/AMDGPU/GlobalISel/srem.i64.ll
+++ b/llvm/test/CodeGen/AMDGPU/GlobalISel/srem.i64.ll
@@ -1017,86 +1017,85 @@
 ; CHECK-NEXT:    v_addc_u32_e32 v6, vcc, v6, v3, vcc
 ; CHECK-NEXT:    v_mad_u64_u32 v[2:3], s[4:5], s6, v5, 0
 ; CHECK-NEXT:    v_ashrrev_i32_e32 v7, 31, v1
-; CHECK-NEXT:    v_add_i32_e32 v0, vcc, v0, v7
+; CHECK-NEXT:    v_add_i32_e32 v8, vcc, v0, v7
 ; CHECK-NEXT:    v_mad_u64_u32 v[3:4], s[4:5], s6, v6, v[3:4]
-; CHECK-NEXT:    v_addc_u32_e32 v1, vcc, v1, v7, vcc
-; CHECK-NEXT:    v_mad_u64_u32 v[3:4], s[4:5], -1, v5, v[3:4]
-; CHECK-NEXT:    v_xor_b32_e32 v4, v0, v7
-; CHECK-NEXT:    v_mul_lo_u32 v0, v6, v2
-; CHECK-NEXT:    v_mul_lo_u32 v8, v5, v3
-; CHECK-NEXT:    v_xor_b32_e32 v9, v1, v7
-; CHECK-NEXT:    v_mul_hi_u32 v1, v5, v2
+; CHECK-NEXT:    v_addc_u32_e32 v9, vcc, v1, v7, vcc
+; CHECK-NEXT:    v_mad_u64_u32 v[0:1], s[4:5], -1, v5, v[3:4]
+; CHECK-NEXT:    v_xor_b32_e32 v3, v8, v7
+; CHECK-NEXT:    v_mul_lo_u32 v1, v6, v2
+; CHECK-NEXT:    v_mul_lo_u32 v8, v5, v0
+; CHECK-NEXT:    v_xor_b32_e32 v4, v9, v7
+; CHECK-NEXT:    v_mul_hi_u32 v9, v5, v2
 ; CHECK-NEXT:    v_mul_hi_u32 v2, v6, v2
-; CHECK-NEXT:    v_add_i32_e32 v0, vcc, v0, v8
-; CHECK-NEXT:    v_cndmask_b32_e64 v8, 0, 1, vcc
-; CHECK-NEXT:    v_add_i32_e32 v0, vcc, v0, v1
-; CHECK-NEXT:    v_cndmask_b32_e64 v0, 0, 1, vcc
-; CHECK-NEXT:    v_mul_lo_u32 v1, v6, v3
-; CHECK-NEXT:    v_add_i32_e32 v0, vcc, v8, v0
-; CHECK-NEXT:    v_mul_hi_u32 v8, v5, v3
-; CHECK-NEXT:    v_add_i32_e32 v1, vcc, v1, v2
-; CHECK-NEXT:    v_cndmask_b32_e64 v2, 0, 1, vcc
 ; CHECK-NEXT:    v_add_i32_e32 v1, vcc, v1, v8
 ; CHECK-NEXT:    v_cndmask_b32_e64 v8, 0, 1, vcc
-; CHECK-NEXT:    v_add_i32_e32 v2, vcc, v2, v8
-; CHECK-NEXT:    v_mul_hi_u32 v3, v6, v3
-; CHECK-NEXT:    v_add_i32_e32 v0, vcc, v1, v0
+; CHECK-NEXT:    v_add_i32_e32 v1, vcc, v1, v9
 ; CHECK-NEXT:    v_cndmask_b32_e64 v1, 0, 1, vcc
+; CHECK-NEXT:    v_mul_lo_u32 v9, v6, v0
+; CHECK-NEXT:    v_add_i32_e32 v1, vcc, v8, v1
+; CHECK-NEXT:    v_mul_hi_u32 v8, v5, v0
+; CHECK-NEXT:    v_add_i32_e32 v2, vcc, v9, v2
+; CHECK-NEXT:    v_cndmask_b32_e64 v9, 0, 1, vcc
+; CHECK-NEXT:    v_add_i32_e32 v2, vcc, v2, v8
+; CHECK-NEXT:    v_cndmask_b32_e64 v8, 0, 1, vcc
+; CHECK-NEXT:    v_add_i32_e32 v8, vcc, v9, v8
+; CHECK-NEXT:    v_mul_hi_u32 v0, v6, v0
 ; CHECK-NEXT:    v_add_i32_e32 v1, vcc, v2, v1
-; CHECK-NEXT:    v_add_i32_e32 v1, vcc, v3, v1
-; CHECK-NEXT:    v_add_i32_e32 v0, vcc, v5, v0
-; CHECK-NEXT:    v_addc_u32_e32 v1, vcc, v6, v1, vcc
-; CHECK-NEXT:    v_mul_lo_u32 v2, v9, v0
-; CHECK-NEXT:    v_mul_lo_u32 v3, v4, v1
-; CHECK-NEXT:    v_mul_hi_u32 v5, v4, v0
-; CHECK-NEXT:    v_mul_hi_u32 v0, v9, v0
+; CHECK-NEXT:    v_cndmask_b32_e64 v2, 0, 1, vcc
+; CHECK-NEXT:    v_add_i32_e32 v2, vcc, v8, v2
+; CHECK-NEXT:    v_add_i32_e32 v0, vcc, v0, v2
+; CHECK-NEXT:    v_add_i32_e32 v1, vcc, v5, v1
+; CHECK-NEXT:    v_addc_u32_e32 v0, vcc, v6, v0, vcc
+; CHECK-NEXT:    v_mul_lo_u32 v2, v4, v1
+; CHECK-NEXT:    v_mul_lo_u32 v5, v3, v0
+; CHECK-NEXT:    v_mul_hi_u32 v8, v3, v1
+; CHECK-NEXT:    v_mul_hi_u32 v1, v4, v1
 ; CHECK-NEXT:    s_movk_i32 s6, 0x1000
-; CHECK-NEXT:    v_add_i32_e32 v2, vcc, v2, v3
-; CHECK-NEXT:    v_cndmask_b32_e64 v3, 0, 1, vcc
 ; CHECK-NEXT:    v_add_i32_e32 v2, vcc, v2, v5
+; CHECK-NEXT:    v_cndmask_b32_e64 v5, 0, 1, vcc
+; CHECK-NEXT:    v_add_i32_e32 v2, vcc, v2, v8
 ; CHECK-NEXT:    v_cndmask_b32_e64 v2, 0, 1, vcc
-; CHECK-NEXT:    v_mul_lo_u32 v5, v9, v1
-; CHECK-NEXT:    v_add_i32_e32 v2, vcc, v3, v2
-; CHECK-NEXT:    v_mul_hi_u32 v3, v4, v1
-; CHECK-NEXT:    v_add_i32_e32 v0, vcc, v5, v0
+; CHECK-NEXT:    v_mul_lo_u32 v8, v4, v0
+; CHECK-NEXT:    v_add_i32_e32 v2, vcc, v5, v2
+; CHECK-NEXT:    v_mul_hi_u32 v5, v3, v0
+; CHECK-NEXT:    v_add_i32_e32 v1, vcc, v8, v1
+; CHECK-NEXT:    v_cndmask_b32_e64 v8, 0, 1, vcc
+; CHECK-NEXT:    v_add_i32_e32 v1, vcc, v1, v5
 ; CHECK-NEXT:    v_cndmask_b32_e64 v5, 0, 1, vcc
-; CHECK-NEXT:    v_add_i32_e32 v0, vcc, v0, v3
-; CHECK-NEXT:    v_cndmask_b32_e64 v3, 0, 1, vcc
-; CHECK-NEXT:    v_add_i32_e32 v3, vcc, v5, v3
-; CHECK-NEXT:    v_add_i32_e32 v5, vcc, v0, v2
-; CHECK-NEXT:    v_mul_hi_u32 v6, v9, v1
-; CHECK-NEXT:    v_mad_u64_u32 v[0:1], s[4:5], s6, v5, 0
+; CHECK-NEXT:    v_add_i32_e32 v5, vcc, v8, v5
+; CHECK-NEXT:    v_add_i32_e32 v1, vcc, v1, v2
+; CHECK-NEXT:    v_mul_hi_u32 v8, v4, v0
+; CHECK-NEXT:    v_mad_u64_u32 v[0:1], s[4:5], s6, v1, 0
 ; CHECK-NEXT:    v_cndmask_b32_e64 v2, 0, 1, vcc
-; CHECK-NEXT:    v_add_i32_e32 v2, vcc, v3, v2
-; CHECK-NEXT:    v_add_i32_e32 v2, vcc, v6, v2
+; CHECK-NEXT:    v_add_i32_e32 v2, vcc, v5, v2
+; CHECK-NEXT:    v_add_i32_e32 v2, vcc, v8, v2
 ; CHECK-NEXT:    v_mad_u64_u32 v[1:2], s[4:5], s6, v2, v[1:2]
-; CHECK-NEXT:    v_sub_i32_e32 v0, vcc, v4, v0
-; CHECK-NEXT:    v_mad_u64_u32 v[1:2], s[4:5], 0, v5, v[1:2]
-; CHECK-NEXT:    v_mov_b32_e32 v3, 0x1000
+; CHECK-NEXT:    v_sub_i32_e32 v0, vcc, v3, v0
+; CHECK-NEXT:    v_mov_b32_e32 v6, 0x1000
+; CHECK-NEXT:    v_subb_u32_e64 v2, s[4:5], v4, v1, vcc
+; CHECK-NEXT:    v_sub_i32_e64 v1, s[4:5], v4, v1
 ; CHECK-NEXT:    s_bfe_i32 s6, -1, 0x10000
-; CHECK-NEXT:    v_subb_u32_e64 v2, s[4:5], v9, v1, vcc
-; CHECK-NEXT:    v_sub_i32_e64 v1, s[4:5], v9, v1
-; CHECK-NEXT:    v_cmp_ge_u32_e64 s[4:5], v0, v3
-; CHECK-NEXT:    v_cndmask_b32_e64 v4, 0, -1, s[4:5]
-; CHECK-NEXT:    v_mov_b32_e32 v5, s6
+; CHECK-NEXT:    v_cmp_ge_u32_e64 s[4:5], v0, v6
+; CHECK-NEXT:    v_cndmask_b32_e64 v3, 0, -1, s[4:5]
+; CHECK-NEXT:    v_mov_b32_e32 v4, s6
 ; CHECK-NEXT:    v_cmp_eq_u32_e64 s[4:5], 0, v2
 ; CHECK-NEXT:    v_subbrev_u32_e32 v1, vcc, 0, v1, vcc
-; CHECK-NEXT:    v_cndmask_b32_e64 v4, v5, v4, s[4:5]
-; CHECK-NEXT:    v_sub_i32_e32 v5, vcc, v0, v3
+; CHECK-NEXT:    v_cndmask_b32_e64 v3, v4, v3, s[4:5]
+; CHECK-NEXT:    v_sub_i32_e32 v4, vcc, v0, v6
 ; CHECK-NEXT:    v_subbrev_u32_e32 v1, vcc, 0, v1, vcc
 ; CHECK-NEXT:    s_bfe_i32 s4, -1, 0x10000
-; CHECK-NEXT:    v_cmp_ge_u32_e32 vcc, v5, v3
-; CHECK-NEXT:    v_cndmask_b32_e64 v6, 0, -1, vcc
+; CHECK-NEXT:    v_cmp_ge_u32_e32 vcc, v4, v6
+; CHECK-NEXT:    v_cndmask_b32_e64 v5, 0, -1, vcc
 ; CHECK-NEXT:    v_mov_b32_e32 v8, s4
 ; CHECK-NEXT:    v_cmp_eq_u32_e32 vcc, 0, v1
-; CHECK-NEXT:    v_cndmask_b32_e32 v6, v8, v6, vcc
-; CHECK-NEXT:    v_sub_i32_e32 v3, vcc, v5, v3
+; CHECK-NEXT:    v_cndmask_b32_e32 v5, v8, v5, vcc
+; CHECK-NEXT:    v_sub_i32_e32 v6, vcc, v4, v6
 ; CHECK-NEXT:    v_subbrev_u32_e32 v8, vcc, 0, v1, vcc
-; CHECK-NEXT:    v_cmp_ne_u32_e32 vcc, 0, v6
-; CHECK-NEXT:    v_cndmask_b32_e32 v3, v5, v3, vcc
+; CHECK-NEXT:    v_cmp_ne_u32_e32 vcc, 0, v5
+; CHECK-NEXT:    v_cndmask_b32_e32 v4, v4, v6, vcc
 ; CHECK-NEXT:    v_cndmask_b32_e32 v1, v1, v8, vcc
-; CHECK-NEXT:    v_cmp_ne_u32_e32 vcc, 0, v4
-; CHECK-NEXT:    v_cndmask_b32_e32 v0, v0, v3, vcc
+; CHECK-NEXT:    v_cmp_ne_u32_e32 vcc, 0, v3
+; CHECK-NEXT:    v_cndmask_b32_e32 v0, v0, v4, vcc
 ; CHECK-NEXT:    v_cndmask_b32_e32 v1, v2, v1, vcc
 ; CHECK-NEXT:    v_xor_b32_e32 v0, v0, v7
 ; CHECK-NEXT:    v_xor_b32_e32 v1, v1, v7
@@ -1415,68 +1414,67 @@
 ; CGP-NEXT:    v_add_i32_e32 v6, vcc, v9, v6
 ; CGP-NEXT:    v_add_i32_e32 v5, vcc, v5, v6
 ; CGP-NEXT:    v_add_i32_e32 v9, vcc, v7, v4
-; CGP-NEXT:    v_addc_u32_e32 v8, vcc, v8, v5, vcc
-; CGP-NEXT:    v_mad_u64_u32 v[5:6], s[4:5], s6, v9, 0
-; CGP-NEXT:    v_mov_b32_e32 v4, v6
-; CGP-NEXT:    v_mad_u64_u32 v[6:7], s[4:5], s6, v8, v[4:5]
-; CGP-NEXT:    v_ashrrev_i32_e32 v4, 31, v1
-; CGP-NEXT:    v_add_i32_e32 v0, vcc, v0, v4
-; CGP-NEXT:    v_mad_u64_u32 v[6:7], s[4:5], -1, v9, v[6:7]
-; CGP-NEXT:    v_addc_u32_e32 v1, vcc, v1, v4, vcc
-; CGP-NEXT:    v_xor_b32_e32 v10, v0, v4
-; CGP-NEXT:    v_mul_lo_u32 v0, v8, v5
-; CGP-NEXT:    v_mul_lo_u32 v7, v9, v6
-; CGP-NEXT:    v_xor_b32_e32 v11, v1, v4
-; CGP-NEXT:    v_mul_hi_u32 v1, v9, v5
-; CGP-NEXT:    v_mul_hi_u32 v5, v8, v5
-; CGP-NEXT:    v_add_i32_e32 v0, vcc, v0, v7
-; CGP-NEXT:    v_cndmask_b32_e64 v7, 0, 1, vcc
-; CGP-NEXT:    v_add_i32_e32 v0, vcc, v0, v1
-; CGP-NEXT:    v_cndmask_b32_e64 v0, 0, 1, vcc
-; CGP-NEXT:    v_mul_lo_u32 v1, v8, v6
-; CGP-NEXT:    v_add_i32_e32 v0, vcc, v7, v0
+; CGP-NEXT:    v_mad_u64_u32 v[6:7], s[4:5], s6, v9, 0
+; CGP-NEXT:    v_addc_u32_e32 v10, vcc, v8, v5, vcc
+; CGP-NEXT:    v_ashrrev_i32_e32 v5, 31, v1
+; CGP-NEXT:    v_mov_b32_e32 v4, v7
+; CGP-NEXT:    v_mad_u64_u32 v[7:8], s[4:5], s6, v10, v[4:5]
+; CGP-NEXT:    v_add_i32_e32 v4, vcc, v0, v5
+; CGP-NEXT:    v_addc_u32_e32 v11, vcc, v1, v5, vcc
+; CGP-NEXT:    v_mad_u64_u32 v[0:1], s[4:5], -1, v9, v[7:8]
+; CGP-NEXT:    v_xor_b32_e32 v8, v4, v5
+; CGP-NEXT:    v_mul_lo_u32 v1, v10, v6
+; CGP-NEXT:    v_mul_lo_u32 v4, v9, v0
 ; CGP-NEXT:    v_mul_hi_u32 v7, v9, v6
-; CGP-NEXT:    v_add_i32_e32 v1, vcc, v1, v5
-; CGP-NEXT:    v_cndmask_b32_e64 v5, 0, 1, vcc
+; CGP-NEXT:    v_mul_hi_u32 v6, v10, v6
+; CGP-NEXT:    v_xor_b32_e32 v11, v11, v5
+; CGP-NEXT:    v_add_i32_e32 v1, vcc, v1, v4
+; CGP-NEXT:    v_cndmask_b32_e64 v4, 0, 1, vcc
 ; CGP-NEXT:    v_add_i32_e32 v1, vcc, v1, v7
-; CGP-NEXT:    v_cndmask_b32_e64 v7, 0, 1, vcc
-; CGP-NEXT:    v_add_i32_e32 v5, vcc, v5, v7
-; CGP-NEXT:    v_mul_hi_u32 v6, v8, v6
-; CGP-NEXT:    v_add_i32_e32 v0, vcc, v1, v0
 ; CGP-NEXT:    v_cndmask_b32_e64 v1, 0, 1, vcc
-; CGP-NEXT:    v_add_i32_e32 v1, vcc, v5, v1
-; CGP-NEXT:    v_add_i32_e32 v1, vcc, v6, v1
-; CGP-NEXT:    v_add_i32_e32 v0, vcc, v9, v0
-; CGP-NEXT:    v_addc_u32_e32 v1, vcc, v8, v1, vcc
-; CGP-NEXT:    v_mul_lo_u32 v5, v11, v0
-; CGP-NEXT:    v_mul_lo_u32 v6, v10, v1
-; CGP-NEXT:    v_mul_hi_u32 v7, v10, v0
-; CGP-NEXT:    v_mul_hi_u32 v0, v11, v0
-; CGP-NEXT:    v_add_i32_e32 v5, vcc, v5, v6
+; CGP-NEXT:    v_mul_lo_u32 v7, v10, v0
+; CGP-NEXT:    v_add_i32_e32 v1, vcc, v4, v1
+; CGP-NEXT:    v_mul_hi_u32 v4, v9, v0
+; CGP-NEXT:    v_add_i32_e32 v6, vcc, v7, v6
+; CGP-NEXT:    v_cndmask_b32_e64 v7, 0, 1, vcc
+; CGP-NEXT:    v_add_i32_e32 v4, vcc, v6, v4
 ; CGP-NEXT:    v_cndmask_b32_e64 v6, 0, 1, vcc
-; CGP-NEXT:    v_add_i32_e32 v5, vcc, v5, v7
-; CGP-NEXT:    v_cndmask_b32_e64 v5, 0, 1, vcc
-; CGP-NEXT:    v_mul_lo_u32 v7, v11, v1
-; CGP-NEXT:    v_add_i32_e32 v5, vcc, v6, v5
-; CGP-NEXT:    v_mul_hi_u32 v6, v10, v1
-; CGP-NEXT:    v_add_i32_e32 v0, vcc, v7, v0
+; CGP-NEXT:    v_add_i32_e32 v6, vcc, v7, v6
+; CGP-NEXT:    v_mul_hi_u32 v0, v10, v0
+; CGP-NEXT:    v_add_i32_e32 v1, vcc, v4, v1
+; CGP-NEXT:    v_cndmask_b32_e64 v4, 0, 1, vcc
+; CGP-NEXT:    v_add_i32_e32 v4, vcc, v6, v4
+; CGP-NEXT:    v_add_i32_e32 v0, vcc, v0, v4
+; CGP-NEXT:    v_add_i32_e32 v1, vcc, v9, v1
+; CGP-NEXT:    v_addc_u32_e32 v0, vcc, v10, v0, vcc
+; CGP-NEXT:    v_mul_lo_u32 v6, v11, v1
+; CGP-NEXT:    v_mul_lo_u32 v7, v8, v0
+; CGP-NEXT:    v_mul_hi_u32 v9, v8, v1
+; CGP-NEXT:    v_mul_hi_u32 v1, v11, v1
+; CGP-NEXT:    v_mov_b32_e32 v4, 0x1000
+; CGP-NEXT:    v_add_i32_e32 v6, vcc, v6, v7
 ; CGP-NEXT:    v_cndmask_b32_e64 v7, 0, 1, vcc
-; CGP-NEXT:    v_add_i32_e32 v0, vcc, v0, v6
+; CGP-NEXT:    v_add_i32_e32 v6, vcc, v6, v9
 ; CGP-NEXT:    v_cndmask_b32_e64 v6, 0, 1, vcc
+; CGP-NEXT:    v_mul_lo_u32 v9, v11, v0
 ; CGP-NEXT:    v_add_i32_e32 v6, vcc, v7, v6
-; CGP-NEXT:    v_add_i32_e32 v8, vcc, v0, v5
-; CGP-NEXT:    v_mul_hi_u32 v7, v11, v1
-; CGP-NEXT:    v_mad_u64_u32 v[0:1], s[4:5], s7, v8, 0
-; CGP-NEXT:    v_cndmask_b32_e64 v5, 0, 1, vcc
-; CGP-NEXT:    v_add_i32_e32 v5, vcc, v6, v5
-; CGP-NEXT:    v_add_i32_e32 v5, vcc, v7, v5
-; CGP-NEXT:    v_mad_u64_u32 v[6:7], s[4:5], s7, v5, v[1:2]
-; CGP-NEXT:    v_mov_b32_e32 v5, 0x1000
-; CGP-NEXT:    v_mad_u64_u32 v[6:7], s[4:5], 0, v8, v[6:7]
-; CGP-NEXT:    v_sub_i32_e32 v8, vcc, v10, v0
+; CGP-NEXT:    v_mul_hi_u32 v7, v8, v0
+; CGP-NEXT:    v_add_i32_e32 v1, vcc, v9, v1
+; CGP-NEXT:    v_cndmask_b32_e64 v9, 0, 1, vcc
+; CGP-NEXT:    v_add_i32_e32 v1, vcc, v1, v7
+; CGP-NEXT:    v_cndmask_b32_e64 v7, 0, 1, vcc
+; CGP-NEXT:    v_add_i32_e32 v7, vcc, v9, v7
+; CGP-NEXT:    v_add_i32_e32 v1, vcc, v1, v6
+; CGP-NEXT:    v_mul_hi_u32 v9, v11, v0
+; CGP-NEXT:    v_mad_u64_u32 v[0:1], s[4:5], s7, v1, 0
+; CGP-NEXT:    v_cndmask_b32_e64 v6, 0, 1, vcc
+; CGP-NEXT:    v_add_i32_e32 v6, vcc, v7, v6
+; CGP-NEXT:    v_add_i32_e32 v6, vcc, v9, v6
+; CGP-NEXT:    v_mad_u64_u32 v[6:7], s[4:5], s7, v6, v[1:2]
+; CGP-NEXT:    v_sub_i32_e32 v8, vcc, v8, v0
 ; CGP-NEXT:    v_subb_u32_e64 v9, s[4:5], v11, v6, vcc
 ; CGP-NEXT:    v_sub_i32_e64 v0, s[4:5], v11, v6
-; CGP-NEXT:    v_cmp_ge_u32_e64 s[4:5], v8, v5
+; CGP-NEXT:    v_cmp_ge_u32_e64 s[4:5], v8, v4
 ; CGP-NEXT:    v_cndmask_b32_e64 v1, 0, -1, s[4:5]
 ; CGP-NEXT:    v_mov_b32_e32 v6, s8
 ; CGP-NEXT:    v_cmp_eq_u32_e64 s[4:5], 0, v9
@@ -1486,7 +1484,7 @@
 ; CGP-NEXT:    v_subbrev_u32_e32 v0, vcc, 0, v0, vcc
 ; CGP-NEXT:    v_mac_f32_e32 v1, 0x4f800000, v6
 ; CGP-NEXT:    v_rcp_iflag_f32_e32 v1, v1
-; CGP-NEXT:    v_sub_i32_e32 v11, vcc, v8, v5
+; CGP-NEXT:    v_sub_i32_e32 v11, vcc, v8, v4
 ; CGP-NEXT:    v_subbrev_u32_e32 v12, vcc, 0, v0, vcc
 ; CGP-NEXT:    v_mul_f32_e32 v0, 0x5f7ffffc, v1
 ; CGP-NEXT:    v_mul_f32_e32 v1, 0x2f800000, v0
@@ -1497,12 +1495,12 @@
 ; CGP-NEXT:    v_mov_b32_e32 v14, s4
 ; CGP-NEXT:    v_cvt_u32_f32_e32 v15, v6
 ; CGP-NEXT:    v_mad_u64_u32 v[0:1], s[4:5], s6, v13, 0
-; CGP-NEXT:    v_cmp_ge_u32_e32 vcc, v11, v5
+; CGP-NEXT:    v_cmp_ge_u32_e32 vcc, v11, v4
 ; CGP-NEXT:    v_cndmask_b32_e64 v7, 0, -1, vcc
 ; CGP-NEXT:    v_cmp_eq_u32_e32 vcc, 0, v12
 ; CGP-NEXT:    v_cndmask_b32_e32 v14, v14, v7, vcc
 ; CGP-NEXT:    v_mad_u64_u32 v[6:7], s[4:5], s6, v15, v[1:2]
-; CGP-NEXT:    v_sub_i32_e32 v1, vcc, v11, v5
+; CGP-NEXT:    v_sub_i32_e32 v1, vcc, v11, v4
 ; CGP-NEXT:    v_mad_u64_u32 v[6:7], s[4:5], -1, v13, v[6:7]
 ; CGP-NEXT:    v_subbrev_u32_e32 v16, vcc, 0, v12, vcc
 ; CGP-NEXT:    v_cmp_ne_u32_e32 vcc, 0, v14
@@ -1533,93 +1531,91 @@
 ; CGP-NEXT:    v_addc_u32_e32 v13, vcc, v15, v1, vcc
 ; CGP-NEXT:    v_mad_u64_u32 v[0:1], s[4:5], s6, v11, 0
 ; CGP-NEXT:    v_cmp_ne_u32_e32 vcc, 0, v10
-; CGP-NEXT:    v_cndmask_b32_e32 v8, v8, v7, vcc
+; CGP-NEXT:    v_cndmask_b32_e32 v6, v8, v7, vcc
+; CGP-NEXT:    v_cndmask_b32_e32 v8, v9, v12, vcc
+; CGP-NEXT:    v_xor_b32_e32 v9, v6, v5
 ; CGP-NEXT:    v_mad_u64_u32 v[6:7], s[4:5], s6, v13, v[1:2]
-; CGP-NEXT:    v_xor_b32_e32 v1, v8, v4
+; CGP-NEXT:    v_xor_b32_e32 v1, v8, v5
 ; CGP-NEXT:    v_ashrrev_i32_e32 v8, 31, v3
 ; CGP-NEXT:    v_mad_u64_u32 v[6:7], s[4:5], -1, v11, v[6:7]
-; CGP-NEXT:    v_cndmask_b32_e32 v9, v9, v12, vcc
 ; CGP-NEXT:    v_add_i32_e32 v2, vcc, v2, v8
 ; CGP-NEXT:    v_addc_u32_e32 v3, vcc, v3, v8, vcc
-; CGP-NEXT:    v_xor_b32_e32 v10, v2, v8
+; CGP-NEXT:    v_xor_b32_e32 v7, v2, v8
 ; CGP-NEXT:    v_mul_lo_u32 v2, v13, v0
-; CGP-NEXT:    v_mul_lo_u32 v7, v11, v6
+; CGP-NEXT:    v_mul_lo_u32 v10, v11, v6
 ; CGP-NEXT:    v_xor_b32_e32 v12, v3, v8
 ; CGP-NEXT:    v_mul_hi_u32 v3, v11, v0
 ; CGP-NEXT:    v_mul_hi_u32 v0, v13, v0
-; CGP-NEXT:    v_add_i32_e32 v2, vcc, v2, v7
-; CGP-NEXT:    v_cndmask_b32_e64 v7, 0, 1, vcc
+; CGP-NEXT:    v_add_i32_e32 v2, vcc, v2, v10
+; CGP-NEXT:    v_cndmask_b32_e64 v10, 0, 1, vcc
 ; CGP-NEXT:    v_add_i32_e32 v2, vcc, v2, v3
 ; CGP-NEXT:    v_cndmask_b32_e64 v2, 0, 1, vcc
 ; CGP-NEXT:    v_mul_lo_u32 v3, v13, v6
-; CGP-NEXT:    v_add_i32_e32 v2, vcc, v7, v2
-; CGP-NEXT:    v_mul_hi_u32 v7, v11, v6
+; CGP-NEXT:    v_add_i32_e32 v2, vcc, v10, v2
+; CGP-NEXT:    v_mul_hi_u32 v10, v11, v6
 ; CGP-NEXT:    v_add_i32_e32 v0, vcc, v3, v0
 ; CGP-NEXT:    v_cndmask_b32_e64 v3, 0, 1, vcc
-; CGP-NEXT:    v_add_i32_e32 v0, vcc, v0, v7
-; CGP-NEXT:    v_cndmask_b32_e64 v7, 0, 1, vcc
-; CGP-NEXT:    v_add_i32_e32 v3, vcc, v3, v7
+; CGP-NEXT:    v_add_i32_e32 v0, vcc, v0, v10
+; CGP-NEXT:    v_cndmask_b32_e64 v10, 0, 1, vcc
+; CGP-NEXT:    v_add_i32_e32 v3, vcc, v3, v10
 ; CGP-NEXT:    v_mul_hi_u32 v6, v13, v6
 ; CGP-NEXT:    v_add_i32_e32 v0, vcc, v0, v2
 ; CGP-NEXT:    v_cndmask_b32_e64 v2, 0, 1, vcc
 ; CGP-NEXT:    v_add_i32_e32 v2, vcc, v3, v2
 ; CGP-NEXT:    v_add_i32_e32 v2, vcc, v6, v2
-; CGP-NEXT:    v_add_i32_e32 v0, vcc, v11, v0
+; CGP-NEXT:    v_add_i32_e32 v3, vcc, v11, v0
 ; CGP-NEXT:    v_addc_u32_e32 v2, vcc, v13, v2, vcc
-; CGP-NEXT:    v_mul_lo_u32 v3, v12, v0
-; CGP-NEXT:    v_mul_lo_u32 v6, v10, v2
-; CGP-NEXT:    v_mul_hi_u32 v7, v10, v0
-; CGP-NEXT:    v_mul_hi_u32 v0, v12, v0
-; CGP-NEXT:    v_xor_b32_e32 v9, v9, v4
-; CGP-NEXT:    v_add_i32_e32 v3, vcc, v3, v6
-; CGP-NEXT:    v_cndmask_b32_e64 v6, 0, 1, vcc
-; CGP-NEXT:    v_add_i32_e32 v3, vcc, v3, v7
-; CGP-NEXT:    v_cndmask_b32_e64 v3, 0, 1, vcc
-; CGP-NEXT:    v_mul_lo_u32 v7, v12, v2
+; CGP-NEXT:    v_mul_lo_u32 v6, v12, v3
+; CGP-NEXT:    v_mul_lo_u32 v10, v7, v2
+; CGP-NEXT:    v_sub_i32_e32 v0, vcc, v9, v5
+; CGP-NEXT:    v_subb_u32_e32 v1, vcc, v1, v5, vcc
+; CGP-NEXT:    v_mul_hi_u32 v5, v7, v3
+; CGP-NEXT:    v_add_i32_e32 v6, vcc, v6, v10
+; CGP-NEXT:    v_cndmask_b32_e64 v9, 0, 1, vcc
+; CGP-NEXT:    v_add_i32_e32 v5, vcc, v6, v5
+; CGP-NEXT:    v_cndmask_b32_e64 v5, 0, 1, vcc
+; CGP-NEXT:    v_mul_lo_u32 v6, v12, v2
+; CGP-NEXT:    v_mul_hi_u32 v3, v12, v3
+; CGP-NEXT:    v_add_i32_e32 v5, vcc, v9, v5
+; CGP-NEXT:    v_mul_hi_u32 v9, v7, v2
 ; CGP-NEXT:    v_add_i32_e32 v3, vcc, v6, v3
-; CGP-NEXT:    v_mul_hi_u32 v6, v10, v2
-; CGP-NEXT:    v_add_i32_e32 v0, vcc, v7, v0
-; CGP-NEXT:    v_cndmask_b32_e64 v7, 0, 1, vcc
-; CGP-NEXT:    v_add_i32_e32 v0, vcc, v0, v6
 ; CGP-NEXT:    v_cndmask_b32_e64 v6, 0, 1, vcc
-; CGP-NEXT:    v_add_i32_e32 v6, vcc, v7, v6
-; CGP-NEXT:    v_add_i32_e32 v11, vcc, v0, v3
-; CGP-NEXT:    v_mul_hi_u32 v7, v12, v2
-; CGP-NEXT:    v_mad_u64_u32 v[2:3], s[4:5], s7, v11, 0
-; CGP-NEXT:    v_cndmask_b32_e64 v0, 0, 1, vcc
-; CGP-NEXT:    v_add_i32_e32 v0, vcc, v6, v0
-; CGP-NEXT:    v_add_i32_e32 v6, vcc, v7, v0
-; CGP-NEXT:    v_mov_b32_e32 v0, v3
-; CGP-NEXT:    v_mad_u64_u32 v[6:7], s[4:5], s7, v6, v[0:1]
-; CGP-NEXT:    v_sub_i32_e32 v0, vcc, v1, v4
-; CGP-NEXT:    v_subb_u32_e32 v1, vcc, v9, v4, vcc
-; CGP-NEXT:    v_mad_u64_u32 v[3:4], s[4:5], 0, v11, v[6:7]
-; CGP-NEXT:    v_sub_i32_e32 v2, vcc, v10, v2
-; CGP-NEXT:    v_subb_u32_e64 v4, s[4:5], v12, v3, vcc
-; CGP-NEXT:    v_sub_i32_e64 v3, s[4:5], v12, v3
+; CGP-NEXT:    v_add_i32_e32 v3, vcc, v3, v9
+; CGP-NEXT:    v_cndmask_b32_e64 v9, 0, 1, vcc
+; CGP-NEXT:    v_add_i32_e32 v6, vcc, v6, v9
+; CGP-NEXT:    v_add_i32_e32 v3, vcc, v3, v5
+; CGP-NEXT:    v_mul_hi_u32 v9, v12, v2
+; CGP-NEXT:    v_mad_u64_u32 v[2:3], s[4:5], s7, v3, 0
+; CGP-NEXT:    v_cndmask_b32_e64 v5, 0, 1, vcc
+; CGP-NEXT:    v_add_i32_e32 v5, vcc, v6, v5
+; CGP-NEXT:    v_add_i32_e32 v5, vcc, v9, v5
+; CGP-NEXT:    v_mad_u64_u32 v[5:6], s[4:5], s7, v5, v[3:4]
+; CGP-NEXT:    v_sub_i32_e32 v2, vcc, v7, v2
+; CGP-NEXT:    v_subb_u32_e64 v3, s[4:5], v12, v5, vcc
+; CGP-NEXT:    v_sub_i32_e64 v5, s[4:5], v12, v5
 ; CGP-NEXT:    s_bfe_i32 s6, -1, 0x10000
-; CGP-NEXT:    v_cmp_ge_u32_e64 s[4:5], v2, v5
+; CGP-NEXT:    v_cmp_ge_u32_e64 s[4:5], v2, v4
 ; CGP-NEXT:    v_cndmask_b32_e64 v6, 0, -1, s[4:5]
 ; CGP-NEXT:    v_mov_b32_e32 v7, s6
-; CGP-NEXT:    v_cmp_eq_u32_e64 s[4:5], 0, v4
-; CGP-NEXT:    v_subbrev_u32_e32 v3, vcc, 0, v3, vcc
+; CGP-NEXT:    v_cmp_eq_u32_e64 s[4:5], 0, v3
+; CGP-NEXT:    v_subbrev_u32_e32 v5, vcc, 0, v5, vcc
 ; CGP-NEXT:    v_cndmask_b32_e64 v6, v7, v6, s[4:5]
-; CGP-NEXT:    v_sub_i32_e32 v7, vcc, v2, v5
-; CGP-NEXT:    v_subbrev_u32_e32 v3, vcc, 0, v3, vcc
+; CGP-NEXT:    v_sub_i32_e32 v7, vcc, v2, v4
+; CGP-NEXT:    v_subbrev_u32_e32 v5, vcc, 0, v5, vcc
 ; CGP-NEXT:    s_bfe_i32 s4, -1, 0x10000
-; CGP-NEXT:    v_cmp_ge_u32_e32 vcc, v7, v5
+; CGP-NEXT:    v_cmp_ge_u32_e32 vcc, v7, v4
 ; CGP-NEXT:    v_cndmask_b32_e64 v9, 0, -1, vcc
 ; CGP-NEXT:    v_mov_b32_e32 v10, s4
-; CGP-NEXT:    v_cmp_eq_u32_e32 vcc, 0, v3
+; CGP-NEXT:    v_cmp_eq_u32_e32 vcc, 0, v5
 ; CGP-NEXT:    v_cndmask_b32_e32 v9, v10, v9, vcc
-; CGP-NEXT:    v_sub_i32_e32 v5, vcc, v7, v5
-; CGP-NEXT:    v_subbrev_u32_e32 v10, vcc, 0, v3, vcc
+; CGP-NEXT:    v_sub_i32_e32 v4, vcc, v7, v4
+; CGP-NEXT:    v_subbrev_u32_e32 v10, vcc, 0, v5, vcc
 ; CGP-NEXT:    v_cmp_ne_u32_e32 vcc, 0, v9
-; CGP-NEXT:    v_cndmask_b32_e32 v5, v7, v5, vcc
-; CGP-NEXT:    v_cndmask_b32_e32 v3, v3, v10, vcc
+; CGP-NEXT:    v_cndmask_b32_e32 v4, v7, v4, vcc
+; CGP-NEXT:    v_cndmask_b32_e32 v5, v5, v10, vcc
 ; CGP-NEXT:    v_cmp_ne_u32_e32 vcc, 0, v6
-; CGP-NEXT:    v_cndmask_b32_e32 v2, v2, v5, vcc
-; CGP-NEXT:    v_cndmask_b32_e32 v3, v4, v3, vcc
+; CGP-NEXT:    v_cndmask_b32_e32 v2, v2, v4, vcc
+; CGP-NEXT:    v_cndmask_b32_e32 v3, v3, v5, vcc
 ; CGP-NEXT:    v_xor_b32_e32 v2, v2, v8
 ; CGP-NEXT:    v_xor_b32_e32 v3, v3, v8
 ; CGP-NEXT:    v_sub_i32_e32 v2, vcc, v2, v8
@@ -1673,86 +1669,85 @@
 ; CHECK-NEXT:    v_addc_u32_e32 v6, vcc, v6, v3, vcc
 ; CHECK-NEXT:    v_mad_u64_u32 v[2:3], s[4:5], s6, v5, 0
 ; CHECK-NEXT:    v_ashrrev_i32_e32 v7, 31, v1
-; CHECK-NEXT:    v_add_i32_e32 v0, vcc, v0, v7
+; CHECK-NEXT:    v_add_i32_e32 v8, vcc, v0, v7
 ; CHECK-NEXT:    v_mad_u64_u32 v[3:4], s[4:5], s6, v6, v[3:4]
-; CHECK-NEXT:    v_addc_u32_e32 v1, vcc, v1, v7, vcc
-; CHECK-NEXT:    v_mad_u64_u32 v[3:4], s[4:5], -1, v5, v[3:4]
-; CHECK-NEXT:    v_xor_b32_e32 v4, v0, v7
-; CHECK-NEXT:    v_mul_lo_u32 v0, v6, v2
-; CHECK-NEXT:    v_mul_lo_u32 v8, v5, v3
-; CHECK-NEXT:    v_xor_b32_e32 v9, v1, v7
-; CHECK-NEXT:    v_mul_hi_u32 v1, v5, v2
+; CHECK-NEXT:    v_addc_u32_e32 v9, vcc, v1, v7, vcc
+; CHECK-NEXT:    v_mad_u64_u32 v[0:1], s[4:5], -1, v5, v[3:4]
+; CHECK-NEXT:    v_xor_b32_e32 v3, v8, v7
+; CHECK-NEXT:    v_mul_lo_u32 v1, v6, v2
+; CHECK-NEXT:    v_mul_lo_u32 v8, v5, v0
+; CHECK-NEXT:    v_xor_b32_e32 v4, v9, v7
+; CHECK-NEXT:    v_mul_hi_u32 v9, v5, v2
 ; CHECK-NEXT:    v_mul_hi_u32 v2, v6, v2
-; CHECK-NEXT:    v_add_i32_e32 v0, vcc, v0, v8
-; CHECK-NEXT:    v_cndmask_b32_e64 v8, 0, 1, vcc
-; CHECK-NEXT:    v_add_i32_e32 v0, vcc, v0, v1
-; CHECK-NEXT:    v_cndmask_b32_e64 v0, 0, 1, vcc
-; CHECK-NEXT:    v_mul_lo_u32 v1, v6, v3
-; CHECK-NEXT:    v_add_i32_e32 v0, vcc, v8, v0
-; CHECK-NEXT:    v_mul_hi_u32 v8, v5, v3
-; CHECK-NEXT:    v_add_i32_e32 v1, vcc, v1, v2
-; CHECK-NEXT:    v_cndmask_b32_e64 v2, 0, 1, vcc
 ; CHECK-NEXT:    v_add_i32_e32 v1, vcc, v1, v8
 ; CHECK-NEXT:    v_cndmask_b32_e64 v8, 0, 1, vcc
-; CHECK-NEXT:    v_add_i32_e32 v2, vcc, v2, v8
-; CHECK-NEXT:    v_mul_hi_u32 v3, v6, v3
-; CHECK-NEXT:    v_add_i32_e32 v0, vcc, v1, v0
+; CHECK-NEXT:    v_add_i32_e32 v1, vcc, v1, v9
 ; CHECK-NEXT:    v_cndmask_b32_e64 v1, 0, 1, vcc
+; CHECK-NEXT:    v_mul_lo_u32 v9, v6, v0
+; CHECK-NEXT:    v_add_i32_e32 v1, vcc, v8, v1
+; CHECK-NEXT:    v_mul_hi_u32 v8, v5, v0
+; CHECK-NEXT:    v_add_i32_e32 v2, vcc, v9, v2
+; CHECK-NEXT:    v_cndmask_b32_e64 v9, 0, 1, vcc
+; CHECK-NEXT:    v_add_i32_e32 v2, vcc, v2, v8
+; CHECK-NEXT:    v_cndmask_b32_e64 v8, 0, 1, vcc
+; CHECK-NEXT:    v_add_i32_e32 v8, vcc, v9, v8
+; CHECK-NEXT:    v_mul_hi_u32 v0, v6, v0
 ; CHECK-NEXT:    v_add_i32_e32 v1, vcc, v2, v1
-; CHECK-NEXT:    v_add_i32_e32 v1, vcc, v3, v1
-; CHECK-NEXT:    v_add_i32_e32 v0, vcc, v5, v0
-; CHECK-NEXT:    v_addc_u32_e32 v1, vcc, v6, v1, vcc
-; CHECK-NEXT:    v_mul_lo_u32 v2, v9, v0
-; CHECK-NEXT:    v_mul_lo_u32 v3, v4, v1
-; CHECK-NEXT:    v_mul_hi_u32 v5, v4, v0
-; CHECK-NEXT:    v_mul_hi_u32 v0, v9, v0
+; CHECK-NEXT:    v_cndmask_b32_e64 v2, 0, 1, vcc
+; CHECK-NEXT:    v_add_i32_e32 v2, vcc, v8, v2
+; CHECK-NEXT:    v_add_i32_e32 v0, vcc, v0, v2
+; CHECK-NEXT:    v_add_i32_e32 v1, vcc, v5, v1
+; CHECK-NEXT:    v_addc_u32_e32 v0, vcc, v6, v0, vcc
+; CHECK-NEXT:    v_mul_lo_u32 v2, v4, v1
+; CHECK-NEXT:    v_mul_lo_u32 v5, v3, v0
+; CHECK-NEXT:    v_mul_hi_u32 v8, v3, v1
+; CHECK-NEXT:    v_mul_hi_u32 v1, v4, v1
 ; CHECK-NEXT:    s_mov_b32 s6, 0x12d8fb
-; CHECK-NEXT:    v_add_i32_e32 v2, vcc, v2, v3
-; CHECK-NEXT:    v_cndmask_b32_e64 v3, 0, 1, vcc
 ; CHECK-NEXT:    v_add_i32_e32 v2, vcc, v2, v5
+; CHECK-NEXT:    v_cndmask_b32_e64 v5, 0, 1, vcc
+; CHECK-NEXT:    v_add_i32_e32 v2, vcc, v2, v8
 ; CHECK-NEXT:    v_cndmask_b32_e64 v2, 0, 1, vcc
-; CHECK-NEXT:    v_mul_lo_u32 v5, v9, v1
-; CHECK-NEXT:    v_add_i32_e32 v2, vcc, v3, v2
-; CHECK-NEXT:    v_mul_hi_u32 v3, v4, v1
-; CHECK-NEXT:    v_add_i32_e32 v0, vcc, v5, v0
+; CHECK-NEXT:    v_mul_lo_u32 v8, v4, v0
+; CHECK-NEXT:    v_add_i32_e32 v2, vcc, v5, v2
+; CHECK-NEXT:    v_mul_hi_u32 v5, v3, v0
+; CHECK-NEXT:    v_add_i32_e32 v1, vcc, v8, v1
+; CHECK-NEXT:    v_cndmask_b32_e64 v8, 0, 1, vcc
+; CHECK-NEXT:    v_add_i32_e32 v1, vcc, v1, v5
 ; CHECK-NEXT:    v_cndmask_b32_e64 v5, 0, 1, vcc
-; CHECK-NEXT:    v_add_i32_e32 v0, vcc, v0, v3
-; CHECK-NEXT:    v_cndmask_b32_e64 v3, 0, 1, vcc
-; CHECK-NEXT:    v_add_i32_e32 v3, vcc, v5, v3
-; CHECK-NEXT:    v_add_i32_e32 v5, vcc, v0, v2
-; CHECK-NEXT:    v_mul_hi_u32 v6, v9, v1
-; CHECK-NEXT:    v_mad_u64_u32 v[0:1], s[4:5], s6, v5, 0
+; CHECK-NEXT:    v_add_i32_e32 v5, vcc, v8, v5
+; CHECK-NEXT:    v_add_i32_e32 v1, vcc, v1, v2
+; CHECK-NEXT:    v_mul_hi_u32 v8, v4, v0
+; CHECK-NEXT:    v_mad_u64_u32 v[0:1], s[4:5], s6, v1, 0
 ; CHECK-NEXT:    v_cndmask_b32_e64 v2, 0, 1, vcc
-; CHECK-NEXT:    v_add_i32_e32 v2, vcc, v3, v2
-; CHECK-NEXT:    v_add_i32_e32 v2, vcc, v6, v2
+; CHECK-NEXT:    v_add_i32_e32 v2, vcc, v5, v2
+; CHECK-NEXT:    v_add_i32_e32 v2, vcc, v8, v2
 ; CHECK-NEXT:    v_mad_u64_u32 v[1:2], s[4:5], s6, v2, v[1:2]
-; CHECK-NEXT:    v_sub_i32_e32 v0, vcc, v4, v0
-; CHECK-NEXT:    v_mad_u64_u32 v[1:2], s[4:5], 0, v5, v[1:2]
-; CHECK-NEXT:    v_mov_b32_e32 v3, 0x12d8fb
+; CHECK-NEXT:    v_sub_i32_e32 v0, vcc, v3, v0
+; CHECK-NEXT:    v_mov_b32_e32 v6, 0x12d8fb
+; CHECK-NEXT:    v_subb_u32_e64 v2, s[4:5], v4, v1, vcc
+; CHECK-NEXT:    v_sub_i32_e64 v1, s[4:5], v4, v1
 ; CHECK-NEXT:    s_bfe_i32 s6, -1, 0x10000
-; CHECK-NEXT:    v_subb_u32_e64 v2, s[4:5], v9, v1, vcc
-; CHECK-NEXT:    v_sub_i32_e64 v1, s[4:5], v9, v1
-; CHECK-NEXT:    v_cmp_ge_u32_e64 s[4:5], v0, v3
-; CHECK-NEXT:    v_cndmask_b32_e64 v4, 0, -1, s[4:5]
-; CHECK-NEXT:    v_mov_b32_e32 v5, s6
+; CHECK-NEXT:    v_cmp_ge_u32_e64 s[4:5], v0, v6
+; CHECK-NEXT:    v_cndmask_b32_e64 v3, 0, -1, s[4:5]
+; CHECK-NEXT:    v_mov_b32_e32 v4, s6
 ; CHECK-NEXT:    v_cmp_eq_u32_e64 s[4:5], 0, v2
 ; CHECK-NEXT:    v_subbrev_u32_e32 v1, vcc, 0, v1, vcc
-; CHECK-NEXT:    v_cndmask_b32_e64 v4, v5, v4, s[4:5]
-; CHECK-NEXT:    v_sub_i32_e32 v5, vcc, v0, v3
+; CHECK-NEXT:    v_cndmask_b32_e64 v3, v4, v3, s[4:5]
+; CHECK-NEXT:    v_sub_i32_e32 v4, vcc, v0, v6
 ; CHECK-NEXT:    v_subbrev_u32_e32 v1, vcc, 0, v1, vcc
 ; CHECK-NEXT:    s_bfe_i32 s4, -1, 0x10000
-; CHECK-NEXT:    v_cmp_ge_u32_e32 vcc, v5, v3
-; CHECK-NEXT:    v_cndmask_b32_e64 v6, 0, -1, vcc
+; CHECK-NEXT:    v_cmp_ge_u32_e32 vcc, v4, v6
+; CHECK-NEXT:    v_cndmask_b32_e64 v5, 0, -1, vcc
 ; CHECK-NEXT:    v_mov_b32_e32 v8, s4
 ; CHECK-NEXT:    v_cmp_eq_u32_e32 vcc, 0, v1
-; CHECK-NEXT:    v_cndmask_b32_e32 v6, v8, v6, vcc
-; CHECK-NEXT:    v_sub_i32_e32 v3, vcc, v5, v3
+; CHECK-NEXT:    v_cndmask_b32_e32 v5, v8, v5, vcc
+; CHECK-NEXT:    v_sub_i32_e32 v6, vcc, v4, v6
 ; CHECK-NEXT:    v_subbrev_u32_e32 v8, vcc, 0, v1, vcc
-; CHECK-NEXT:    v_cmp_ne_u32_e32 vcc, 0, v6
-; CHECK-NEXT:    v_cndmask_b32_e32 v3, v5, v3, vcc
+; CHECK-NEXT:    v_cmp_ne_u32_e32 vcc, 0, v5
+; CHECK-NEXT:    v_cndmask_b32_e32 v4, v4, v6, vcc
 ; CHECK-NEXT:    v_cndmask_b32_e32 v1, v1, v8, vcc
-; CHECK-NEXT:    v_cmp_ne_u32_e32 vcc, 0, v4
-; CHECK-NEXT:    v_cndmask_b32_e32 v0, v0, v3, vcc
+; CHECK-NEXT:    v_cmp_ne_u32_e32 vcc, 0, v3
+; CHECK-NEXT:    v_cndmask_b32_e32 v0, v0, v4, vcc
 ; CHECK-NEXT:    v_cndmask_b32_e32 v1, v2, v1, vcc
 ; CHECK-NEXT:    v_xor_b32_e32 v0, v0, v7
 ; CHECK-NEXT:    v_xor_b32_e32 v1, v1, v7
@@ -2071,68 +2066,67 @@
 ; CGP-NEXT:    v_add_i32_e32 v6, vcc, v9, v6
 ; CGP-NEXT:    v_add_i32_e32 v5, vcc, v5, v6
 ; CGP-NEXT:    v_add_i32_e32 v9, vcc, v7, v4
-; CGP-NEXT:    v_addc_u32_e32 v8, vcc, v8, v5, vcc
-; CGP-NEXT:    v_mad_u64_u32 v[5:6], s[4:5], s6, v9, 0
-; CGP-NEXT:    v_mov_b32_e32 v4, v6
-; CGP-NEXT:    v_mad_u64_u32 v[6:7], s[4:5], s6, v8, v[4:5]
-; CGP-NEXT:    v_ashrrev_i32_e32 v4, 31, v1
-; CGP-NEXT:    v_add_i32_e32 v0, vcc, v0, v4
-; CGP-NEXT:    v_mad_u64_u32 v[6:7], s[4:5], -1, v9, v[6:7]
-; CGP-NEXT:    v_addc_u32_e32 v1, vcc, v1, v4, vcc
-; CGP-NEXT:    v_xor_b32_e32 v10, v0, v4
-; CGP-NEXT:    v_mul_lo_u32 v0, v8, v5
-; CGP-NEXT:    v_mul_lo_u32 v7, v9, v6
-; CGP-NEXT:    v_xor_b32_e32 v11, v1, v4
-; CGP-NEXT:    v_mul_hi_u32 v1, v9, v5
-; CGP-NEXT:    v_mul_hi_u32 v5, v8, v5
-; CGP-NEXT:    v_add_i32_e32 v0, vcc, v0, v7
-; CGP-NEXT:    v_cndmask_b32_e64 v7, 0, 1, vcc
-; CGP-NEXT:    v_add_i32_e32 v0, vcc, v0, v1
-; CGP-NEXT:    v_cndmask_b32_e64 v0, 0, 1, vcc
-; CGP-NEXT:    v_mul_lo_u32 v1, v8, v6
-; CGP-NEXT:    v_add_i32_e32 v0, vcc, v7, v0
+; CGP-NEXT:    v_mad_u64_u32 v[6:7], s[4:5], s6, v9, 0
+; CGP-NEXT:    v_addc_u32_e32 v10, vcc, v8, v5, vcc
+; CGP-NEXT:    v_ashrrev_i32_e32 v5, 31, v1
+; CGP-NEXT:    v_mov_b32_e32 v4, v7
+; CGP-NEXT:    v_mad_u64_u32 v[7:8], s[4:5], s6, v10, v[4:5]
+; CGP-NEXT:    v_add_i32_e32 v4, vcc, v0, v5
+; CGP-NEXT:    v_addc_u32_e32 v11, vcc, v1, v5, vcc
+; CGP-NEXT:    v_mad_u64_u32 v[0:1], s[4:5], -1, v9, v[7:8]
+; CGP-NEXT:    v_xor_b32_e32 v8, v4, v5
+; CGP-NEXT:    v_mul_lo_u32 v1, v10, v6
+; CGP-NEXT:    v_mul_lo_u32 v4, v9, v0
 ; CGP-NEXT:    v_mul_hi_u32 v7, v9, v6
-; CGP-NEXT:    v_add_i32_e32 v1, vcc, v1, v5
-; CGP-NEXT:    v_cndmask_b32_e64 v5, 0, 1, vcc
+; CGP-NEXT:    v_mul_hi_u32 v6, v10, v6
+; CGP-NEXT:    v_xor_b32_e32 v11, v11, v5
+; CGP-NEXT:    v_add_i32_e32 v1, vcc, v1, v4
+; CGP-NEXT:    v_cndmask_b32_e64 v4, 0, 1, vcc
 ; CGP-NEXT:    v_add_i32_e32 v1, vcc, v1, v7
-; CGP-NEXT:    v_cndmask_b32_e64 v7, 0, 1, vcc
-; CGP-NEXT:    v_add_i32_e32 v5, vcc, v5, v7
-; CGP-NEXT:    v_mul_hi_u32 v6, v8, v6
-; CGP-NEXT:    v_add_i32_e32 v0, vcc, v1, v0
 ; CGP-NEXT:    v_cndmask_b32_e64 v1, 0, 1, vcc
-; CGP-NEXT:    v_add_i32_e32 v1, vcc, v5, v1
-; CGP-NEXT:    v_add_i32_e32 v1, vcc, v6, v1
-; CGP-NEXT:    v_add_i32_e32 v0, vcc, v9, v0
-; CGP-NEXT:    v_addc_u32_e32 v1, vcc, v8, v1, vcc
-; CGP-NEXT:    v_mul_lo_u32 v5, v11, v0
-; CGP-NEXT:    v_mul_lo_u32 v6, v10, v1
-; CGP-NEXT:    v_mul_hi_u32 v7, v10, v0
-; CGP-NEXT:    v_mul_hi_u32 v0, v11, v0
-; CGP-NEXT:    v_add_i32_e32 v5, vcc, v5, v6
+; CGP-NEXT:    v_mul_lo_u32 v7, v10, v0
+; CGP-NEXT:    v_add_i32_e32 v1, vcc, v4, v1
+; CGP-NEXT:    v_mul_hi_u32 v4, v9, v0
+; CGP-NEXT:    v_add_i32_e32 v6, vcc, v7, v6
+; CGP-NEXT:    v_cndmask_b32_e64 v7, 0, 1, vcc
+; CGP-NEXT:    v_add_i32_e32 v4, vcc, v6, v4
 ; CGP-NEXT:    v_cndmask_b32_e64 v6, 0, 1, vcc
-; CGP-NEXT:    v_add_i32_e32 v5, vcc, v5, v7
-; CGP-NEXT:    v_cndmask_b32_e64 v5, 0, 1, vcc
-; CGP-NEXT:    v_mul_lo_u32 v7, v11, v1
-; CGP-NEXT:    v_add_i32_e32 v5, vcc, v6, v5
-; CGP-NEXT:    v_mul_hi_u32 v6, v10, v1
-; CGP-NEXT:    v_add_i32_e32 v0, vcc, v7, v0
+; CGP-NEXT:    v_add_i32_e32 v6, vcc, v7, v6
+; CGP-NEXT:    v_mul_hi_u32 v0, v10, v0
+; CGP-NEXT:    v_add_i32_e32 v1, vcc, v4, v1
+; CGP-NEXT:    v_cndmask_b32_e64 v4, 0, 1, vcc
+; CGP-NEXT:    v_add_i32_e32 v4, vcc, v6, v4
+; CGP-NEXT:    v_add_i32_e32 v0, vcc, v0, v4
+; CGP-NEXT:    v_add_i32_e32 v1, vcc, v9, v1
+; CGP-NEXT:    v_addc_u32_e32 v0, vcc, v10, v0, vcc
+; CGP-NEXT:    v_mul_lo_u32 v6, v11, v1
+; CGP-NEXT:    v_mul_lo_u32 v7, v8, v0
+; CGP-NEXT:    v_mul_hi_u32 v9, v8, v1
+; CGP-NEXT:    v_mul_hi_u32 v1, v11, v1
+; CGP-NEXT:    v_mov_b32_e32 v4, 0x12d8fb
+; CGP-NEXT:    v_add_i32_e32 v6, vcc, v6, v7
 ; CGP-NEXT:    v_cndmask_b32_e64 v7, 0, 1, vcc
-; CGP-NEXT:    v_add_i32_e32 v0, vcc, v0, v6
+; CGP-NEXT:    v_add_i32_e32 v6, vcc, v6, v9
 ; CGP-NEXT:    v_cndmask_b32_e64 v6, 0, 1, vcc
+; CGP-NEXT:    v_mul_lo_u32 v9, v11, v0
 ; CGP-NEXT:    v_add_i32_e32 v6, vcc, v7, v6
-; CGP-NEXT:    v_add_i32_e32 v8, vcc, v0, v5
-; CGP-NEXT:    v_mul_hi_u32 v7, v11, v1
-; CGP-NEXT:    v_mad_u64_u32 v[0:1], s[4:5], s7, v8, 0
-; CGP-NEXT:    v_cndmask_b32_e64 v5, 0, 1, vcc
-; CGP-NEXT:    v_add_i32_e32 v5, vcc, v6, v5
-; CGP-NEXT:    v_add_i32_e32 v5, vcc, v7, v5
-; CGP-NEXT:    v_mad_u64_u32 v[6:7], s[4:5], s7, v5, v[1:2]
-; CGP-NEXT:    v_mov_b32_e32 v5, 0x12d8fb
-; CGP-NEXT:    v_mad_u64_u32 v[6:7], s[4:5], 0, v8, v[6:7]
-; CGP-NEXT:    v_sub_i32_e32 v8, vcc, v10, v0
+; CGP-NEXT:    v_mul_hi_u32 v7, v8, v0
+; CGP-NEXT:    v_add_i32_e32 v1, vcc, v9, v1
+; CGP-NEXT:    v_cndmask_b32_e64 v9, 0, 1, vcc
+; CGP-NEXT:    v_add_i32_e32 v1, vcc, v1, v7
+; CGP-NEXT:    v_cndmask_b32_e64 v7, 0, 1, vcc
+; CGP-NEXT:    v_add_i32_e32 v7, vcc, v9, v7
+; CGP-NEXT:    v_add_i32_e32 v1, vcc, v1, v6
+; CGP-NEXT:    v_mul_hi_u32 v9, v11, v0
+; CGP-NEXT:    v_mad_u64_u32 v[0:1], s[4:5], s7, v1, 0
+; CGP-NEXT:    v_cndmask_b32_e64 v6, 0, 1, vcc
+; CGP-NEXT:    v_add_i32_e32 v6, vcc, v7, v6
+; CGP-NEXT:    v_add_i32_e32 v6, vcc, v9, v6
+; CGP-NEXT:    v_mad_u64_u32 v[6:7], s[4:5], s7, v6, v[1:2]
+; CGP-NEXT:    v_sub_i32_e32 v8, vcc, v8, v0
 ; CGP-NEXT:    v_subb_u32_e64 v9, s[4:5], v11, v6, vcc
 ; CGP-NEXT:    v_sub_i32_e64 v0, s[4:5], v11, v6
-; CGP-NEXT:    v_cmp_ge_u32_e64 s[4:5], v8, v5
+; CGP-NEXT:    v_cmp_ge_u32_e64 s[4:5], v8, v4
 ; CGP-NEXT:    v_cndmask_b32_e64 v1, 0, -1, s[4:5]
 ; CGP-NEXT:    v_mov_b32_e32 v6, s8
 ; CGP-NEXT:    v_cmp_eq_u32_e64 s[4:5], 0, v9
@@ -2142,7 +2136,7 @@
 ; CGP-NEXT:    v_subbrev_u32_e32 v0, vcc, 0, v0, vcc
 ; CGP-NEXT:    v_mac_f32_e32 v1, 0x4f800000, v6
 ; CGP-NEXT:    v_rcp_iflag_f32_e32 v1, v1
-; CGP-NEXT:    v_sub_i32_e32 v11, vcc, v8, v5
+; CGP-NEXT:    v_sub_i32_e32 v11, vcc, v8, v4
 ; CGP-NEXT:    v_subbrev_u32_e32 v12, vcc, 0, v0, vcc
 ; CGP-NEXT:    v_mul_f32_e32 v0, 0x5f7ffffc, v1
 ; CGP-NEXT:    v_mul_f32_e32 v1, 0x2f800000, v0
@@ -2153,12 +2147,12 @@
 ; CGP-NEXT:    v_mov_b32_e32 v14, s4
 ; CGP-NEXT:    v_cvt_u32_f32_e32 v15, v6
 ; CGP-NEXT:    v_mad_u64_u32 v[0:1], s[4:5], s6, v13, 0
-; CGP-NEXT:    v_cmp_ge_u32_e32 vcc, v11, v5
+; CGP-NEXT:    v_cmp_ge_u32_e32 vcc, v11, v4
 ; CGP-NEXT:    v_cndmask_b32_e64 v7, 0, -1, vcc
 ; CGP-NEXT:    v_cmp_eq_u32_e32 vcc, 0, v12
 ; CGP-NEXT:    v_cndmask_b32_e32 v14, v14, v7, vcc
 ; CGP-NEXT:    v_mad_u64_u32 v[6:7], s[4:5], s6, v15, v[1:2]
-; CGP-NEXT:    v_sub_i32_e32 v1, vcc, v11, v5
+; CGP-NEXT:    v_sub_i32_e32 v1, vcc, v11, v4
 ; CGP-NEXT:    v_mad_u64_u32 v[6:7], s[4:5], -1, v13, v[6:7]
 ; CGP-NEXT:    v_subbrev_u32_e32 v16, vcc, 0, v12, vcc
 ; CGP-NEXT:    v_cmp_ne_u32_e32 vcc, 0, v14
@@ -2189,93 +2183,91 @@
 ; CGP-NEXT:    v_addc_u32_e32 v13, vcc, v15, v1, vcc
 ; CGP-NEXT:    v_mad_u64_u32 v[0:1], s[4:5], s6, v11, 0
 ; CGP-NEXT:    v_cmp_ne_u32_e32 vcc, 0, v10
-; CGP-NEXT:    v_cndmask_b32_e32 v8, v8, v7, vcc
+; CGP-NEXT:    v_cndmask_b32_e32 v6, v8, v7, vcc
+; CGP-NEXT:    v_cndmask_b32_e32 v8, v9, v12, vcc
+; CGP-NEXT:    v_xor_b32_e32 v9, v6, v5
 ; CGP-NEXT:    v_mad_u64_u32 v[6:7], s[4:5], s6, v13, v[1:2]
-; CGP-NEXT:    v_xor_b32_e32 v1, v8, v4
+; CGP-NEXT:    v_xor_b32_e32 v1, v8, v5
 ; CGP-NEXT:    v_ashrrev_i32_e32 v8, 31, v3
 ; CGP-NEXT:    v_mad_u64_u32 v[6:7], s[4:5], -1, v11, v[6:7]
-; CGP-NEXT:    v_cndmask_b32_e32 v9, v9, v12, vcc
 ; CGP-NEXT:    v_add_i32_e32 v2, vcc, v2, v8
 ; CGP-NEXT:    v_addc_u32_e32 v3, vcc, v3, v8, vcc
-; CGP-NEXT:    v_xor_b32_e32 v10, v2, v8
+; CGP-NEXT:    v_xor_b32_e32 v7, v2, v8
 ; CGP-NEXT:    v_mul_lo_u32 v2, v13, v0
-; CGP-NEXT:    v_mul_lo_u32 v7, v11, v6
+; CGP-NEXT:    v_mul_lo_u32 v10, v11, v6
 ; CGP-NEXT:    v_xor_b32_e32 v12, v3, v8
 ; CGP-NEXT:    v_mul_hi_u32 v3, v11, v0
 ; CGP-NEXT:    v_mul_hi_u32 v0, v13, v0
-; CGP-NEXT:    v_add_i32_e32 v2, vcc, v2, v7
-; CGP-NEXT:    v_cndmask_b32_e64 v7, 0, 1, vcc
+; CGP-NEXT:    v_add_i32_e32 v2, vcc, v2, v10
+; CGP-NEXT:    v_cndmask_b32_e64 v10, 0, 1, vcc
 ; CGP-NEXT:    v_add_i32_e32 v2, vcc, v2, v3
 ; CGP-NEXT:    v_cndmask_b32_e64 v2, 0, 1, vcc
 ; CGP-NEXT:    v_mul_lo_u32 v3, v13, v6
-; CGP-NEXT:    v_add_i32_e32 v2, vcc, v7, v2
-; CGP-NEXT:    v_mul_hi_u32 v7, v11, v6
+; CGP-NEXT:    v_add_i32_e32 v2, vcc, v10, v2
+; CGP-NEXT:    v_mul_hi_u32 v10, v11, v6
 ; CGP-NEXT:    v_add_i32_e32 v0, vcc, v3, v0
 ; CGP-NEXT:    v_cndmask_b32_e64 v3, 0, 1, vcc
-; CGP-NEXT:    v_add_i32_e32 v0, vcc, v0, v7
-; CGP-NEXT:    v_cndmask_b32_e64 v7, 0, 1, vcc
-; CGP-NEXT:    v_add_i32_e32 v3, vcc, v3, v7
+; CGP-NEXT:    v_add_i32_e32 v0, vcc, v0, v10
+; CGP-NEXT:    v_cndmask_b32_e64 v10, 0, 1, vcc
+; CGP-NEXT:    v_add_i32_e32 v3, vcc, v3, v10
 ; CGP-NEXT:    v_mul_hi_u32 v6, v13, v6
 ; CGP-NEXT:    v_add_i32_e32 v0, vcc, v0, v2
 ; CGP-NEXT:    v_cndmask_b32_e64 v2, 0, 1, vcc
 ; CGP-NEXT:    v_add_i32_e32 v2, vcc, v3, v2
 ; CGP-NEXT:    v_add_i32_e32 v2, vcc, v6, v2
-; CGP-NEXT:    v_add_i32_e32 v0, vcc, v11, v0
+; CGP-NEXT:    v_add_i32_e32 v3, vcc, v11, v0
 ; CGP-NEXT:    v_addc_u32_e32 v2, vcc, v13, v2, vcc
-; CGP-NEXT:    v_mul_lo_u32 v3, v12, v0
-; CGP-NEXT:    v_mul_lo_u32 v6, v10, v2
-; CGP-NEXT:    v_mul_hi_u32 v7, v10, v0
-; CGP-NEXT:    v_mul_hi_u32 v0, v12, v0
-; CGP-NEXT:    v_xor_b32_e32 v9, v9, v4
-; CGP-NEXT:    v_add_i32_e32 v3, vcc, v3, v6
-; CGP-NEXT:    v_cndmask_b32_e64 v6, 0, 1, vcc
-; CGP-NEXT:    v_add_i32_e32 v3, vcc, v3, v7
-; CGP-NEXT:    v_cndmask_b32_e64 v3, 0, 1, vcc
-; CGP-NEXT:    v_mul_lo_u32 v7, v12, v2
+; CGP-NEXT:    v_mul_lo_u32 v6, v12, v3
+; CGP-NEXT:    v_mul_lo_u32 v10, v7, v2
+; CGP-NEXT:    v_sub_i32_e32 v0, vcc, v9, v5
+; CGP-NEXT:    v_subb_u32_e32 v1, vcc, v1, v5, vcc
+; CGP-NEXT:    v_mul_hi_u32 v5, v7, v3
+; CGP-NEXT:    v_add_i32_e32 v6, vcc, v6, v10
+; CGP-NEXT:    v_cndmask_b32_e64 v9, 0, 1, vcc
+; CGP-NEXT:    v_add_i32_e32 v5, vcc, v6, v5
+; CGP-NEXT:    v_cndmask_b32_e64 v5, 0, 1, vcc
+; CGP-NEXT:    v_mul_lo_u32 v6, v12, v2
+; CGP-NEXT:    v_mul_hi_u32 v3, v12, v3
+; CGP-NEXT:    v_add_i32_e32 v5, vcc, v9, v5
+; CGP-NEXT:    v_mul_hi_u32 v9, v7, v2
 ; CGP-NEXT:    v_add_i32_e32 v3, vcc, v6, v3
-; CGP-NEXT:    v_mul_hi_u32 v6, v10, v2
-; CGP-NEXT:    v_add_i32_e32 v0, vcc, v7, v0
-; CGP-NEXT:    v_cndmask_b32_e64 v7, 0, 1, vcc
-; CGP-NEXT:    v_add_i32_e32 v0, vcc, v0, v6
 ; CGP-NEXT:    v_cndmask_b32_e64 v6, 0, 1, vcc
-; CGP-NEXT:    v_add_i32_e32 v6, vcc, v7, v6
-; CGP-NEXT:    v_add_i32_e32 v11, vcc, v0, v3
-; CGP-NEXT:    v_mul_hi_u32 v7, v12, v2
-; CGP-NEXT:    v_mad_u64_u32 v[2:3], s[4:5], s7, v11, 0
-; CGP-NEXT:    v_cndmask_b32_e64 v0, 0, 1, vcc
-; CGP-NEXT:    v_add_i32_e32 v0, vcc, v6, v0
-; CGP-NEXT:    v_add_i32_e32 v6, vcc, v7, v0
-; CGP-NEXT:    v_mov_b32_e32 v0, v3
-; CGP-NEXT:    v_mad_u64_u32 v[6:7], s[4:5], s7, v6, v[0:1]
-; CGP-NEXT:    v_sub_i32_e32 v0, vcc, v1, v4
-; CGP-NEXT:    v_subb_u32_e32 v1, vcc, v9, v4, vcc
-; CGP-NEXT:    v_mad_u64_u32 v[3:4], s[4:5], 0, v11, v[6:7]
-; CGP-NEXT:    v_sub_i32_e32 v2, vcc, v10, v2
-; CGP-NEXT:    v_subb_u32_e64 v4, s[4:5], v12, v3, vcc
-; CGP-NEXT:    v_sub_i32_e64 v3, s[4:5], v12, v3
+; CGP-NEXT:    v_add_i32_e32 v3, vcc, v3, v9
+; CGP-NEXT:    v_cndmask_b32_e64 v9, 0, 1, vcc
+; CGP-NEXT:    v_add_i32_e32 v6, vcc, v6, v9
+; CGP-NEXT:    v_add_i32_e32 v3, vcc, v3, v5
+; CGP-NEXT:    v_mul_hi_u32 v9, v12, v2
+; CGP-NEXT:    v_mad_u64_u32 v[2:3], s[4:5], s7, v3, 0
+; CGP-NEXT:    v_cndmask_b32_e64 v5, 0, 1, vcc
+; CGP-NEXT:    v_add_i32_e32 v5, vcc, v6, v5
+; CGP-NEXT:    v_add_i32_e32 v5, vcc, v9, v5
+; CGP-NEXT:    v_mad_u64_u32 v[5:6], s[4:5], s7, v5, v[3:4]
+; CGP-NEXT:    v_sub_i32_e32 v2, vcc, v7, v2
+; CGP-NEXT:    v_subb_u32_e64 v3, s[4:5], v12, v5, vcc
+; CGP-NEXT:    v_sub_i32_e64 v5, s[4:5], v12, v5
 ; CGP-NEXT:    s_bfe_i32 s6, -1, 0x10000
-; CGP-NEXT:    v_cmp_ge_u32_e64 s[4:5], v2, v5
+; CGP-NEXT:    v_cmp_ge_u32_e64 s[4:5], v2, v4
 ; CGP-NEXT:    v_cndmask_b32_e64 v6, 0, -1, s[4:5]
 ; CGP-NEXT:    v_mov_b32_e32 v7, s6
-; CGP-NEXT:    v_cmp_eq_u32_e64 s[4:5], 0, v4
-; CGP-NEXT:    v_subbrev_u32_e32 v3, vcc, 0, v3, vcc
+; CGP-NEXT:    v_cmp_eq_u32_e64 s[4:5], 0, v3
+; CGP-NEXT:    v_subbrev_u32_e32 v5, vcc, 0, v5, vcc
 ; CGP-NEXT:    v_cndmask_b32_e64 v6, v7, v6, s[4:5]
-; CGP-NEXT:    v_sub_i32_e32 v7, vcc, v2, v5
-; CGP-NEXT:    v_subbrev_u32_e32 v3, vcc, 0, v3, vcc
+; CGP-NEXT:    v_sub_i32_e32 v7, vcc, v2, v4
+; CGP-NEXT:    v_subbrev_u32_e32 v5, vcc, 0, v5, vcc
 ; CGP-NEXT:    s_bfe_i32 s4, -1, 0x10000
-; CGP-NEXT:    v_cmp_ge_u32_e32 vcc, v7, v5
+; CGP-NEXT:    v_cmp_ge_u32_e32 vcc, v7, v4
 ; CGP-NEXT:    v_cndmask_b32_e64 v9, 0, -1, vcc
 ; CGP-NEXT:    v_mov_b32_e32 v10, s4
-; CGP-NEXT:    v_cmp_eq_u32_e32 vcc, 0, v3
+; CGP-NEXT:    v_cmp_eq_u32_e32 vcc, 0, v5
 ; CGP-NEXT:    v_cndmask_b32_e32 v9, v10, v9, vcc
-; CGP-NEXT:    v_sub_i32_e32 v5, vcc, v7, v5
-; CGP-NEXT:    v_subbrev_u32_e32 v10, vcc, 0, v3, vcc
+; CGP-NEXT:    v_sub_i32_e32 v4, vcc, v7, v4
+; CGP-NEXT:    v_subbrev_u32_e32 v10, vcc, 0, v5, vcc
 ; CGP-NEXT:    v_cmp_ne_u32_e32 vcc, 0, v9
-; CGP-NEXT:    v_cndmask_b32_e32 v5, v7, v5, vcc
-; CGP-NEXT:    v_cndmask_b32_e32 v3, v3, v10, vcc
+; CGP-NEXT:    v_cndmask_b32_e32 v4, v7, v4, vcc
+; CGP-NEXT:    v_cndmask_b32_e32 v5, v5, v10, vcc
 ; CGP-NEXT:    v_cmp_ne_u32_e32 vcc, 0, v6
-; CGP-NEXT:    v_cndmask_b32_e32 v2, v2, v5, vcc
-; CGP-NEXT:    v_cndmask_b32_e32 v3, v4, v3, vcc
+; CGP-NEXT:    v_cndmask_b32_e32 v2, v2, v4, vcc
+; CGP-NEXT:    v_cndmask_b32_e32 v3, v3, v5, vcc
 ; CGP-NEXT:    v_xor_b32_e32 v2, v2, v8
 ; CGP-NEXT:    v_xor_b32_e32 v3, v3, v8
 ; CGP-NEXT:    v_sub_i32_e32 v2, vcc, v2, v8
diff --git a/llvm/unittests/CodeGen/GlobalISel/LegalizerTest.cpp b/llvm/unittests/CodeGen/GlobalISel/LegalizerTest.cpp
--- a/llvm/unittests/CodeGen/GlobalISel/LegalizerTest.cpp
+++ b/llvm/unittests/CodeGen/GlobalISel/LegalizerTest.cpp
@@ -8,6 +8,7 @@
 
 #include "llvm/CodeGen/GlobalISel/Legalizer.h"
 #include "GISelMITest.h"
+#include "llvm/CodeGen/GlobalISel/GISelKnownBits.h"
 #include "llvm/CodeGen/GlobalISel/LostDebugLocObserver.h"
 
 #define DEBUG_TYPE "legalizer-test"
@@ -65,9 +66,10 @@
 
   ALegalizerInfo LI(MF->getSubtarget());
   LostDebugLocObserver LocObserver(DEBUG_TYPE);
+  GISelKnownBits KB(*MF);
 
   Legalizer::MFResult Result = Legalizer::legalizeMachineFunction(
-      *MF, LI, {&LocObserver}, LocObserver, B);
+      *MF, LI, {&LocObserver}, LocObserver, B, &KB);
 
   EXPECT_TRUE(isNullMIPtr(Result.FailedOn));
   EXPECT_TRUE(Result.Changed);
@@ -102,6 +104,7 @@
 
   ALegalizerInfo LI(MF->getSubtarget());
   LostDebugLocObserver LocObserver(DEBUG_TYPE);
+  GISelKnownBits KB(*MF);
 
   // The events here unfold as follows:
   // 1. First, the function is scanned pre-forming the worklist of artifacts:
@@ -158,7 +161,7 @@
   //  the process follows def-use chains, making them shorter at each step, thus
   //  combining everything that can be combined in O(n) time.
   Legalizer::MFResult Result = Legalizer::legalizeMachineFunction(
-      *MF, LI, {&LocObserver}, LocObserver, B);
+      *MF, LI, {&LocObserver}, LocObserver, B, &KB);
 
   EXPECT_TRUE(isNullMIPtr(Result.FailedOn));
   EXPECT_TRUE(Result.Changed);
@@ -195,9 +198,10 @@
 
   ALegalizerInfo LI(MF->getSubtarget());
   LostDebugLocObserver LocObserver(DEBUG_TYPE);
+  GISelKnownBits KB(*MF);
 
   Legalizer::MFResult Result = Legalizer::legalizeMachineFunction(
-      *MF, LI, {&LocObserver}, LocObserver, B);
+      *MF, LI, {&LocObserver}, LocObserver, B, &KB);
 
   EXPECT_TRUE(isNullMIPtr(Result.FailedOn));
   EXPECT_TRUE(Result.Changed);