diff --git a/llvm/lib/CodeGen/GlobalISel/LegalizerHelper.cpp b/llvm/lib/CodeGen/GlobalISel/LegalizerHelper.cpp --- a/llvm/lib/CodeGen/GlobalISel/LegalizerHelper.cpp +++ b/llvm/lib/CodeGen/GlobalISel/LegalizerHelper.cpp @@ -108,8 +108,8 @@ LegalizerHelper::LegalizerHelper(MachineFunction &MF, const LegalizerInfo &LI, GISelChangeObserver &Observer, MachineIRBuilder &B) - : MIRBuilder(B), Observer(Observer), MRI(MF.getRegInfo()), LI(LI), - TLI(*MF.getSubtarget().getTargetLowering()) { } + : MIRBuilder(B), Observer(Observer), MRI(MF.getRegInfo()), LI(LI), + TLI(*MF.getSubtarget().getTargetLowering()), KB(nullptr) {} LegalizerHelper::LegalizerHelper(MachineFunction &MF, const LegalizerInfo &LI, GISelChangeObserver &Observer, diff --git a/llvm/lib/Target/AMDGPU/AMDGPULegalizerInfo.cpp b/llvm/lib/Target/AMDGPU/AMDGPULegalizerInfo.cpp --- a/llvm/lib/Target/AMDGPU/AMDGPULegalizerInfo.cpp +++ b/llvm/lib/Target/AMDGPU/AMDGPULegalizerInfo.cpp @@ -2898,6 +2898,7 @@ using Carry = SmallVector; MachineIRBuilder &B = Helper.MIRBuilder; + GISelKnownBits &KB = *Helper.getKnownBits(); const LLT S1 = LLT::scalar(1); const LLT S32 = LLT::scalar(32); @@ -2917,6 +2918,12 @@ return Zero64; }; + SmallVector Src0KB, Src1KB; + for (unsigned i = 0; i < Src0.size(); ++i) { + Src0KB.push_back(KB.getKnownBits(Src0[i])); + Src1KB.push_back(KB.getKnownBits(Src1[i])); + } + // Merge the given carries into the 32-bit LocalAccum, which is modified // in-place. // @@ -2979,9 +2986,15 @@ if (LocalAccum.size() == 1 && (!UsePartialMad64_32 || !CarryIn.empty())) { do { + // Skip multiplication if one of the operands is 0 unsigned j1 = DstIndex - j0; + bool AtLeastOneArgIsZero = Src0KB[j0].isZero() || Src1KB[j1].isZero(); + if (AtLeastOneArgIsZero) { + ++j0; + continue; + } auto Mul = B.buildMul(S32, Src0[j0], Src1[j1]); - if (!LocalAccum[0]) { + if (!LocalAccum[0] || KB.getKnownBits(LocalAccum[0]).isZero()) { LocalAccum[0] = Mul.getReg(0); } else { if (CarryIn.empty()) { @@ -3021,12 +3034,18 @@ do { unsigned j1 = DstIndex - j0; + bool AtLeastOneArgIsZero = Src0KB[j0].isZero() || Src1KB[j1].isZero(); + if (AtLeastOneArgIsZero) { + ++j0; + continue; + } auto Mad = B.buildInstr(AMDGPU::G_AMDGPU_MAD_U64_U32, {S64, S1}, {Src0[j0], Src1[j1], Tmp}); Tmp = Mad.getReg(0); if (!HaveSmallAccum) CarryOut.push_back(Mad.getReg(1)); HaveSmallAccum = false; + ++j0; } while (j0 <= DstIndex); @@ -3153,6 +3172,16 @@ // in an even-aligned VGPR. const bool SeparateOddAlignedProducts = ST.hasFullRate64Ops(); + const bool AtLeastOneSrcIsZero = + Helper.getKnownBits()->getKnownBits(Src0).isZero() || + Helper.getKnownBits()->getKnownBits(Src1).isZero(); + + if (AtLeastOneSrcIsZero) { + B.buildConstant(DstReg, 0); + MI.eraseFromParent(); + return true; + } + LLT S32 = LLT::scalar(32); SmallVector Src0Parts, Src1Parts; for (unsigned i = 0; i < NumParts; ++i) { @@ -3167,6 +3196,7 @@ SeparateOddAlignedProducts); B.buildMerge(DstReg, AccumRegs); + MI.eraseFromParent(); return true; diff --git a/llvm/test/CodeGen/AMDGPU/GlobalISel/mul-known-bits.i64.ll b/llvm/test/CodeGen/AMDGPU/GlobalISel/mul-known-bits.i64.ll --- a/llvm/test/CodeGen/AMDGPU/GlobalISel/mul-known-bits.i64.ll +++ b/llvm/test/CodeGen/AMDGPU/GlobalISel/mul-known-bits.i64.ll @@ -1,261 +1,460 @@ ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py -; RUN: llc -march=amdgcn -mcpu=gfx1010 -global-isel=1 -verify-machineinstrs < %s | FileCheck -allow-deprecated-dag-overlap -check-prefixes=FUNC %s +; RUN: llc -march=amdgcn -mcpu=gfx1010 -global-isel=1 -verify-machineinstrs < %s | FileCheck -allow-deprecated-dag-overlap -check-prefixes=GFX10 %s +; RUN: llc -march=amdgcn -mcpu=gfx1100 -global-isel=1 -verify-machineinstrs < %s | FileCheck -allow-deprecated-dag-overlap -check-prefixes=GFX11 %s declare i32 @llvm.amdgcn.workitem.id.x() ; A 64-bit multiplication where no arguments were zero extended. -define amdgpu_kernel void @v_mul_i64_zext_00(i64 addrspace(1)* %out, i64 addrspace(1)* %aptr, i64 addrspace(1)* %bptr) nounwind { -; FUNC-LABEL: v_mul_i64_zext_00: -; FUNC: ; %bb.0: -; FUNC-NEXT: s_load_dwordx4 s[0:3], s[0:1], 0x2c -; FUNC-NEXT: v_lshlrev_b32_e32 v6, 3, v0 -; FUNC-NEXT: s_waitcnt lgkmcnt(0) -; FUNC-NEXT: s_clause 0x1 -; FUNC-NEXT: global_load_dwordx2 v[0:1], v6, s[0:1] -; FUNC-NEXT: global_load_dwordx2 v[2:3], v6, s[2:3] -; FUNC-NEXT: s_waitcnt vmcnt(0) -; FUNC-NEXT: v_mad_u64_u32 v[4:5], s0, v0, v2, 0 -; FUNC-NEXT: v_mul_lo_u32 v0, v0, v3 -; FUNC-NEXT: v_mul_lo_u32 v1, v1, v2 -; FUNC-NEXT: v_add3_u32 v5, v5, v0, v1 -; FUNC-NEXT: global_store_dwordx2 v6, v[4:5], s[2:3] -; FUNC-NEXT: s_endpgm +define amdgpu_kernel void @v_mul_i64_no_zext(ptr addrspace(1) %out, ptr addrspace(1) %aptr, ptr addrspace(1) %bptr) nounwind { +; GFX10-LABEL: v_mul_i64_no_zext: +; GFX10: ; %bb.0: +; GFX10-NEXT: s_load_dwordx4 s[0:3], s[0:1], 0x2c +; GFX10-NEXT: v_lshlrev_b32_e32 v6, 3, v0 +; GFX10-NEXT: s_waitcnt lgkmcnt(0) +; GFX10-NEXT: s_clause 0x1 +; GFX10-NEXT: global_load_dwordx2 v[0:1], v6, s[0:1] +; GFX10-NEXT: global_load_dwordx2 v[2:3], v6, s[2:3] +; GFX10-NEXT: s_waitcnt vmcnt(0) +; GFX10-NEXT: v_mad_u64_u32 v[4:5], s0, v0, v2, 0 +; GFX10-NEXT: v_mul_lo_u32 v0, v0, v3 +; GFX10-NEXT: v_mul_lo_u32 v1, v1, v2 +; GFX10-NEXT: v_add3_u32 v5, v5, v0, v1 +; GFX10-NEXT: global_store_dwordx2 v6, v[4:5], s[2:3] +; GFX10-NEXT: s_endpgm +; +; GFX11-LABEL: v_mul_i64_no_zext: +; GFX11: ; %bb.0: +; GFX11-NEXT: s_load_b128 s[0:3], s[0:1], 0x2c +; GFX11-NEXT: v_lshlrev_b32_e32 v6, 3, v0 +; GFX11-NEXT: s_waitcnt lgkmcnt(0) +; GFX11-NEXT: s_clause 0x1 +; GFX11-NEXT: global_load_b64 v[0:1], v6, s[0:1] +; GFX11-NEXT: global_load_b64 v[2:3], v6, s[2:3] +; GFX11-NEXT: s_waitcnt vmcnt(0) +; GFX11-NEXT: v_mad_u64_u32 v[4:5], null, v0, v2, 0 +; GFX11-NEXT: v_mul_lo_u32 v0, v0, v3 +; GFX11-NEXT: v_mul_lo_u32 v1, v1, v2 +; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1) +; GFX11-NEXT: v_add3_u32 v5, v5, v0, v1 +; GFX11-NEXT: global_store_b64 v6, v[4:5], s[2:3] +; GFX11-NEXT: s_sendmsg sendmsg(MSG_DEALLOC_VGPRS) +; GFX11-NEXT: s_endpgm %tid = call i32 @llvm.amdgcn.workitem.id.x() - %gep.a = getelementptr inbounds i64, i64 addrspace(1)* %aptr, i32 %tid - %gep.b = getelementptr inbounds i64, i64 addrspace(1)* %bptr, i32 %tid - %gep.out = getelementptr inbounds i64, i64 addrspace(1)* %bptr, i32 %tid - %a = load i64, i64 addrspace(1)* %gep.a - %b = load i64, i64 addrspace(1)* %gep.b + %gep.a = getelementptr inbounds i64, ptr addrspace(1) %aptr, i32 %tid + %gep.b = getelementptr inbounds i64, ptr addrspace(1) %bptr, i32 %tid + %gep.out = getelementptr inbounds i64, ptr addrspace(1) %bptr, i32 %tid + %a = load i64, ptr addrspace(1) %gep.a + %b = load i64, ptr addrspace(1) %gep.b %mul = mul i64 %a, %b - store i64 %mul, i64 addrspace(1)* %gep.out + store i64 %mul, ptr addrspace(1) %gep.out ret void } ; a 64 bit multiplication where the second argument was zero extended. -define amdgpu_kernel void @v_mul_i64_zext_01(i64 addrspace(1)* %out, i64 addrspace(1)* %aptr, i32 addrspace(1)* %bptr) { -; FUNC-LABEL: v_mul_i64_zext_01: -; FUNC: ; %bb.0: -; FUNC-NEXT: s_clause 0x1 -; FUNC-NEXT: s_load_dwordx4 s[4:7], s[0:1], 0x24 -; FUNC-NEXT: s_load_dwordx2 s[2:3], s[0:1], 0x34 -; FUNC-NEXT: v_lshlrev_b32_e32 v2, 3, v0 -; FUNC-NEXT: v_lshlrev_b32_e32 v3, 2, v0 -; FUNC-NEXT: s_waitcnt lgkmcnt(0) -; FUNC-NEXT: global_load_dwordx2 v[0:1], v2, s[6:7] -; FUNC-NEXT: global_load_dword v4, v3, s[2:3] -; FUNC-NEXT: s_waitcnt vmcnt(0) -; FUNC-NEXT: v_mad_u64_u32 v[2:3], s0, v0, v4, 0 -; FUNC-NEXT: v_mul_lo_u32 v0, v1, v4 -; FUNC-NEXT: v_add_nc_u32_e32 v3, v3, v0 -; FUNC-NEXT: v_mov_b32_e32 v0, 0 -; FUNC-NEXT: global_store_dwordx2 v0, v[2:3], s[4:5] -; FUNC-NEXT: s_endpgm +define amdgpu_kernel void @v_mul_i64_zext_src1(ptr addrspace(1) %out, ptr addrspace(1) %aptr, ptr addrspace(1) %bptr) { +; GFX10-LABEL: v_mul_i64_zext_src1: +; GFX10: ; %bb.0: +; GFX10-NEXT: s_clause 0x1 +; GFX10-NEXT: s_load_dwordx4 s[4:7], s[0:1], 0x24 +; GFX10-NEXT: s_load_dwordx2 s[2:3], s[0:1], 0x34 +; GFX10-NEXT: v_lshlrev_b32_e32 v2, 3, v0 +; GFX10-NEXT: v_lshlrev_b32_e32 v3, 2, v0 +; GFX10-NEXT: s_waitcnt lgkmcnt(0) +; GFX10-NEXT: global_load_dwordx2 v[0:1], v2, s[6:7] +; GFX10-NEXT: global_load_dword v4, v3, s[2:3] +; GFX10-NEXT: s_waitcnt vmcnt(0) +; GFX10-NEXT: v_mad_u64_u32 v[2:3], s0, v0, v4, 0 +; GFX10-NEXT: v_mul_lo_u32 v0, v1, v4 +; GFX10-NEXT: v_add_nc_u32_e32 v3, v3, v0 +; GFX10-NEXT: v_mov_b32_e32 v0, 0 +; GFX10-NEXT: global_store_dwordx2 v0, v[2:3], s[4:5] +; GFX10-NEXT: s_endpgm +; +; GFX11-LABEL: v_mul_i64_zext_src1: +; GFX11: ; %bb.0: +; GFX11-NEXT: s_clause 0x1 +; GFX11-NEXT: s_load_b128 s[4:7], s[0:1], 0x24 +; GFX11-NEXT: s_load_b64 s[0:1], s[0:1], 0x34 +; GFX11-NEXT: v_lshlrev_b32_e32 v1, 3, v0 +; GFX11-NEXT: v_lshlrev_b32_e32 v2, 2, v0 +; GFX11-NEXT: s_waitcnt lgkmcnt(0) +; GFX11-NEXT: global_load_b64 v[0:1], v1, s[6:7] +; GFX11-NEXT: global_load_b32 v4, v2, s[0:1] +; GFX11-NEXT: s_waitcnt vmcnt(0) +; GFX11-NEXT: v_mad_u64_u32 v[2:3], null, v0, v4, 0 +; GFX11-NEXT: v_mul_lo_u32 v0, v1, v4 +; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1) +; GFX11-NEXT: v_dual_mov_b32 v0, 0 :: v_dual_add_nc_u32 v3, v3, v0 +; GFX11-NEXT: global_store_b64 v0, v[2:3], s[4:5] +; GFX11-NEXT: s_sendmsg sendmsg(MSG_DEALLOC_VGPRS) +; GFX11-NEXT: s_endpgm %tid = call i32 @llvm.amdgcn.workitem.id.x() - %gep.a = getelementptr inbounds i64, i64 addrspace(1)* %aptr, i32 %tid - %gep.b = getelementptr inbounds i32, i32 addrspace(1)* %bptr, i32 %tid - %a = load i64, i64 addrspace(1)* %gep.a - %b = load i32, i32 addrspace(1)* %gep.b + %gep.a = getelementptr inbounds i64, ptr addrspace(1) %aptr, i32 %tid + %gep.b = getelementptr inbounds i32, ptr addrspace(1) %bptr, i32 %tid + %a = load i64, ptr addrspace(1) %gep.a + %b = load i32, ptr addrspace(1) %gep.b %b_ext = zext i32 %b to i64 %mul = mul i64 %a, %b_ext - store i64 %mul, i64 addrspace(1)* %out + store i64 %mul, ptr addrspace(1) %out ret void } ; 64 bit multiplication where the first argument was zero extended. -define amdgpu_kernel void @v_mul_i64_zext_10(i64 addrspace(1)* %out, i32 addrspace(1)* %aptr, i64 addrspace(1)* %bptr) { -; FUNC-LABEL: v_mul_i64_zext_10: -; FUNC: ; %bb.0: -; FUNC-NEXT: s_clause 0x1 -; FUNC-NEXT: s_load_dwordx4 s[4:7], s[0:1], 0x24 -; FUNC-NEXT: s_load_dwordx2 s[2:3], s[0:1], 0x34 -; FUNC-NEXT: v_lshlrev_b32_e32 v2, 2, v0 -; FUNC-NEXT: v_lshlrev_b32_e32 v3, 3, v0 -; FUNC-NEXT: s_waitcnt lgkmcnt(0) -; FUNC-NEXT: global_load_dword v4, v2, s[6:7] -; FUNC-NEXT: global_load_dwordx2 v[0:1], v3, s[2:3] -; FUNC-NEXT: s_waitcnt vmcnt(0) -; FUNC-NEXT: v_mad_u64_u32 v[2:3], s0, v4, v0, 0 -; FUNC-NEXT: v_mul_lo_u32 v1, v4, v1 -; FUNC-NEXT: v_mul_lo_u32 v0, 0, v0 -; FUNC-NEXT: v_add3_u32 v3, v3, v1, v0 -; FUNC-NEXT: v_mov_b32_e32 v0, 0 -; FUNC-NEXT: global_store_dwordx2 v0, v[2:3], s[4:5] -; FUNC-NEXT: s_endpgm +define amdgpu_kernel void @v_mul_i64_zext_src0(ptr addrspace(1) %out, ptr addrspace(1) %aptr, ptr addrspace(1) %bptr) { +; GFX10-LABEL: v_mul_i64_zext_src0: +; GFX10: ; %bb.0: +; GFX10-NEXT: s_clause 0x1 +; GFX10-NEXT: s_load_dwordx4 s[4:7], s[0:1], 0x24 +; GFX10-NEXT: s_load_dwordx2 s[2:3], s[0:1], 0x34 +; GFX10-NEXT: v_lshlrev_b32_e32 v2, 2, v0 +; GFX10-NEXT: v_lshlrev_b32_e32 v3, 3, v0 +; GFX10-NEXT: s_waitcnt lgkmcnt(0) +; GFX10-NEXT: global_load_dword v4, v2, s[6:7] +; GFX10-NEXT: global_load_dwordx2 v[0:1], v3, s[2:3] +; GFX10-NEXT: s_waitcnt vmcnt(0) +; GFX10-NEXT: v_mad_u64_u32 v[2:3], s0, v4, v0, 0 +; GFX10-NEXT: v_mul_lo_u32 v0, v4, v1 +; GFX10-NEXT: v_add_nc_u32_e32 v3, v3, v0 +; GFX10-NEXT: v_mov_b32_e32 v0, 0 +; GFX10-NEXT: global_store_dwordx2 v0, v[2:3], s[4:5] +; GFX10-NEXT: s_endpgm +; +; GFX11-LABEL: v_mul_i64_zext_src0: +; GFX11: ; %bb.0: +; GFX11-NEXT: s_clause 0x1 +; GFX11-NEXT: s_load_b128 s[4:7], s[0:1], 0x24 +; GFX11-NEXT: s_load_b64 s[0:1], s[0:1], 0x34 +; GFX11-NEXT: v_lshlrev_b32_e32 v1, 2, v0 +; GFX11-NEXT: v_lshlrev_b32_e32 v0, 3, v0 +; GFX11-NEXT: s_waitcnt lgkmcnt(0) +; GFX11-NEXT: global_load_b32 v4, v1, s[6:7] +; GFX11-NEXT: global_load_b64 v[0:1], v0, s[0:1] +; GFX11-NEXT: s_waitcnt vmcnt(0) +; GFX11-NEXT: v_mad_u64_u32 v[2:3], null, v4, v0, 0 +; GFX11-NEXT: v_mul_lo_u32 v0, v4, v1 +; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1) +; GFX11-NEXT: v_dual_mov_b32 v0, 0 :: v_dual_add_nc_u32 v3, v3, v0 +; GFX11-NEXT: global_store_b64 v0, v[2:3], s[4:5] +; GFX11-NEXT: s_sendmsg sendmsg(MSG_DEALLOC_VGPRS) +; GFX11-NEXT: s_endpgm %tid = call i32 @llvm.amdgcn.workitem.id.x() - %gep.a = getelementptr inbounds i32, i32 addrspace(1)* %aptr, i32 %tid - %gep.b = getelementptr inbounds i64, i64 addrspace(1)* %bptr, i32 %tid - %a = load i32, i32 addrspace(1)* %gep.a - %b = load i64, i64 addrspace(1)* %gep.b + %gep.a = getelementptr inbounds i32, ptr addrspace(1) %aptr, i32 %tid + %gep.b = getelementptr inbounds i64, ptr addrspace(1) %bptr, i32 %tid + %a = load i32, ptr addrspace(1) %gep.a + %b = load i64, ptr addrspace(1) %gep.b %a_ext = zext i32 %a to i64 %mul = mul i64 %a_ext, %b - store i64 %mul, i64 addrspace(1)* %out + store i64 %mul, ptr addrspace(1) %out ret void } ; 64-bit multiplication where both arguments were zero extended. -define amdgpu_kernel void @v_mul_i64_zext_11(i64 addrspace(1)* %out, i32 addrspace(1)* %aptr, i32 addrspace(1)* %bptr) { -; FUNC-LABEL: v_mul_i64_zext_11: -; FUNC: ; %bb.0: -; FUNC-NEXT: s_clause 0x1 -; FUNC-NEXT: s_load_dwordx4 s[4:7], s[0:1], 0x24 -; FUNC-NEXT: s_load_dwordx2 s[2:3], s[0:1], 0x34 -; FUNC-NEXT: v_lshlrev_b32_e32 v0, 2, v0 -; FUNC-NEXT: s_waitcnt lgkmcnt(0) -; FUNC-NEXT: s_clause 0x1 -; FUNC-NEXT: global_load_dword v1, v0, s[6:7] -; FUNC-NEXT: global_load_dword v2, v0, s[2:3] -; FUNC-NEXT: s_waitcnt vmcnt(0) -; FUNC-NEXT: v_mad_u64_u32 v[0:1], s0, v1, v2, 0 -; FUNC-NEXT: v_mul_lo_u32 v2, 0, v2 -; FUNC-NEXT: v_add_nc_u32_e32 v1, v1, v2 -; FUNC-NEXT: v_mov_b32_e32 v2, 0 -; FUNC-NEXT: global_store_dwordx2 v2, v[0:1], s[4:5] -; FUNC-NEXT: s_endpgm +define amdgpu_kernel void @v_mul_i64_zext_src0_src1(ptr addrspace(1) %out, ptr addrspace(1) %aptr, ptr addrspace(1) %bptr) { +; GFX10-LABEL: v_mul_i64_zext_src0_src1: +; GFX10: ; %bb.0: +; GFX10-NEXT: s_clause 0x1 +; GFX10-NEXT: s_load_dwordx4 s[4:7], s[0:1], 0x24 +; GFX10-NEXT: s_load_dwordx2 s[2:3], s[0:1], 0x34 +; GFX10-NEXT: v_lshlrev_b32_e32 v0, 2, v0 +; GFX10-NEXT: s_waitcnt lgkmcnt(0) +; GFX10-NEXT: s_clause 0x1 +; GFX10-NEXT: global_load_dword v1, v0, s[6:7] +; GFX10-NEXT: global_load_dword v2, v0, s[2:3] +; GFX10-NEXT: s_waitcnt vmcnt(0) +; GFX10-NEXT: v_mad_u64_u32 v[0:1], s0, v1, v2, 0 +; GFX10-NEXT: v_mov_b32_e32 v2, 0 +; GFX10-NEXT: global_store_dwordx2 v2, v[0:1], s[4:5] +; GFX10-NEXT: s_endpgm +; +; GFX11-LABEL: v_mul_i64_zext_src0_src1: +; GFX11: ; %bb.0: +; GFX11-NEXT: s_clause 0x1 +; GFX11-NEXT: s_load_b128 s[4:7], s[0:1], 0x24 +; GFX11-NEXT: s_load_b64 s[0:1], s[0:1], 0x34 +; GFX11-NEXT: v_lshlrev_b32_e32 v0, 2, v0 +; GFX11-NEXT: v_mov_b32_e32 v2, 0 +; GFX11-NEXT: s_waitcnt lgkmcnt(0) +; GFX11-NEXT: s_clause 0x1 +; GFX11-NEXT: global_load_b32 v1, v0, s[6:7] +; GFX11-NEXT: global_load_b32 v0, v0, s[0:1] +; GFX11-NEXT: s_waitcnt vmcnt(0) +; GFX11-NEXT: v_mad_u64_u32 v[0:1], null, v1, v0, 0 +; GFX11-NEXT: global_store_b64 v2, v[0:1], s[4:5] +; GFX11-NEXT: s_sendmsg sendmsg(MSG_DEALLOC_VGPRS) +; GFX11-NEXT: s_endpgm %tid = call i32 @llvm.amdgcn.workitem.id.x() - %gep.a = getelementptr inbounds i32, i32 addrspace(1)* %aptr, i32 %tid - %gep.b = getelementptr inbounds i32, i32 addrspace(1)* %bptr, i32 %tid - %a = load i32, i32 addrspace(1)* %gep.a - %b = load i32, i32 addrspace(1)* %gep.b + %gep.a = getelementptr inbounds i32, ptr addrspace(1) %aptr, i32 %tid + %gep.b = getelementptr inbounds i32, ptr addrspace(1) %bptr, i32 %tid + %a = load i32, ptr addrspace(1) %gep.a + %b = load i32, ptr addrspace(1) %gep.b %a_ext = zext i32 %a to i64 %b_ext = zext i32 %b to i64 %mul = mul i64 %a_ext, %b_ext - store i64 %mul, i64 addrspace(1)* %out + store i64 %mul, ptr addrspace(1) %out ret void } ; 64-bit multiplication where the upper bytes of the first argument were masked. -define amdgpu_kernel void @v_mul_i64_and_a_hi(i64 addrspace(1)* %out, i64 addrspace(1)* %aptr, i64 addrspace(1)* %bptr) { -; FUNC-LABEL: v_mul_i64_and_a_hi: -; FUNC: ; %bb.0: -; FUNC-NEXT: s_clause 0x1 -; FUNC-NEXT: s_load_dwordx4 s[4:7], s[0:1], 0x24 -; FUNC-NEXT: s_load_dwordx2 s[2:3], s[0:1], 0x34 -; FUNC-NEXT: v_lshlrev_b32_e32 v2, 3, v0 -; FUNC-NEXT: s_waitcnt lgkmcnt(0) -; FUNC-NEXT: s_clause 0x1 -; FUNC-NEXT: global_load_dword v4, v2, s[6:7] -; FUNC-NEXT: global_load_dwordx2 v[0:1], v2, s[2:3] -; FUNC-NEXT: s_waitcnt vmcnt(0) -; FUNC-NEXT: v_mad_u64_u32 v[2:3], s0, v4, v0, 0 -; FUNC-NEXT: v_mul_lo_u32 v1, v4, v1 -; FUNC-NEXT: v_mul_lo_u32 v0, 0, v0 -; FUNC-NEXT: v_add3_u32 v3, v3, v1, v0 -; FUNC-NEXT: v_mov_b32_e32 v0, 0 -; FUNC-NEXT: global_store_dwordx2 v0, v[2:3], s[4:5] -; FUNC-NEXT: s_endpgm -%tid = call i32 @llvm.amdgcn.workitem.id.x() - %gep.a = getelementptr inbounds i64, i64 addrspace(1)* %aptr, i32 %tid - %gep.b = getelementptr inbounds i64, i64 addrspace(1)* %bptr, i32 %tid - %a = load i64, i64 addrspace(1)* %gep.a - %b = load i64, i64 addrspace(1)* %gep.b +define amdgpu_kernel void @v_mul_i64_masked_src0_hi(ptr addrspace(1) %out, ptr addrspace(1) %aptr, ptr addrspace(1) %bptr) { +; GFX10-LABEL: v_mul_i64_masked_src0_hi: +; GFX10: ; %bb.0: +; GFX10-NEXT: s_clause 0x1 +; GFX10-NEXT: s_load_dwordx4 s[4:7], s[0:1], 0x24 +; GFX10-NEXT: s_load_dwordx2 s[2:3], s[0:1], 0x34 +; GFX10-NEXT: v_lshlrev_b32_e32 v2, 3, v0 +; GFX10-NEXT: s_waitcnt lgkmcnt(0) +; GFX10-NEXT: s_clause 0x1 +; GFX10-NEXT: global_load_dword v4, v2, s[6:7] +; GFX10-NEXT: global_load_dwordx2 v[0:1], v2, s[2:3] +; GFX10-NEXT: s_waitcnt vmcnt(0) +; GFX10-NEXT: v_mad_u64_u32 v[2:3], s0, v4, v0, 0 +; GFX10-NEXT: v_mul_lo_u32 v0, v4, v1 +; GFX10-NEXT: v_add_nc_u32_e32 v3, v3, v0 +; GFX10-NEXT: v_mov_b32_e32 v0, 0 +; GFX10-NEXT: global_store_dwordx2 v0, v[2:3], s[4:5] +; GFX10-NEXT: s_endpgm +; +; GFX11-LABEL: v_mul_i64_masked_src0_hi: +; GFX11: ; %bb.0: +; GFX11-NEXT: s_clause 0x1 +; GFX11-NEXT: s_load_b128 s[4:7], s[0:1], 0x24 +; GFX11-NEXT: s_load_b64 s[0:1], s[0:1], 0x34 +; GFX11-NEXT: v_lshlrev_b32_e32 v0, 3, v0 +; GFX11-NEXT: s_waitcnt lgkmcnt(0) +; GFX11-NEXT: s_clause 0x1 +; GFX11-NEXT: global_load_b32 v4, v0, s[6:7] +; GFX11-NEXT: global_load_b64 v[0:1], v0, s[0:1] +; GFX11-NEXT: s_waitcnt vmcnt(0) +; GFX11-NEXT: v_mad_u64_u32 v[2:3], null, v4, v0, 0 +; GFX11-NEXT: v_mul_lo_u32 v0, v4, v1 +; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1) +; GFX11-NEXT: v_dual_mov_b32 v0, 0 :: v_dual_add_nc_u32 v3, v3, v0 +; GFX11-NEXT: global_store_b64 v0, v[2:3], s[4:5] +; GFX11-NEXT: s_sendmsg sendmsg(MSG_DEALLOC_VGPRS) +; GFX11-NEXT: s_endpgm + %tid = call i32 @llvm.amdgcn.workitem.id.x() + %gep.a = getelementptr inbounds i64, ptr addrspace(1) %aptr, i32 %tid + %gep.b = getelementptr inbounds i64, ptr addrspace(1) %bptr, i32 %tid + %a = load i64, ptr addrspace(1) %gep.a + %b = load i64, ptr addrspace(1) %gep.b %a_and = and i64 %a, u0x00000000FFFFFFFF %mul = mul i64 %a_and, %b - store i64 %mul, i64 addrspace(1)* %out + store i64 %mul, ptr addrspace(1) %out ret void } ; 64-bit multiplication where lower bytes of first argument were masked. -define amdgpu_kernel void @v_mul_i64_and_a_lo(i64 addrspace(1)* %out, i64 addrspace(1)* %aptr, i64 addrspace(1)* %bptr) { -; FUNC-LABEL: v_mul_i64_and_a_lo: -; FUNC: ; %bb.0: -; FUNC-NEXT: s_clause 0x1 -; FUNC-NEXT: s_load_dwordx2 s[2:3], s[0:1], 0x34 -; FUNC-NEXT: s_load_dwordx4 s[4:7], s[0:1], 0x24 -; FUNC-NEXT: v_lshlrev_b32_e32 v4, 3, v0 -; FUNC-NEXT: s_waitcnt lgkmcnt(0) -; FUNC-NEXT: s_clause 0x1 -; FUNC-NEXT: global_load_dwordx2 v[0:1], v4, s[2:3] -; FUNC-NEXT: global_load_dwordx2 v[2:3], v4, s[6:7] -; FUNC-NEXT: s_waitcnt vmcnt(1) -; FUNC-NEXT: v_mad_u64_u32 v[4:5], s0, 0, v0, 0 -; FUNC-NEXT: v_mul_lo_u32 v1, 0, v1 -; FUNC-NEXT: s_waitcnt vmcnt(0) -; FUNC-NEXT: v_mul_lo_u32 v0, v3, v0 -; FUNC-NEXT: v_add3_u32 v5, v5, v1, v0 -; FUNC-NEXT: v_mov_b32_e32 v0, 0 -; FUNC-NEXT: global_store_dwordx2 v0, v[4:5], s[4:5] -; FUNC-NEXT: s_endpgm +define amdgpu_kernel void @v_mul_i64_masked_src0_lo(ptr addrspace(1) %out, ptr addrspace(1) %aptr, ptr addrspace(1) %bptr) { +; GFX10-LABEL: v_mul_i64_masked_src0_lo: +; GFX10: ; %bb.0: +; GFX10-NEXT: s_clause 0x1 +; GFX10-NEXT: s_load_dwordx4 s[4:7], s[0:1], 0x24 +; GFX10-NEXT: s_load_dwordx2 s[2:3], s[0:1], 0x34 +; GFX10-NEXT: v_lshlrev_b32_e32 v4, 3, v0 +; GFX10-NEXT: s_waitcnt lgkmcnt(0) +; GFX10-NEXT: s_clause 0x1 +; GFX10-NEXT: global_load_dwordx2 v[0:1], v4, s[6:7] +; GFX10-NEXT: global_load_dwordx2 v[2:3], v4, s[2:3] +; GFX10-NEXT: s_waitcnt vmcnt(1) +; GFX10-NEXT: v_mov_b32_e32 v0, 0 +; GFX10-NEXT: s_waitcnt vmcnt(0) +; GFX10-NEXT: v_mul_lo_u32 v1, v1, v2 +; GFX10-NEXT: global_store_dwordx2 v0, v[0:1], s[4:5] +; GFX10-NEXT: s_endpgm +; +; GFX11-LABEL: v_mul_i64_masked_src0_lo: +; GFX11: ; %bb.0: +; GFX11-NEXT: s_clause 0x1 +; GFX11-NEXT: s_load_b128 s[4:7], s[0:1], 0x24 +; GFX11-NEXT: s_load_b64 s[0:1], s[0:1], 0x34 +; GFX11-NEXT: v_lshlrev_b32_e32 v2, 3, v0 +; GFX11-NEXT: s_waitcnt lgkmcnt(0) +; GFX11-NEXT: s_clause 0x1 +; GFX11-NEXT: global_load_b64 v[0:1], v2, s[6:7] +; GFX11-NEXT: global_load_b64 v[2:3], v2, s[0:1] +; GFX11-NEXT: s_waitcnt vmcnt(1) +; GFX11-NEXT: v_mov_b32_e32 v0, 0 +; GFX11-NEXT: s_waitcnt vmcnt(0) +; GFX11-NEXT: v_mul_lo_u32 v1, v1, v2 +; GFX11-NEXT: global_store_b64 v0, v[0:1], s[4:5] +; GFX11-NEXT: s_sendmsg sendmsg(MSG_DEALLOC_VGPRS) +; GFX11-NEXT: s_endpgm %tid = call i32 @llvm.amdgcn.workitem.id.x() - %gep.a = getelementptr inbounds i64, i64 addrspace(1)* %aptr, i32 %tid - %gep.b = getelementptr inbounds i64, i64 addrspace(1)* %bptr, i32 %tid - %a = load i64, i64 addrspace(1)* %gep.a - %b = load i64, i64 addrspace(1)* %gep.b + %gep.a = getelementptr inbounds i64, ptr addrspace(1) %aptr, i32 %tid + %gep.b = getelementptr inbounds i64, ptr addrspace(1) %bptr, i32 %tid + %a = load i64, ptr addrspace(1) %gep.a + %b = load i64, ptr addrspace(1) %gep.b %a_and = and i64 %a, u0xFFFFFFFF00000000 %mul = mul i64 %a_and, %b - store i64 %mul, i64 addrspace(1)* %out + store i64 %mul, ptr addrspace(1) %out ret void } ; 64-bit multiplication where the lower bytes of the second argument were masked. -define amdgpu_kernel void @v_mul_i64_and_b_lo(i64 addrspace(1)* %out, i64 addrspace(1)* %aptr, i64 addrspace(1)* %bptr) { -; FUNC-LABEL: v_mul_i64_and_b_lo: -; FUNC: ; %bb.0: -; FUNC-NEXT: s_clause 0x1 -; FUNC-NEXT: s_load_dwordx4 s[4:7], s[0:1], 0x24 -; FUNC-NEXT: s_load_dwordx2 s[2:3], s[0:1], 0x34 -; FUNC-NEXT: v_lshlrev_b32_e32 v4, 3, v0 -; FUNC-NEXT: s_waitcnt lgkmcnt(0) -; FUNC-NEXT: s_clause 0x1 -; FUNC-NEXT: global_load_dwordx2 v[0:1], v4, s[6:7] -; FUNC-NEXT: global_load_dwordx2 v[2:3], v4, s[2:3] -; FUNC-NEXT: s_waitcnt vmcnt(1) -; FUNC-NEXT: v_mad_u64_u32 v[4:5], s0, v0, 0, 0 -; FUNC-NEXT: s_waitcnt vmcnt(0) -; FUNC-NEXT: v_mul_lo_u32 v0, v0, v3 -; FUNC-NEXT: v_mul_lo_u32 v1, v1, 0 -; FUNC-NEXT: v_add3_u32 v5, v5, v0, v1 -; FUNC-NEXT: v_mov_b32_e32 v0, 0 -; FUNC-NEXT: global_store_dwordx2 v0, v[4:5], s[4:5] -; FUNC-NEXT: s_endpgm +define amdgpu_kernel void @v_mul_i64_masked_src1_lo(ptr addrspace(1) %out, ptr addrspace(1) %aptr, ptr addrspace(1) %bptr) { +; GFX10-LABEL: v_mul_i64_masked_src1_lo: +; GFX10: ; %bb.0: +; GFX10-NEXT: s_clause 0x1 +; GFX10-NEXT: s_load_dwordx4 s[4:7], s[0:1], 0x24 +; GFX10-NEXT: s_load_dwordx2 s[2:3], s[0:1], 0x34 +; GFX10-NEXT: v_lshlrev_b32_e32 v3, 3, v0 +; GFX10-NEXT: ; kill: killed $vgpr3 +; GFX10-NEXT: ; kill: killed $sgpr6_sgpr7 +; GFX10-NEXT: s_waitcnt lgkmcnt(0) +; GFX10-NEXT: s_clause 0x1 +; GFX10-NEXT: global_load_dwordx2 v[0:1], v3, s[6:7] +; GFX10-NEXT: global_load_dwordx2 v[1:2], v3, s[2:3] +; GFX10-NEXT: ; kill: killed $sgpr2_sgpr3 +; GFX10-NEXT: s_waitcnt vmcnt(0) +; GFX10-NEXT: v_mul_lo_u32 v1, v0, v2 +; GFX10-NEXT: v_mov_b32_e32 v0, 0 +; GFX10-NEXT: global_store_dwordx2 v0, v[0:1], s[4:5] +; GFX10-NEXT: s_endpgm +; +; GFX11-LABEL: v_mul_i64_masked_src1_lo: +; GFX11: ; %bb.0: +; GFX11-NEXT: s_clause 0x1 +; GFX11-NEXT: s_load_b128 s[4:7], s[0:1], 0x24 +; GFX11-NEXT: s_load_b64 s[0:1], s[0:1], 0x34 +; GFX11-NEXT: v_lshlrev_b32_e32 v2, 3, v0 +; GFX11-NEXT: s_waitcnt lgkmcnt(0) +; GFX11-NEXT: s_clause 0x1 +; GFX11-NEXT: global_load_b64 v[0:1], v2, s[6:7] +; GFX11-NEXT: global_load_b64 v[1:2], v2, s[0:1] +; GFX11-NEXT: s_waitcnt vmcnt(0) +; GFX11-NEXT: v_mul_lo_u32 v1, v0, v2 +; GFX11-NEXT: v_mov_b32_e32 v0, 0 +; GFX11-NEXT: global_store_b64 v0, v[0:1], s[4:5] +; GFX11-NEXT: s_sendmsg sendmsg(MSG_DEALLOC_VGPRS) +; GFX11-NEXT: s_endpgm %tid = call i32 @llvm.amdgcn.workitem.id.x() - %gep.a = getelementptr inbounds i64, i64 addrspace(1)* %aptr, i32 %tid - %gep.b = getelementptr inbounds i64, i64 addrspace(1)* %bptr, i32 %tid - %a = load i64, i64 addrspace(1)* %gep.a - %b = load i64, i64 addrspace(1)* %gep.b + %gep.a = getelementptr inbounds i64, ptr addrspace(1) %aptr, i32 %tid + %gep.b = getelementptr inbounds i64, ptr addrspace(1) %bptr, i32 %tid + %a = load i64, ptr addrspace(1) %gep.a + %b = load i64, ptr addrspace(1) %gep.b %b_and = and i64 %b, u0xFFFFFFFF00000000 %mul = mul i64 %a, %b_and - store i64 %mul, i64 addrspace(1)* %out + store i64 %mul, ptr addrspace(1) %out ret void } ; 64-bit multiplication where the entire first argument is masked. -define amdgpu_kernel void @v_mul_i64_and_hilo(i64 addrspace(1)* %out, i64 addrspace(1)* %aptr, i64 addrspace(1)* %bptr) { -; FUNC-LABEL: v_mul_i64_and_hilo: -; FUNC: ; %bb.0: -; FUNC-NEXT: s_load_dwordx2 s[0:1], s[0:1], 0x24 -; FUNC-NEXT: v_mov_b32_e32 v0, 0 -; FUNC-NEXT: v_mov_b32_e32 v1, 0 -; FUNC-NEXT: v_mov_b32_e32 v2, 0 -; FUNC-NEXT: s_waitcnt lgkmcnt(0) -; FUNC-NEXT: global_store_dwordx2 v2, v[0:1], s[0:1] -; FUNC-NEXT: s_endpgm +define amdgpu_kernel void @v_mul_i64_masked_src0(ptr addrspace(1) %out, ptr addrspace(1) %aptr, ptr addrspace(1) %bptr) { +; GFX10-LABEL: v_mul_i64_masked_src0: +; GFX10: ; %bb.0: +; GFX10-NEXT: s_load_dwordx2 s[0:1], s[0:1], 0x24 +; GFX10-NEXT: v_mov_b32_e32 v0, 0 +; GFX10-NEXT: v_mov_b32_e32 v1, 0 +; GFX10-NEXT: v_mov_b32_e32 v2, 0 +; GFX10-NEXT: s_waitcnt lgkmcnt(0) +; GFX10-NEXT: global_store_dwordx2 v2, v[0:1], s[0:1] +; GFX10-NEXT: s_endpgm +; +; GFX11-LABEL: v_mul_i64_masked_src0: +; GFX11: ; %bb.0: +; GFX11-NEXT: s_load_b64 s[0:1], s[0:1], 0x24 +; GFX11-NEXT: v_mov_b32_e32 v0, 0 +; GFX11-NEXT: v_dual_mov_b32 v1, 0 :: v_dual_mov_b32 v2, 0 +; GFX11-NEXT: s_waitcnt lgkmcnt(0) +; GFX11-NEXT: global_store_b64 v2, v[0:1], s[0:1] +; GFX11-NEXT: s_sendmsg sendmsg(MSG_DEALLOC_VGPRS) +; GFX11-NEXT: s_endpgm %tid = call i32 @llvm.amdgcn.workitem.id.x() - %gep.a = getelementptr inbounds i64, i64 addrspace(1)* %aptr, i32 %tid - %gep.b = getelementptr inbounds i64, i64 addrspace(1)* %bptr, i32 %tid - %a = load i64, i64 addrspace(1)* %gep.a - %b = load i64, i64 addrspace(1)* %gep.b + %gep.a = getelementptr inbounds i64, ptr addrspace(1) %aptr, i32 %tid + %gep.b = getelementptr inbounds i64, ptr addrspace(1) %bptr, i32 %tid + %a = load i64, ptr addrspace(1) %gep.a + %b = load i64, ptr addrspace(1) %gep.b %a_and = and i64 %a, u0x0000000000000000 %mul = mul i64 %a_and, %b - store i64 %mul, i64 addrspace(1)* %out + store i64 %mul, ptr addrspace(1) %out + ret void +} + +; 64-bit multiplication where the parts of the high and low bytes of the first argument are masked. +define amdgpu_kernel void @v_mul_i64_partially_masked_src0(ptr addrspace(1) %out, ptr addrspace(1) %aptr, ptr addrspace(1) %bptr) { +; GFX10-LABEL: v_mul_i64_partially_masked_src0: +; GFX10: ; %bb.0: +; GFX10-NEXT: s_clause 0x1 +; GFX10-NEXT: s_load_dwordx4 s[4:7], s[0:1], 0x24 +; GFX10-NEXT: s_load_dwordx2 s[2:3], s[0:1], 0x34 +; GFX10-NEXT: v_lshlrev_b32_e32 v4, 3, v0 +; GFX10-NEXT: s_waitcnt lgkmcnt(0) +; GFX10-NEXT: s_clause 0x1 +; GFX10-NEXT: global_load_dwordx2 v[0:1], v4, s[6:7] +; GFX10-NEXT: global_load_dwordx2 v[2:3], v4, s[2:3] +; GFX10-NEXT: s_waitcnt vmcnt(1) +; GFX10-NEXT: v_and_b32_e32 v4, 0xfff00000, v0 +; GFX10-NEXT: v_and_b32_e32 v5, 0xf00f, v1 +; GFX10-NEXT: s_waitcnt vmcnt(0) +; GFX10-NEXT: v_mad_u64_u32 v[0:1], s0, v4, v2, 0 +; GFX10-NEXT: v_mul_lo_u32 v3, v4, v3 +; GFX10-NEXT: v_mul_lo_u32 v2, v5, v2 +; GFX10-NEXT: v_add3_u32 v1, v1, v3, v2 +; GFX10-NEXT: v_mov_b32_e32 v2, 0 +; GFX10-NEXT: global_store_dwordx2 v2, v[0:1], s[4:5] +; GFX10-NEXT: s_endpgm +; +; GFX11-LABEL: v_mul_i64_partially_masked_src0: +; GFX11: ; %bb.0: +; GFX11-NEXT: s_clause 0x1 +; GFX11-NEXT: s_load_b128 s[4:7], s[0:1], 0x24 +; GFX11-NEXT: s_load_b64 s[0:1], s[0:1], 0x34 +; GFX11-NEXT: v_lshlrev_b32_e32 v2, 3, v0 +; GFX11-NEXT: s_waitcnt lgkmcnt(0) +; GFX11-NEXT: s_clause 0x1 +; GFX11-NEXT: global_load_b64 v[0:1], v2, s[6:7] +; GFX11-NEXT: global_load_b64 v[2:3], v2, s[0:1] +; GFX11-NEXT: s_waitcnt vmcnt(1) +; GFX11-NEXT: v_and_b32_e32 v4, 0xfff00000, v0 +; GFX11-NEXT: v_and_b32_e32 v5, 0xf00f, v1 +; GFX11-NEXT: s_waitcnt vmcnt(0) +; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_3) +; GFX11-NEXT: v_mad_u64_u32 v[0:1], null, v4, v2, 0 +; GFX11-NEXT: v_mul_lo_u32 v3, v4, v3 +; GFX11-NEXT: v_mul_lo_u32 v2, v5, v2 +; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1) +; GFX11-NEXT: v_add3_u32 v1, v1, v3, v2 +; GFX11-NEXT: v_mov_b32_e32 v2, 0 +; GFX11-NEXT: global_store_b64 v2, v[0:1], s[4:5] +; GFX11-NEXT: s_sendmsg sendmsg(MSG_DEALLOC_VGPRS) +; GFX11-NEXT: s_endpgm + %tid = call i32 @llvm.amdgcn.workitem.id.x() + %gep.a = getelementptr inbounds i64, ptr addrspace(1) %aptr, i32 %tid + %gep.b = getelementptr inbounds i64, ptr addrspace(1) %bptr, i32 %tid + %a = load i64, ptr addrspace(1) %gep.a + %b = load i64, ptr addrspace(1) %gep.b + %a_and = and i64 %a, u0x0000F00FFFF00000 + %mul = mul i64 %a_and, %b + store i64 %mul, ptr addrspace(1) %out ret void } ; 64-bit multiplication, where the first argument is masked before a branch -define amdgpu_kernel void @mul64_and_in_branch(i64 addrspace(1)* %out, i64 addrspace(1)* %aptr, i64 addrspace(1)* %bptr) { -; FUNC-LABEL: mul64_and_in_branch: -; FUNC: ; %bb.0: ; %entry -; FUNC-NEXT: s_load_dwordx2 s[0:1], s[0:1], 0x24 -; FUNC-NEXT: v_mov_b32_e32 v0, 0 -; FUNC-NEXT: v_mov_b32_e32 v1, 0 -; FUNC-NEXT: v_mov_b32_e32 v2, 0 -; FUNC-NEXT: s_waitcnt lgkmcnt(0) -; FUNC-NEXT: global_store_dwordx2 v2, v[0:1], s[0:1] -; FUNC-NEXT: s_endpgm +define amdgpu_kernel void @v_mul64_masked_before_branch(ptr addrspace(1) %out, ptr addrspace(1) %aptr, ptr addrspace(1) %bptr) { +; GFX10-LABEL: v_mul64_masked_before_branch: +; GFX10: ; %bb.0: ; %entry +; GFX10-NEXT: s_load_dwordx2 s[0:1], s[0:1], 0x24 +; GFX10-NEXT: v_mov_b32_e32 v0, 0 +; GFX10-NEXT: v_mov_b32_e32 v1, 0 +; GFX10-NEXT: v_mov_b32_e32 v2, 0 +; GFX10-NEXT: s_waitcnt lgkmcnt(0) +; GFX10-NEXT: global_store_dwordx2 v2, v[0:1], s[0:1] +; GFX10-NEXT: s_endpgm +; +; GFX11-LABEL: v_mul64_masked_before_branch: +; GFX11: ; %bb.0: ; %entry +; GFX11-NEXT: s_load_b64 s[0:1], s[0:1], 0x24 +; GFX11-NEXT: v_mov_b32_e32 v0, 0 +; GFX11-NEXT: v_dual_mov_b32 v1, 0 :: v_dual_mov_b32 v2, 0 +; GFX11-NEXT: s_waitcnt lgkmcnt(0) +; GFX11-NEXT: global_store_b64 v2, v[0:1], s[0:1] +; GFX11-NEXT: s_sendmsg sendmsg(MSG_DEALLOC_VGPRS) +; GFX11-NEXT: s_endpgm entry: %tid = call i32 @llvm.amdgcn.workitem.id.x() - %gep.a = getelementptr inbounds i64, i64 addrspace(1)* %aptr, i32 %tid - %gep.b = getelementptr inbounds i64, i64 addrspace(1)* %bptr, i32 %tid - %a = load i64, i64 addrspace(1)* %gep.a - %b = load i64, i64 addrspace(1)* %gep.b + %gep.a = getelementptr inbounds i64, ptr addrspace(1) %aptr, i32 %tid + %gep.b = getelementptr inbounds i64, ptr addrspace(1) %bptr, i32 %tid + %a = load i64, ptr addrspace(1) %gep.a + %b = load i64, ptr addrspace(1) %gep.b %a_and = and i64 %a, u0x0000000000000000 %0 = icmp eq i64 %b, 0 br i1 %0, label %if, label %else @@ -271,56 +470,79 @@ endif: %3 = phi i64 [%1, %if], [%2, %else] - store i64 %3, i64 addrspace(1)* %out + store i64 %3, ptr addrspace(1) %out ret void } -; 64-bit multiplication with both arguments changed in differnt basic blocks. -define amdgpu_kernel void @mul64_and_in_branch_2(i64 addrspace(1)* %out, i64 addrspace(1)* %aptr, i64 addrspace(1)* %bptr) { -; FUNC-LABEL: mul64_and_in_branch_2: -; FUNC: ; %bb.0: ; %entry -; FUNC-NEXT: s_clause 0x1 -; FUNC-NEXT: s_load_dwordx4 s[4:7], s[0:1], 0x24 -; FUNC-NEXT: s_load_dwordx2 s[2:3], s[0:1], 0x34 -; FUNC-NEXT: v_lshlrev_b32_e32 v0, 3, v0 -; FUNC-NEXT: s_waitcnt lgkmcnt(0) -; FUNC-NEXT: s_clause 0x1 -; FUNC-NEXT: global_load_dwordx2 v[2:3], v0, s[6:7] -; FUNC-NEXT: global_load_dwordx2 v[4:5], v0, s[2:3] -; FUNC-NEXT: ; implicit-def: $vgpr0_vgpr1 -; FUNC-NEXT: s_waitcnt vmcnt(1) -; FUNC-NEXT: v_cmp_ge_u64_e32 vcc_lo, 0, v[2:3] -; FUNC-NEXT: s_and_saveexec_b32 s0, vcc_lo -; FUNC-NEXT: s_xor_b32 s0, exec_lo, s0 -; FUNC-NEXT: s_cbranch_execz .LBB9_2 -; FUNC-NEXT: ; %bb.1: ; %else -; FUNC-NEXT: s_waitcnt vmcnt(0) -; FUNC-NEXT: v_mad_u64_u32 v[0:1], s1, v2, v4, 0 -; FUNC-NEXT: v_mul_lo_u32 v2, v2, v5 -; FUNC-NEXT: v_mul_lo_u32 v3, 0, v4 -; FUNC-NEXT: ; implicit-def: $vgpr4_vgpr5 -; FUNC-NEXT: v_add3_u32 v1, v1, v2, v3 -; FUNC-NEXT: ; implicit-def: $vgpr2_vgpr3 -; FUNC-NEXT: .LBB9_2: ; %Flow -; FUNC-NEXT: s_andn2_saveexec_b32 s0, s0 -; FUNC-NEXT: s_cbranch_execz .LBB9_4 -; FUNC-NEXT: ; %bb.3: ; %if -; FUNC-NEXT: v_mad_u64_u32 v[0:1], s1, v2, 0, 0 -; FUNC-NEXT: s_waitcnt vmcnt(0) -; FUNC-NEXT: v_mul_lo_u32 v2, v2, v5 -; FUNC-NEXT: v_mul_lo_u32 v3, 0, 0 -; FUNC-NEXT: v_add3_u32 v1, v1, v2, v3 -; FUNC-NEXT: .LBB9_4: ; %endif -; FUNC-NEXT: s_or_b32 exec_lo, exec_lo, s0 -; FUNC-NEXT: v_mov_b32_e32 v2, 0 -; FUNC-NEXT: global_store_dwordx2 v2, v[0:1], s[4:5] -; FUNC-NEXT: s_endpgm +; 64-bit multiplication with both arguments changed in different basic blocks. +define amdgpu_kernel void @v_mul64_masked_before_and_in_branch(ptr addrspace(1) %out, ptr addrspace(1) %aptr, ptr addrspace(1) %bptr) { +; GFX10-LABEL: v_mul64_masked_before_and_in_branch: +; GFX10: ; %bb.0: ; %entry +; GFX10-NEXT: s_clause 0x1 +; GFX10-NEXT: s_load_dwordx4 s[4:7], s[0:1], 0x24 +; GFX10-NEXT: s_load_dwordx2 s[2:3], s[0:1], 0x34 +; GFX10-NEXT: v_lshlrev_b32_e32 v4, 3, v0 +; GFX10-NEXT: s_waitcnt lgkmcnt(0) +; GFX10-NEXT: s_clause 0x1 +; GFX10-NEXT: global_load_dwordx2 v[2:3], v4, s[6:7] +; GFX10-NEXT: global_load_dwordx2 v[0:1], v4, s[2:3] +; GFX10-NEXT: s_waitcnt vmcnt(1) +; GFX10-NEXT: v_cmp_ge_u64_e32 vcc_lo, 0, v[2:3] +; GFX10-NEXT: s_waitcnt vmcnt(0) +; GFX10-NEXT: v_mul_lo_u32 v1, v2, v1 +; GFX10-NEXT: s_and_saveexec_b32 s0, vcc_lo +; GFX10-NEXT: s_xor_b32 s0, exec_lo, s0 +; GFX10-NEXT: ; %bb.1: ; %else +; GFX10-NEXT: v_mad_u64_u32 v[2:3], s1, v2, v0, 0 +; GFX10-NEXT: v_add_nc_u32_e32 v3, v3, v1 +; GFX10-NEXT: v_mov_b32_e32 v0, v2 +; GFX10-NEXT: v_mov_b32_e32 v1, v3 +; GFX10-NEXT: ; %bb.2: ; %Flow +; GFX10-NEXT: s_andn2_saveexec_b32 s0, s0 +; GFX10-NEXT: ; %bb.3: ; %if +; GFX10-NEXT: v_mov_b32_e32 v0, 0 +; GFX10-NEXT: ; %bb.4: ; %endif +; GFX10-NEXT: s_or_b32 exec_lo, exec_lo, s0 +; GFX10-NEXT: v_mov_b32_e32 v2, 0 +; GFX10-NEXT: global_store_dwordx2 v2, v[0:1], s[4:5] +; GFX10-NEXT: s_endpgm +; +; GFX11-LABEL: v_mul64_masked_before_and_in_branch: +; GFX11: ; %bb.0: ; %entry +; GFX11-NEXT: s_clause 0x1 +; GFX11-NEXT: s_load_b128 s[4:7], s[0:1], 0x24 +; GFX11-NEXT: s_load_b64 s[0:1], s[0:1], 0x34 +; GFX11-NEXT: v_lshlrev_b32_e32 v0, 3, v0 +; GFX11-NEXT: s_waitcnt lgkmcnt(0) +; GFX11-NEXT: s_clause 0x1 +; GFX11-NEXT: global_load_b64 v[2:3], v0, s[6:7] +; GFX11-NEXT: global_load_b64 v[0:1], v0, s[0:1] +; GFX11-NEXT: s_mov_b32 s0, exec_lo +; GFX11-NEXT: s_waitcnt vmcnt(0) +; GFX11-NEXT: v_mul_lo_u32 v1, v2, v1 +; GFX11-NEXT: v_cmpx_ge_u64_e32 0, v[2:3] +; GFX11-NEXT: s_xor_b32 s0, exec_lo, s0 +; GFX11-NEXT: ; %bb.1: ; %else +; GFX11-NEXT: v_mad_u64_u32 v[2:3], null, v2, v0, 0 +; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1) +; GFX11-NEXT: v_dual_mov_b32 v0, v2 :: v_dual_add_nc_u32 v3, v3, v1 +; GFX11-NEXT: v_mov_b32_e32 v1, v3 +; GFX11-NEXT: ; %bb.2: ; %Flow +; GFX11-NEXT: s_and_not1_saveexec_b32 s0, s0 +; GFX11-NEXT: ; %bb.3: ; %if +; GFX11-NEXT: v_mov_b32_e32 v0, 0 +; GFX11-NEXT: ; %bb.4: ; %endif +; GFX11-NEXT: s_or_b32 exec_lo, exec_lo, s0 +; GFX11-NEXT: v_mov_b32_e32 v2, 0 +; GFX11-NEXT: global_store_b64 v2, v[0:1], s[4:5] +; GFX11-NEXT: s_sendmsg sendmsg(MSG_DEALLOC_VGPRS) +; GFX11-NEXT: s_endpgm entry: %tid = call i32 @llvm.amdgcn.workitem.id.x() - %gep.a = getelementptr inbounds i64, i64 addrspace(1)* %aptr, i32 %tid - %gep.b = getelementptr inbounds i64, i64 addrspace(1)* %bptr, i32 %tid - %a = load i64, i64 addrspace(1)* %gep.a - %b = load i64, i64 addrspace(1)* %gep.b + %gep.a = getelementptr inbounds i64, ptr addrspace(1) %aptr, i32 %tid + %gep.b = getelementptr inbounds i64, ptr addrspace(1) %bptr, i32 %tid + %a = load i64, ptr addrspace(1) %gep.a + %b = load i64, ptr addrspace(1) %gep.b %a_and = and i64 %a, u0x00000000FFFFFFFF %0 = icmp ugt i64 %a, 0 br i1 %0, label %if, label %else @@ -336,7 +558,8 @@ endif: %3 = phi i64 [%1, %if], [%2, %else] - store i64 %3, i64 addrspace(1)* %out + store i64 %3, ptr addrspace(1) %out ret void } + diff --git a/llvm/test/CodeGen/AMDGPU/GlobalISel/sdiv.i64.ll b/llvm/test/CodeGen/AMDGPU/GlobalISel/sdiv.i64.ll --- a/llvm/test/CodeGen/AMDGPU/GlobalISel/sdiv.i64.ll +++ b/llvm/test/CodeGen/AMDGPU/GlobalISel/sdiv.i64.ll @@ -1035,89 +1035,88 @@ ; CHECK-NEXT: v_addc_u32_e32 v6, vcc, v6, v3, vcc ; CHECK-NEXT: v_mad_u64_u32 v[2:3], s[4:5], s6, v5, 0 ; CHECK-NEXT: v_ashrrev_i32_e32 v7, 31, v1 -; CHECK-NEXT: v_add_i32_e32 v0, vcc, v0, v7 +; CHECK-NEXT: v_add_i32_e32 v8, vcc, v0, v7 ; CHECK-NEXT: v_mad_u64_u32 v[3:4], s[4:5], s6, v6, v[3:4] -; CHECK-NEXT: v_addc_u32_e32 v1, vcc, v1, v7, vcc -; CHECK-NEXT: v_mad_u64_u32 v[3:4], s[4:5], -1, v5, v[3:4] -; CHECK-NEXT: v_xor_b32_e32 v4, v0, v7 -; CHECK-NEXT: v_mul_lo_u32 v0, v6, v2 -; CHECK-NEXT: v_mul_lo_u32 v8, v5, v3 -; CHECK-NEXT: v_xor_b32_e32 v9, v1, v7 -; CHECK-NEXT: v_mul_hi_u32 v1, v5, v2 +; CHECK-NEXT: v_addc_u32_e32 v9, vcc, v1, v7, vcc +; CHECK-NEXT: v_mad_u64_u32 v[0:1], s[4:5], -1, v5, v[3:4] +; CHECK-NEXT: v_xor_b32_e32 v3, v8, v7 +; CHECK-NEXT: v_mul_lo_u32 v1, v6, v2 +; CHECK-NEXT: v_mul_lo_u32 v8, v5, v0 +; CHECK-NEXT: v_xor_b32_e32 v4, v9, v7 +; CHECK-NEXT: v_mul_hi_u32 v9, v5, v2 ; CHECK-NEXT: v_mul_hi_u32 v2, v6, v2 -; CHECK-NEXT: v_add_i32_e32 v0, vcc, v0, v8 -; CHECK-NEXT: v_cndmask_b32_e64 v8, 0, 1, vcc -; CHECK-NEXT: v_add_i32_e32 v0, vcc, v0, v1 -; CHECK-NEXT: v_cndmask_b32_e64 v0, 0, 1, vcc -; CHECK-NEXT: v_mul_lo_u32 v1, v6, v3 -; CHECK-NEXT: v_add_i32_e32 v0, vcc, v8, v0 -; CHECK-NEXT: v_mul_hi_u32 v8, v5, v3 -; CHECK-NEXT: v_add_i32_e32 v1, vcc, v1, v2 -; CHECK-NEXT: v_cndmask_b32_e64 v2, 0, 1, vcc ; CHECK-NEXT: v_add_i32_e32 v1, vcc, v1, v8 ; CHECK-NEXT: v_cndmask_b32_e64 v8, 0, 1, vcc -; CHECK-NEXT: v_add_i32_e32 v2, vcc, v2, v8 -; CHECK-NEXT: v_mul_hi_u32 v3, v6, v3 -; CHECK-NEXT: v_add_i32_e32 v0, vcc, v1, v0 +; CHECK-NEXT: v_add_i32_e32 v1, vcc, v1, v9 ; CHECK-NEXT: v_cndmask_b32_e64 v1, 0, 1, vcc +; CHECK-NEXT: v_mul_lo_u32 v9, v6, v0 +; CHECK-NEXT: v_add_i32_e32 v1, vcc, v8, v1 +; CHECK-NEXT: v_mul_hi_u32 v8, v5, v0 +; CHECK-NEXT: v_add_i32_e32 v2, vcc, v9, v2 +; CHECK-NEXT: v_cndmask_b32_e64 v9, 0, 1, vcc +; CHECK-NEXT: v_add_i32_e32 v2, vcc, v2, v8 +; CHECK-NEXT: v_cndmask_b32_e64 v8, 0, 1, vcc +; CHECK-NEXT: v_add_i32_e32 v8, vcc, v9, v8 +; CHECK-NEXT: v_mul_hi_u32 v0, v6, v0 ; CHECK-NEXT: v_add_i32_e32 v1, vcc, v2, v1 -; CHECK-NEXT: v_add_i32_e32 v1, vcc, v3, v1 -; CHECK-NEXT: v_add_i32_e32 v0, vcc, v5, v0 -; CHECK-NEXT: v_addc_u32_e32 v1, vcc, v6, v1, vcc -; CHECK-NEXT: v_mul_lo_u32 v2, v9, v0 -; CHECK-NEXT: v_mul_lo_u32 v3, v4, v1 -; CHECK-NEXT: v_mul_hi_u32 v5, v4, v0 -; CHECK-NEXT: v_mul_hi_u32 v0, v9, v0 +; CHECK-NEXT: v_cndmask_b32_e64 v2, 0, 1, vcc +; CHECK-NEXT: v_add_i32_e32 v2, vcc, v8, v2 +; CHECK-NEXT: v_add_i32_e32 v0, vcc, v0, v2 +; CHECK-NEXT: v_add_i32_e32 v1, vcc, v5, v1 +; CHECK-NEXT: v_addc_u32_e32 v0, vcc, v6, v0, vcc +; CHECK-NEXT: v_mul_lo_u32 v2, v4, v1 +; CHECK-NEXT: v_mul_lo_u32 v5, v3, v0 +; CHECK-NEXT: v_mul_hi_u32 v8, v3, v1 +; CHECK-NEXT: v_mul_hi_u32 v1, v4, v1 ; CHECK-NEXT: s_movk_i32 s6, 0x1000 -; CHECK-NEXT: v_add_i32_e32 v2, vcc, v2, v3 -; CHECK-NEXT: v_cndmask_b32_e64 v3, 0, 1, vcc ; CHECK-NEXT: v_add_i32_e32 v2, vcc, v2, v5 +; CHECK-NEXT: v_cndmask_b32_e64 v5, 0, 1, vcc +; CHECK-NEXT: v_add_i32_e32 v2, vcc, v2, v8 ; CHECK-NEXT: v_cndmask_b32_e64 v2, 0, 1, vcc -; CHECK-NEXT: v_mul_lo_u32 v5, v9, v1 -; CHECK-NEXT: v_add_i32_e32 v2, vcc, v3, v2 -; CHECK-NEXT: v_mul_hi_u32 v3, v4, v1 -; CHECK-NEXT: v_add_i32_e32 v0, vcc, v5, v0 +; CHECK-NEXT: v_mul_lo_u32 v8, v4, v0 +; CHECK-NEXT: v_add_i32_e32 v2, vcc, v5, v2 +; CHECK-NEXT: v_mul_hi_u32 v5, v3, v0 +; CHECK-NEXT: v_add_i32_e32 v1, vcc, v8, v1 +; CHECK-NEXT: v_cndmask_b32_e64 v8, 0, 1, vcc +; CHECK-NEXT: v_add_i32_e32 v1, vcc, v1, v5 ; CHECK-NEXT: v_cndmask_b32_e64 v5, 0, 1, vcc -; CHECK-NEXT: v_add_i32_e32 v0, vcc, v0, v3 -; CHECK-NEXT: v_cndmask_b32_e64 v3, 0, 1, vcc -; CHECK-NEXT: v_add_i32_e32 v3, vcc, v5, v3 -; CHECK-NEXT: v_add_i32_e32 v5, vcc, v0, v2 -; CHECK-NEXT: v_mul_hi_u32 v6, v9, v1 -; CHECK-NEXT: v_mad_u64_u32 v[0:1], s[4:5], s6, v5, 0 +; CHECK-NEXT: v_add_i32_e32 v5, vcc, v8, v5 +; CHECK-NEXT: v_add_i32_e32 v8, vcc, v1, v2 +; CHECK-NEXT: v_mul_hi_u32 v9, v4, v0 +; CHECK-NEXT: v_mad_u64_u32 v[0:1], s[4:5], s6, v8, 0 ; CHECK-NEXT: v_cndmask_b32_e64 v2, 0, 1, vcc -; CHECK-NEXT: v_add_i32_e32 v2, vcc, v3, v2 -; CHECK-NEXT: v_add_i32_e32 v3, vcc, v6, v2 -; CHECK-NEXT: v_mad_u64_u32 v[1:2], s[4:5], s6, v3, v[1:2] -; CHECK-NEXT: v_sub_i32_e32 v0, vcc, v4, v0 -; CHECK-NEXT: v_mad_u64_u32 v[1:2], s[4:5], 0, v5, v[1:2] +; CHECK-NEXT: v_add_i32_e32 v2, vcc, v5, v2 +; CHECK-NEXT: v_add_i32_e32 v5, vcc, v9, v2 +; CHECK-NEXT: v_mad_u64_u32 v[1:2], s[4:5], s6, v5, v[1:2] +; CHECK-NEXT: v_sub_i32_e32 v0, vcc, v3, v0 +; CHECK-NEXT: v_subb_u32_e64 v2, s[4:5], v4, v1, vcc +; CHECK-NEXT: v_sub_i32_e64 v1, s[4:5], v4, v1 ; CHECK-NEXT: v_mov_b32_e32 v6, 0x1000 -; CHECK-NEXT: s_bfe_i32 s6, -1, 0x10000 -; CHECK-NEXT: v_subb_u32_e64 v2, s[4:5], v9, v1, vcc -; CHECK-NEXT: v_sub_i32_e64 v1, s[4:5], v9, v1 ; CHECK-NEXT: v_subbrev_u32_e32 v1, vcc, 0, v1, vcc +; CHECK-NEXT: s_bfe_i32 s6, -1, 0x10000 ; CHECK-NEXT: v_cmp_ge_u32_e64 s[4:5], v0, v6 ; CHECK-NEXT: v_sub_i32_e32 v0, vcc, v0, v6 -; CHECK-NEXT: v_cndmask_b32_e64 v4, 0, -1, s[4:5] -; CHECK-NEXT: v_mov_b32_e32 v8, s6 +; CHECK-NEXT: v_cndmask_b32_e64 v3, 0, -1, s[4:5] +; CHECK-NEXT: v_mov_b32_e32 v4, s6 ; CHECK-NEXT: v_cmp_eq_u32_e64 s[4:5], 0, v2 ; CHECK-NEXT: v_subbrev_u32_e32 v1, vcc, 0, v1, vcc -; CHECK-NEXT: v_cndmask_b32_e64 v2, v8, v4, s[4:5] -; CHECK-NEXT: v_add_i32_e32 v4, vcc, 1, v5 -; CHECK-NEXT: v_addc_u32_e32 v8, vcc, 0, v3, vcc +; CHECK-NEXT: v_cndmask_b32_e64 v2, v4, v3, s[4:5] +; CHECK-NEXT: v_add_i32_e32 v3, vcc, 1, v8 +; CHECK-NEXT: v_addc_u32_e32 v4, vcc, 0, v5, vcc ; CHECK-NEXT: s_bfe_i32 s4, -1, 0x10000 ; CHECK-NEXT: v_cmp_ge_u32_e32 vcc, v0, v6 ; CHECK-NEXT: v_cndmask_b32_e64 v0, 0, -1, vcc ; CHECK-NEXT: v_mov_b32_e32 v6, s4 ; CHECK-NEXT: v_cmp_eq_u32_e32 vcc, 0, v1 ; CHECK-NEXT: v_cndmask_b32_e32 v0, v6, v0, vcc -; CHECK-NEXT: v_add_i32_e32 v1, vcc, 1, v4 -; CHECK-NEXT: v_addc_u32_e32 v6, vcc, 0, v8, vcc +; CHECK-NEXT: v_add_i32_e32 v1, vcc, 1, v3 +; CHECK-NEXT: v_addc_u32_e32 v6, vcc, 0, v4, vcc ; CHECK-NEXT: v_cmp_ne_u32_e32 vcc, 0, v0 -; CHECK-NEXT: v_cndmask_b32_e32 v0, v4, v1, vcc -; CHECK-NEXT: v_cndmask_b32_e32 v1, v8, v6, vcc +; CHECK-NEXT: v_cndmask_b32_e32 v0, v3, v1, vcc +; CHECK-NEXT: v_cndmask_b32_e32 v1, v4, v6, vcc ; CHECK-NEXT: v_cmp_ne_u32_e32 vcc, 0, v2 -; CHECK-NEXT: v_cndmask_b32_e32 v0, v5, v0, vcc -; CHECK-NEXT: v_cndmask_b32_e32 v1, v3, v1, vcc +; CHECK-NEXT: v_cndmask_b32_e32 v0, v8, v0, vcc +; CHECK-NEXT: v_cndmask_b32_e32 v1, v5, v1, vcc ; CHECK-NEXT: v_xor_b32_e32 v0, v0, v7 ; CHECK-NEXT: v_xor_b32_e32 v1, v1, v7 ; CHECK-NEXT: v_sub_i32_e32 v0, vcc, v0, v7 @@ -1437,88 +1436,87 @@ ; CGP-NEXT: v_add_i32_e32 v6, vcc, v9, v6 ; CGP-NEXT: v_add_i32_e32 v5, vcc, v5, v6 ; CGP-NEXT: v_add_i32_e32 v9, vcc, v7, v4 -; CGP-NEXT: v_addc_u32_e32 v8, vcc, v8, v5, vcc -; CGP-NEXT: v_mad_u64_u32 v[5:6], s[4:5], s6, v9, 0 -; CGP-NEXT: v_mov_b32_e32 v4, v6 -; CGP-NEXT: v_mad_u64_u32 v[6:7], s[4:5], s6, v8, v[4:5] -; CGP-NEXT: v_ashrrev_i32_e32 v4, 31, v1 -; CGP-NEXT: v_add_i32_e32 v0, vcc, v0, v4 -; CGP-NEXT: v_mad_u64_u32 v[6:7], s[4:5], -1, v9, v[6:7] -; CGP-NEXT: v_addc_u32_e32 v1, vcc, v1, v4, vcc -; CGP-NEXT: v_xor_b32_e32 v10, v0, v4 -; CGP-NEXT: v_mul_lo_u32 v0, v8, v5 -; CGP-NEXT: v_mul_lo_u32 v7, v9, v6 -; CGP-NEXT: v_xor_b32_e32 v11, v1, v4 -; CGP-NEXT: v_mul_hi_u32 v1, v9, v5 -; CGP-NEXT: v_mul_hi_u32 v5, v8, v5 -; CGP-NEXT: v_add_i32_e32 v0, vcc, v0, v7 -; CGP-NEXT: v_cndmask_b32_e64 v7, 0, 1, vcc -; CGP-NEXT: v_add_i32_e32 v0, vcc, v0, v1 -; CGP-NEXT: v_cndmask_b32_e64 v0, 0, 1, vcc -; CGP-NEXT: v_mul_lo_u32 v1, v8, v6 -; CGP-NEXT: v_add_i32_e32 v0, vcc, v7, v0 +; CGP-NEXT: v_mad_u64_u32 v[6:7], s[4:5], s6, v9, 0 +; CGP-NEXT: v_addc_u32_e32 v10, vcc, v8, v5, vcc +; CGP-NEXT: v_ashrrev_i32_e32 v5, 31, v1 +; CGP-NEXT: v_mov_b32_e32 v4, v7 +; CGP-NEXT: v_mad_u64_u32 v[7:8], s[4:5], s6, v10, v[4:5] +; CGP-NEXT: v_add_i32_e32 v4, vcc, v0, v5 +; CGP-NEXT: v_addc_u32_e32 v11, vcc, v1, v5, vcc +; CGP-NEXT: v_mad_u64_u32 v[0:1], s[4:5], -1, v9, v[7:8] +; CGP-NEXT: v_xor_b32_e32 v8, v4, v5 +; CGP-NEXT: v_mul_lo_u32 v1, v10, v6 +; CGP-NEXT: v_mul_lo_u32 v4, v9, v0 ; CGP-NEXT: v_mul_hi_u32 v7, v9, v6 -; CGP-NEXT: v_add_i32_e32 v1, vcc, v1, v5 -; CGP-NEXT: v_cndmask_b32_e64 v5, 0, 1, vcc +; CGP-NEXT: v_mul_hi_u32 v6, v10, v6 +; CGP-NEXT: v_xor_b32_e32 v11, v11, v5 +; CGP-NEXT: v_add_i32_e32 v1, vcc, v1, v4 +; CGP-NEXT: v_cndmask_b32_e64 v4, 0, 1, vcc ; CGP-NEXT: v_add_i32_e32 v1, vcc, v1, v7 -; CGP-NEXT: v_cndmask_b32_e64 v7, 0, 1, vcc -; CGP-NEXT: v_add_i32_e32 v5, vcc, v5, v7 -; CGP-NEXT: v_mul_hi_u32 v6, v8, v6 -; CGP-NEXT: v_add_i32_e32 v0, vcc, v1, v0 ; CGP-NEXT: v_cndmask_b32_e64 v1, 0, 1, vcc -; CGP-NEXT: v_add_i32_e32 v1, vcc, v5, v1 -; CGP-NEXT: v_add_i32_e32 v1, vcc, v6, v1 -; CGP-NEXT: v_add_i32_e32 v0, vcc, v9, v0 -; CGP-NEXT: v_addc_u32_e32 v1, vcc, v8, v1, vcc -; CGP-NEXT: v_mul_lo_u32 v5, v11, v0 -; CGP-NEXT: v_mul_lo_u32 v6, v10, v1 -; CGP-NEXT: v_mul_hi_u32 v7, v10, v0 -; CGP-NEXT: v_mul_hi_u32 v0, v11, v0 -; CGP-NEXT: v_add_i32_e32 v5, vcc, v5, v6 +; CGP-NEXT: v_mul_lo_u32 v7, v10, v0 +; CGP-NEXT: v_add_i32_e32 v1, vcc, v4, v1 +; CGP-NEXT: v_mul_hi_u32 v4, v9, v0 +; CGP-NEXT: v_add_i32_e32 v6, vcc, v7, v6 +; CGP-NEXT: v_cndmask_b32_e64 v7, 0, 1, vcc +; CGP-NEXT: v_add_i32_e32 v4, vcc, v6, v4 ; CGP-NEXT: v_cndmask_b32_e64 v6, 0, 1, vcc -; CGP-NEXT: v_add_i32_e32 v5, vcc, v5, v7 -; CGP-NEXT: v_cndmask_b32_e64 v5, 0, 1, vcc -; CGP-NEXT: v_mul_lo_u32 v7, v11, v1 -; CGP-NEXT: v_add_i32_e32 v5, vcc, v6, v5 -; CGP-NEXT: v_mul_hi_u32 v6, v10, v1 -; CGP-NEXT: v_add_i32_e32 v0, vcc, v7, v0 +; CGP-NEXT: v_add_i32_e32 v6, vcc, v7, v6 +; CGP-NEXT: v_mul_hi_u32 v0, v10, v0 +; CGP-NEXT: v_add_i32_e32 v1, vcc, v4, v1 +; CGP-NEXT: v_cndmask_b32_e64 v4, 0, 1, vcc +; CGP-NEXT: v_add_i32_e32 v4, vcc, v6, v4 +; CGP-NEXT: v_add_i32_e32 v0, vcc, v0, v4 +; CGP-NEXT: v_add_i32_e32 v1, vcc, v9, v1 +; CGP-NEXT: v_addc_u32_e32 v0, vcc, v10, v0, vcc +; CGP-NEXT: v_mul_lo_u32 v6, v11, v1 +; CGP-NEXT: v_mul_lo_u32 v7, v8, v0 +; CGP-NEXT: v_mul_hi_u32 v9, v8, v1 +; CGP-NEXT: v_mul_hi_u32 v1, v11, v1 +; CGP-NEXT: v_mul_hi_u32 v10, v11, v0 +; CGP-NEXT: v_add_i32_e32 v6, vcc, v6, v7 ; CGP-NEXT: v_cndmask_b32_e64 v7, 0, 1, vcc -; CGP-NEXT: v_add_i32_e32 v0, vcc, v0, v6 +; CGP-NEXT: v_add_i32_e32 v6, vcc, v6, v9 ; CGP-NEXT: v_cndmask_b32_e64 v6, 0, 1, vcc +; CGP-NEXT: v_mul_lo_u32 v9, v11, v0 ; CGP-NEXT: v_add_i32_e32 v6, vcc, v7, v6 -; CGP-NEXT: v_add_i32_e32 v8, vcc, v0, v5 -; CGP-NEXT: v_mul_hi_u32 v7, v11, v1 -; CGP-NEXT: v_mad_u64_u32 v[0:1], s[4:5], s7, v8, 0 -; CGP-NEXT: v_cndmask_b32_e64 v5, 0, 1, vcc -; CGP-NEXT: v_add_i32_e32 v5, vcc, v6, v5 -; CGP-NEXT: v_add_i32_e32 v9, vcc, v7, v5 -; CGP-NEXT: v_mad_u64_u32 v[6:7], s[4:5], s7, v9, v[1:2] -; CGP-NEXT: v_sub_i32_e32 v0, vcc, v10, v0 -; CGP-NEXT: v_mad_u64_u32 v[6:7], s[4:5], 0, v8, v[6:7] -; CGP-NEXT: v_mov_b32_e32 v5, 0x1000 -; CGP-NEXT: v_mov_b32_e32 v10, s8 +; CGP-NEXT: v_mul_hi_u32 v7, v8, v0 +; CGP-NEXT: v_add_i32_e32 v1, vcc, v9, v1 +; CGP-NEXT: v_cndmask_b32_e64 v9, 0, 1, vcc +; CGP-NEXT: v_add_i32_e32 v1, vcc, v1, v7 +; CGP-NEXT: v_cndmask_b32_e64 v7, 0, 1, vcc +; CGP-NEXT: v_add_i32_e32 v7, vcc, v9, v7 +; CGP-NEXT: v_add_i32_e32 v9, vcc, v1, v6 +; CGP-NEXT: v_mad_u64_u32 v[0:1], s[4:5], s7, v9, 0 +; CGP-NEXT: v_cndmask_b32_e64 v6, 0, 1, vcc +; CGP-NEXT: v_add_i32_e32 v6, vcc, v7, v6 +; CGP-NEXT: v_add_i32_e32 v10, vcc, v10, v6 +; CGP-NEXT: v_mad_u64_u32 v[6:7], s[4:5], s7, v10, v[1:2] +; CGP-NEXT: v_sub_i32_e32 v0, vcc, v8, v0 +; CGP-NEXT: v_mov_b32_e32 v4, 0x1000 ; CGP-NEXT: v_subb_u32_e64 v1, s[4:5], v11, v6, vcc ; CGP-NEXT: v_sub_i32_e64 v6, s[4:5], v11, v6 -; CGP-NEXT: v_cmp_ge_u32_e64 s[4:5], v0, v5 +; CGP-NEXT: v_cmp_ge_u32_e64 s[4:5], v0, v4 ; CGP-NEXT: v_cndmask_b32_e64 v7, 0, -1, s[4:5] ; CGP-NEXT: v_cmp_eq_u32_e64 s[4:5], 0, v1 ; CGP-NEXT: v_subbrev_u32_e32 v1, vcc, 0, v6, vcc ; CGP-NEXT: v_cvt_f32_u32_e32 v6, 0x1000 -; CGP-NEXT: v_sub_i32_e32 v0, vcc, v0, v5 -; CGP-NEXT: v_cndmask_b32_e64 v10, v10, v7, s[4:5] +; CGP-NEXT: v_mov_b32_e32 v8, s8 +; CGP-NEXT: v_sub_i32_e32 v0, vcc, v0, v4 +; CGP-NEXT: v_cndmask_b32_e64 v8, v8, v7, s[4:5] ; CGP-NEXT: v_subbrev_u32_e32 v7, vcc, 0, v1, vcc ; CGP-NEXT: v_cvt_f32_ubyte0_e32 v1, 0 ; CGP-NEXT: v_mac_f32_e32 v6, 0x4f800000, v1 ; CGP-NEXT: v_rcp_iflag_f32_e32 v1, v6 -; CGP-NEXT: v_add_i32_e32 v11, vcc, 1, v8 -; CGP-NEXT: v_addc_u32_e32 v12, vcc, 0, v9, vcc +; CGP-NEXT: v_add_i32_e32 v11, vcc, 1, v9 +; CGP-NEXT: v_addc_u32_e32 v12, vcc, 0, v10, vcc ; CGP-NEXT: v_mul_f32_e32 v1, 0x5f7ffffc, v1 ; CGP-NEXT: v_mul_f32_e32 v6, 0x2f800000, v1 ; CGP-NEXT: v_trunc_f32_e32 v6, v6 ; CGP-NEXT: v_mac_f32_e32 v1, 0xcf800000, v6 ; CGP-NEXT: v_cvt_u32_f32_e32 v13, v1 ; CGP-NEXT: s_bfe_i32 s4, -1, 0x10000 -; CGP-NEXT: v_cmp_ge_u32_e32 vcc, v0, v5 +; CGP-NEXT: v_cmp_ge_u32_e32 vcc, v0, v4 ; CGP-NEXT: v_mov_b32_e32 v15, s4 ; CGP-NEXT: v_mad_u64_u32 v[0:1], s[4:5], s6, v13, 0 ; CGP-NEXT: v_cvt_u32_f32_e32 v16, v6 @@ -1556,96 +1554,94 @@ ; CGP-NEXT: v_add_i32_e32 v11, vcc, v13, v0 ; CGP-NEXT: v_addc_u32_e32 v13, vcc, v16, v1, vcc ; CGP-NEXT: v_mad_u64_u32 v[0:1], s[4:5], s6, v11, 0 -; CGP-NEXT: v_cmp_ne_u32_e32 vcc, 0, v10 -; CGP-NEXT: v_cndmask_b32_e32 v8, v8, v7, vcc +; CGP-NEXT: v_cmp_ne_u32_e32 vcc, 0, v8 +; CGP-NEXT: v_cndmask_b32_e32 v6, v9, v7, vcc +; CGP-NEXT: v_xor_b32_e32 v9, v6, v5 ; CGP-NEXT: v_mad_u64_u32 v[6:7], s[4:5], s6, v13, v[1:2] -; CGP-NEXT: v_xor_b32_e32 v1, v8, v4 -; CGP-NEXT: v_ashrrev_i32_e32 v8, 31, v3 +; CGP-NEXT: v_cndmask_b32_e32 v8, v10, v12, vcc +; CGP-NEXT: v_xor_b32_e32 v1, v8, v5 ; CGP-NEXT: v_mad_u64_u32 v[6:7], s[4:5], -1, v11, v[6:7] -; CGP-NEXT: v_cndmask_b32_e32 v9, v9, v12, vcc +; CGP-NEXT: v_ashrrev_i32_e32 v8, 31, v3 ; CGP-NEXT: v_add_i32_e32 v2, vcc, v2, v8 ; CGP-NEXT: v_addc_u32_e32 v3, vcc, v3, v8, vcc -; CGP-NEXT: v_xor_b32_e32 v10, v2, v8 +; CGP-NEXT: v_xor_b32_e32 v7, v2, v8 ; CGP-NEXT: v_mul_lo_u32 v2, v13, v0 -; CGP-NEXT: v_mul_lo_u32 v7, v11, v6 +; CGP-NEXT: v_mul_lo_u32 v10, v11, v6 ; CGP-NEXT: v_xor_b32_e32 v12, v3, v8 ; CGP-NEXT: v_mul_hi_u32 v3, v11, v0 ; CGP-NEXT: v_mul_hi_u32 v0, v13, v0 -; CGP-NEXT: v_add_i32_e32 v2, vcc, v2, v7 -; CGP-NEXT: v_cndmask_b32_e64 v7, 0, 1, vcc +; CGP-NEXT: v_add_i32_e32 v2, vcc, v2, v10 +; CGP-NEXT: v_cndmask_b32_e64 v10, 0, 1, vcc ; CGP-NEXT: v_add_i32_e32 v2, vcc, v2, v3 ; CGP-NEXT: v_cndmask_b32_e64 v2, 0, 1, vcc ; CGP-NEXT: v_mul_lo_u32 v3, v13, v6 -; CGP-NEXT: v_add_i32_e32 v2, vcc, v7, v2 -; CGP-NEXT: v_mul_hi_u32 v7, v11, v6 +; CGP-NEXT: v_add_i32_e32 v2, vcc, v10, v2 +; CGP-NEXT: v_mul_hi_u32 v10, v11, v6 ; CGP-NEXT: v_add_i32_e32 v0, vcc, v3, v0 ; CGP-NEXT: v_cndmask_b32_e64 v3, 0, 1, vcc -; CGP-NEXT: v_add_i32_e32 v0, vcc, v0, v7 -; CGP-NEXT: v_cndmask_b32_e64 v7, 0, 1, vcc -; CGP-NEXT: v_add_i32_e32 v3, vcc, v3, v7 +; CGP-NEXT: v_add_i32_e32 v0, vcc, v0, v10 +; CGP-NEXT: v_cndmask_b32_e64 v10, 0, 1, vcc +; CGP-NEXT: v_add_i32_e32 v3, vcc, v3, v10 ; CGP-NEXT: v_mul_hi_u32 v6, v13, v6 ; CGP-NEXT: v_add_i32_e32 v0, vcc, v0, v2 ; CGP-NEXT: v_cndmask_b32_e64 v2, 0, 1, vcc ; CGP-NEXT: v_add_i32_e32 v2, vcc, v3, v2 ; CGP-NEXT: v_add_i32_e32 v2, vcc, v6, v2 -; CGP-NEXT: v_add_i32_e32 v0, vcc, v11, v0 +; CGP-NEXT: v_add_i32_e32 v3, vcc, v11, v0 ; CGP-NEXT: v_addc_u32_e32 v2, vcc, v13, v2, vcc -; CGP-NEXT: v_mul_lo_u32 v3, v12, v0 -; CGP-NEXT: v_mul_lo_u32 v6, v10, v2 -; CGP-NEXT: v_mul_hi_u32 v7, v10, v0 -; CGP-NEXT: v_mul_hi_u32 v0, v12, v0 -; CGP-NEXT: v_xor_b32_e32 v9, v9, v4 -; CGP-NEXT: v_add_i32_e32 v3, vcc, v3, v6 -; CGP-NEXT: v_cndmask_b32_e64 v6, 0, 1, vcc -; CGP-NEXT: v_add_i32_e32 v3, vcc, v3, v7 -; CGP-NEXT: v_cndmask_b32_e64 v3, 0, 1, vcc -; CGP-NEXT: v_mul_lo_u32 v7, v12, v2 +; CGP-NEXT: v_mul_lo_u32 v6, v12, v3 +; CGP-NEXT: v_mul_lo_u32 v10, v7, v2 +; CGP-NEXT: v_sub_i32_e32 v0, vcc, v9, v5 +; CGP-NEXT: v_subb_u32_e32 v1, vcc, v1, v5, vcc +; CGP-NEXT: v_mul_hi_u32 v5, v7, v3 +; CGP-NEXT: v_add_i32_e32 v6, vcc, v6, v10 +; CGP-NEXT: v_cndmask_b32_e64 v9, 0, 1, vcc +; CGP-NEXT: v_add_i32_e32 v5, vcc, v6, v5 +; CGP-NEXT: v_cndmask_b32_e64 v5, 0, 1, vcc +; CGP-NEXT: v_mul_lo_u32 v6, v12, v2 +; CGP-NEXT: v_mul_hi_u32 v3, v12, v3 +; CGP-NEXT: v_add_i32_e32 v5, vcc, v9, v5 +; CGP-NEXT: v_mul_hi_u32 v9, v7, v2 ; CGP-NEXT: v_add_i32_e32 v3, vcc, v6, v3 -; CGP-NEXT: v_mul_hi_u32 v6, v10, v2 -; CGP-NEXT: v_add_i32_e32 v0, vcc, v7, v0 -; CGP-NEXT: v_cndmask_b32_e64 v7, 0, 1, vcc -; CGP-NEXT: v_add_i32_e32 v0, vcc, v0, v6 ; CGP-NEXT: v_cndmask_b32_e64 v6, 0, 1, vcc -; CGP-NEXT: v_add_i32_e32 v6, vcc, v7, v6 -; CGP-NEXT: v_add_i32_e32 v11, vcc, v0, v3 -; CGP-NEXT: v_mul_hi_u32 v7, v12, v2 -; CGP-NEXT: v_mad_u64_u32 v[2:3], s[4:5], s7, v11, 0 -; CGP-NEXT: v_cndmask_b32_e64 v0, 0, 1, vcc -; CGP-NEXT: v_add_i32_e32 v0, vcc, v6, v0 -; CGP-NEXT: v_add_i32_e32 v13, vcc, v7, v0 -; CGP-NEXT: v_mov_b32_e32 v0, v3 -; CGP-NEXT: v_mad_u64_u32 v[6:7], s[4:5], s7, v13, v[0:1] -; CGP-NEXT: v_sub_i32_e32 v0, vcc, v1, v4 -; CGP-NEXT: v_subb_u32_e32 v1, vcc, v9, v4, vcc -; CGP-NEXT: v_mad_u64_u32 v[3:4], s[4:5], 0, v11, v[6:7] -; CGP-NEXT: v_sub_i32_e32 v2, vcc, v10, v2 -; CGP-NEXT: v_subb_u32_e64 v4, s[4:5], v12, v3, vcc -; CGP-NEXT: v_sub_i32_e64 v3, s[4:5], v12, v3 -; CGP-NEXT: v_subbrev_u32_e32 v3, vcc, 0, v3, vcc +; CGP-NEXT: v_add_i32_e32 v3, vcc, v3, v9 +; CGP-NEXT: v_cndmask_b32_e64 v9, 0, 1, vcc +; CGP-NEXT: v_add_i32_e32 v6, vcc, v6, v9 +; CGP-NEXT: v_add_i32_e32 v9, vcc, v3, v5 +; CGP-NEXT: v_mul_hi_u32 v10, v12, v2 +; CGP-NEXT: v_mad_u64_u32 v[2:3], s[4:5], s7, v9, 0 +; CGP-NEXT: v_cndmask_b32_e64 v5, 0, 1, vcc +; CGP-NEXT: v_add_i32_e32 v5, vcc, v6, v5 +; CGP-NEXT: v_add_i32_e32 v10, vcc, v10, v5 +; CGP-NEXT: v_mad_u64_u32 v[5:6], s[4:5], s7, v10, v[3:4] +; CGP-NEXT: v_sub_i32_e32 v2, vcc, v7, v2 +; CGP-NEXT: v_subb_u32_e64 v3, s[4:5], v12, v5, vcc +; CGP-NEXT: v_sub_i32_e64 v5, s[4:5], v12, v5 +; CGP-NEXT: v_subbrev_u32_e32 v5, vcc, 0, v5, vcc ; CGP-NEXT: s_bfe_i32 s6, -1, 0x10000 -; CGP-NEXT: v_cmp_ge_u32_e64 s[4:5], v2, v5 -; CGP-NEXT: v_sub_i32_e32 v2, vcc, v2, v5 +; CGP-NEXT: v_cmp_ge_u32_e64 s[4:5], v2, v4 +; CGP-NEXT: v_sub_i32_e32 v2, vcc, v2, v4 ; CGP-NEXT: v_cndmask_b32_e64 v6, 0, -1, s[4:5] ; CGP-NEXT: v_mov_b32_e32 v7, s6 -; CGP-NEXT: v_cmp_eq_u32_e64 s[4:5], 0, v4 -; CGP-NEXT: v_subbrev_u32_e32 v3, vcc, 0, v3, vcc -; CGP-NEXT: v_cndmask_b32_e64 v4, v7, v6, s[4:5] -; CGP-NEXT: v_add_i32_e32 v6, vcc, 1, v11 -; CGP-NEXT: v_addc_u32_e32 v7, vcc, 0, v13, vcc +; CGP-NEXT: v_cmp_eq_u32_e64 s[4:5], 0, v3 +; CGP-NEXT: v_subbrev_u32_e32 v5, vcc, 0, v5, vcc +; CGP-NEXT: v_cndmask_b32_e64 v3, v7, v6, s[4:5] +; CGP-NEXT: v_add_i32_e32 v6, vcc, 1, v9 +; CGP-NEXT: v_addc_u32_e32 v7, vcc, 0, v10, vcc ; CGP-NEXT: s_bfe_i32 s4, -1, 0x10000 -; CGP-NEXT: v_cmp_ge_u32_e32 vcc, v2, v5 +; CGP-NEXT: v_cmp_ge_u32_e32 vcc, v2, v4 ; CGP-NEXT: v_cndmask_b32_e64 v2, 0, -1, vcc -; CGP-NEXT: v_mov_b32_e32 v5, s4 -; CGP-NEXT: v_cmp_eq_u32_e32 vcc, 0, v3 -; CGP-NEXT: v_cndmask_b32_e32 v2, v5, v2, vcc -; CGP-NEXT: v_add_i32_e32 v3, vcc, 1, v6 +; CGP-NEXT: v_mov_b32_e32 v4, s4 +; CGP-NEXT: v_cmp_eq_u32_e32 vcc, 0, v5 +; CGP-NEXT: v_cndmask_b32_e32 v2, v4, v2, vcc +; CGP-NEXT: v_add_i32_e32 v4, vcc, 1, v6 ; CGP-NEXT: v_addc_u32_e32 v5, vcc, 0, v7, vcc ; CGP-NEXT: v_cmp_ne_u32_e32 vcc, 0, v2 -; CGP-NEXT: v_cndmask_b32_e32 v2, v6, v3, vcc -; CGP-NEXT: v_cndmask_b32_e32 v3, v7, v5, vcc -; CGP-NEXT: v_cmp_ne_u32_e32 vcc, 0, v4 -; CGP-NEXT: v_cndmask_b32_e32 v2, v11, v2, vcc -; CGP-NEXT: v_cndmask_b32_e32 v3, v13, v3, vcc +; CGP-NEXT: v_cndmask_b32_e32 v2, v6, v4, vcc +; CGP-NEXT: v_cndmask_b32_e32 v4, v7, v5, vcc +; CGP-NEXT: v_cmp_ne_u32_e32 vcc, 0, v3 +; CGP-NEXT: v_cndmask_b32_e32 v2, v9, v2, vcc +; CGP-NEXT: v_cndmask_b32_e32 v3, v10, v4, vcc ; CGP-NEXT: v_xor_b32_e32 v2, v2, v8 ; CGP-NEXT: v_xor_b32_e32 v3, v3, v8 ; CGP-NEXT: v_sub_i32_e32 v2, vcc, v2, v8 @@ -1699,89 +1695,88 @@ ; CHECK-NEXT: v_addc_u32_e32 v6, vcc, v6, v3, vcc ; CHECK-NEXT: v_mad_u64_u32 v[2:3], s[4:5], s6, v5, 0 ; CHECK-NEXT: v_ashrrev_i32_e32 v7, 31, v1 -; CHECK-NEXT: v_add_i32_e32 v0, vcc, v0, v7 +; CHECK-NEXT: v_add_i32_e32 v8, vcc, v0, v7 ; CHECK-NEXT: v_mad_u64_u32 v[3:4], s[4:5], s6, v6, v[3:4] -; CHECK-NEXT: v_addc_u32_e32 v1, vcc, v1, v7, vcc -; CHECK-NEXT: v_mad_u64_u32 v[3:4], s[4:5], -1, v5, v[3:4] -; CHECK-NEXT: v_xor_b32_e32 v4, v0, v7 -; CHECK-NEXT: v_mul_lo_u32 v0, v6, v2 -; CHECK-NEXT: v_mul_lo_u32 v8, v5, v3 -; CHECK-NEXT: v_xor_b32_e32 v9, v1, v7 -; CHECK-NEXT: v_mul_hi_u32 v1, v5, v2 +; CHECK-NEXT: v_addc_u32_e32 v9, vcc, v1, v7, vcc +; CHECK-NEXT: v_mad_u64_u32 v[0:1], s[4:5], -1, v5, v[3:4] +; CHECK-NEXT: v_xor_b32_e32 v3, v8, v7 +; CHECK-NEXT: v_mul_lo_u32 v1, v6, v2 +; CHECK-NEXT: v_mul_lo_u32 v8, v5, v0 +; CHECK-NEXT: v_xor_b32_e32 v4, v9, v7 +; CHECK-NEXT: v_mul_hi_u32 v9, v5, v2 ; CHECK-NEXT: v_mul_hi_u32 v2, v6, v2 -; CHECK-NEXT: v_add_i32_e32 v0, vcc, v0, v8 -; CHECK-NEXT: v_cndmask_b32_e64 v8, 0, 1, vcc -; CHECK-NEXT: v_add_i32_e32 v0, vcc, v0, v1 -; CHECK-NEXT: v_cndmask_b32_e64 v0, 0, 1, vcc -; CHECK-NEXT: v_mul_lo_u32 v1, v6, v3 -; CHECK-NEXT: v_add_i32_e32 v0, vcc, v8, v0 -; CHECK-NEXT: v_mul_hi_u32 v8, v5, v3 -; CHECK-NEXT: v_add_i32_e32 v1, vcc, v1, v2 -; CHECK-NEXT: v_cndmask_b32_e64 v2, 0, 1, vcc ; CHECK-NEXT: v_add_i32_e32 v1, vcc, v1, v8 ; CHECK-NEXT: v_cndmask_b32_e64 v8, 0, 1, vcc -; CHECK-NEXT: v_add_i32_e32 v2, vcc, v2, v8 -; CHECK-NEXT: v_mul_hi_u32 v3, v6, v3 -; CHECK-NEXT: v_add_i32_e32 v0, vcc, v1, v0 +; CHECK-NEXT: v_add_i32_e32 v1, vcc, v1, v9 ; CHECK-NEXT: v_cndmask_b32_e64 v1, 0, 1, vcc +; CHECK-NEXT: v_mul_lo_u32 v9, v6, v0 +; CHECK-NEXT: v_add_i32_e32 v1, vcc, v8, v1 +; CHECK-NEXT: v_mul_hi_u32 v8, v5, v0 +; CHECK-NEXT: v_add_i32_e32 v2, vcc, v9, v2 +; CHECK-NEXT: v_cndmask_b32_e64 v9, 0, 1, vcc +; CHECK-NEXT: v_add_i32_e32 v2, vcc, v2, v8 +; CHECK-NEXT: v_cndmask_b32_e64 v8, 0, 1, vcc +; CHECK-NEXT: v_add_i32_e32 v8, vcc, v9, v8 +; CHECK-NEXT: v_mul_hi_u32 v0, v6, v0 ; CHECK-NEXT: v_add_i32_e32 v1, vcc, v2, v1 -; CHECK-NEXT: v_add_i32_e32 v1, vcc, v3, v1 -; CHECK-NEXT: v_add_i32_e32 v0, vcc, v5, v0 -; CHECK-NEXT: v_addc_u32_e32 v1, vcc, v6, v1, vcc -; CHECK-NEXT: v_mul_lo_u32 v2, v9, v0 -; CHECK-NEXT: v_mul_lo_u32 v3, v4, v1 -; CHECK-NEXT: v_mul_hi_u32 v5, v4, v0 -; CHECK-NEXT: v_mul_hi_u32 v0, v9, v0 +; CHECK-NEXT: v_cndmask_b32_e64 v2, 0, 1, vcc +; CHECK-NEXT: v_add_i32_e32 v2, vcc, v8, v2 +; CHECK-NEXT: v_add_i32_e32 v0, vcc, v0, v2 +; CHECK-NEXT: v_add_i32_e32 v1, vcc, v5, v1 +; CHECK-NEXT: v_addc_u32_e32 v0, vcc, v6, v0, vcc +; CHECK-NEXT: v_mul_lo_u32 v2, v4, v1 +; CHECK-NEXT: v_mul_lo_u32 v5, v3, v0 +; CHECK-NEXT: v_mul_hi_u32 v8, v3, v1 +; CHECK-NEXT: v_mul_hi_u32 v1, v4, v1 ; CHECK-NEXT: s_mov_b32 s6, 0x12d8fb -; CHECK-NEXT: v_add_i32_e32 v2, vcc, v2, v3 -; CHECK-NEXT: v_cndmask_b32_e64 v3, 0, 1, vcc ; CHECK-NEXT: v_add_i32_e32 v2, vcc, v2, v5 +; CHECK-NEXT: v_cndmask_b32_e64 v5, 0, 1, vcc +; CHECK-NEXT: v_add_i32_e32 v2, vcc, v2, v8 ; CHECK-NEXT: v_cndmask_b32_e64 v2, 0, 1, vcc -; CHECK-NEXT: v_mul_lo_u32 v5, v9, v1 -; CHECK-NEXT: v_add_i32_e32 v2, vcc, v3, v2 -; CHECK-NEXT: v_mul_hi_u32 v3, v4, v1 -; CHECK-NEXT: v_add_i32_e32 v0, vcc, v5, v0 +; CHECK-NEXT: v_mul_lo_u32 v8, v4, v0 +; CHECK-NEXT: v_add_i32_e32 v2, vcc, v5, v2 +; CHECK-NEXT: v_mul_hi_u32 v5, v3, v0 +; CHECK-NEXT: v_add_i32_e32 v1, vcc, v8, v1 +; CHECK-NEXT: v_cndmask_b32_e64 v8, 0, 1, vcc +; CHECK-NEXT: v_add_i32_e32 v1, vcc, v1, v5 ; CHECK-NEXT: v_cndmask_b32_e64 v5, 0, 1, vcc -; CHECK-NEXT: v_add_i32_e32 v0, vcc, v0, v3 -; CHECK-NEXT: v_cndmask_b32_e64 v3, 0, 1, vcc -; CHECK-NEXT: v_add_i32_e32 v3, vcc, v5, v3 -; CHECK-NEXT: v_add_i32_e32 v5, vcc, v0, v2 -; CHECK-NEXT: v_mul_hi_u32 v6, v9, v1 -; CHECK-NEXT: v_mad_u64_u32 v[0:1], s[4:5], s6, v5, 0 +; CHECK-NEXT: v_add_i32_e32 v5, vcc, v8, v5 +; CHECK-NEXT: v_add_i32_e32 v8, vcc, v1, v2 +; CHECK-NEXT: v_mul_hi_u32 v9, v4, v0 +; CHECK-NEXT: v_mad_u64_u32 v[0:1], s[4:5], s6, v8, 0 ; CHECK-NEXT: v_cndmask_b32_e64 v2, 0, 1, vcc -; CHECK-NEXT: v_add_i32_e32 v2, vcc, v3, v2 -; CHECK-NEXT: v_add_i32_e32 v3, vcc, v6, v2 -; CHECK-NEXT: v_mad_u64_u32 v[1:2], s[4:5], s6, v3, v[1:2] -; CHECK-NEXT: v_sub_i32_e32 v0, vcc, v4, v0 -; CHECK-NEXT: v_mad_u64_u32 v[1:2], s[4:5], 0, v5, v[1:2] +; CHECK-NEXT: v_add_i32_e32 v2, vcc, v5, v2 +; CHECK-NEXT: v_add_i32_e32 v5, vcc, v9, v2 +; CHECK-NEXT: v_mad_u64_u32 v[1:2], s[4:5], s6, v5, v[1:2] +; CHECK-NEXT: v_sub_i32_e32 v0, vcc, v3, v0 +; CHECK-NEXT: v_subb_u32_e64 v2, s[4:5], v4, v1, vcc +; CHECK-NEXT: v_sub_i32_e64 v1, s[4:5], v4, v1 ; CHECK-NEXT: v_mov_b32_e32 v6, 0x12d8fb -; CHECK-NEXT: s_bfe_i32 s6, -1, 0x10000 -; CHECK-NEXT: v_subb_u32_e64 v2, s[4:5], v9, v1, vcc -; CHECK-NEXT: v_sub_i32_e64 v1, s[4:5], v9, v1 ; CHECK-NEXT: v_subbrev_u32_e32 v1, vcc, 0, v1, vcc +; CHECK-NEXT: s_bfe_i32 s6, -1, 0x10000 ; CHECK-NEXT: v_cmp_ge_u32_e64 s[4:5], v0, v6 ; CHECK-NEXT: v_sub_i32_e32 v0, vcc, v0, v6 -; CHECK-NEXT: v_cndmask_b32_e64 v4, 0, -1, s[4:5] -; CHECK-NEXT: v_mov_b32_e32 v8, s6 +; CHECK-NEXT: v_cndmask_b32_e64 v3, 0, -1, s[4:5] +; CHECK-NEXT: v_mov_b32_e32 v4, s6 ; CHECK-NEXT: v_cmp_eq_u32_e64 s[4:5], 0, v2 ; CHECK-NEXT: v_subbrev_u32_e32 v1, vcc, 0, v1, vcc -; CHECK-NEXT: v_cndmask_b32_e64 v2, v8, v4, s[4:5] -; CHECK-NEXT: v_add_i32_e32 v4, vcc, 1, v5 -; CHECK-NEXT: v_addc_u32_e32 v8, vcc, 0, v3, vcc +; CHECK-NEXT: v_cndmask_b32_e64 v2, v4, v3, s[4:5] +; CHECK-NEXT: v_add_i32_e32 v3, vcc, 1, v8 +; CHECK-NEXT: v_addc_u32_e32 v4, vcc, 0, v5, vcc ; CHECK-NEXT: s_bfe_i32 s4, -1, 0x10000 ; CHECK-NEXT: v_cmp_ge_u32_e32 vcc, v0, v6 ; CHECK-NEXT: v_cndmask_b32_e64 v0, 0, -1, vcc ; CHECK-NEXT: v_mov_b32_e32 v6, s4 ; CHECK-NEXT: v_cmp_eq_u32_e32 vcc, 0, v1 ; CHECK-NEXT: v_cndmask_b32_e32 v0, v6, v0, vcc -; CHECK-NEXT: v_add_i32_e32 v1, vcc, 1, v4 -; CHECK-NEXT: v_addc_u32_e32 v6, vcc, 0, v8, vcc +; CHECK-NEXT: v_add_i32_e32 v1, vcc, 1, v3 +; CHECK-NEXT: v_addc_u32_e32 v6, vcc, 0, v4, vcc ; CHECK-NEXT: v_cmp_ne_u32_e32 vcc, 0, v0 -; CHECK-NEXT: v_cndmask_b32_e32 v0, v4, v1, vcc -; CHECK-NEXT: v_cndmask_b32_e32 v1, v8, v6, vcc +; CHECK-NEXT: v_cndmask_b32_e32 v0, v3, v1, vcc +; CHECK-NEXT: v_cndmask_b32_e32 v1, v4, v6, vcc ; CHECK-NEXT: v_cmp_ne_u32_e32 vcc, 0, v2 -; CHECK-NEXT: v_cndmask_b32_e32 v0, v5, v0, vcc -; CHECK-NEXT: v_cndmask_b32_e32 v1, v3, v1, vcc +; CHECK-NEXT: v_cndmask_b32_e32 v0, v8, v0, vcc +; CHECK-NEXT: v_cndmask_b32_e32 v1, v5, v1, vcc ; CHECK-NEXT: v_xor_b32_e32 v0, v0, v7 ; CHECK-NEXT: v_xor_b32_e32 v1, v1, v7 ; CHECK-NEXT: v_sub_i32_e32 v0, vcc, v0, v7 @@ -2101,88 +2096,87 @@ ; CGP-NEXT: v_add_i32_e32 v6, vcc, v9, v6 ; CGP-NEXT: v_add_i32_e32 v5, vcc, v5, v6 ; CGP-NEXT: v_add_i32_e32 v9, vcc, v7, v4 -; CGP-NEXT: v_addc_u32_e32 v8, vcc, v8, v5, vcc -; CGP-NEXT: v_mad_u64_u32 v[5:6], s[4:5], s6, v9, 0 -; CGP-NEXT: v_mov_b32_e32 v4, v6 -; CGP-NEXT: v_mad_u64_u32 v[6:7], s[4:5], s6, v8, v[4:5] -; CGP-NEXT: v_ashrrev_i32_e32 v4, 31, v1 -; CGP-NEXT: v_add_i32_e32 v0, vcc, v0, v4 -; CGP-NEXT: v_mad_u64_u32 v[6:7], s[4:5], -1, v9, v[6:7] -; CGP-NEXT: v_addc_u32_e32 v1, vcc, v1, v4, vcc -; CGP-NEXT: v_xor_b32_e32 v10, v0, v4 -; CGP-NEXT: v_mul_lo_u32 v0, v8, v5 -; CGP-NEXT: v_mul_lo_u32 v7, v9, v6 -; CGP-NEXT: v_xor_b32_e32 v11, v1, v4 -; CGP-NEXT: v_mul_hi_u32 v1, v9, v5 -; CGP-NEXT: v_mul_hi_u32 v5, v8, v5 -; CGP-NEXT: v_add_i32_e32 v0, vcc, v0, v7 -; CGP-NEXT: v_cndmask_b32_e64 v7, 0, 1, vcc -; CGP-NEXT: v_add_i32_e32 v0, vcc, v0, v1 -; CGP-NEXT: v_cndmask_b32_e64 v0, 0, 1, vcc -; CGP-NEXT: v_mul_lo_u32 v1, v8, v6 -; CGP-NEXT: v_add_i32_e32 v0, vcc, v7, v0 +; CGP-NEXT: v_mad_u64_u32 v[6:7], s[4:5], s6, v9, 0 +; CGP-NEXT: v_addc_u32_e32 v10, vcc, v8, v5, vcc +; CGP-NEXT: v_ashrrev_i32_e32 v5, 31, v1 +; CGP-NEXT: v_mov_b32_e32 v4, v7 +; CGP-NEXT: v_mad_u64_u32 v[7:8], s[4:5], s6, v10, v[4:5] +; CGP-NEXT: v_add_i32_e32 v4, vcc, v0, v5 +; CGP-NEXT: v_addc_u32_e32 v11, vcc, v1, v5, vcc +; CGP-NEXT: v_mad_u64_u32 v[0:1], s[4:5], -1, v9, v[7:8] +; CGP-NEXT: v_xor_b32_e32 v8, v4, v5 +; CGP-NEXT: v_mul_lo_u32 v1, v10, v6 +; CGP-NEXT: v_mul_lo_u32 v4, v9, v0 ; CGP-NEXT: v_mul_hi_u32 v7, v9, v6 -; CGP-NEXT: v_add_i32_e32 v1, vcc, v1, v5 -; CGP-NEXT: v_cndmask_b32_e64 v5, 0, 1, vcc +; CGP-NEXT: v_mul_hi_u32 v6, v10, v6 +; CGP-NEXT: v_xor_b32_e32 v11, v11, v5 +; CGP-NEXT: v_add_i32_e32 v1, vcc, v1, v4 +; CGP-NEXT: v_cndmask_b32_e64 v4, 0, 1, vcc ; CGP-NEXT: v_add_i32_e32 v1, vcc, v1, v7 -; CGP-NEXT: v_cndmask_b32_e64 v7, 0, 1, vcc -; CGP-NEXT: v_add_i32_e32 v5, vcc, v5, v7 -; CGP-NEXT: v_mul_hi_u32 v6, v8, v6 -; CGP-NEXT: v_add_i32_e32 v0, vcc, v1, v0 ; CGP-NEXT: v_cndmask_b32_e64 v1, 0, 1, vcc -; CGP-NEXT: v_add_i32_e32 v1, vcc, v5, v1 -; CGP-NEXT: v_add_i32_e32 v1, vcc, v6, v1 -; CGP-NEXT: v_add_i32_e32 v0, vcc, v9, v0 -; CGP-NEXT: v_addc_u32_e32 v1, vcc, v8, v1, vcc -; CGP-NEXT: v_mul_lo_u32 v5, v11, v0 -; CGP-NEXT: v_mul_lo_u32 v6, v10, v1 -; CGP-NEXT: v_mul_hi_u32 v7, v10, v0 -; CGP-NEXT: v_mul_hi_u32 v0, v11, v0 -; CGP-NEXT: v_add_i32_e32 v5, vcc, v5, v6 +; CGP-NEXT: v_mul_lo_u32 v7, v10, v0 +; CGP-NEXT: v_add_i32_e32 v1, vcc, v4, v1 +; CGP-NEXT: v_mul_hi_u32 v4, v9, v0 +; CGP-NEXT: v_add_i32_e32 v6, vcc, v7, v6 +; CGP-NEXT: v_cndmask_b32_e64 v7, 0, 1, vcc +; CGP-NEXT: v_add_i32_e32 v4, vcc, v6, v4 ; CGP-NEXT: v_cndmask_b32_e64 v6, 0, 1, vcc -; CGP-NEXT: v_add_i32_e32 v5, vcc, v5, v7 -; CGP-NEXT: v_cndmask_b32_e64 v5, 0, 1, vcc -; CGP-NEXT: v_mul_lo_u32 v7, v11, v1 -; CGP-NEXT: v_add_i32_e32 v5, vcc, v6, v5 -; CGP-NEXT: v_mul_hi_u32 v6, v10, v1 -; CGP-NEXT: v_add_i32_e32 v0, vcc, v7, v0 +; CGP-NEXT: v_add_i32_e32 v6, vcc, v7, v6 +; CGP-NEXT: v_mul_hi_u32 v0, v10, v0 +; CGP-NEXT: v_add_i32_e32 v1, vcc, v4, v1 +; CGP-NEXT: v_cndmask_b32_e64 v4, 0, 1, vcc +; CGP-NEXT: v_add_i32_e32 v4, vcc, v6, v4 +; CGP-NEXT: v_add_i32_e32 v0, vcc, v0, v4 +; CGP-NEXT: v_add_i32_e32 v1, vcc, v9, v1 +; CGP-NEXT: v_addc_u32_e32 v0, vcc, v10, v0, vcc +; CGP-NEXT: v_mul_lo_u32 v6, v11, v1 +; CGP-NEXT: v_mul_lo_u32 v7, v8, v0 +; CGP-NEXT: v_mul_hi_u32 v9, v8, v1 +; CGP-NEXT: v_mul_hi_u32 v1, v11, v1 +; CGP-NEXT: v_mul_hi_u32 v10, v11, v0 +; CGP-NEXT: v_add_i32_e32 v6, vcc, v6, v7 ; CGP-NEXT: v_cndmask_b32_e64 v7, 0, 1, vcc -; CGP-NEXT: v_add_i32_e32 v0, vcc, v0, v6 +; CGP-NEXT: v_add_i32_e32 v6, vcc, v6, v9 ; CGP-NEXT: v_cndmask_b32_e64 v6, 0, 1, vcc +; CGP-NEXT: v_mul_lo_u32 v9, v11, v0 ; CGP-NEXT: v_add_i32_e32 v6, vcc, v7, v6 -; CGP-NEXT: v_add_i32_e32 v8, vcc, v0, v5 -; CGP-NEXT: v_mul_hi_u32 v7, v11, v1 -; CGP-NEXT: v_mad_u64_u32 v[0:1], s[4:5], s7, v8, 0 -; CGP-NEXT: v_cndmask_b32_e64 v5, 0, 1, vcc -; CGP-NEXT: v_add_i32_e32 v5, vcc, v6, v5 -; CGP-NEXT: v_add_i32_e32 v9, vcc, v7, v5 -; CGP-NEXT: v_mad_u64_u32 v[6:7], s[4:5], s7, v9, v[1:2] -; CGP-NEXT: v_sub_i32_e32 v0, vcc, v10, v0 -; CGP-NEXT: v_mad_u64_u32 v[6:7], s[4:5], 0, v8, v[6:7] -; CGP-NEXT: v_mov_b32_e32 v5, 0x12d8fb -; CGP-NEXT: v_mov_b32_e32 v10, s8 +; CGP-NEXT: v_mul_hi_u32 v7, v8, v0 +; CGP-NEXT: v_add_i32_e32 v1, vcc, v9, v1 +; CGP-NEXT: v_cndmask_b32_e64 v9, 0, 1, vcc +; CGP-NEXT: v_add_i32_e32 v1, vcc, v1, v7 +; CGP-NEXT: v_cndmask_b32_e64 v7, 0, 1, vcc +; CGP-NEXT: v_add_i32_e32 v7, vcc, v9, v7 +; CGP-NEXT: v_add_i32_e32 v9, vcc, v1, v6 +; CGP-NEXT: v_mad_u64_u32 v[0:1], s[4:5], s7, v9, 0 +; CGP-NEXT: v_cndmask_b32_e64 v6, 0, 1, vcc +; CGP-NEXT: v_add_i32_e32 v6, vcc, v7, v6 +; CGP-NEXT: v_add_i32_e32 v10, vcc, v10, v6 +; CGP-NEXT: v_mad_u64_u32 v[6:7], s[4:5], s7, v10, v[1:2] +; CGP-NEXT: v_sub_i32_e32 v0, vcc, v8, v0 +; CGP-NEXT: v_mov_b32_e32 v4, 0x12d8fb ; CGP-NEXT: v_subb_u32_e64 v1, s[4:5], v11, v6, vcc ; CGP-NEXT: v_sub_i32_e64 v6, s[4:5], v11, v6 -; CGP-NEXT: v_cmp_ge_u32_e64 s[4:5], v0, v5 +; CGP-NEXT: v_cmp_ge_u32_e64 s[4:5], v0, v4 ; CGP-NEXT: v_cndmask_b32_e64 v7, 0, -1, s[4:5] ; CGP-NEXT: v_cmp_eq_u32_e64 s[4:5], 0, v1 ; CGP-NEXT: v_subbrev_u32_e32 v1, vcc, 0, v6, vcc ; CGP-NEXT: v_cvt_f32_u32_e32 v6, 0x12d8fb -; CGP-NEXT: v_sub_i32_e32 v0, vcc, v0, v5 -; CGP-NEXT: v_cndmask_b32_e64 v10, v10, v7, s[4:5] +; CGP-NEXT: v_mov_b32_e32 v8, s8 +; CGP-NEXT: v_sub_i32_e32 v0, vcc, v0, v4 +; CGP-NEXT: v_cndmask_b32_e64 v8, v8, v7, s[4:5] ; CGP-NEXT: v_subbrev_u32_e32 v7, vcc, 0, v1, vcc ; CGP-NEXT: v_cvt_f32_ubyte0_e32 v1, 0 ; CGP-NEXT: v_mac_f32_e32 v6, 0x4f800000, v1 ; CGP-NEXT: v_rcp_iflag_f32_e32 v1, v6 -; CGP-NEXT: v_add_i32_e32 v11, vcc, 1, v8 -; CGP-NEXT: v_addc_u32_e32 v12, vcc, 0, v9, vcc +; CGP-NEXT: v_add_i32_e32 v11, vcc, 1, v9 +; CGP-NEXT: v_addc_u32_e32 v12, vcc, 0, v10, vcc ; CGP-NEXT: v_mul_f32_e32 v1, 0x5f7ffffc, v1 ; CGP-NEXT: v_mul_f32_e32 v6, 0x2f800000, v1 ; CGP-NEXT: v_trunc_f32_e32 v6, v6 ; CGP-NEXT: v_mac_f32_e32 v1, 0xcf800000, v6 ; CGP-NEXT: v_cvt_u32_f32_e32 v13, v1 ; CGP-NEXT: s_bfe_i32 s4, -1, 0x10000 -; CGP-NEXT: v_cmp_ge_u32_e32 vcc, v0, v5 +; CGP-NEXT: v_cmp_ge_u32_e32 vcc, v0, v4 ; CGP-NEXT: v_mov_b32_e32 v15, s4 ; CGP-NEXT: v_mad_u64_u32 v[0:1], s[4:5], s6, v13, 0 ; CGP-NEXT: v_cvt_u32_f32_e32 v16, v6 @@ -2220,96 +2214,94 @@ ; CGP-NEXT: v_add_i32_e32 v11, vcc, v13, v0 ; CGP-NEXT: v_addc_u32_e32 v13, vcc, v16, v1, vcc ; CGP-NEXT: v_mad_u64_u32 v[0:1], s[4:5], s6, v11, 0 -; CGP-NEXT: v_cmp_ne_u32_e32 vcc, 0, v10 -; CGP-NEXT: v_cndmask_b32_e32 v8, v8, v7, vcc +; CGP-NEXT: v_cmp_ne_u32_e32 vcc, 0, v8 +; CGP-NEXT: v_cndmask_b32_e32 v6, v9, v7, vcc +; CGP-NEXT: v_xor_b32_e32 v9, v6, v5 ; CGP-NEXT: v_mad_u64_u32 v[6:7], s[4:5], s6, v13, v[1:2] -; CGP-NEXT: v_xor_b32_e32 v1, v8, v4 -; CGP-NEXT: v_ashrrev_i32_e32 v8, 31, v3 +; CGP-NEXT: v_cndmask_b32_e32 v8, v10, v12, vcc +; CGP-NEXT: v_xor_b32_e32 v1, v8, v5 ; CGP-NEXT: v_mad_u64_u32 v[6:7], s[4:5], -1, v11, v[6:7] -; CGP-NEXT: v_cndmask_b32_e32 v9, v9, v12, vcc +; CGP-NEXT: v_ashrrev_i32_e32 v8, 31, v3 ; CGP-NEXT: v_add_i32_e32 v2, vcc, v2, v8 ; CGP-NEXT: v_addc_u32_e32 v3, vcc, v3, v8, vcc -; CGP-NEXT: v_xor_b32_e32 v10, v2, v8 +; CGP-NEXT: v_xor_b32_e32 v7, v2, v8 ; CGP-NEXT: v_mul_lo_u32 v2, v13, v0 -; CGP-NEXT: v_mul_lo_u32 v7, v11, v6 +; CGP-NEXT: v_mul_lo_u32 v10, v11, v6 ; CGP-NEXT: v_xor_b32_e32 v12, v3, v8 ; CGP-NEXT: v_mul_hi_u32 v3, v11, v0 ; CGP-NEXT: v_mul_hi_u32 v0, v13, v0 -; CGP-NEXT: v_add_i32_e32 v2, vcc, v2, v7 -; CGP-NEXT: v_cndmask_b32_e64 v7, 0, 1, vcc +; CGP-NEXT: v_add_i32_e32 v2, vcc, v2, v10 +; CGP-NEXT: v_cndmask_b32_e64 v10, 0, 1, vcc ; CGP-NEXT: v_add_i32_e32 v2, vcc, v2, v3 ; CGP-NEXT: v_cndmask_b32_e64 v2, 0, 1, vcc ; CGP-NEXT: v_mul_lo_u32 v3, v13, v6 -; CGP-NEXT: v_add_i32_e32 v2, vcc, v7, v2 -; CGP-NEXT: v_mul_hi_u32 v7, v11, v6 +; CGP-NEXT: v_add_i32_e32 v2, vcc, v10, v2 +; CGP-NEXT: v_mul_hi_u32 v10, v11, v6 ; CGP-NEXT: v_add_i32_e32 v0, vcc, v3, v0 ; CGP-NEXT: v_cndmask_b32_e64 v3, 0, 1, vcc -; CGP-NEXT: v_add_i32_e32 v0, vcc, v0, v7 -; CGP-NEXT: v_cndmask_b32_e64 v7, 0, 1, vcc -; CGP-NEXT: v_add_i32_e32 v3, vcc, v3, v7 +; CGP-NEXT: v_add_i32_e32 v0, vcc, v0, v10 +; CGP-NEXT: v_cndmask_b32_e64 v10, 0, 1, vcc +; CGP-NEXT: v_add_i32_e32 v3, vcc, v3, v10 ; CGP-NEXT: v_mul_hi_u32 v6, v13, v6 ; CGP-NEXT: v_add_i32_e32 v0, vcc, v0, v2 ; CGP-NEXT: v_cndmask_b32_e64 v2, 0, 1, vcc ; CGP-NEXT: v_add_i32_e32 v2, vcc, v3, v2 ; CGP-NEXT: v_add_i32_e32 v2, vcc, v6, v2 -; CGP-NEXT: v_add_i32_e32 v0, vcc, v11, v0 +; CGP-NEXT: v_add_i32_e32 v3, vcc, v11, v0 ; CGP-NEXT: v_addc_u32_e32 v2, vcc, v13, v2, vcc -; CGP-NEXT: v_mul_lo_u32 v3, v12, v0 -; CGP-NEXT: v_mul_lo_u32 v6, v10, v2 -; CGP-NEXT: v_mul_hi_u32 v7, v10, v0 -; CGP-NEXT: v_mul_hi_u32 v0, v12, v0 -; CGP-NEXT: v_xor_b32_e32 v9, v9, v4 -; CGP-NEXT: v_add_i32_e32 v3, vcc, v3, v6 -; CGP-NEXT: v_cndmask_b32_e64 v6, 0, 1, vcc -; CGP-NEXT: v_add_i32_e32 v3, vcc, v3, v7 -; CGP-NEXT: v_cndmask_b32_e64 v3, 0, 1, vcc -; CGP-NEXT: v_mul_lo_u32 v7, v12, v2 +; CGP-NEXT: v_mul_lo_u32 v6, v12, v3 +; CGP-NEXT: v_mul_lo_u32 v10, v7, v2 +; CGP-NEXT: v_sub_i32_e32 v0, vcc, v9, v5 +; CGP-NEXT: v_subb_u32_e32 v1, vcc, v1, v5, vcc +; CGP-NEXT: v_mul_hi_u32 v5, v7, v3 +; CGP-NEXT: v_add_i32_e32 v6, vcc, v6, v10 +; CGP-NEXT: v_cndmask_b32_e64 v9, 0, 1, vcc +; CGP-NEXT: v_add_i32_e32 v5, vcc, v6, v5 +; CGP-NEXT: v_cndmask_b32_e64 v5, 0, 1, vcc +; CGP-NEXT: v_mul_lo_u32 v6, v12, v2 +; CGP-NEXT: v_mul_hi_u32 v3, v12, v3 +; CGP-NEXT: v_add_i32_e32 v5, vcc, v9, v5 +; CGP-NEXT: v_mul_hi_u32 v9, v7, v2 ; CGP-NEXT: v_add_i32_e32 v3, vcc, v6, v3 -; CGP-NEXT: v_mul_hi_u32 v6, v10, v2 -; CGP-NEXT: v_add_i32_e32 v0, vcc, v7, v0 -; CGP-NEXT: v_cndmask_b32_e64 v7, 0, 1, vcc -; CGP-NEXT: v_add_i32_e32 v0, vcc, v0, v6 ; CGP-NEXT: v_cndmask_b32_e64 v6, 0, 1, vcc -; CGP-NEXT: v_add_i32_e32 v6, vcc, v7, v6 -; CGP-NEXT: v_add_i32_e32 v11, vcc, v0, v3 -; CGP-NEXT: v_mul_hi_u32 v7, v12, v2 -; CGP-NEXT: v_mad_u64_u32 v[2:3], s[4:5], s7, v11, 0 -; CGP-NEXT: v_cndmask_b32_e64 v0, 0, 1, vcc -; CGP-NEXT: v_add_i32_e32 v0, vcc, v6, v0 -; CGP-NEXT: v_add_i32_e32 v13, vcc, v7, v0 -; CGP-NEXT: v_mov_b32_e32 v0, v3 -; CGP-NEXT: v_mad_u64_u32 v[6:7], s[4:5], s7, v13, v[0:1] -; CGP-NEXT: v_sub_i32_e32 v0, vcc, v1, v4 -; CGP-NEXT: v_subb_u32_e32 v1, vcc, v9, v4, vcc -; CGP-NEXT: v_mad_u64_u32 v[3:4], s[4:5], 0, v11, v[6:7] -; CGP-NEXT: v_sub_i32_e32 v2, vcc, v10, v2 -; CGP-NEXT: v_subb_u32_e64 v4, s[4:5], v12, v3, vcc -; CGP-NEXT: v_sub_i32_e64 v3, s[4:5], v12, v3 -; CGP-NEXT: v_subbrev_u32_e32 v3, vcc, 0, v3, vcc +; CGP-NEXT: v_add_i32_e32 v3, vcc, v3, v9 +; CGP-NEXT: v_cndmask_b32_e64 v9, 0, 1, vcc +; CGP-NEXT: v_add_i32_e32 v6, vcc, v6, v9 +; CGP-NEXT: v_add_i32_e32 v9, vcc, v3, v5 +; CGP-NEXT: v_mul_hi_u32 v10, v12, v2 +; CGP-NEXT: v_mad_u64_u32 v[2:3], s[4:5], s7, v9, 0 +; CGP-NEXT: v_cndmask_b32_e64 v5, 0, 1, vcc +; CGP-NEXT: v_add_i32_e32 v5, vcc, v6, v5 +; CGP-NEXT: v_add_i32_e32 v10, vcc, v10, v5 +; CGP-NEXT: v_mad_u64_u32 v[5:6], s[4:5], s7, v10, v[3:4] +; CGP-NEXT: v_sub_i32_e32 v2, vcc, v7, v2 +; CGP-NEXT: v_subb_u32_e64 v3, s[4:5], v12, v5, vcc +; CGP-NEXT: v_sub_i32_e64 v5, s[4:5], v12, v5 +; CGP-NEXT: v_subbrev_u32_e32 v5, vcc, 0, v5, vcc ; CGP-NEXT: s_bfe_i32 s6, -1, 0x10000 -; CGP-NEXT: v_cmp_ge_u32_e64 s[4:5], v2, v5 -; CGP-NEXT: v_sub_i32_e32 v2, vcc, v2, v5 +; CGP-NEXT: v_cmp_ge_u32_e64 s[4:5], v2, v4 +; CGP-NEXT: v_sub_i32_e32 v2, vcc, v2, v4 ; CGP-NEXT: v_cndmask_b32_e64 v6, 0, -1, s[4:5] ; CGP-NEXT: v_mov_b32_e32 v7, s6 -; CGP-NEXT: v_cmp_eq_u32_e64 s[4:5], 0, v4 -; CGP-NEXT: v_subbrev_u32_e32 v3, vcc, 0, v3, vcc -; CGP-NEXT: v_cndmask_b32_e64 v4, v7, v6, s[4:5] -; CGP-NEXT: v_add_i32_e32 v6, vcc, 1, v11 -; CGP-NEXT: v_addc_u32_e32 v7, vcc, 0, v13, vcc +; CGP-NEXT: v_cmp_eq_u32_e64 s[4:5], 0, v3 +; CGP-NEXT: v_subbrev_u32_e32 v5, vcc, 0, v5, vcc +; CGP-NEXT: v_cndmask_b32_e64 v3, v7, v6, s[4:5] +; CGP-NEXT: v_add_i32_e32 v6, vcc, 1, v9 +; CGP-NEXT: v_addc_u32_e32 v7, vcc, 0, v10, vcc ; CGP-NEXT: s_bfe_i32 s4, -1, 0x10000 -; CGP-NEXT: v_cmp_ge_u32_e32 vcc, v2, v5 +; CGP-NEXT: v_cmp_ge_u32_e32 vcc, v2, v4 ; CGP-NEXT: v_cndmask_b32_e64 v2, 0, -1, vcc -; CGP-NEXT: v_mov_b32_e32 v5, s4 -; CGP-NEXT: v_cmp_eq_u32_e32 vcc, 0, v3 -; CGP-NEXT: v_cndmask_b32_e32 v2, v5, v2, vcc -; CGP-NEXT: v_add_i32_e32 v3, vcc, 1, v6 +; CGP-NEXT: v_mov_b32_e32 v4, s4 +; CGP-NEXT: v_cmp_eq_u32_e32 vcc, 0, v5 +; CGP-NEXT: v_cndmask_b32_e32 v2, v4, v2, vcc +; CGP-NEXT: v_add_i32_e32 v4, vcc, 1, v6 ; CGP-NEXT: v_addc_u32_e32 v5, vcc, 0, v7, vcc ; CGP-NEXT: v_cmp_ne_u32_e32 vcc, 0, v2 -; CGP-NEXT: v_cndmask_b32_e32 v2, v6, v3, vcc -; CGP-NEXT: v_cndmask_b32_e32 v3, v7, v5, vcc -; CGP-NEXT: v_cmp_ne_u32_e32 vcc, 0, v4 -; CGP-NEXT: v_cndmask_b32_e32 v2, v11, v2, vcc -; CGP-NEXT: v_cndmask_b32_e32 v3, v13, v3, vcc +; CGP-NEXT: v_cndmask_b32_e32 v2, v6, v4, vcc +; CGP-NEXT: v_cndmask_b32_e32 v4, v7, v5, vcc +; CGP-NEXT: v_cmp_ne_u32_e32 vcc, 0, v3 +; CGP-NEXT: v_cndmask_b32_e32 v2, v9, v2, vcc +; CGP-NEXT: v_cndmask_b32_e32 v3, v10, v4, vcc ; CGP-NEXT: v_xor_b32_e32 v2, v2, v8 ; CGP-NEXT: v_xor_b32_e32 v3, v3, v8 ; CGP-NEXT: v_sub_i32_e32 v2, vcc, v2, v8 diff --git a/llvm/test/CodeGen/AMDGPU/GlobalISel/srem.i64.ll b/llvm/test/CodeGen/AMDGPU/GlobalISel/srem.i64.ll --- a/llvm/test/CodeGen/AMDGPU/GlobalISel/srem.i64.ll +++ b/llvm/test/CodeGen/AMDGPU/GlobalISel/srem.i64.ll @@ -1017,86 +1017,85 @@ ; CHECK-NEXT: v_addc_u32_e32 v6, vcc, v6, v3, vcc ; CHECK-NEXT: v_mad_u64_u32 v[2:3], s[4:5], s6, v5, 0 ; CHECK-NEXT: v_ashrrev_i32_e32 v7, 31, v1 -; CHECK-NEXT: v_add_i32_e32 v0, vcc, v0, v7 +; CHECK-NEXT: v_add_i32_e32 v8, vcc, v0, v7 ; CHECK-NEXT: v_mad_u64_u32 v[3:4], s[4:5], s6, v6, v[3:4] -; CHECK-NEXT: v_addc_u32_e32 v1, vcc, v1, v7, vcc -; CHECK-NEXT: v_mad_u64_u32 v[3:4], s[4:5], -1, v5, v[3:4] -; CHECK-NEXT: v_xor_b32_e32 v4, v0, v7 -; CHECK-NEXT: v_mul_lo_u32 v0, v6, v2 -; CHECK-NEXT: v_mul_lo_u32 v8, v5, v3 -; CHECK-NEXT: v_xor_b32_e32 v9, v1, v7 -; CHECK-NEXT: v_mul_hi_u32 v1, v5, v2 +; CHECK-NEXT: v_addc_u32_e32 v9, vcc, v1, v7, vcc +; CHECK-NEXT: v_mad_u64_u32 v[0:1], s[4:5], -1, v5, v[3:4] +; CHECK-NEXT: v_xor_b32_e32 v3, v8, v7 +; CHECK-NEXT: v_mul_lo_u32 v1, v6, v2 +; CHECK-NEXT: v_mul_lo_u32 v8, v5, v0 +; CHECK-NEXT: v_xor_b32_e32 v4, v9, v7 +; CHECK-NEXT: v_mul_hi_u32 v9, v5, v2 ; CHECK-NEXT: v_mul_hi_u32 v2, v6, v2 -; CHECK-NEXT: v_add_i32_e32 v0, vcc, v0, v8 -; CHECK-NEXT: v_cndmask_b32_e64 v8, 0, 1, vcc -; CHECK-NEXT: v_add_i32_e32 v0, vcc, v0, v1 -; CHECK-NEXT: v_cndmask_b32_e64 v0, 0, 1, vcc -; CHECK-NEXT: v_mul_lo_u32 v1, v6, v3 -; CHECK-NEXT: v_add_i32_e32 v0, vcc, v8, v0 -; CHECK-NEXT: v_mul_hi_u32 v8, v5, v3 -; CHECK-NEXT: v_add_i32_e32 v1, vcc, v1, v2 -; CHECK-NEXT: v_cndmask_b32_e64 v2, 0, 1, vcc ; CHECK-NEXT: v_add_i32_e32 v1, vcc, v1, v8 ; CHECK-NEXT: v_cndmask_b32_e64 v8, 0, 1, vcc -; CHECK-NEXT: v_add_i32_e32 v2, vcc, v2, v8 -; CHECK-NEXT: v_mul_hi_u32 v3, v6, v3 -; CHECK-NEXT: v_add_i32_e32 v0, vcc, v1, v0 +; CHECK-NEXT: v_add_i32_e32 v1, vcc, v1, v9 ; CHECK-NEXT: v_cndmask_b32_e64 v1, 0, 1, vcc +; CHECK-NEXT: v_mul_lo_u32 v9, v6, v0 +; CHECK-NEXT: v_add_i32_e32 v1, vcc, v8, v1 +; CHECK-NEXT: v_mul_hi_u32 v8, v5, v0 +; CHECK-NEXT: v_add_i32_e32 v2, vcc, v9, v2 +; CHECK-NEXT: v_cndmask_b32_e64 v9, 0, 1, vcc +; CHECK-NEXT: v_add_i32_e32 v2, vcc, v2, v8 +; CHECK-NEXT: v_cndmask_b32_e64 v8, 0, 1, vcc +; CHECK-NEXT: v_add_i32_e32 v8, vcc, v9, v8 +; CHECK-NEXT: v_mul_hi_u32 v0, v6, v0 ; CHECK-NEXT: v_add_i32_e32 v1, vcc, v2, v1 -; CHECK-NEXT: v_add_i32_e32 v1, vcc, v3, v1 -; CHECK-NEXT: v_add_i32_e32 v0, vcc, v5, v0 -; CHECK-NEXT: v_addc_u32_e32 v1, vcc, v6, v1, vcc -; CHECK-NEXT: v_mul_lo_u32 v2, v9, v0 -; CHECK-NEXT: v_mul_lo_u32 v3, v4, v1 -; CHECK-NEXT: v_mul_hi_u32 v5, v4, v0 -; CHECK-NEXT: v_mul_hi_u32 v0, v9, v0 +; CHECK-NEXT: v_cndmask_b32_e64 v2, 0, 1, vcc +; CHECK-NEXT: v_add_i32_e32 v2, vcc, v8, v2 +; CHECK-NEXT: v_add_i32_e32 v0, vcc, v0, v2 +; CHECK-NEXT: v_add_i32_e32 v1, vcc, v5, v1 +; CHECK-NEXT: v_addc_u32_e32 v0, vcc, v6, v0, vcc +; CHECK-NEXT: v_mul_lo_u32 v2, v4, v1 +; CHECK-NEXT: v_mul_lo_u32 v5, v3, v0 +; CHECK-NEXT: v_mul_hi_u32 v8, v3, v1 +; CHECK-NEXT: v_mul_hi_u32 v1, v4, v1 ; CHECK-NEXT: s_movk_i32 s6, 0x1000 -; CHECK-NEXT: v_add_i32_e32 v2, vcc, v2, v3 -; CHECK-NEXT: v_cndmask_b32_e64 v3, 0, 1, vcc ; CHECK-NEXT: v_add_i32_e32 v2, vcc, v2, v5 +; CHECK-NEXT: v_cndmask_b32_e64 v5, 0, 1, vcc +; CHECK-NEXT: v_add_i32_e32 v2, vcc, v2, v8 ; CHECK-NEXT: v_cndmask_b32_e64 v2, 0, 1, vcc -; CHECK-NEXT: v_mul_lo_u32 v5, v9, v1 -; CHECK-NEXT: v_add_i32_e32 v2, vcc, v3, v2 -; CHECK-NEXT: v_mul_hi_u32 v3, v4, v1 -; CHECK-NEXT: v_add_i32_e32 v0, vcc, v5, v0 +; CHECK-NEXT: v_mul_lo_u32 v8, v4, v0 +; CHECK-NEXT: v_add_i32_e32 v2, vcc, v5, v2 +; CHECK-NEXT: v_mul_hi_u32 v5, v3, v0 +; CHECK-NEXT: v_add_i32_e32 v1, vcc, v8, v1 +; CHECK-NEXT: v_cndmask_b32_e64 v8, 0, 1, vcc +; CHECK-NEXT: v_add_i32_e32 v1, vcc, v1, v5 ; CHECK-NEXT: v_cndmask_b32_e64 v5, 0, 1, vcc -; CHECK-NEXT: v_add_i32_e32 v0, vcc, v0, v3 -; CHECK-NEXT: v_cndmask_b32_e64 v3, 0, 1, vcc -; CHECK-NEXT: v_add_i32_e32 v3, vcc, v5, v3 -; CHECK-NEXT: v_add_i32_e32 v5, vcc, v0, v2 -; CHECK-NEXT: v_mul_hi_u32 v6, v9, v1 -; CHECK-NEXT: v_mad_u64_u32 v[0:1], s[4:5], s6, v5, 0 +; CHECK-NEXT: v_add_i32_e32 v5, vcc, v8, v5 +; CHECK-NEXT: v_add_i32_e32 v1, vcc, v1, v2 +; CHECK-NEXT: v_mul_hi_u32 v8, v4, v0 +; CHECK-NEXT: v_mad_u64_u32 v[0:1], s[4:5], s6, v1, 0 ; CHECK-NEXT: v_cndmask_b32_e64 v2, 0, 1, vcc -; CHECK-NEXT: v_add_i32_e32 v2, vcc, v3, v2 -; CHECK-NEXT: v_add_i32_e32 v2, vcc, v6, v2 +; CHECK-NEXT: v_add_i32_e32 v2, vcc, v5, v2 +; CHECK-NEXT: v_add_i32_e32 v2, vcc, v8, v2 ; CHECK-NEXT: v_mad_u64_u32 v[1:2], s[4:5], s6, v2, v[1:2] -; CHECK-NEXT: v_sub_i32_e32 v0, vcc, v4, v0 -; CHECK-NEXT: v_mad_u64_u32 v[1:2], s[4:5], 0, v5, v[1:2] -; CHECK-NEXT: v_mov_b32_e32 v3, 0x1000 +; CHECK-NEXT: v_sub_i32_e32 v0, vcc, v3, v0 +; CHECK-NEXT: v_mov_b32_e32 v6, 0x1000 +; CHECK-NEXT: v_subb_u32_e64 v2, s[4:5], v4, v1, vcc +; CHECK-NEXT: v_sub_i32_e64 v1, s[4:5], v4, v1 ; CHECK-NEXT: s_bfe_i32 s6, -1, 0x10000 -; CHECK-NEXT: v_subb_u32_e64 v2, s[4:5], v9, v1, vcc -; CHECK-NEXT: v_sub_i32_e64 v1, s[4:5], v9, v1 -; CHECK-NEXT: v_cmp_ge_u32_e64 s[4:5], v0, v3 -; CHECK-NEXT: v_cndmask_b32_e64 v4, 0, -1, s[4:5] -; CHECK-NEXT: v_mov_b32_e32 v5, s6 +; CHECK-NEXT: v_cmp_ge_u32_e64 s[4:5], v0, v6 +; CHECK-NEXT: v_cndmask_b32_e64 v3, 0, -1, s[4:5] +; CHECK-NEXT: v_mov_b32_e32 v4, s6 ; CHECK-NEXT: v_cmp_eq_u32_e64 s[4:5], 0, v2 ; CHECK-NEXT: v_subbrev_u32_e32 v1, vcc, 0, v1, vcc -; CHECK-NEXT: v_cndmask_b32_e64 v4, v5, v4, s[4:5] -; CHECK-NEXT: v_sub_i32_e32 v5, vcc, v0, v3 +; CHECK-NEXT: v_cndmask_b32_e64 v3, v4, v3, s[4:5] +; CHECK-NEXT: v_sub_i32_e32 v4, vcc, v0, v6 ; CHECK-NEXT: v_subbrev_u32_e32 v1, vcc, 0, v1, vcc ; CHECK-NEXT: s_bfe_i32 s4, -1, 0x10000 -; CHECK-NEXT: v_cmp_ge_u32_e32 vcc, v5, v3 -; CHECK-NEXT: v_cndmask_b32_e64 v6, 0, -1, vcc +; CHECK-NEXT: v_cmp_ge_u32_e32 vcc, v4, v6 +; CHECK-NEXT: v_cndmask_b32_e64 v5, 0, -1, vcc ; CHECK-NEXT: v_mov_b32_e32 v8, s4 ; CHECK-NEXT: v_cmp_eq_u32_e32 vcc, 0, v1 -; CHECK-NEXT: v_cndmask_b32_e32 v6, v8, v6, vcc -; CHECK-NEXT: v_sub_i32_e32 v3, vcc, v5, v3 +; CHECK-NEXT: v_cndmask_b32_e32 v5, v8, v5, vcc +; CHECK-NEXT: v_sub_i32_e32 v6, vcc, v4, v6 ; CHECK-NEXT: v_subbrev_u32_e32 v8, vcc, 0, v1, vcc -; CHECK-NEXT: v_cmp_ne_u32_e32 vcc, 0, v6 -; CHECK-NEXT: v_cndmask_b32_e32 v3, v5, v3, vcc +; CHECK-NEXT: v_cmp_ne_u32_e32 vcc, 0, v5 +; CHECK-NEXT: v_cndmask_b32_e32 v4, v4, v6, vcc ; CHECK-NEXT: v_cndmask_b32_e32 v1, v1, v8, vcc -; CHECK-NEXT: v_cmp_ne_u32_e32 vcc, 0, v4 -; CHECK-NEXT: v_cndmask_b32_e32 v0, v0, v3, vcc +; CHECK-NEXT: v_cmp_ne_u32_e32 vcc, 0, v3 +; CHECK-NEXT: v_cndmask_b32_e32 v0, v0, v4, vcc ; CHECK-NEXT: v_cndmask_b32_e32 v1, v2, v1, vcc ; CHECK-NEXT: v_xor_b32_e32 v0, v0, v7 ; CHECK-NEXT: v_xor_b32_e32 v1, v1, v7 @@ -1415,68 +1414,67 @@ ; CGP-NEXT: v_add_i32_e32 v6, vcc, v9, v6 ; CGP-NEXT: v_add_i32_e32 v5, vcc, v5, v6 ; CGP-NEXT: v_add_i32_e32 v9, vcc, v7, v4 -; CGP-NEXT: v_addc_u32_e32 v8, vcc, v8, v5, vcc -; CGP-NEXT: v_mad_u64_u32 v[5:6], s[4:5], s6, v9, 0 -; CGP-NEXT: v_mov_b32_e32 v4, v6 -; CGP-NEXT: v_mad_u64_u32 v[6:7], s[4:5], s6, v8, v[4:5] -; CGP-NEXT: v_ashrrev_i32_e32 v4, 31, v1 -; CGP-NEXT: v_add_i32_e32 v0, vcc, v0, v4 -; CGP-NEXT: v_mad_u64_u32 v[6:7], s[4:5], -1, v9, v[6:7] -; CGP-NEXT: v_addc_u32_e32 v1, vcc, v1, v4, vcc -; CGP-NEXT: v_xor_b32_e32 v10, v0, v4 -; CGP-NEXT: v_mul_lo_u32 v0, v8, v5 -; CGP-NEXT: v_mul_lo_u32 v7, v9, v6 -; CGP-NEXT: v_xor_b32_e32 v11, v1, v4 -; CGP-NEXT: v_mul_hi_u32 v1, v9, v5 -; CGP-NEXT: v_mul_hi_u32 v5, v8, v5 -; CGP-NEXT: v_add_i32_e32 v0, vcc, v0, v7 -; CGP-NEXT: v_cndmask_b32_e64 v7, 0, 1, vcc -; CGP-NEXT: v_add_i32_e32 v0, vcc, v0, v1 -; CGP-NEXT: v_cndmask_b32_e64 v0, 0, 1, vcc -; CGP-NEXT: v_mul_lo_u32 v1, v8, v6 -; CGP-NEXT: v_add_i32_e32 v0, vcc, v7, v0 +; CGP-NEXT: v_mad_u64_u32 v[6:7], s[4:5], s6, v9, 0 +; CGP-NEXT: v_addc_u32_e32 v10, vcc, v8, v5, vcc +; CGP-NEXT: v_ashrrev_i32_e32 v5, 31, v1 +; CGP-NEXT: v_mov_b32_e32 v4, v7 +; CGP-NEXT: v_mad_u64_u32 v[7:8], s[4:5], s6, v10, v[4:5] +; CGP-NEXT: v_add_i32_e32 v4, vcc, v0, v5 +; CGP-NEXT: v_addc_u32_e32 v11, vcc, v1, v5, vcc +; CGP-NEXT: v_mad_u64_u32 v[0:1], s[4:5], -1, v9, v[7:8] +; CGP-NEXT: v_xor_b32_e32 v8, v4, v5 +; CGP-NEXT: v_mul_lo_u32 v1, v10, v6 +; CGP-NEXT: v_mul_lo_u32 v4, v9, v0 ; CGP-NEXT: v_mul_hi_u32 v7, v9, v6 -; CGP-NEXT: v_add_i32_e32 v1, vcc, v1, v5 -; CGP-NEXT: v_cndmask_b32_e64 v5, 0, 1, vcc +; CGP-NEXT: v_mul_hi_u32 v6, v10, v6 +; CGP-NEXT: v_xor_b32_e32 v11, v11, v5 +; CGP-NEXT: v_add_i32_e32 v1, vcc, v1, v4 +; CGP-NEXT: v_cndmask_b32_e64 v4, 0, 1, vcc ; CGP-NEXT: v_add_i32_e32 v1, vcc, v1, v7 -; CGP-NEXT: v_cndmask_b32_e64 v7, 0, 1, vcc -; CGP-NEXT: v_add_i32_e32 v5, vcc, v5, v7 -; CGP-NEXT: v_mul_hi_u32 v6, v8, v6 -; CGP-NEXT: v_add_i32_e32 v0, vcc, v1, v0 ; CGP-NEXT: v_cndmask_b32_e64 v1, 0, 1, vcc -; CGP-NEXT: v_add_i32_e32 v1, vcc, v5, v1 -; CGP-NEXT: v_add_i32_e32 v1, vcc, v6, v1 -; CGP-NEXT: v_add_i32_e32 v0, vcc, v9, v0 -; CGP-NEXT: v_addc_u32_e32 v1, vcc, v8, v1, vcc -; CGP-NEXT: v_mul_lo_u32 v5, v11, v0 -; CGP-NEXT: v_mul_lo_u32 v6, v10, v1 -; CGP-NEXT: v_mul_hi_u32 v7, v10, v0 -; CGP-NEXT: v_mul_hi_u32 v0, v11, v0 -; CGP-NEXT: v_add_i32_e32 v5, vcc, v5, v6 +; CGP-NEXT: v_mul_lo_u32 v7, v10, v0 +; CGP-NEXT: v_add_i32_e32 v1, vcc, v4, v1 +; CGP-NEXT: v_mul_hi_u32 v4, v9, v0 +; CGP-NEXT: v_add_i32_e32 v6, vcc, v7, v6 +; CGP-NEXT: v_cndmask_b32_e64 v7, 0, 1, vcc +; CGP-NEXT: v_add_i32_e32 v4, vcc, v6, v4 ; CGP-NEXT: v_cndmask_b32_e64 v6, 0, 1, vcc -; CGP-NEXT: v_add_i32_e32 v5, vcc, v5, v7 -; CGP-NEXT: v_cndmask_b32_e64 v5, 0, 1, vcc -; CGP-NEXT: v_mul_lo_u32 v7, v11, v1 -; CGP-NEXT: v_add_i32_e32 v5, vcc, v6, v5 -; CGP-NEXT: v_mul_hi_u32 v6, v10, v1 -; CGP-NEXT: v_add_i32_e32 v0, vcc, v7, v0 +; CGP-NEXT: v_add_i32_e32 v6, vcc, v7, v6 +; CGP-NEXT: v_mul_hi_u32 v0, v10, v0 +; CGP-NEXT: v_add_i32_e32 v1, vcc, v4, v1 +; CGP-NEXT: v_cndmask_b32_e64 v4, 0, 1, vcc +; CGP-NEXT: v_add_i32_e32 v4, vcc, v6, v4 +; CGP-NEXT: v_add_i32_e32 v0, vcc, v0, v4 +; CGP-NEXT: v_add_i32_e32 v1, vcc, v9, v1 +; CGP-NEXT: v_addc_u32_e32 v0, vcc, v10, v0, vcc +; CGP-NEXT: v_mul_lo_u32 v6, v11, v1 +; CGP-NEXT: v_mul_lo_u32 v7, v8, v0 +; CGP-NEXT: v_mul_hi_u32 v9, v8, v1 +; CGP-NEXT: v_mul_hi_u32 v1, v11, v1 +; CGP-NEXT: v_mov_b32_e32 v4, 0x1000 +; CGP-NEXT: v_add_i32_e32 v6, vcc, v6, v7 ; CGP-NEXT: v_cndmask_b32_e64 v7, 0, 1, vcc -; CGP-NEXT: v_add_i32_e32 v0, vcc, v0, v6 +; CGP-NEXT: v_add_i32_e32 v6, vcc, v6, v9 ; CGP-NEXT: v_cndmask_b32_e64 v6, 0, 1, vcc +; CGP-NEXT: v_mul_lo_u32 v9, v11, v0 ; CGP-NEXT: v_add_i32_e32 v6, vcc, v7, v6 -; CGP-NEXT: v_add_i32_e32 v8, vcc, v0, v5 -; CGP-NEXT: v_mul_hi_u32 v7, v11, v1 -; CGP-NEXT: v_mad_u64_u32 v[0:1], s[4:5], s7, v8, 0 -; CGP-NEXT: v_cndmask_b32_e64 v5, 0, 1, vcc -; CGP-NEXT: v_add_i32_e32 v5, vcc, v6, v5 -; CGP-NEXT: v_add_i32_e32 v5, vcc, v7, v5 -; CGP-NEXT: v_mad_u64_u32 v[6:7], s[4:5], s7, v5, v[1:2] -; CGP-NEXT: v_mov_b32_e32 v5, 0x1000 -; CGP-NEXT: v_mad_u64_u32 v[6:7], s[4:5], 0, v8, v[6:7] -; CGP-NEXT: v_sub_i32_e32 v8, vcc, v10, v0 +; CGP-NEXT: v_mul_hi_u32 v7, v8, v0 +; CGP-NEXT: v_add_i32_e32 v1, vcc, v9, v1 +; CGP-NEXT: v_cndmask_b32_e64 v9, 0, 1, vcc +; CGP-NEXT: v_add_i32_e32 v1, vcc, v1, v7 +; CGP-NEXT: v_cndmask_b32_e64 v7, 0, 1, vcc +; CGP-NEXT: v_add_i32_e32 v7, vcc, v9, v7 +; CGP-NEXT: v_add_i32_e32 v1, vcc, v1, v6 +; CGP-NEXT: v_mul_hi_u32 v9, v11, v0 +; CGP-NEXT: v_mad_u64_u32 v[0:1], s[4:5], s7, v1, 0 +; CGP-NEXT: v_cndmask_b32_e64 v6, 0, 1, vcc +; CGP-NEXT: v_add_i32_e32 v6, vcc, v7, v6 +; CGP-NEXT: v_add_i32_e32 v6, vcc, v9, v6 +; CGP-NEXT: v_mad_u64_u32 v[6:7], s[4:5], s7, v6, v[1:2] +; CGP-NEXT: v_sub_i32_e32 v8, vcc, v8, v0 ; CGP-NEXT: v_subb_u32_e64 v9, s[4:5], v11, v6, vcc ; CGP-NEXT: v_sub_i32_e64 v0, s[4:5], v11, v6 -; CGP-NEXT: v_cmp_ge_u32_e64 s[4:5], v8, v5 +; CGP-NEXT: v_cmp_ge_u32_e64 s[4:5], v8, v4 ; CGP-NEXT: v_cndmask_b32_e64 v1, 0, -1, s[4:5] ; CGP-NEXT: v_mov_b32_e32 v6, s8 ; CGP-NEXT: v_cmp_eq_u32_e64 s[4:5], 0, v9 @@ -1486,7 +1484,7 @@ ; CGP-NEXT: v_subbrev_u32_e32 v0, vcc, 0, v0, vcc ; CGP-NEXT: v_mac_f32_e32 v1, 0x4f800000, v6 ; CGP-NEXT: v_rcp_iflag_f32_e32 v1, v1 -; CGP-NEXT: v_sub_i32_e32 v11, vcc, v8, v5 +; CGP-NEXT: v_sub_i32_e32 v11, vcc, v8, v4 ; CGP-NEXT: v_subbrev_u32_e32 v12, vcc, 0, v0, vcc ; CGP-NEXT: v_mul_f32_e32 v0, 0x5f7ffffc, v1 ; CGP-NEXT: v_mul_f32_e32 v1, 0x2f800000, v0 @@ -1497,12 +1495,12 @@ ; CGP-NEXT: v_mov_b32_e32 v14, s4 ; CGP-NEXT: v_cvt_u32_f32_e32 v15, v6 ; CGP-NEXT: v_mad_u64_u32 v[0:1], s[4:5], s6, v13, 0 -; CGP-NEXT: v_cmp_ge_u32_e32 vcc, v11, v5 +; CGP-NEXT: v_cmp_ge_u32_e32 vcc, v11, v4 ; CGP-NEXT: v_cndmask_b32_e64 v7, 0, -1, vcc ; CGP-NEXT: v_cmp_eq_u32_e32 vcc, 0, v12 ; CGP-NEXT: v_cndmask_b32_e32 v14, v14, v7, vcc ; CGP-NEXT: v_mad_u64_u32 v[6:7], s[4:5], s6, v15, v[1:2] -; CGP-NEXT: v_sub_i32_e32 v1, vcc, v11, v5 +; CGP-NEXT: v_sub_i32_e32 v1, vcc, v11, v4 ; CGP-NEXT: v_mad_u64_u32 v[6:7], s[4:5], -1, v13, v[6:7] ; CGP-NEXT: v_subbrev_u32_e32 v16, vcc, 0, v12, vcc ; CGP-NEXT: v_cmp_ne_u32_e32 vcc, 0, v14 @@ -1533,93 +1531,91 @@ ; CGP-NEXT: v_addc_u32_e32 v13, vcc, v15, v1, vcc ; CGP-NEXT: v_mad_u64_u32 v[0:1], s[4:5], s6, v11, 0 ; CGP-NEXT: v_cmp_ne_u32_e32 vcc, 0, v10 -; CGP-NEXT: v_cndmask_b32_e32 v8, v8, v7, vcc +; CGP-NEXT: v_cndmask_b32_e32 v6, v8, v7, vcc +; CGP-NEXT: v_cndmask_b32_e32 v8, v9, v12, vcc +; CGP-NEXT: v_xor_b32_e32 v9, v6, v5 ; CGP-NEXT: v_mad_u64_u32 v[6:7], s[4:5], s6, v13, v[1:2] -; CGP-NEXT: v_xor_b32_e32 v1, v8, v4 +; CGP-NEXT: v_xor_b32_e32 v1, v8, v5 ; CGP-NEXT: v_ashrrev_i32_e32 v8, 31, v3 ; CGP-NEXT: v_mad_u64_u32 v[6:7], s[4:5], -1, v11, v[6:7] -; CGP-NEXT: v_cndmask_b32_e32 v9, v9, v12, vcc ; CGP-NEXT: v_add_i32_e32 v2, vcc, v2, v8 ; CGP-NEXT: v_addc_u32_e32 v3, vcc, v3, v8, vcc -; CGP-NEXT: v_xor_b32_e32 v10, v2, v8 +; CGP-NEXT: v_xor_b32_e32 v7, v2, v8 ; CGP-NEXT: v_mul_lo_u32 v2, v13, v0 -; CGP-NEXT: v_mul_lo_u32 v7, v11, v6 +; CGP-NEXT: v_mul_lo_u32 v10, v11, v6 ; CGP-NEXT: v_xor_b32_e32 v12, v3, v8 ; CGP-NEXT: v_mul_hi_u32 v3, v11, v0 ; CGP-NEXT: v_mul_hi_u32 v0, v13, v0 -; CGP-NEXT: v_add_i32_e32 v2, vcc, v2, v7 -; CGP-NEXT: v_cndmask_b32_e64 v7, 0, 1, vcc +; CGP-NEXT: v_add_i32_e32 v2, vcc, v2, v10 +; CGP-NEXT: v_cndmask_b32_e64 v10, 0, 1, vcc ; CGP-NEXT: v_add_i32_e32 v2, vcc, v2, v3 ; CGP-NEXT: v_cndmask_b32_e64 v2, 0, 1, vcc ; CGP-NEXT: v_mul_lo_u32 v3, v13, v6 -; CGP-NEXT: v_add_i32_e32 v2, vcc, v7, v2 -; CGP-NEXT: v_mul_hi_u32 v7, v11, v6 +; CGP-NEXT: v_add_i32_e32 v2, vcc, v10, v2 +; CGP-NEXT: v_mul_hi_u32 v10, v11, v6 ; CGP-NEXT: v_add_i32_e32 v0, vcc, v3, v0 ; CGP-NEXT: v_cndmask_b32_e64 v3, 0, 1, vcc -; CGP-NEXT: v_add_i32_e32 v0, vcc, v0, v7 -; CGP-NEXT: v_cndmask_b32_e64 v7, 0, 1, vcc -; CGP-NEXT: v_add_i32_e32 v3, vcc, v3, v7 +; CGP-NEXT: v_add_i32_e32 v0, vcc, v0, v10 +; CGP-NEXT: v_cndmask_b32_e64 v10, 0, 1, vcc +; CGP-NEXT: v_add_i32_e32 v3, vcc, v3, v10 ; CGP-NEXT: v_mul_hi_u32 v6, v13, v6 ; CGP-NEXT: v_add_i32_e32 v0, vcc, v0, v2 ; CGP-NEXT: v_cndmask_b32_e64 v2, 0, 1, vcc ; CGP-NEXT: v_add_i32_e32 v2, vcc, v3, v2 ; CGP-NEXT: v_add_i32_e32 v2, vcc, v6, v2 -; CGP-NEXT: v_add_i32_e32 v0, vcc, v11, v0 +; CGP-NEXT: v_add_i32_e32 v3, vcc, v11, v0 ; CGP-NEXT: v_addc_u32_e32 v2, vcc, v13, v2, vcc -; CGP-NEXT: v_mul_lo_u32 v3, v12, v0 -; CGP-NEXT: v_mul_lo_u32 v6, v10, v2 -; CGP-NEXT: v_mul_hi_u32 v7, v10, v0 -; CGP-NEXT: v_mul_hi_u32 v0, v12, v0 -; CGP-NEXT: v_xor_b32_e32 v9, v9, v4 -; CGP-NEXT: v_add_i32_e32 v3, vcc, v3, v6 -; CGP-NEXT: v_cndmask_b32_e64 v6, 0, 1, vcc -; CGP-NEXT: v_add_i32_e32 v3, vcc, v3, v7 -; CGP-NEXT: v_cndmask_b32_e64 v3, 0, 1, vcc -; CGP-NEXT: v_mul_lo_u32 v7, v12, v2 +; CGP-NEXT: v_mul_lo_u32 v6, v12, v3 +; CGP-NEXT: v_mul_lo_u32 v10, v7, v2 +; CGP-NEXT: v_sub_i32_e32 v0, vcc, v9, v5 +; CGP-NEXT: v_subb_u32_e32 v1, vcc, v1, v5, vcc +; CGP-NEXT: v_mul_hi_u32 v5, v7, v3 +; CGP-NEXT: v_add_i32_e32 v6, vcc, v6, v10 +; CGP-NEXT: v_cndmask_b32_e64 v9, 0, 1, vcc +; CGP-NEXT: v_add_i32_e32 v5, vcc, v6, v5 +; CGP-NEXT: v_cndmask_b32_e64 v5, 0, 1, vcc +; CGP-NEXT: v_mul_lo_u32 v6, v12, v2 +; CGP-NEXT: v_mul_hi_u32 v3, v12, v3 +; CGP-NEXT: v_add_i32_e32 v5, vcc, v9, v5 +; CGP-NEXT: v_mul_hi_u32 v9, v7, v2 ; CGP-NEXT: v_add_i32_e32 v3, vcc, v6, v3 -; CGP-NEXT: v_mul_hi_u32 v6, v10, v2 -; CGP-NEXT: v_add_i32_e32 v0, vcc, v7, v0 -; CGP-NEXT: v_cndmask_b32_e64 v7, 0, 1, vcc -; CGP-NEXT: v_add_i32_e32 v0, vcc, v0, v6 ; CGP-NEXT: v_cndmask_b32_e64 v6, 0, 1, vcc -; CGP-NEXT: v_add_i32_e32 v6, vcc, v7, v6 -; CGP-NEXT: v_add_i32_e32 v11, vcc, v0, v3 -; CGP-NEXT: v_mul_hi_u32 v7, v12, v2 -; CGP-NEXT: v_mad_u64_u32 v[2:3], s[4:5], s7, v11, 0 -; CGP-NEXT: v_cndmask_b32_e64 v0, 0, 1, vcc -; CGP-NEXT: v_add_i32_e32 v0, vcc, v6, v0 -; CGP-NEXT: v_add_i32_e32 v6, vcc, v7, v0 -; CGP-NEXT: v_mov_b32_e32 v0, v3 -; CGP-NEXT: v_mad_u64_u32 v[6:7], s[4:5], s7, v6, v[0:1] -; CGP-NEXT: v_sub_i32_e32 v0, vcc, v1, v4 -; CGP-NEXT: v_subb_u32_e32 v1, vcc, v9, v4, vcc -; CGP-NEXT: v_mad_u64_u32 v[3:4], s[4:5], 0, v11, v[6:7] -; CGP-NEXT: v_sub_i32_e32 v2, vcc, v10, v2 -; CGP-NEXT: v_subb_u32_e64 v4, s[4:5], v12, v3, vcc -; CGP-NEXT: v_sub_i32_e64 v3, s[4:5], v12, v3 +; CGP-NEXT: v_add_i32_e32 v3, vcc, v3, v9 +; CGP-NEXT: v_cndmask_b32_e64 v9, 0, 1, vcc +; CGP-NEXT: v_add_i32_e32 v6, vcc, v6, v9 +; CGP-NEXT: v_add_i32_e32 v3, vcc, v3, v5 +; CGP-NEXT: v_mul_hi_u32 v9, v12, v2 +; CGP-NEXT: v_mad_u64_u32 v[2:3], s[4:5], s7, v3, 0 +; CGP-NEXT: v_cndmask_b32_e64 v5, 0, 1, vcc +; CGP-NEXT: v_add_i32_e32 v5, vcc, v6, v5 +; CGP-NEXT: v_add_i32_e32 v5, vcc, v9, v5 +; CGP-NEXT: v_mad_u64_u32 v[5:6], s[4:5], s7, v5, v[3:4] +; CGP-NEXT: v_sub_i32_e32 v2, vcc, v7, v2 +; CGP-NEXT: v_subb_u32_e64 v3, s[4:5], v12, v5, vcc +; CGP-NEXT: v_sub_i32_e64 v5, s[4:5], v12, v5 ; CGP-NEXT: s_bfe_i32 s6, -1, 0x10000 -; CGP-NEXT: v_cmp_ge_u32_e64 s[4:5], v2, v5 +; CGP-NEXT: v_cmp_ge_u32_e64 s[4:5], v2, v4 ; CGP-NEXT: v_cndmask_b32_e64 v6, 0, -1, s[4:5] ; CGP-NEXT: v_mov_b32_e32 v7, s6 -; CGP-NEXT: v_cmp_eq_u32_e64 s[4:5], 0, v4 -; CGP-NEXT: v_subbrev_u32_e32 v3, vcc, 0, v3, vcc +; CGP-NEXT: v_cmp_eq_u32_e64 s[4:5], 0, v3 +; CGP-NEXT: v_subbrev_u32_e32 v5, vcc, 0, v5, vcc ; CGP-NEXT: v_cndmask_b32_e64 v6, v7, v6, s[4:5] -; CGP-NEXT: v_sub_i32_e32 v7, vcc, v2, v5 -; CGP-NEXT: v_subbrev_u32_e32 v3, vcc, 0, v3, vcc +; CGP-NEXT: v_sub_i32_e32 v7, vcc, v2, v4 +; CGP-NEXT: v_subbrev_u32_e32 v5, vcc, 0, v5, vcc ; CGP-NEXT: s_bfe_i32 s4, -1, 0x10000 -; CGP-NEXT: v_cmp_ge_u32_e32 vcc, v7, v5 +; CGP-NEXT: v_cmp_ge_u32_e32 vcc, v7, v4 ; CGP-NEXT: v_cndmask_b32_e64 v9, 0, -1, vcc ; CGP-NEXT: v_mov_b32_e32 v10, s4 -; CGP-NEXT: v_cmp_eq_u32_e32 vcc, 0, v3 +; CGP-NEXT: v_cmp_eq_u32_e32 vcc, 0, v5 ; CGP-NEXT: v_cndmask_b32_e32 v9, v10, v9, vcc -; CGP-NEXT: v_sub_i32_e32 v5, vcc, v7, v5 -; CGP-NEXT: v_subbrev_u32_e32 v10, vcc, 0, v3, vcc +; CGP-NEXT: v_sub_i32_e32 v4, vcc, v7, v4 +; CGP-NEXT: v_subbrev_u32_e32 v10, vcc, 0, v5, vcc ; CGP-NEXT: v_cmp_ne_u32_e32 vcc, 0, v9 -; CGP-NEXT: v_cndmask_b32_e32 v5, v7, v5, vcc -; CGP-NEXT: v_cndmask_b32_e32 v3, v3, v10, vcc +; CGP-NEXT: v_cndmask_b32_e32 v4, v7, v4, vcc +; CGP-NEXT: v_cndmask_b32_e32 v5, v5, v10, vcc ; CGP-NEXT: v_cmp_ne_u32_e32 vcc, 0, v6 -; CGP-NEXT: v_cndmask_b32_e32 v2, v2, v5, vcc -; CGP-NEXT: v_cndmask_b32_e32 v3, v4, v3, vcc +; CGP-NEXT: v_cndmask_b32_e32 v2, v2, v4, vcc +; CGP-NEXT: v_cndmask_b32_e32 v3, v3, v5, vcc ; CGP-NEXT: v_xor_b32_e32 v2, v2, v8 ; CGP-NEXT: v_xor_b32_e32 v3, v3, v8 ; CGP-NEXT: v_sub_i32_e32 v2, vcc, v2, v8 @@ -1673,86 +1669,85 @@ ; CHECK-NEXT: v_addc_u32_e32 v6, vcc, v6, v3, vcc ; CHECK-NEXT: v_mad_u64_u32 v[2:3], s[4:5], s6, v5, 0 ; CHECK-NEXT: v_ashrrev_i32_e32 v7, 31, v1 -; CHECK-NEXT: v_add_i32_e32 v0, vcc, v0, v7 +; CHECK-NEXT: v_add_i32_e32 v8, vcc, v0, v7 ; CHECK-NEXT: v_mad_u64_u32 v[3:4], s[4:5], s6, v6, v[3:4] -; CHECK-NEXT: v_addc_u32_e32 v1, vcc, v1, v7, vcc -; CHECK-NEXT: v_mad_u64_u32 v[3:4], s[4:5], -1, v5, v[3:4] -; CHECK-NEXT: v_xor_b32_e32 v4, v0, v7 -; CHECK-NEXT: v_mul_lo_u32 v0, v6, v2 -; CHECK-NEXT: v_mul_lo_u32 v8, v5, v3 -; CHECK-NEXT: v_xor_b32_e32 v9, v1, v7 -; CHECK-NEXT: v_mul_hi_u32 v1, v5, v2 +; CHECK-NEXT: v_addc_u32_e32 v9, vcc, v1, v7, vcc +; CHECK-NEXT: v_mad_u64_u32 v[0:1], s[4:5], -1, v5, v[3:4] +; CHECK-NEXT: v_xor_b32_e32 v3, v8, v7 +; CHECK-NEXT: v_mul_lo_u32 v1, v6, v2 +; CHECK-NEXT: v_mul_lo_u32 v8, v5, v0 +; CHECK-NEXT: v_xor_b32_e32 v4, v9, v7 +; CHECK-NEXT: v_mul_hi_u32 v9, v5, v2 ; CHECK-NEXT: v_mul_hi_u32 v2, v6, v2 -; CHECK-NEXT: v_add_i32_e32 v0, vcc, v0, v8 -; CHECK-NEXT: v_cndmask_b32_e64 v8, 0, 1, vcc -; CHECK-NEXT: v_add_i32_e32 v0, vcc, v0, v1 -; CHECK-NEXT: v_cndmask_b32_e64 v0, 0, 1, vcc -; CHECK-NEXT: v_mul_lo_u32 v1, v6, v3 -; CHECK-NEXT: v_add_i32_e32 v0, vcc, v8, v0 -; CHECK-NEXT: v_mul_hi_u32 v8, v5, v3 -; CHECK-NEXT: v_add_i32_e32 v1, vcc, v1, v2 -; CHECK-NEXT: v_cndmask_b32_e64 v2, 0, 1, vcc ; CHECK-NEXT: v_add_i32_e32 v1, vcc, v1, v8 ; CHECK-NEXT: v_cndmask_b32_e64 v8, 0, 1, vcc -; CHECK-NEXT: v_add_i32_e32 v2, vcc, v2, v8 -; CHECK-NEXT: v_mul_hi_u32 v3, v6, v3 -; CHECK-NEXT: v_add_i32_e32 v0, vcc, v1, v0 +; CHECK-NEXT: v_add_i32_e32 v1, vcc, v1, v9 ; CHECK-NEXT: v_cndmask_b32_e64 v1, 0, 1, vcc +; CHECK-NEXT: v_mul_lo_u32 v9, v6, v0 +; CHECK-NEXT: v_add_i32_e32 v1, vcc, v8, v1 +; CHECK-NEXT: v_mul_hi_u32 v8, v5, v0 +; CHECK-NEXT: v_add_i32_e32 v2, vcc, v9, v2 +; CHECK-NEXT: v_cndmask_b32_e64 v9, 0, 1, vcc +; CHECK-NEXT: v_add_i32_e32 v2, vcc, v2, v8 +; CHECK-NEXT: v_cndmask_b32_e64 v8, 0, 1, vcc +; CHECK-NEXT: v_add_i32_e32 v8, vcc, v9, v8 +; CHECK-NEXT: v_mul_hi_u32 v0, v6, v0 ; CHECK-NEXT: v_add_i32_e32 v1, vcc, v2, v1 -; CHECK-NEXT: v_add_i32_e32 v1, vcc, v3, v1 -; CHECK-NEXT: v_add_i32_e32 v0, vcc, v5, v0 -; CHECK-NEXT: v_addc_u32_e32 v1, vcc, v6, v1, vcc -; CHECK-NEXT: v_mul_lo_u32 v2, v9, v0 -; CHECK-NEXT: v_mul_lo_u32 v3, v4, v1 -; CHECK-NEXT: v_mul_hi_u32 v5, v4, v0 -; CHECK-NEXT: v_mul_hi_u32 v0, v9, v0 +; CHECK-NEXT: v_cndmask_b32_e64 v2, 0, 1, vcc +; CHECK-NEXT: v_add_i32_e32 v2, vcc, v8, v2 +; CHECK-NEXT: v_add_i32_e32 v0, vcc, v0, v2 +; CHECK-NEXT: v_add_i32_e32 v1, vcc, v5, v1 +; CHECK-NEXT: v_addc_u32_e32 v0, vcc, v6, v0, vcc +; CHECK-NEXT: v_mul_lo_u32 v2, v4, v1 +; CHECK-NEXT: v_mul_lo_u32 v5, v3, v0 +; CHECK-NEXT: v_mul_hi_u32 v8, v3, v1 +; CHECK-NEXT: v_mul_hi_u32 v1, v4, v1 ; CHECK-NEXT: s_mov_b32 s6, 0x12d8fb -; CHECK-NEXT: v_add_i32_e32 v2, vcc, v2, v3 -; CHECK-NEXT: v_cndmask_b32_e64 v3, 0, 1, vcc ; CHECK-NEXT: v_add_i32_e32 v2, vcc, v2, v5 +; CHECK-NEXT: v_cndmask_b32_e64 v5, 0, 1, vcc +; CHECK-NEXT: v_add_i32_e32 v2, vcc, v2, v8 ; CHECK-NEXT: v_cndmask_b32_e64 v2, 0, 1, vcc -; CHECK-NEXT: v_mul_lo_u32 v5, v9, v1 -; CHECK-NEXT: v_add_i32_e32 v2, vcc, v3, v2 -; CHECK-NEXT: v_mul_hi_u32 v3, v4, v1 -; CHECK-NEXT: v_add_i32_e32 v0, vcc, v5, v0 +; CHECK-NEXT: v_mul_lo_u32 v8, v4, v0 +; CHECK-NEXT: v_add_i32_e32 v2, vcc, v5, v2 +; CHECK-NEXT: v_mul_hi_u32 v5, v3, v0 +; CHECK-NEXT: v_add_i32_e32 v1, vcc, v8, v1 +; CHECK-NEXT: v_cndmask_b32_e64 v8, 0, 1, vcc +; CHECK-NEXT: v_add_i32_e32 v1, vcc, v1, v5 ; CHECK-NEXT: v_cndmask_b32_e64 v5, 0, 1, vcc -; CHECK-NEXT: v_add_i32_e32 v0, vcc, v0, v3 -; CHECK-NEXT: v_cndmask_b32_e64 v3, 0, 1, vcc -; CHECK-NEXT: v_add_i32_e32 v3, vcc, v5, v3 -; CHECK-NEXT: v_add_i32_e32 v5, vcc, v0, v2 -; CHECK-NEXT: v_mul_hi_u32 v6, v9, v1 -; CHECK-NEXT: v_mad_u64_u32 v[0:1], s[4:5], s6, v5, 0 +; CHECK-NEXT: v_add_i32_e32 v5, vcc, v8, v5 +; CHECK-NEXT: v_add_i32_e32 v1, vcc, v1, v2 +; CHECK-NEXT: v_mul_hi_u32 v8, v4, v0 +; CHECK-NEXT: v_mad_u64_u32 v[0:1], s[4:5], s6, v1, 0 ; CHECK-NEXT: v_cndmask_b32_e64 v2, 0, 1, vcc -; CHECK-NEXT: v_add_i32_e32 v2, vcc, v3, v2 -; CHECK-NEXT: v_add_i32_e32 v2, vcc, v6, v2 +; CHECK-NEXT: v_add_i32_e32 v2, vcc, v5, v2 +; CHECK-NEXT: v_add_i32_e32 v2, vcc, v8, v2 ; CHECK-NEXT: v_mad_u64_u32 v[1:2], s[4:5], s6, v2, v[1:2] -; CHECK-NEXT: v_sub_i32_e32 v0, vcc, v4, v0 -; CHECK-NEXT: v_mad_u64_u32 v[1:2], s[4:5], 0, v5, v[1:2] -; CHECK-NEXT: v_mov_b32_e32 v3, 0x12d8fb +; CHECK-NEXT: v_sub_i32_e32 v0, vcc, v3, v0 +; CHECK-NEXT: v_mov_b32_e32 v6, 0x12d8fb +; CHECK-NEXT: v_subb_u32_e64 v2, s[4:5], v4, v1, vcc +; CHECK-NEXT: v_sub_i32_e64 v1, s[4:5], v4, v1 ; CHECK-NEXT: s_bfe_i32 s6, -1, 0x10000 -; CHECK-NEXT: v_subb_u32_e64 v2, s[4:5], v9, v1, vcc -; CHECK-NEXT: v_sub_i32_e64 v1, s[4:5], v9, v1 -; CHECK-NEXT: v_cmp_ge_u32_e64 s[4:5], v0, v3 -; CHECK-NEXT: v_cndmask_b32_e64 v4, 0, -1, s[4:5] -; CHECK-NEXT: v_mov_b32_e32 v5, s6 +; CHECK-NEXT: v_cmp_ge_u32_e64 s[4:5], v0, v6 +; CHECK-NEXT: v_cndmask_b32_e64 v3, 0, -1, s[4:5] +; CHECK-NEXT: v_mov_b32_e32 v4, s6 ; CHECK-NEXT: v_cmp_eq_u32_e64 s[4:5], 0, v2 ; CHECK-NEXT: v_subbrev_u32_e32 v1, vcc, 0, v1, vcc -; CHECK-NEXT: v_cndmask_b32_e64 v4, v5, v4, s[4:5] -; CHECK-NEXT: v_sub_i32_e32 v5, vcc, v0, v3 +; CHECK-NEXT: v_cndmask_b32_e64 v3, v4, v3, s[4:5] +; CHECK-NEXT: v_sub_i32_e32 v4, vcc, v0, v6 ; CHECK-NEXT: v_subbrev_u32_e32 v1, vcc, 0, v1, vcc ; CHECK-NEXT: s_bfe_i32 s4, -1, 0x10000 -; CHECK-NEXT: v_cmp_ge_u32_e32 vcc, v5, v3 -; CHECK-NEXT: v_cndmask_b32_e64 v6, 0, -1, vcc +; CHECK-NEXT: v_cmp_ge_u32_e32 vcc, v4, v6 +; CHECK-NEXT: v_cndmask_b32_e64 v5, 0, -1, vcc ; CHECK-NEXT: v_mov_b32_e32 v8, s4 ; CHECK-NEXT: v_cmp_eq_u32_e32 vcc, 0, v1 -; CHECK-NEXT: v_cndmask_b32_e32 v6, v8, v6, vcc -; CHECK-NEXT: v_sub_i32_e32 v3, vcc, v5, v3 +; CHECK-NEXT: v_cndmask_b32_e32 v5, v8, v5, vcc +; CHECK-NEXT: v_sub_i32_e32 v6, vcc, v4, v6 ; CHECK-NEXT: v_subbrev_u32_e32 v8, vcc, 0, v1, vcc -; CHECK-NEXT: v_cmp_ne_u32_e32 vcc, 0, v6 -; CHECK-NEXT: v_cndmask_b32_e32 v3, v5, v3, vcc +; CHECK-NEXT: v_cmp_ne_u32_e32 vcc, 0, v5 +; CHECK-NEXT: v_cndmask_b32_e32 v4, v4, v6, vcc ; CHECK-NEXT: v_cndmask_b32_e32 v1, v1, v8, vcc -; CHECK-NEXT: v_cmp_ne_u32_e32 vcc, 0, v4 -; CHECK-NEXT: v_cndmask_b32_e32 v0, v0, v3, vcc +; CHECK-NEXT: v_cmp_ne_u32_e32 vcc, 0, v3 +; CHECK-NEXT: v_cndmask_b32_e32 v0, v0, v4, vcc ; CHECK-NEXT: v_cndmask_b32_e32 v1, v2, v1, vcc ; CHECK-NEXT: v_xor_b32_e32 v0, v0, v7 ; CHECK-NEXT: v_xor_b32_e32 v1, v1, v7 @@ -2071,68 +2066,67 @@ ; CGP-NEXT: v_add_i32_e32 v6, vcc, v9, v6 ; CGP-NEXT: v_add_i32_e32 v5, vcc, v5, v6 ; CGP-NEXT: v_add_i32_e32 v9, vcc, v7, v4 -; CGP-NEXT: v_addc_u32_e32 v8, vcc, v8, v5, vcc -; CGP-NEXT: v_mad_u64_u32 v[5:6], s[4:5], s6, v9, 0 -; CGP-NEXT: v_mov_b32_e32 v4, v6 -; CGP-NEXT: v_mad_u64_u32 v[6:7], s[4:5], s6, v8, v[4:5] -; CGP-NEXT: v_ashrrev_i32_e32 v4, 31, v1 -; CGP-NEXT: v_add_i32_e32 v0, vcc, v0, v4 -; CGP-NEXT: v_mad_u64_u32 v[6:7], s[4:5], -1, v9, v[6:7] -; CGP-NEXT: v_addc_u32_e32 v1, vcc, v1, v4, vcc -; CGP-NEXT: v_xor_b32_e32 v10, v0, v4 -; CGP-NEXT: v_mul_lo_u32 v0, v8, v5 -; CGP-NEXT: v_mul_lo_u32 v7, v9, v6 -; CGP-NEXT: v_xor_b32_e32 v11, v1, v4 -; CGP-NEXT: v_mul_hi_u32 v1, v9, v5 -; CGP-NEXT: v_mul_hi_u32 v5, v8, v5 -; CGP-NEXT: v_add_i32_e32 v0, vcc, v0, v7 -; CGP-NEXT: v_cndmask_b32_e64 v7, 0, 1, vcc -; CGP-NEXT: v_add_i32_e32 v0, vcc, v0, v1 -; CGP-NEXT: v_cndmask_b32_e64 v0, 0, 1, vcc -; CGP-NEXT: v_mul_lo_u32 v1, v8, v6 -; CGP-NEXT: v_add_i32_e32 v0, vcc, v7, v0 +; CGP-NEXT: v_mad_u64_u32 v[6:7], s[4:5], s6, v9, 0 +; CGP-NEXT: v_addc_u32_e32 v10, vcc, v8, v5, vcc +; CGP-NEXT: v_ashrrev_i32_e32 v5, 31, v1 +; CGP-NEXT: v_mov_b32_e32 v4, v7 +; CGP-NEXT: v_mad_u64_u32 v[7:8], s[4:5], s6, v10, v[4:5] +; CGP-NEXT: v_add_i32_e32 v4, vcc, v0, v5 +; CGP-NEXT: v_addc_u32_e32 v11, vcc, v1, v5, vcc +; CGP-NEXT: v_mad_u64_u32 v[0:1], s[4:5], -1, v9, v[7:8] +; CGP-NEXT: v_xor_b32_e32 v8, v4, v5 +; CGP-NEXT: v_mul_lo_u32 v1, v10, v6 +; CGP-NEXT: v_mul_lo_u32 v4, v9, v0 ; CGP-NEXT: v_mul_hi_u32 v7, v9, v6 -; CGP-NEXT: v_add_i32_e32 v1, vcc, v1, v5 -; CGP-NEXT: v_cndmask_b32_e64 v5, 0, 1, vcc +; CGP-NEXT: v_mul_hi_u32 v6, v10, v6 +; CGP-NEXT: v_xor_b32_e32 v11, v11, v5 +; CGP-NEXT: v_add_i32_e32 v1, vcc, v1, v4 +; CGP-NEXT: v_cndmask_b32_e64 v4, 0, 1, vcc ; CGP-NEXT: v_add_i32_e32 v1, vcc, v1, v7 -; CGP-NEXT: v_cndmask_b32_e64 v7, 0, 1, vcc -; CGP-NEXT: v_add_i32_e32 v5, vcc, v5, v7 -; CGP-NEXT: v_mul_hi_u32 v6, v8, v6 -; CGP-NEXT: v_add_i32_e32 v0, vcc, v1, v0 ; CGP-NEXT: v_cndmask_b32_e64 v1, 0, 1, vcc -; CGP-NEXT: v_add_i32_e32 v1, vcc, v5, v1 -; CGP-NEXT: v_add_i32_e32 v1, vcc, v6, v1 -; CGP-NEXT: v_add_i32_e32 v0, vcc, v9, v0 -; CGP-NEXT: v_addc_u32_e32 v1, vcc, v8, v1, vcc -; CGP-NEXT: v_mul_lo_u32 v5, v11, v0 -; CGP-NEXT: v_mul_lo_u32 v6, v10, v1 -; CGP-NEXT: v_mul_hi_u32 v7, v10, v0 -; CGP-NEXT: v_mul_hi_u32 v0, v11, v0 -; CGP-NEXT: v_add_i32_e32 v5, vcc, v5, v6 +; CGP-NEXT: v_mul_lo_u32 v7, v10, v0 +; CGP-NEXT: v_add_i32_e32 v1, vcc, v4, v1 +; CGP-NEXT: v_mul_hi_u32 v4, v9, v0 +; CGP-NEXT: v_add_i32_e32 v6, vcc, v7, v6 +; CGP-NEXT: v_cndmask_b32_e64 v7, 0, 1, vcc +; CGP-NEXT: v_add_i32_e32 v4, vcc, v6, v4 ; CGP-NEXT: v_cndmask_b32_e64 v6, 0, 1, vcc -; CGP-NEXT: v_add_i32_e32 v5, vcc, v5, v7 -; CGP-NEXT: v_cndmask_b32_e64 v5, 0, 1, vcc -; CGP-NEXT: v_mul_lo_u32 v7, v11, v1 -; CGP-NEXT: v_add_i32_e32 v5, vcc, v6, v5 -; CGP-NEXT: v_mul_hi_u32 v6, v10, v1 -; CGP-NEXT: v_add_i32_e32 v0, vcc, v7, v0 +; CGP-NEXT: v_add_i32_e32 v6, vcc, v7, v6 +; CGP-NEXT: v_mul_hi_u32 v0, v10, v0 +; CGP-NEXT: v_add_i32_e32 v1, vcc, v4, v1 +; CGP-NEXT: v_cndmask_b32_e64 v4, 0, 1, vcc +; CGP-NEXT: v_add_i32_e32 v4, vcc, v6, v4 +; CGP-NEXT: v_add_i32_e32 v0, vcc, v0, v4 +; CGP-NEXT: v_add_i32_e32 v1, vcc, v9, v1 +; CGP-NEXT: v_addc_u32_e32 v0, vcc, v10, v0, vcc +; CGP-NEXT: v_mul_lo_u32 v6, v11, v1 +; CGP-NEXT: v_mul_lo_u32 v7, v8, v0 +; CGP-NEXT: v_mul_hi_u32 v9, v8, v1 +; CGP-NEXT: v_mul_hi_u32 v1, v11, v1 +; CGP-NEXT: v_mov_b32_e32 v4, 0x12d8fb +; CGP-NEXT: v_add_i32_e32 v6, vcc, v6, v7 ; CGP-NEXT: v_cndmask_b32_e64 v7, 0, 1, vcc -; CGP-NEXT: v_add_i32_e32 v0, vcc, v0, v6 +; CGP-NEXT: v_add_i32_e32 v6, vcc, v6, v9 ; CGP-NEXT: v_cndmask_b32_e64 v6, 0, 1, vcc +; CGP-NEXT: v_mul_lo_u32 v9, v11, v0 ; CGP-NEXT: v_add_i32_e32 v6, vcc, v7, v6 -; CGP-NEXT: v_add_i32_e32 v8, vcc, v0, v5 -; CGP-NEXT: v_mul_hi_u32 v7, v11, v1 -; CGP-NEXT: v_mad_u64_u32 v[0:1], s[4:5], s7, v8, 0 -; CGP-NEXT: v_cndmask_b32_e64 v5, 0, 1, vcc -; CGP-NEXT: v_add_i32_e32 v5, vcc, v6, v5 -; CGP-NEXT: v_add_i32_e32 v5, vcc, v7, v5 -; CGP-NEXT: v_mad_u64_u32 v[6:7], s[4:5], s7, v5, v[1:2] -; CGP-NEXT: v_mov_b32_e32 v5, 0x12d8fb -; CGP-NEXT: v_mad_u64_u32 v[6:7], s[4:5], 0, v8, v[6:7] -; CGP-NEXT: v_sub_i32_e32 v8, vcc, v10, v0 +; CGP-NEXT: v_mul_hi_u32 v7, v8, v0 +; CGP-NEXT: v_add_i32_e32 v1, vcc, v9, v1 +; CGP-NEXT: v_cndmask_b32_e64 v9, 0, 1, vcc +; CGP-NEXT: v_add_i32_e32 v1, vcc, v1, v7 +; CGP-NEXT: v_cndmask_b32_e64 v7, 0, 1, vcc +; CGP-NEXT: v_add_i32_e32 v7, vcc, v9, v7 +; CGP-NEXT: v_add_i32_e32 v1, vcc, v1, v6 +; CGP-NEXT: v_mul_hi_u32 v9, v11, v0 +; CGP-NEXT: v_mad_u64_u32 v[0:1], s[4:5], s7, v1, 0 +; CGP-NEXT: v_cndmask_b32_e64 v6, 0, 1, vcc +; CGP-NEXT: v_add_i32_e32 v6, vcc, v7, v6 +; CGP-NEXT: v_add_i32_e32 v6, vcc, v9, v6 +; CGP-NEXT: v_mad_u64_u32 v[6:7], s[4:5], s7, v6, v[1:2] +; CGP-NEXT: v_sub_i32_e32 v8, vcc, v8, v0 ; CGP-NEXT: v_subb_u32_e64 v9, s[4:5], v11, v6, vcc ; CGP-NEXT: v_sub_i32_e64 v0, s[4:5], v11, v6 -; CGP-NEXT: v_cmp_ge_u32_e64 s[4:5], v8, v5 +; CGP-NEXT: v_cmp_ge_u32_e64 s[4:5], v8, v4 ; CGP-NEXT: v_cndmask_b32_e64 v1, 0, -1, s[4:5] ; CGP-NEXT: v_mov_b32_e32 v6, s8 ; CGP-NEXT: v_cmp_eq_u32_e64 s[4:5], 0, v9 @@ -2142,7 +2136,7 @@ ; CGP-NEXT: v_subbrev_u32_e32 v0, vcc, 0, v0, vcc ; CGP-NEXT: v_mac_f32_e32 v1, 0x4f800000, v6 ; CGP-NEXT: v_rcp_iflag_f32_e32 v1, v1 -; CGP-NEXT: v_sub_i32_e32 v11, vcc, v8, v5 +; CGP-NEXT: v_sub_i32_e32 v11, vcc, v8, v4 ; CGP-NEXT: v_subbrev_u32_e32 v12, vcc, 0, v0, vcc ; CGP-NEXT: v_mul_f32_e32 v0, 0x5f7ffffc, v1 ; CGP-NEXT: v_mul_f32_e32 v1, 0x2f800000, v0 @@ -2153,12 +2147,12 @@ ; CGP-NEXT: v_mov_b32_e32 v14, s4 ; CGP-NEXT: v_cvt_u32_f32_e32 v15, v6 ; CGP-NEXT: v_mad_u64_u32 v[0:1], s[4:5], s6, v13, 0 -; CGP-NEXT: v_cmp_ge_u32_e32 vcc, v11, v5 +; CGP-NEXT: v_cmp_ge_u32_e32 vcc, v11, v4 ; CGP-NEXT: v_cndmask_b32_e64 v7, 0, -1, vcc ; CGP-NEXT: v_cmp_eq_u32_e32 vcc, 0, v12 ; CGP-NEXT: v_cndmask_b32_e32 v14, v14, v7, vcc ; CGP-NEXT: v_mad_u64_u32 v[6:7], s[4:5], s6, v15, v[1:2] -; CGP-NEXT: v_sub_i32_e32 v1, vcc, v11, v5 +; CGP-NEXT: v_sub_i32_e32 v1, vcc, v11, v4 ; CGP-NEXT: v_mad_u64_u32 v[6:7], s[4:5], -1, v13, v[6:7] ; CGP-NEXT: v_subbrev_u32_e32 v16, vcc, 0, v12, vcc ; CGP-NEXT: v_cmp_ne_u32_e32 vcc, 0, v14 @@ -2189,93 +2183,91 @@ ; CGP-NEXT: v_addc_u32_e32 v13, vcc, v15, v1, vcc ; CGP-NEXT: v_mad_u64_u32 v[0:1], s[4:5], s6, v11, 0 ; CGP-NEXT: v_cmp_ne_u32_e32 vcc, 0, v10 -; CGP-NEXT: v_cndmask_b32_e32 v8, v8, v7, vcc +; CGP-NEXT: v_cndmask_b32_e32 v6, v8, v7, vcc +; CGP-NEXT: v_cndmask_b32_e32 v8, v9, v12, vcc +; CGP-NEXT: v_xor_b32_e32 v9, v6, v5 ; CGP-NEXT: v_mad_u64_u32 v[6:7], s[4:5], s6, v13, v[1:2] -; CGP-NEXT: v_xor_b32_e32 v1, v8, v4 +; CGP-NEXT: v_xor_b32_e32 v1, v8, v5 ; CGP-NEXT: v_ashrrev_i32_e32 v8, 31, v3 ; CGP-NEXT: v_mad_u64_u32 v[6:7], s[4:5], -1, v11, v[6:7] -; CGP-NEXT: v_cndmask_b32_e32 v9, v9, v12, vcc ; CGP-NEXT: v_add_i32_e32 v2, vcc, v2, v8 ; CGP-NEXT: v_addc_u32_e32 v3, vcc, v3, v8, vcc -; CGP-NEXT: v_xor_b32_e32 v10, v2, v8 +; CGP-NEXT: v_xor_b32_e32 v7, v2, v8 ; CGP-NEXT: v_mul_lo_u32 v2, v13, v0 -; CGP-NEXT: v_mul_lo_u32 v7, v11, v6 +; CGP-NEXT: v_mul_lo_u32 v10, v11, v6 ; CGP-NEXT: v_xor_b32_e32 v12, v3, v8 ; CGP-NEXT: v_mul_hi_u32 v3, v11, v0 ; CGP-NEXT: v_mul_hi_u32 v0, v13, v0 -; CGP-NEXT: v_add_i32_e32 v2, vcc, v2, v7 -; CGP-NEXT: v_cndmask_b32_e64 v7, 0, 1, vcc +; CGP-NEXT: v_add_i32_e32 v2, vcc, v2, v10 +; CGP-NEXT: v_cndmask_b32_e64 v10, 0, 1, vcc ; CGP-NEXT: v_add_i32_e32 v2, vcc, v2, v3 ; CGP-NEXT: v_cndmask_b32_e64 v2, 0, 1, vcc ; CGP-NEXT: v_mul_lo_u32 v3, v13, v6 -; CGP-NEXT: v_add_i32_e32 v2, vcc, v7, v2 -; CGP-NEXT: v_mul_hi_u32 v7, v11, v6 +; CGP-NEXT: v_add_i32_e32 v2, vcc, v10, v2 +; CGP-NEXT: v_mul_hi_u32 v10, v11, v6 ; CGP-NEXT: v_add_i32_e32 v0, vcc, v3, v0 ; CGP-NEXT: v_cndmask_b32_e64 v3, 0, 1, vcc -; CGP-NEXT: v_add_i32_e32 v0, vcc, v0, v7 -; CGP-NEXT: v_cndmask_b32_e64 v7, 0, 1, vcc -; CGP-NEXT: v_add_i32_e32 v3, vcc, v3, v7 +; CGP-NEXT: v_add_i32_e32 v0, vcc, v0, v10 +; CGP-NEXT: v_cndmask_b32_e64 v10, 0, 1, vcc +; CGP-NEXT: v_add_i32_e32 v3, vcc, v3, v10 ; CGP-NEXT: v_mul_hi_u32 v6, v13, v6 ; CGP-NEXT: v_add_i32_e32 v0, vcc, v0, v2 ; CGP-NEXT: v_cndmask_b32_e64 v2, 0, 1, vcc ; CGP-NEXT: v_add_i32_e32 v2, vcc, v3, v2 ; CGP-NEXT: v_add_i32_e32 v2, vcc, v6, v2 -; CGP-NEXT: v_add_i32_e32 v0, vcc, v11, v0 +; CGP-NEXT: v_add_i32_e32 v3, vcc, v11, v0 ; CGP-NEXT: v_addc_u32_e32 v2, vcc, v13, v2, vcc -; CGP-NEXT: v_mul_lo_u32 v3, v12, v0 -; CGP-NEXT: v_mul_lo_u32 v6, v10, v2 -; CGP-NEXT: v_mul_hi_u32 v7, v10, v0 -; CGP-NEXT: v_mul_hi_u32 v0, v12, v0 -; CGP-NEXT: v_xor_b32_e32 v9, v9, v4 -; CGP-NEXT: v_add_i32_e32 v3, vcc, v3, v6 -; CGP-NEXT: v_cndmask_b32_e64 v6, 0, 1, vcc -; CGP-NEXT: v_add_i32_e32 v3, vcc, v3, v7 -; CGP-NEXT: v_cndmask_b32_e64 v3, 0, 1, vcc -; CGP-NEXT: v_mul_lo_u32 v7, v12, v2 +; CGP-NEXT: v_mul_lo_u32 v6, v12, v3 +; CGP-NEXT: v_mul_lo_u32 v10, v7, v2 +; CGP-NEXT: v_sub_i32_e32 v0, vcc, v9, v5 +; CGP-NEXT: v_subb_u32_e32 v1, vcc, v1, v5, vcc +; CGP-NEXT: v_mul_hi_u32 v5, v7, v3 +; CGP-NEXT: v_add_i32_e32 v6, vcc, v6, v10 +; CGP-NEXT: v_cndmask_b32_e64 v9, 0, 1, vcc +; CGP-NEXT: v_add_i32_e32 v5, vcc, v6, v5 +; CGP-NEXT: v_cndmask_b32_e64 v5, 0, 1, vcc +; CGP-NEXT: v_mul_lo_u32 v6, v12, v2 +; CGP-NEXT: v_mul_hi_u32 v3, v12, v3 +; CGP-NEXT: v_add_i32_e32 v5, vcc, v9, v5 +; CGP-NEXT: v_mul_hi_u32 v9, v7, v2 ; CGP-NEXT: v_add_i32_e32 v3, vcc, v6, v3 -; CGP-NEXT: v_mul_hi_u32 v6, v10, v2 -; CGP-NEXT: v_add_i32_e32 v0, vcc, v7, v0 -; CGP-NEXT: v_cndmask_b32_e64 v7, 0, 1, vcc -; CGP-NEXT: v_add_i32_e32 v0, vcc, v0, v6 ; CGP-NEXT: v_cndmask_b32_e64 v6, 0, 1, vcc -; CGP-NEXT: v_add_i32_e32 v6, vcc, v7, v6 -; CGP-NEXT: v_add_i32_e32 v11, vcc, v0, v3 -; CGP-NEXT: v_mul_hi_u32 v7, v12, v2 -; CGP-NEXT: v_mad_u64_u32 v[2:3], s[4:5], s7, v11, 0 -; CGP-NEXT: v_cndmask_b32_e64 v0, 0, 1, vcc -; CGP-NEXT: v_add_i32_e32 v0, vcc, v6, v0 -; CGP-NEXT: v_add_i32_e32 v6, vcc, v7, v0 -; CGP-NEXT: v_mov_b32_e32 v0, v3 -; CGP-NEXT: v_mad_u64_u32 v[6:7], s[4:5], s7, v6, v[0:1] -; CGP-NEXT: v_sub_i32_e32 v0, vcc, v1, v4 -; CGP-NEXT: v_subb_u32_e32 v1, vcc, v9, v4, vcc -; CGP-NEXT: v_mad_u64_u32 v[3:4], s[4:5], 0, v11, v[6:7] -; CGP-NEXT: v_sub_i32_e32 v2, vcc, v10, v2 -; CGP-NEXT: v_subb_u32_e64 v4, s[4:5], v12, v3, vcc -; CGP-NEXT: v_sub_i32_e64 v3, s[4:5], v12, v3 +; CGP-NEXT: v_add_i32_e32 v3, vcc, v3, v9 +; CGP-NEXT: v_cndmask_b32_e64 v9, 0, 1, vcc +; CGP-NEXT: v_add_i32_e32 v6, vcc, v6, v9 +; CGP-NEXT: v_add_i32_e32 v3, vcc, v3, v5 +; CGP-NEXT: v_mul_hi_u32 v9, v12, v2 +; CGP-NEXT: v_mad_u64_u32 v[2:3], s[4:5], s7, v3, 0 +; CGP-NEXT: v_cndmask_b32_e64 v5, 0, 1, vcc +; CGP-NEXT: v_add_i32_e32 v5, vcc, v6, v5 +; CGP-NEXT: v_add_i32_e32 v5, vcc, v9, v5 +; CGP-NEXT: v_mad_u64_u32 v[5:6], s[4:5], s7, v5, v[3:4] +; CGP-NEXT: v_sub_i32_e32 v2, vcc, v7, v2 +; CGP-NEXT: v_subb_u32_e64 v3, s[4:5], v12, v5, vcc +; CGP-NEXT: v_sub_i32_e64 v5, s[4:5], v12, v5 ; CGP-NEXT: s_bfe_i32 s6, -1, 0x10000 -; CGP-NEXT: v_cmp_ge_u32_e64 s[4:5], v2, v5 +; CGP-NEXT: v_cmp_ge_u32_e64 s[4:5], v2, v4 ; CGP-NEXT: v_cndmask_b32_e64 v6, 0, -1, s[4:5] ; CGP-NEXT: v_mov_b32_e32 v7, s6 -; CGP-NEXT: v_cmp_eq_u32_e64 s[4:5], 0, v4 -; CGP-NEXT: v_subbrev_u32_e32 v3, vcc, 0, v3, vcc +; CGP-NEXT: v_cmp_eq_u32_e64 s[4:5], 0, v3 +; CGP-NEXT: v_subbrev_u32_e32 v5, vcc, 0, v5, vcc ; CGP-NEXT: v_cndmask_b32_e64 v6, v7, v6, s[4:5] -; CGP-NEXT: v_sub_i32_e32 v7, vcc, v2, v5 -; CGP-NEXT: v_subbrev_u32_e32 v3, vcc, 0, v3, vcc +; CGP-NEXT: v_sub_i32_e32 v7, vcc, v2, v4 +; CGP-NEXT: v_subbrev_u32_e32 v5, vcc, 0, v5, vcc ; CGP-NEXT: s_bfe_i32 s4, -1, 0x10000 -; CGP-NEXT: v_cmp_ge_u32_e32 vcc, v7, v5 +; CGP-NEXT: v_cmp_ge_u32_e32 vcc, v7, v4 ; CGP-NEXT: v_cndmask_b32_e64 v9, 0, -1, vcc ; CGP-NEXT: v_mov_b32_e32 v10, s4 -; CGP-NEXT: v_cmp_eq_u32_e32 vcc, 0, v3 +; CGP-NEXT: v_cmp_eq_u32_e32 vcc, 0, v5 ; CGP-NEXT: v_cndmask_b32_e32 v9, v10, v9, vcc -; CGP-NEXT: v_sub_i32_e32 v5, vcc, v7, v5 -; CGP-NEXT: v_subbrev_u32_e32 v10, vcc, 0, v3, vcc +; CGP-NEXT: v_sub_i32_e32 v4, vcc, v7, v4 +; CGP-NEXT: v_subbrev_u32_e32 v10, vcc, 0, v5, vcc ; CGP-NEXT: v_cmp_ne_u32_e32 vcc, 0, v9 -; CGP-NEXT: v_cndmask_b32_e32 v5, v7, v5, vcc -; CGP-NEXT: v_cndmask_b32_e32 v3, v3, v10, vcc +; CGP-NEXT: v_cndmask_b32_e32 v4, v7, v4, vcc +; CGP-NEXT: v_cndmask_b32_e32 v5, v5, v10, vcc ; CGP-NEXT: v_cmp_ne_u32_e32 vcc, 0, v6 -; CGP-NEXT: v_cndmask_b32_e32 v2, v2, v5, vcc -; CGP-NEXT: v_cndmask_b32_e32 v3, v4, v3, vcc +; CGP-NEXT: v_cndmask_b32_e32 v2, v2, v4, vcc +; CGP-NEXT: v_cndmask_b32_e32 v3, v3, v5, vcc ; CGP-NEXT: v_xor_b32_e32 v2, v2, v8 ; CGP-NEXT: v_xor_b32_e32 v3, v3, v8 ; CGP-NEXT: v_sub_i32_e32 v2, vcc, v2, v8