Index: lld/ELF/ARMErrataFix.cpp =================================================================== --- lld/ELF/ARMErrataFix.cpp +++ lld/ELF/ARMErrataFix.cpp @@ -24,6 +24,7 @@ #include "lld/Common/CommonLinkerContext.h" #include "lld/Common/Strings.h" #include "llvm/Support/Endian.h" +#include "llvm/Support/Error.h" #include using namespace llvm; @@ -176,6 +177,8 @@ void Patch657417Section::writeTo(uint8_t *buf) { // The base instruction of the patch is always a 32-bit unconditional branch. + if (config->be32 || config->be8) + error("Unsupported for big-endian"); if (isARM) write32le(buf, 0xea000000); else Index: lld/ELF/Arch/ARM.cpp =================================================================== --- lld/ELF/Arch/ARM.cpp +++ lld/ELF/Arch/ARM.cpp @@ -21,7 +21,7 @@ using namespace lld::elf; namespace { -class ARM final : public TargetInfo { +template class ARM final : public TargetInfo { public: ARM(); uint32_t calcEFlags() const override; @@ -46,7 +46,7 @@ }; } // namespace -ARM::ARM() { +template ARM::ARM() { copyRel = R_ARM_COPY; relativeRel = R_ARM_RELATIVE; iRelativeRel = R_ARM_IRELATIVE; @@ -64,7 +64,7 @@ defaultMaxPageSize = 65536; } -uint32_t ARM::calcEFlags() const { +template uint32_t ARM::calcEFlags() const { // The ABIFloatType is used by loaders to detect the floating point calling // convention. uint32_t abiFloatType = 0; @@ -80,7 +80,7 @@ return EF_ARM_EABI_VER5 | abiFloatType; } -RelExpr ARM::getRelExpr(RelType type, const Symbol &s, +template RelExpr ARM::getRelExpr(RelType type, const Symbol &s, const uint8_t *loc) const { switch (type) { case R_ARM_ABS32: @@ -177,19 +177,19 @@ } } -RelType ARM::getDynRel(RelType type) const { +template RelType ARM::getDynRel(RelType type) const { if ((type == R_ARM_ABS32) || (type == R_ARM_TARGET1 && !config->target1Rel)) return R_ARM_ABS32; return R_ARM_NONE; } -void ARM::writeGotPlt(uint8_t *buf, const Symbol &) const { - write32le(buf, in.plt->getVA()); +template void ARM::writeGotPlt(uint8_t *buf, const Symbol &) const { + write32(buf, in.plt->getVA()); } -void ARM::writeIgotPlt(uint8_t *buf, const Symbol &s) const { +template void ARM::writeIgotPlt(uint8_t *buf, const Symbol &s) const { // An ARM entry is the address of the ifunc resolver function. - write32le(buf, s.getVA()); + write32(buf, s.getVA()); } // Long form PLT Header that does not have any restrictions on the displacement @@ -205,12 +205,12 @@ write32(buf + 28, 0xd4d4d4d4); uint64_t gotPlt = in.gotPlt->getVA(); uint64_t l1 = in.plt->getVA() + 8; - write32le(buf + 16, gotPlt - l1 - 8); + write32(buf + 16, gotPlt - l1 - 8); } // The default PLT header requires the .got.plt to be within 128 Mb of the // .plt in the positive direction. -void ARM::writePltHeader(uint8_t *buf) const { +template void ARM::writePltHeader(uint8_t *buf) const { // Use a similar sequence to that in writePlt(), the difference is the calling // conventions mean we use lr instead of ip. The PLT entry is responsible for // saving lr on the stack, the dynamic loader is responsible for reloading @@ -228,17 +228,17 @@ writePltHeaderLong(buf); return; } - write32le(buf + 0, pltData[0]); - write32le(buf + 4, pltData[1] | ((offset >> 20) & 0xff)); - write32le(buf + 8, pltData[2] | ((offset >> 12) & 0xff)); - write32le(buf + 12, pltData[3] | (offset & 0xfff)); + write32(buf + 0, pltData[0]); + write32(buf + 4, pltData[1] | ((offset >> 20) & 0xff)); + write32(buf + 8, pltData[2] | ((offset >> 12) & 0xff)); + write32(buf + 12, pltData[3] | (offset & 0xfff)); memcpy(buf + 16, trapInstr.data(), 4); // Pad to 32-byte boundary memcpy(buf + 20, trapInstr.data(), 4); memcpy(buf + 24, trapInstr.data(), 4); memcpy(buf + 28, trapInstr.data(), 4); } -void ARM::addPltHeaderSymbols(InputSection &isec) const { +template void ARM::addPltHeaderSymbols(InputSection &isec) const { addSyntheticLocal("$a", STT_NOTYPE, 0, 0, isec); addSyntheticLocal("$d", STT_NOTYPE, 16, 0, isec); } @@ -252,12 +252,12 @@ write32(buf + 8, 0xe59cf000); // ldr pc, [ip] write32(buf + 12, 0x00000000); // L2: .word Offset(&(.got.plt) - L1 - 8 uint64_t l1 = pltEntryAddr + 4; - write32le(buf + 12, gotPltEntryAddr - l1 - 8); + write32(buf + 12, gotPltEntryAddr - l1 - 8); } // The default PLT entries require the .got.plt to be within 128 Mb of the // .plt in the positive direction. -void ARM::writePlt(uint8_t *buf, const Symbol &sym, +template void ARM::writePlt(uint8_t *buf, const Symbol &sym, uint64_t pltEntryAddr) const { // The PLT entry is similar to the example given in Appendix A of ELF for // the Arm Architecture. Instead of using the Group Relocations to find the @@ -276,18 +276,18 @@ writePltLong(buf, sym.getGotPltVA(), pltEntryAddr); return; } - write32le(buf + 0, pltData[0] | ((offset >> 20) & 0xff)); - write32le(buf + 4, pltData[1] | ((offset >> 12) & 0xff)); - write32le(buf + 8, pltData[2] | (offset & 0xfff)); + write32(buf + 0, pltData[0] | ((offset >> 20) & 0xff)); + write32(buf + 4, pltData[1] | ((offset >> 12) & 0xff)); + write32(buf + 8, pltData[2] | (offset & 0xfff)); memcpy(buf + 12, trapInstr.data(), 4); // Pad to 16-byte boundary } -void ARM::addPltSymbols(InputSection &isec, uint64_t off) const { +template void ARM::addPltSymbols(InputSection &isec, uint64_t off) const { addSyntheticLocal("$a", STT_NOTYPE, off, 0, isec); addSyntheticLocal("$d", STT_NOTYPE, off + 12, 0, isec); } -bool ARM::needsThunk(RelExpr expr, RelType type, const InputFile *file, +template bool ARM::needsThunk(RelExpr expr, RelType type, const InputFile *file, uint64_t branchAddr, const Symbol &s, int64_t a) const { // If s is an undefined weak symbol and does not have a PLT entry then it will @@ -327,7 +327,7 @@ return false; } -uint32_t ARM::getThunkSectionSpacing() const { +template uint32_t ARM::getThunkSectionSpacing() const { // The placing of pre-created ThunkSections is controlled by the value // thunkSectionSpacing returned by getThunkSectionSpacing(). The aim is to // place the ThunkSection such that all branches from the InputSections @@ -361,7 +361,7 @@ : 0x400000 - 0x7500; } -bool ARM::inBranchRange(RelType type, uint64_t src, uint64_t dst) const { +template bool ARM::inBranchRange(RelType type, uint64_t src, uint64_t dst) const { if ((dst & 0x1) == 0) // Destination is ARM, if ARM caller then Src is already 4-byte aligned. // If Thumb Caller (BLX) the Src address has bottom 2 bits cleared to ensure @@ -455,7 +455,7 @@ if (check && imm > 0xff) error(getErrorLocation(loc) + "unencodeable immediate " + Twine(val).str() + " for relocation " + toString(rel.type)); - write32le(loc, (read32le(loc) & 0xff3ff000) | opcode | rot | (imm & 0xff)); + write32(loc, (read32(loc) & 0xff3ff000) | opcode | rot | (imm & 0xff)); } static void encodeLdrGroup(uint8_t *loc, const Relocation &rel, uint64_t val, @@ -473,7 +473,7 @@ } uint32_t imm = getRemAndLZForGroup(group, val).first; checkUInt(loc, imm, 12, rel); - write32le(loc, (read32le(loc) & 0xff7ff000) | opcode | imm); + write32(loc, (read32(loc) & 0xff7ff000) | opcode | imm); } static void encodeLdrsGroup(uint8_t *loc, const Relocation &rel, uint64_t val, @@ -491,11 +491,11 @@ } uint32_t imm = getRemAndLZForGroup(group, val).first; checkUInt(loc, imm, 8, rel); - write32le(loc, (read32le(loc) & 0xff7ff0f0) | opcode | ((imm & 0xf0) << 4) | + write32(loc, (read32(loc) & 0xff7ff0f0) | opcode | ((imm & 0xf0) << 4) | (imm & 0xf)); } -void ARM::relocate(uint8_t *loc, const Relocation &rel, uint64_t val) const { +template void ARM::relocate(uint8_t *loc, const Relocation &rel, uint64_t val) const { switch (rel.type) { case R_ARM_ABS32: case R_ARM_BASE_PREL: @@ -514,11 +514,11 @@ case R_ARM_TLS_LE32: case R_ARM_TLS_TPOFF32: case R_ARM_TLS_DTPOFF32: - write32le(loc, val); + write32(loc, val); break; case R_ARM_PREL31: checkInt(loc, val, 31, rel); - write32le(loc, (read32le(loc) & 0x80000000) | (val & ~0x80000000)); + write32(loc, (read32(loc) & 0x80000000) | (val & ~0x80000000)); break; case R_ARM_CALL: { // R_ARM_CALL is used for BL and BLX instructions, for symbols of type @@ -528,7 +528,7 @@ // PLT entries are always ARM state so we know we don't need to interwork. assert(rel.sym); // R_ARM_CALL is always reached via relocate(). bool bit0Thumb = val & 1; - bool isBlx = (read32le(loc) & 0xfe000000) == 0xfa000000; + bool isBlx = (read32(loc) & 0xfe000000) == 0xfa000000; // lld 10.0 and before always used bit0Thumb when deciding to write a BLX // even when type not STT_FUNC. if (!rel.sym->isFunc() && isBlx != bit0Thumb) @@ -536,14 +536,14 @@ if (rel.sym->isFunc() ? bit0Thumb : isBlx) { // The BLX encoding is 0xfa:H:imm24 where Val = imm24:H:'1' checkInt(loc, val, 26, rel); - write32le(loc, 0xfa000000 | // opcode + write32(loc, 0xfa000000 | // opcode ((val & 2) << 23) | // H ((val >> 2) & 0x00ffffff)); // imm24 break; } // BLX (always unconditional) instruction to an ARM Target, select an // unconditional BL. - write32le(loc, 0xeb000000 | (read32le(loc) & 0x00ffffff)); + write32(loc, 0xeb000000 | (read32(loc) & 0x00ffffff)); // fall through as BL encoding is shared with B } [[fallthrough]]; @@ -551,26 +551,26 @@ case R_ARM_PC24: case R_ARM_PLT32: checkInt(loc, val, 26, rel); - write32le(loc, (read32le(loc) & ~0x00ffffff) | ((val >> 2) & 0x00ffffff)); + write32(loc, (read32(loc) & ~0x00ffffff) | ((val >> 2) & 0x00ffffff)); break; case R_ARM_THM_JUMP8: // We do a 9 bit check because val is right-shifted by 1 bit. checkInt(loc, val, 9, rel); - write16le(loc, (read32le(loc) & 0xff00) | ((val >> 1) & 0x00ff)); + write16(loc, (read32(loc) & 0xff00) | ((val >> 1) & 0x00ff)); break; case R_ARM_THM_JUMP11: // We do a 12 bit check because val is right-shifted by 1 bit. checkInt(loc, val, 12, rel); - write16le(loc, (read32le(loc) & 0xf800) | ((val >> 1) & 0x07ff)); + write16(loc, (read32(loc) & 0xf800) | ((val >> 1) & 0x07ff)); break; case R_ARM_THM_JUMP19: // Encoding T3: Val = S:J2:J1:imm6:imm11:0 checkInt(loc, val, 21, rel); - write16le(loc, - (read16le(loc) & 0xfbc0) | // opcode cond + write16(loc, + (read16(loc) & 0xfbc0) | // opcode cond ((val >> 10) & 0x0400) | // S ((val >> 12) & 0x003f)); // imm6 - write16le(loc + 2, + write16(loc + 2, 0x8000 | // opcode ((val >> 8) & 0x0800) | // J2 ((val >> 5) & 0x2000) | // J1 @@ -584,7 +584,7 @@ // PLT entries are always ARM state so we know we need to interwork. assert(rel.sym); // R_ARM_THM_CALL is always reached via relocate(). bool bit0Thumb = val & 1; - bool isBlx = (read16le(loc + 2) & 0x1000) == 0; + bool isBlx = (read16(loc + 2) & 0x1000) == 0; // lld 10.0 and before always used bit0Thumb when deciding to write a BLX // even when type not STT_FUNC. PLT entries generated by LLD are always ARM. if (!rel.sym->isFunc() && !rel.sym->isInPlt() && isBlx == bit0Thumb) @@ -594,19 +594,19 @@ // the BLX instruction may only be two byte aligned. This must be done // before overflow check. val = alignTo(val, 4); - write16le(loc + 2, read16le(loc + 2) & ~0x1000); + write16(loc + 2, read16(loc + 2) & ~0x1000); } else { - write16le(loc + 2, (read16le(loc + 2) & ~0x1000) | 1 << 12); + write16(loc + 2, (read16(loc + 2) & ~0x1000) | 1 << 12); } if (!config->armJ1J2BranchEncoding) { // Older Arm architectures do not support R_ARM_THM_JUMP24 and have // different encoding rules and range due to J1 and J2 always being 1. checkInt(loc, val, 23, rel); - write16le(loc, + write16(loc, 0xf000 | // opcode ((val >> 12) & 0x07ff)); // imm11 - write16le(loc + 2, - (read16le(loc + 2) & 0xd000) | // opcode + write16(loc + 2, + (read16(loc + 2) & 0xd000) | // opcode 0x2800 | // J1 == J2 == 1 ((val >> 1) & 0x07ff)); // imm11 break; @@ -617,12 +617,12 @@ case R_ARM_THM_JUMP24: // Encoding B T4, BL T1, BLX T2: Val = S:I1:I2:imm10:imm11:0 checkInt(loc, val, 25, rel); - write16le(loc, + write16(loc, 0xf000 | // opcode ((val >> 14) & 0x0400) | // S ((val >> 12) & 0x03ff)); // imm10 - write16le(loc + 2, - (read16le(loc + 2) & 0xd000) | // opcode + write16(loc + 2, + (read16(loc + 2) & 0xd000) | // opcode (((~(val >> 10)) ^ (val >> 11)) & 0x2000) | // J1 (((~(val >> 11)) ^ (val >> 13)) & 0x0800) | // J2 ((val >> 1) & 0x07ff)); // imm11 @@ -630,25 +630,27 @@ case R_ARM_MOVW_ABS_NC: case R_ARM_MOVW_PREL_NC: case R_ARM_MOVW_BREL_NC: - write32le(loc, (read32le(loc) & ~0x000f0fff) | ((val & 0xf000) << 4) | + write32(loc, (read32(loc) & ~0x000f0fff) | ((val & 0xf000) << 4) | (val & 0x0fff)); break; case R_ARM_MOVT_ABS: case R_ARM_MOVT_PREL: case R_ARM_MOVT_BREL: - write32le(loc, (read32le(loc) & ~0x000f0fff) | + write32(loc, (read32(loc) & ~0x000f0fff) | (((val >> 16) & 0xf000) << 4) | ((val >> 16) & 0xfff)); break; case R_ARM_THM_MOVT_ABS: case R_ARM_THM_MOVT_PREL: case R_ARM_THM_MOVT_BREL: // Encoding T1: A = imm4:i:imm3:imm8 - write16le(loc, - 0xf2c0 | // opcode - ((val >> 17) & 0x0400) | // i - ((val >> 28) & 0x000f)); // imm4 - write16le(loc + 2, - (read16le(loc + 2) & 0x8f00) | // opcode + + write16(loc, + 0xf2c0 | // opcode + ((val >> 17) & 0x0400) | // i + ((val >> 28) & 0x000f)); // imm4 + + write16(loc + 2, + (read16(loc + 2) & 0x8f00) | // opcode ((val >> 12) & 0x7000) | // imm3 ((val >> 16) & 0x00ff)); // imm8 break; @@ -656,12 +658,12 @@ case R_ARM_THM_MOVW_PREL_NC: case R_ARM_THM_MOVW_BREL_NC: // Encoding T3: A = imm4:i:imm3:imm8 - write16le(loc, + write16(loc, 0xf240 | // opcode ((val >> 1) & 0x0400) | // i ((val >> 12) & 0x000f)); // imm4 - write16le(loc + 2, - (read16le(loc + 2) & 0x8f00) | // opcode + write16(loc + 2, + (read16(loc + 2) & 0x8f00) | // opcode ((val << 4) & 0x7000) | // imm3 (val & 0x00ff)); // imm8 break; @@ -707,9 +709,9 @@ sub = 0x00a0; } checkUInt(loc, imm, 12, rel); - write16le(loc, (read16le(loc) & 0xfb0f) | sub | (imm & 0x800) >> 1); - write16le(loc + 2, - (read16le(loc + 2) & 0x8f00) | (imm & 0x700) << 4 | (imm & 0xff)); + write16(loc, (read16(loc) & 0xfb0f) | sub | (imm & 0x800) >> 1); + write16(loc + 2, + (read16(loc + 2) & 0x8f00) | (imm & 0x700) << 4 | (imm & 0xff)); break; } case R_ARM_THM_PC8: @@ -721,7 +723,7 @@ val &= ~0x1; checkUInt(loc, val, 10, rel); checkAlignment(loc, val, 4, rel); - write16le(loc, (read16le(loc) & 0xff00) | (val & 0x3fc) >> 2); + write16(loc, (read16(loc) & 0xff00) | (val & 0x3fc) >> 2); break; case R_ARM_THM_PC12: { // LDR (literal) encoding T2, add = (U == '1') imm12 @@ -738,8 +740,8 @@ u = 0; } checkUInt(loc, imm12, 12, rel); - write16le(loc, read16le(loc) | u); - write16le(loc + 2, (read16le(loc + 2) & 0xf000) | imm12); + write16(loc, read16(loc) | u); + write16(loc + 2, (read16(loc + 2) & 0xf000) | imm12); break; } default: @@ -747,7 +749,7 @@ } } -int64_t ARM::getImplicitAddend(const uint8_t *buf, RelType type) const { +template int64_t ARM::getImplicitAddend(const uint8_t *buf, RelType type) const { switch (type) { default: internalLinkerError(getErrorLocation(buf), @@ -773,22 +775,22 @@ case R_ARM_TLS_LE32: case R_ARM_TLS_LDO32: case R_ARM_TLS_TPOFF32: - return SignExtend64<32>(read32le(buf)); + return SignExtend64<32>(read32(buf)); case R_ARM_PREL31: - return SignExtend64<31>(read32le(buf)); + return SignExtend64<31>(read32(buf)); case R_ARM_CALL: case R_ARM_JUMP24: case R_ARM_PC24: case R_ARM_PLT32: - return SignExtend64<26>(read32le(buf) << 2); + return SignExtend64<26>(read32(buf) << 2); case R_ARM_THM_JUMP8: - return SignExtend64<9>(read16le(buf) << 1); + return SignExtend64<9>(read16(buf) << 1); case R_ARM_THM_JUMP11: - return SignExtend64<12>(read16le(buf) << 1); + return SignExtend64<12>(read16(buf) << 1); case R_ARM_THM_JUMP19: { // Encoding T3: A = S:J2:J1:imm10:imm6:0 - uint16_t hi = read16le(buf); - uint16_t lo = read16le(buf + 2); + uint16_t hi = read16(buf); + uint16_t lo = read16(buf + 2); return SignExtend64<20>(((hi & 0x0400) << 10) | // S ((lo & 0x0800) << 8) | // J2 ((lo & 0x2000) << 5) | // J1 @@ -799,8 +801,8 @@ if (!config->armJ1J2BranchEncoding) { // Older Arm architectures do not support R_ARM_THM_JUMP24 and have // different encoding rules and range due to J1 and J2 always being 1. - uint16_t hi = read16le(buf); - uint16_t lo = read16le(buf + 2); + uint16_t hi = read16(buf); + uint16_t lo = read16(buf + 2); return SignExtend64<22>(((hi & 0x7ff) << 12) | // imm11 ((lo & 0x7ff) << 1)); // imm11:0 break; @@ -809,8 +811,8 @@ case R_ARM_THM_JUMP24: { // Encoding B T4, BL T1, BLX T2: A = S:I1:I2:imm10:imm11:0 // I1 = NOT(J1 EOR S), I2 = NOT(J2 EOR S) - uint16_t hi = read16le(buf); - uint16_t lo = read16le(buf + 2); + uint16_t hi = read16(buf); + uint16_t lo = read16(buf + 2); return SignExtend64<24>(((hi & 0x0400) << 14) | // S (~((lo ^ (hi << 3)) << 10) & 0x00800000) | // I1 (~((lo ^ (hi << 1)) << 11) & 0x00400000) | // I2 @@ -825,7 +827,7 @@ case R_ARM_MOVT_PREL: case R_ARM_MOVW_BREL_NC: case R_ARM_MOVT_BREL: { - uint64_t val = read32le(buf) & 0x000f0fff; + uint64_t val = read32(buf) & 0x000f0fff; return SignExtend64<16>(((val & 0x000f0000) >> 4) | (val & 0x00fff)); } case R_ARM_THM_MOVW_ABS_NC: @@ -835,8 +837,8 @@ case R_ARM_THM_MOVW_BREL_NC: case R_ARM_THM_MOVT_BREL: { // Encoding T3: A = imm4:i:imm3:imm8 - uint16_t hi = read16le(buf); - uint16_t lo = read16le(buf + 2); + uint16_t hi = read16(buf); + uint16_t lo = read16(buf + 2); return SignExtend64<16>(((hi & 0x000f) << 12) | // imm4 ((hi & 0x0400) << 1) | // i ((lo & 0x7000) >> 4) | // imm3 @@ -851,7 +853,7 @@ // right rotation and 8-bit constant. After the rotation the value // is zero-extended. When bit 23 is set the instruction is an add, when // bit 22 is set it is a sub. - uint32_t instr = read32le(buf); + uint32_t instr = read32(buf); uint32_t val = rotr32(instr & 0xff, ((instr & 0xf00) >> 8) * 2); return (instr & 0x00400000) ? -val : val; } @@ -860,15 +862,15 @@ case R_ARM_LDR_PC_G2: { // ADR (literal) add = bit23, sub = bit22 // LDR (literal) u = bit23 unsigned imm12 - bool u = read32le(buf) & 0x00800000; - uint32_t imm12 = read32le(buf) & 0xfff; + bool u = read32(buf) & 0x00800000; + uint32_t imm12 = read32(buf) & 0xfff; return u ? imm12 : -imm12; } case R_ARM_LDRS_PC_G0: case R_ARM_LDRS_PC_G1: case R_ARM_LDRS_PC_G2: { // LDRD/LDRH/LDRSB/LDRSH (literal) u = bit23 unsigned imm8 - uint32_t opcode = read32le(buf); + uint32_t opcode = read32(buf); bool u = opcode & 0x00800000; uint32_t imm4l = opcode & 0xf; uint32_t imm4h = (opcode & 0xf00) >> 4; @@ -878,8 +880,8 @@ // Thumb2 ADR, which is an alias for a sub or add instruction with an // unsigned immediate. // ADR encoding T2 (sub), T3 (add) i:imm3:imm8 - uint16_t hi = read16le(buf); - uint16_t lo = read16le(buf + 2); + uint16_t hi = read16(buf); + uint16_t lo = read16(buf + 2); uint64_t imm = (hi & 0x0400) << 1 | // i (lo & 0x7000) >> 4 | // imm3 (lo & 0x00ff); // imm8 @@ -891,11 +893,11 @@ // From ELF for the ARM Architecture the initial signed addend is formed // from an unsigned field using expression (((imm8:00 + 4) & 0x3ff) – 4) // this trick permits the PC bias of -4 to be encoded using imm8 = 0xff - return ((((read16le(buf) & 0xff) << 2) + 4) & 0x3ff) - 4; + return ((((read16(buf) & 0xff) << 2) + 4) & 0x3ff) - 4; case R_ARM_THM_PC12: { // LDR (literal) encoding T2, add = (U == '1') imm12 - bool u = read16le(buf) & 0x0080; - uint64_t imm12 = read16le(buf + 2) & 0x0fff; + bool u = read16(buf) & 0x0080; + uint64_t imm12 = read16(buf + 2) & 0x0fff; return u ? imm12 : -imm12; } case R_ARM_NONE: @@ -906,7 +908,10 @@ } } -TargetInfo *elf::getARMTargetInfo() { - static ARM target; +template TargetInfo *elf::getARMTargetInfo() { + static ARM target; return ⌖ } + +template TargetInfo *elf::getARMTargetInfo(); +template TargetInfo *elf::getARMTargetInfo(); \ No newline at end of file Index: lld/ELF/Config.h =================================================================== --- lld/ELF/Config.h +++ lld/ELF/Config.h @@ -192,6 +192,8 @@ bool armHasMovtMovw = false; bool armJ1J2BranchEncoding = false; bool asNeeded = false; + bool be32 = false; + bool be8 = false; BsymbolicKind bsymbolic = BsymbolicKind::None; bool callGraphProfileSort; bool checkSections; Index: lld/ELF/Driver.cpp =================================================================== --- lld/ELF/Driver.cpp +++ lld/ELF/Driver.cpp @@ -160,6 +160,7 @@ .Cases("aarch64elf", "aarch64linux", {ELF64LEKind, EM_AARCH64}) .Cases("aarch64elfb", "aarch64linuxb", {ELF64BEKind, EM_AARCH64}) .Cases("armelf", "armelf_linux_eabi", {ELF32LEKind, EM_ARM}) + .Cases("armelfb", "armelfb_linux_eabi", {ELF32BEKind, EM_ARM}) .Case("elf32_x86_64", {ELF32LEKind, EM_X86_64}) .Cases("elf32btsmip", "elf32btsmipn32", {ELF32BEKind, EM_MIPS}) .Cases("elf32ltsmip", "elf32ltsmipn32", {ELF32LEKind, EM_MIPS}) @@ -342,6 +343,9 @@ if (config->fixCortexA53Errata843419 && config->emachine != EM_AARCH64) error("--fix-cortex-a53-843419 is only supported on AArch64 targets"); + if (config->be8 && config->emachine != EM_ARM) + error("--be8 is only supported on Arm targets"); + if (config->fixCortexA8 && config->emachine != EM_ARM) error("--fix-cortex-a8 is only supported on ARM targets"); @@ -1067,6 +1071,9 @@ OPT_no_android_memtag_stack, false); config->androidMemtagMode = getMemtagMode(args); config->auxiliaryList = args::getStrings(args, OPT_auxiliary); + config->be8 = args.hasArg(OPT_be8); + if (config->be8) error("byte invariant not yet supported"); + config->be32 = args.hasArg(OPT_be32); if (opt::Arg *arg = args.getLastArg(OPT_Bno_symbolic, OPT_Bsymbolic_non_weak_functions, OPT_Bsymbolic_functions, OPT_Bsymbolic)) { Index: lld/ELF/Options.td =================================================================== --- lld/ELF/Options.td +++ lld/ELF/Options.td @@ -36,6 +36,10 @@ defm auxiliary: Eq<"auxiliary", "Set DT_AUXILIARY field to the specified name">; +def be8: FF<"be8">, HelpText<"Big-endian via a byte invariant, reverses the endianness of the instructions " + "to give little-endian code and big-endian data for input objects that have been compiled or assembled as big-endian">; +def be32: FF<"be32">, HelpText<"Big-endian via a word invariant, produces big-endian code and data">; + def Bno_symbolic: F<"Bno-symbolic">, HelpText<"Don't bind default visibility defined symbols locally for -shared (default)">; def Bsymbolic: F<"Bsymbolic">, HelpText<"Bind default visibility defined symbols locally for -shared">; Index: lld/ELF/ScriptParser.cpp =================================================================== --- lld/ELF/ScriptParser.cpp +++ lld/ELF/ScriptParser.cpp @@ -419,6 +419,7 @@ .Case("elf32-avr", {ELF32LEKind, EM_AVR}) .Case("elf32-iamcu", {ELF32LEKind, EM_IAMCU}) .Case("elf32-littlearm", {ELF32LEKind, EM_ARM}) + .Case("elf32-bigarm", {ELF32BEKind, EM_ARM}) .Case("elf32-x86-64", {ELF32LEKind, EM_X86_64}) .Case("elf64-aarch64", {ELF64LEKind, EM_AARCH64}) .Case("elf64-littleaarch64", {ELF64LEKind, EM_AARCH64}) Index: lld/ELF/Target.h =================================================================== --- lld/ELF/Target.h +++ lld/ELF/Target.h @@ -169,7 +169,6 @@ TargetInfo *getAArch64TargetInfo(); TargetInfo *getAMDGPUTargetInfo(); -TargetInfo *getARMTargetInfo(); TargetInfo *getAVRTargetInfo(); TargetInfo *getHexagonTargetInfo(); TargetInfo *getMSP430TargetInfo(); @@ -179,6 +178,7 @@ TargetInfo *getSPARCV9TargetInfo(); TargetInfo *getX86TargetInfo(); TargetInfo *getX86_64TargetInfo(); +template TargetInfo *getARMTargetInfo(); template TargetInfo *getMipsTargetInfo(); struct ErrorPlace { Index: lld/ELF/Target.cpp =================================================================== --- lld/ELF/Target.cpp +++ lld/ELF/Target.cpp @@ -57,7 +57,14 @@ case EM_AMDGPU: return getAMDGPUTargetInfo(); case EM_ARM: - return getARMTargetInfo(); + switch (config->ekind) { + case ELF32BEKind: + return getARMTargetInfo(); + case ELF32LEKind: + return getARMTargetInfo(); + default: + llvm_unreachable("unsupported ARM target"); + } case EM_AVR: return getAVRTargetInfo(); case EM_HEXAGON: Index: lld/ELF/Writer.cpp =================================================================== --- lld/ELF/Writer.cpp +++ lld/ELF/Writer.cpp @@ -2770,6 +2770,9 @@ eHdr->e_entry = getEntryAddr(); eHdr->e_shoff = sectionHeaderOff; + if (config->be8 && eHdr->e_type == ET_EXEC && !config->be32) + eHdr->e_flags |= 0x00800000; + // Write the section header table. // // The ELF header can only store numbers up to SHN_LORESERVE in the e_shnum Index: lld/docs/ld.lld.1 =================================================================== --- lld/docs/ld.lld.1 +++ lld/docs/ld.lld.1 @@ -88,6 +88,10 @@ .It Fl Bsymbolic-non-weak-functions Bind default visibility defined STB_GLOBAL function symbols locally for .Fl shared. +.It Fl --be8 +The default Byte Addressing mode for ARMv6 and later big-endian images. The linker reverses the endianness of the instructions to give little-endian code and big-endian data for input objects that have been compiled or assembled as big-endian. +.It Fl --be32 +Specifies legacy Word Invariant Addressing big-endian mode, that is, identical to big-endian images prior to ARMv6. This produces big-endian code and data. .It Fl -build-id Ns = Ns Ar value Generate a build ID note. .Ar value