diff --git a/lld/ELF/Arch/ARM.cpp b/lld/ELF/Arch/ARM.cpp
--- a/lld/ELF/Arch/ARM.cpp
+++ b/lld/ELF/Arch/ARM.cpp
@@ -21,7 +21,7 @@
 using namespace lld::elf;
 
 namespace {
-class ARM final : public TargetInfo {
+template <class ELFT> class ARM final : public TargetInfo {
 public:
   ARM();
   uint32_t calcEFlags() const override;
@@ -46,7 +46,7 @@
 };
 } // namespace
 
-ARM::ARM() {
+template <class ELFT> ARM<ELFT>::ARM() {
   copyRel = R_ARM_COPY;
   relativeRel = R_ARM_RELATIVE;
   iRelativeRel = R_ARM_IRELATIVE;
@@ -64,7 +64,7 @@
   defaultMaxPageSize = 65536;
 }
 
-uint32_t ARM::calcEFlags() const {
+template <class ELFT> uint32_t ARM<ELFT>::calcEFlags() const {
   // The ABIFloatType is used by loaders to detect the floating point calling
   // convention.
   uint32_t abiFloatType = 0;
@@ -80,7 +80,7 @@
   return EF_ARM_EABI_VER5 | abiFloatType;
 }
 
-RelExpr ARM::getRelExpr(RelType type, const Symbol &s,
+template <class ELFT> RelExpr ARM<ELFT>::getRelExpr(RelType type, const Symbol &s,
                         const uint8_t *loc) const {
   switch (type) {
   case R_ARM_ABS32:
@@ -177,19 +177,19 @@
   }
 }
 
-RelType ARM::getDynRel(RelType type) const {
+template <class ELFT> RelType ARM<ELFT>::getDynRel(RelType type) const {
   if ((type == R_ARM_ABS32) || (type == R_ARM_TARGET1 && !config->target1Rel))
     return R_ARM_ABS32;
   return R_ARM_NONE;
 }
 
-void ARM::writeGotPlt(uint8_t *buf, const Symbol &) const {
-  write32le(buf, in.plt->getVA());
+template <class ELFT> void ARM<ELFT>::writeGotPlt(uint8_t *buf, const Symbol &) const {
+  write32(buf, in.plt->getVA());
 }
 
-void ARM::writeIgotPlt(uint8_t *buf, const Symbol &s) const {
+template <class ELFT> void ARM<ELFT>::writeIgotPlt(uint8_t *buf, const Symbol &s) const {
   // An ARM entry is the address of the ifunc resolver function.
-  write32le(buf, s.getVA());
+  write32(buf, s.getVA());
 }
 
 // Long form PLT Header that does not have any restrictions on the displacement
@@ -205,12 +205,12 @@
   write32(buf + 28, 0xd4d4d4d4);
   uint64_t gotPlt = in.gotPlt->getVA();
   uint64_t l1 = in.plt->getVA() + 8;
-  write32le(buf + 16, gotPlt - l1 - 8);
+  write32(buf + 16, gotPlt - l1 - 8);
 }
 
 // The default PLT header requires the .got.plt to be within 128 Mb of the
 // .plt in the positive direction.
-void ARM::writePltHeader(uint8_t *buf) const {
+template <class ELFT> void ARM<ELFT>::writePltHeader(uint8_t *buf) const {
   // Use a similar sequence to that in writePlt(), the difference is the calling
   // conventions mean we use lr instead of ip. The PLT entry is responsible for
   // saving lr on the stack, the dynamic loader is responsible for reloading
@@ -228,17 +228,17 @@
     writePltHeaderLong(buf);
     return;
   }
-  write32le(buf + 0, pltData[0]);
-  write32le(buf + 4, pltData[1] | ((offset >> 20) & 0xff));
-  write32le(buf + 8, pltData[2] | ((offset >> 12) & 0xff));
-  write32le(buf + 12, pltData[3] | (offset & 0xfff));
+  write32(buf + 0, pltData[0]);
+  write32(buf + 4, pltData[1] | ((offset >> 20) & 0xff));
+  write32(buf + 8, pltData[2] | ((offset >> 12) & 0xff));
+  write32(buf + 12, pltData[3] | (offset & 0xfff));
   memcpy(buf + 16, trapInstr.data(), 4); // Pad to 32-byte boundary
   memcpy(buf + 20, trapInstr.data(), 4);
   memcpy(buf + 24, trapInstr.data(), 4);
   memcpy(buf + 28, trapInstr.data(), 4);
 }
 
-void ARM::addPltHeaderSymbols(InputSection &isec) const {
+template <class ELFT> void ARM<ELFT>::addPltHeaderSymbols(InputSection &isec) const {
   addSyntheticLocal("$a", STT_NOTYPE, 0, 0, isec);
   addSyntheticLocal("$d", STT_NOTYPE, 16, 0, isec);
 }
@@ -252,12 +252,12 @@
   write32(buf + 8, 0xe59cf000);   //     ldr pc, [ip]
   write32(buf + 12, 0x00000000);  // L2: .word   Offset(&(.got.plt) - L1 - 8
   uint64_t l1 = pltEntryAddr + 4;
-  write32le(buf + 12, gotPltEntryAddr - l1 - 8);
+  write32(buf + 12, gotPltEntryAddr - l1 - 8);
 }
 
 // The default PLT entries require the .got.plt to be within 128 Mb of the
 // .plt in the positive direction.
-void ARM::writePlt(uint8_t *buf, const Symbol &sym,
+template <class ELFT> void ARM<ELFT>::writePlt(uint8_t *buf, const Symbol &sym,
                    uint64_t pltEntryAddr) const {
   // The PLT entry is similar to the example given in Appendix A of ELF for
   // the Arm Architecture. Instead of using the Group Relocations to find the
@@ -276,18 +276,18 @@
     writePltLong(buf, sym.getGotPltVA(), pltEntryAddr);
     return;
   }
-  write32le(buf + 0, pltData[0] | ((offset >> 20) & 0xff));
-  write32le(buf + 4, pltData[1] | ((offset >> 12) & 0xff));
-  write32le(buf + 8, pltData[2] | (offset & 0xfff));
+  write32(buf + 0, pltData[0] | ((offset >> 20) & 0xff));
+  write32(buf + 4, pltData[1] | ((offset >> 12) & 0xff));
+  write32(buf + 8, pltData[2] | (offset & 0xfff));
   memcpy(buf + 12, trapInstr.data(), 4); // Pad to 16-byte boundary
 }
 
-void ARM::addPltSymbols(InputSection &isec, uint64_t off) const {
+template <class ELFT> void ARM<ELFT>::addPltSymbols(InputSection &isec, uint64_t off) const {
   addSyntheticLocal("$a", STT_NOTYPE, off, 0, isec);
   addSyntheticLocal("$d", STT_NOTYPE, off + 12, 0, isec);
 }
 
-bool ARM::needsThunk(RelExpr expr, RelType type, const InputFile *file,
+template <class ELFT> bool ARM<ELFT>::needsThunk(RelExpr expr, RelType type, const InputFile *file,
                      uint64_t branchAddr, const Symbol &s,
                      int64_t a) const {
   // If s is an undefined weak symbol and does not have a PLT entry then it will
@@ -329,7 +329,7 @@
   return false;
 }
 
-uint32_t ARM::getThunkSectionSpacing() const {
+template <class ELFT> uint32_t ARM<ELFT>::getThunkSectionSpacing() const {
   // The placing of pre-created ThunkSections is controlled by the value
   // thunkSectionSpacing returned by getThunkSectionSpacing(). The aim is to
   // place the ThunkSection such that all branches from the InputSections
@@ -363,7 +363,7 @@
                                          : 0x400000 - 0x7500;
 }
 
-bool ARM::inBranchRange(RelType type, uint64_t src, uint64_t dst) const {
+template <class ELFT> bool ARM<ELFT>::inBranchRange(RelType type, uint64_t src, uint64_t dst) const {
   if ((dst & 0x1) == 0)
     // Destination is ARM, if ARM caller then Src is already 4-byte aligned.
     // If Thumb Caller (BLX) the Src address has bottom 2 bits cleared to ensure
@@ -457,7 +457,7 @@
   if (check && imm > 0xff)
     error(getErrorLocation(loc) + "unencodeable immediate " + Twine(val).str() +
           " for relocation " + toString(rel.type));
-  write32le(loc, (read32le(loc) & 0xff3ff000) | opcode | rot | (imm & 0xff));
+  write32(loc, (read32(loc) & 0xff3ff000) | opcode | rot | (imm & 0xff));
 }
 
 static void encodeLdrGroup(uint8_t *loc, const Relocation &rel, uint64_t val,
@@ -475,7 +475,7 @@
   }
   uint32_t imm = getRemAndLZForGroup(group, val).first;
   checkUInt(loc, imm, 12, rel);
-  write32le(loc, (read32le(loc) & 0xff7ff000) | opcode | imm);
+  write32(loc, (read32(loc) & 0xff7ff000) | opcode | imm);
 }
 
 static void encodeLdrsGroup(uint8_t *loc, const Relocation &rel, uint64_t val,
@@ -493,11 +493,11 @@
   }
   uint32_t imm = getRemAndLZForGroup(group, val).first;
   checkUInt(loc, imm, 8, rel);
-  write32le(loc, (read32le(loc) & 0xff7ff0f0) | opcode | ((imm & 0xf0) << 4) |
+  write32(loc, (read32(loc) & 0xff7ff0f0) | opcode | ((imm & 0xf0) << 4) |
                      (imm & 0xf));
 }
 
-void ARM::relocate(uint8_t *loc, const Relocation &rel, uint64_t val) const {
+template <class ELFT> void ARM<ELFT>::relocate(uint8_t *loc, const Relocation &rel, uint64_t val) const {
   switch (rel.type) {
   case R_ARM_ABS32:
   case R_ARM_BASE_PREL:
@@ -516,11 +516,11 @@
   case R_ARM_TLS_LE32:
   case R_ARM_TLS_TPOFF32:
   case R_ARM_TLS_DTPOFF32:
-    write32le(loc, val);
+    write32(loc, val);
     break;
   case R_ARM_PREL31:
     checkInt(loc, val, 31, rel);
-    write32le(loc, (read32le(loc) & 0x80000000) | (val & ~0x80000000));
+    write32(loc, (read32(loc) & 0x80000000) | (val & ~0x80000000));
     break;
   case R_ARM_CALL: {
     // R_ARM_CALL is used for BL and BLX instructions, for symbols of type
@@ -530,7 +530,7 @@
     // PLT entries are always ARM state so we know we don't need to interwork.
     assert(rel.sym); // R_ARM_CALL is always reached via relocate().
     bool bit0Thumb = val & 1;
-    bool isBlx = (read32le(loc) & 0xfe000000) == 0xfa000000;
+    bool isBlx = (read32(loc) & 0xfe000000) == 0xfa000000;
     // lld 10.0 and before always used bit0Thumb when deciding to write a BLX
     // even when type not STT_FUNC.
     if (!rel.sym->isFunc() && isBlx != bit0Thumb)
@@ -538,14 +538,14 @@
     if (rel.sym->isFunc() ? bit0Thumb : isBlx) {
       // The BLX encoding is 0xfa:H:imm24 where Val = imm24:H:'1'
       checkInt(loc, val, 26, rel);
-      write32le(loc, 0xfa000000 |                    // opcode
+      write32(loc, 0xfa000000 |                    // opcode
                          ((val & 2) << 23) |         // H
                          ((val >> 2) & 0x00ffffff)); // imm24
       break;
     }
     // BLX (always unconditional) instruction to an ARM Target, select an
     // unconditional BL.
-    write32le(loc, 0xeb000000 | (read32le(loc) & 0x00ffffff));
+    write32(loc, 0xeb000000 | (read32(loc) & 0x00ffffff));
     // fall through as BL encoding is shared with B
   }
     [[fallthrough]];
@@ -553,26 +553,26 @@
   case R_ARM_PC24:
   case R_ARM_PLT32:
     checkInt(loc, val, 26, rel);
-    write32le(loc, (read32le(loc) & ~0x00ffffff) | ((val >> 2) & 0x00ffffff));
+    write32(loc, (read32(loc) & ~0x00ffffff) | ((val >> 2) & 0x00ffffff));
     break;
   case R_ARM_THM_JUMP8:
     // We do a 9 bit check because val is right-shifted by 1 bit.
     checkInt(loc, val, 9, rel);
-    write16le(loc, (read32le(loc) & 0xff00) | ((val >> 1) & 0x00ff));
+    write16(loc, (read32(loc) & 0xff00) | ((val >> 1) & 0x00ff));
     break;
   case R_ARM_THM_JUMP11:
     // We do a 12 bit check because val is right-shifted by 1 bit.
     checkInt(loc, val, 12, rel);
-    write16le(loc, (read32le(loc) & 0xf800) | ((val >> 1) & 0x07ff));
+    write16(loc, (read32(loc) & 0xf800) | ((val >> 1) & 0x07ff));
     break;
   case R_ARM_THM_JUMP19:
     // Encoding T3: Val = S:J2:J1:imm6:imm11:0
     checkInt(loc, val, 21, rel);
-    write16le(loc,
-              (read16le(loc) & 0xfbc0) |   // opcode cond
+    write16(loc,
+              (read16(loc) & 0xfbc0) |   // opcode cond
                   ((val >> 10) & 0x0400) | // S
                   ((val >> 12) & 0x003f)); // imm6
-    write16le(loc + 2,
+    write16(loc + 2,
               0x8000 |                    // opcode
                   ((val >> 8) & 0x0800) | // J2
                   ((val >> 5) & 0x2000) | // J1
@@ -586,7 +586,7 @@
     // PLT entries are always ARM state so we know we need to interwork.
     assert(rel.sym); // R_ARM_THM_CALL is always reached via relocate().
     bool bit0Thumb = val & 1;
-    bool isBlx = (read16le(loc + 2) & 0x1000) == 0;
+    bool isBlx = (read16(loc + 2) & 0x1000) == 0;
     // lld 10.0 and before always used bit0Thumb when deciding to write a BLX
     // even when type not STT_FUNC. PLT entries generated by LLD are always ARM.
     if (!rel.sym->isFunc() && !rel.sym->isInPlt() && isBlx == bit0Thumb)
@@ -596,19 +596,19 @@
       // the BLX instruction may only be two byte aligned. This must be done
       // before overflow check.
       val = alignTo(val, 4);
-      write16le(loc + 2, read16le(loc + 2) & ~0x1000);
+      write16(loc + 2, read16(loc + 2) & ~0x1000);
     } else {
-      write16le(loc + 2, (read16le(loc + 2) & ~0x1000) | 1 << 12);
+      write16(loc + 2, (read16(loc + 2) & ~0x1000) | 1 << 12);
     }
     if (!config->armJ1J2BranchEncoding) {
       // Older Arm architectures do not support R_ARM_THM_JUMP24 and have
       // different encoding rules and range due to J1 and J2 always being 1.
       checkInt(loc, val, 23, rel);
-      write16le(loc,
+      write16(loc,
                 0xf000 |                     // opcode
                     ((val >> 12) & 0x07ff)); // imm11
-      write16le(loc + 2,
-                (read16le(loc + 2) & 0xd000) | // opcode
+      write16(loc + 2,
+                (read16(loc + 2) & 0xd000) | // opcode
                     0x2800 |                   // J1 == J2 == 1
                     ((val >> 1) & 0x07ff));    // imm11
       break;
@@ -619,12 +619,12 @@
   case R_ARM_THM_JUMP24:
     // Encoding B  T4, BL T1, BLX T2: Val = S:I1:I2:imm10:imm11:0
     checkInt(loc, val, 25, rel);
-    write16le(loc,
+    write16(loc,
               0xf000 |                     // opcode
                   ((val >> 14) & 0x0400) | // S
                   ((val >> 12) & 0x03ff)); // imm10
-    write16le(loc + 2,
-              (read16le(loc + 2) & 0xd000) |                  // opcode
+    write16(loc + 2,
+              (read16(loc + 2) & 0xd000) |                  // opcode
                   (((~(val >> 10)) ^ (val >> 11)) & 0x2000) | // J1
                   (((~(val >> 11)) ^ (val >> 13)) & 0x0800) | // J2
                   ((val >> 1) & 0x07ff));                     // imm11
@@ -632,25 +632,27 @@
   case R_ARM_MOVW_ABS_NC:
   case R_ARM_MOVW_PREL_NC:
   case R_ARM_MOVW_BREL_NC:
-    write32le(loc, (read32le(loc) & ~0x000f0fff) | ((val & 0xf000) << 4) |
+    write32(loc, (read32(loc) & ~0x000f0fff) | ((val & 0xf000) << 4) |
                        (val & 0x0fff));
     break;
   case R_ARM_MOVT_ABS:
   case R_ARM_MOVT_PREL:
   case R_ARM_MOVT_BREL:
-    write32le(loc, (read32le(loc) & ~0x000f0fff) |
+    write32(loc, (read32(loc) & ~0x000f0fff) |
                        (((val >> 16) & 0xf000) << 4) | ((val >> 16) & 0xfff));
     break;
   case R_ARM_THM_MOVT_ABS:
   case R_ARM_THM_MOVT_PREL:
   case R_ARM_THM_MOVT_BREL:
     // Encoding T1: A = imm4:i:imm3:imm8
-    write16le(loc,
-              0xf2c0 |                     // opcode
-                  ((val >> 17) & 0x0400) | // i
-                  ((val >> 28) & 0x000f)); // imm4
-    write16le(loc + 2,
-              (read16le(loc + 2) & 0x8f00) | // opcode
+
+    write16(loc,
+            0xf2c0 |                     // opcode
+                ((val >> 17) & 0x0400) | // i
+                ((val >> 28) & 0x000f)); // imm4
+
+    write16(loc + 2,
+              (read16(loc + 2) & 0x8f00) | // opcode
                   ((val >> 12) & 0x7000) |   // imm3
                   ((val >> 16) & 0x00ff));   // imm8
     break;
@@ -658,12 +660,12 @@
   case R_ARM_THM_MOVW_PREL_NC:
   case R_ARM_THM_MOVW_BREL_NC:
     // Encoding T3: A = imm4:i:imm3:imm8
-    write16le(loc,
+    write16(loc,
               0xf240 |                     // opcode
                   ((val >> 1) & 0x0400) |  // i
                   ((val >> 12) & 0x000f)); // imm4
-    write16le(loc + 2,
-              (read16le(loc + 2) & 0x8f00) | // opcode
+    write16(loc + 2,
+              (read16(loc + 2) & 0x8f00) | // opcode
                   ((val << 4) & 0x7000) |    // imm3
                   (val & 0x00ff));           // imm8
     break;
@@ -709,9 +711,9 @@
       sub = 0x00a0;
     }
     checkUInt(loc, imm, 12, rel);
-    write16le(loc, (read16le(loc) & 0xfb0f) | sub | (imm & 0x800) >> 1);
-    write16le(loc + 2,
-              (read16le(loc + 2) & 0x8f00) | (imm & 0x700) << 4 | (imm & 0xff));
+    write16(loc, (read16(loc) & 0xfb0f) | sub | (imm & 0x800) >> 1);
+    write16(loc + 2,
+              (read16(loc + 2) & 0x8f00) | (imm & 0x700) << 4 | (imm & 0xff));
     break;
   }
   case R_ARM_THM_PC8:
@@ -723,7 +725,7 @@
       val &= ~0x1;
     checkUInt(loc, val, 10, rel);
     checkAlignment(loc, val, 4, rel);
-    write16le(loc, (read16le(loc) & 0xff00) | (val & 0x3fc) >> 2);
+    write16(loc, (read16(loc) & 0xff00) | (val & 0x3fc) >> 2);
     break;
   case R_ARM_THM_PC12: {
     // LDR (literal) encoding T2, add = (U == '1') imm12
@@ -740,8 +742,8 @@
       u = 0;
     }
     checkUInt(loc, imm12, 12, rel);
-    write16le(loc, read16le(loc) | u);
-    write16le(loc + 2, (read16le(loc + 2) & 0xf000) | imm12);
+    write16(loc, read16(loc) | u);
+    write16(loc + 2, (read16(loc + 2) & 0xf000) | imm12);
     break;
   }
   default:
@@ -749,7 +751,7 @@
   }
 }
 
-int64_t ARM::getImplicitAddend(const uint8_t *buf, RelType type) const {
+template <class ELFT> int64_t ARM<ELFT>::getImplicitAddend(const uint8_t *buf, RelType type) const {
   switch (type) {
   default:
     internalLinkerError(getErrorLocation(buf),
@@ -775,22 +777,22 @@
   case R_ARM_TLS_LE32:
   case R_ARM_TLS_LDO32:
   case R_ARM_TLS_TPOFF32:
-    return SignExtend64<32>(read32le(buf));
+    return SignExtend64<32>(read32(buf));
   case R_ARM_PREL31:
-    return SignExtend64<31>(read32le(buf));
+    return SignExtend64<31>(read32(buf));
   case R_ARM_CALL:
   case R_ARM_JUMP24:
   case R_ARM_PC24:
   case R_ARM_PLT32:
-    return SignExtend64<26>(read32le(buf) << 2);
+    return SignExtend64<26>(read32(buf) << 2);
   case R_ARM_THM_JUMP8:
-    return SignExtend64<9>(read16le(buf) << 1);
+    return SignExtend64<9>(read16(buf) << 1);
   case R_ARM_THM_JUMP11:
-    return SignExtend64<12>(read16le(buf) << 1);
+    return SignExtend64<12>(read16(buf) << 1);
   case R_ARM_THM_JUMP19: {
     // Encoding T3: A = S:J2:J1:imm10:imm6:0
-    uint16_t hi = read16le(buf);
-    uint16_t lo = read16le(buf + 2);
+    uint16_t hi = read16(buf);
+    uint16_t lo = read16(buf + 2);
     return SignExtend64<20>(((hi & 0x0400) << 10) | // S
                             ((lo & 0x0800) << 8) |  // J2
                             ((lo & 0x2000) << 5) |  // J1
@@ -801,8 +803,8 @@
     if (!config->armJ1J2BranchEncoding) {
       // Older Arm architectures do not support R_ARM_THM_JUMP24 and have
       // different encoding rules and range due to J1 and J2 always being 1.
-      uint16_t hi = read16le(buf);
-      uint16_t lo = read16le(buf + 2);
+      uint16_t hi = read16(buf);
+      uint16_t lo = read16(buf + 2);
       return SignExtend64<22>(((hi & 0x7ff) << 12) | // imm11
                               ((lo & 0x7ff) << 1));  // imm11:0
       break;
@@ -811,8 +813,8 @@
   case R_ARM_THM_JUMP24: {
     // Encoding B T4, BL T1, BLX T2: A = S:I1:I2:imm10:imm11:0
     // I1 = NOT(J1 EOR S), I2 = NOT(J2 EOR S)
-    uint16_t hi = read16le(buf);
-    uint16_t lo = read16le(buf + 2);
+    uint16_t hi = read16(buf);
+    uint16_t lo = read16(buf + 2);
     return SignExtend64<24>(((hi & 0x0400) << 14) |                    // S
                             (~((lo ^ (hi << 3)) << 10) & 0x00800000) | // I1
                             (~((lo ^ (hi << 1)) << 11) & 0x00400000) | // I2
@@ -827,7 +829,7 @@
   case R_ARM_MOVT_PREL:
   case R_ARM_MOVW_BREL_NC:
   case R_ARM_MOVT_BREL: {
-    uint64_t val = read32le(buf) & 0x000f0fff;
+    uint64_t val = read32(buf) & 0x000f0fff;
     return SignExtend64<16>(((val & 0x000f0000) >> 4) | (val & 0x00fff));
   }
   case R_ARM_THM_MOVW_ABS_NC:
@@ -837,8 +839,8 @@
   case R_ARM_THM_MOVW_BREL_NC:
   case R_ARM_THM_MOVT_BREL: {
     // Encoding T3: A = imm4:i:imm3:imm8
-    uint16_t hi = read16le(buf);
-    uint16_t lo = read16le(buf + 2);
+    uint16_t hi = read16(buf);
+    uint16_t lo = read16(buf + 2);
     return SignExtend64<16>(((hi & 0x000f) << 12) | // imm4
                             ((hi & 0x0400) << 1) |  // i
                             ((lo & 0x7000) >> 4) |  // imm3
@@ -853,7 +855,7 @@
     // right rotation and 8-bit constant. After the rotation the value
     // is zero-extended. When bit 23 is set the instruction is an add, when
     // bit 22 is set it is a sub.
-    uint32_t instr = read32le(buf);
+    uint32_t instr = read32(buf);
     uint32_t val = rotr32(instr & 0xff, ((instr & 0xf00) >> 8) * 2);
     return (instr & 0x00400000) ? -val : val;
   }
@@ -862,15 +864,15 @@
   case R_ARM_LDR_PC_G2: {
     // ADR (literal) add = bit23, sub = bit22
     // LDR (literal) u = bit23 unsigned imm12
-    bool u = read32le(buf) & 0x00800000;
-    uint32_t imm12 = read32le(buf) & 0xfff;
+    bool u = read32(buf) & 0x00800000;
+    uint32_t imm12 = read32(buf) & 0xfff;
     return u ? imm12 : -imm12;
   }
   case R_ARM_LDRS_PC_G0:
   case R_ARM_LDRS_PC_G1:
   case R_ARM_LDRS_PC_G2: {
     // LDRD/LDRH/LDRSB/LDRSH (literal) u = bit23 unsigned imm8
-    uint32_t opcode = read32le(buf);
+    uint32_t opcode = read32(buf);
     bool u = opcode & 0x00800000;
     uint32_t imm4l = opcode & 0xf;
     uint32_t imm4h = (opcode & 0xf00) >> 4;
@@ -880,8 +882,8 @@
     // Thumb2 ADR, which is an alias for a sub or add instruction with an
     // unsigned immediate.
     // ADR encoding T2 (sub), T3 (add) i:imm3:imm8
-    uint16_t hi = read16le(buf);
-    uint16_t lo = read16le(buf + 2);
+    uint16_t hi = read16(buf);
+    uint16_t lo = read16(buf + 2);
     uint64_t imm = (hi & 0x0400) << 1 | // i
                    (lo & 0x7000) >> 4 | // imm3
                    (lo & 0x00ff);       // imm8
@@ -893,11 +895,11 @@
     // From ELF for the ARM Architecture the initial signed addend is formed
     // from an unsigned field using expression (((imm8:00 + 4) & 0x3ff) – 4)
     // this trick permits the PC bias of -4 to be encoded using imm8 = 0xff
-    return ((((read16le(buf) & 0xff) << 2) + 4) & 0x3ff) - 4;
+    return ((((read16(buf) & 0xff) << 2) + 4) & 0x3ff) - 4;
   case R_ARM_THM_PC12: {
     // LDR (literal) encoding T2, add = (U == '1') imm12
-    bool u = read16le(buf) & 0x0080;
-    uint64_t imm12 = read16le(buf + 2) & 0x0fff;
+    bool u = read16(buf) & 0x0080;
+    uint64_t imm12 = read16(buf + 2) & 0x0fff;
     return u ? imm12 : -imm12;
   }
   case R_ARM_NONE:
@@ -908,7 +910,11 @@
   }
 }
 
-TargetInfo *elf::getARMTargetInfo() {
-  static ARM target;
+template <class ELFT> TargetInfo *elf::getARMTargetInfo() {
+  static ARM<ELFT> target;
   return &target;
 }
+
+template TargetInfo *elf::getARMTargetInfo<llvm::object::ELF32LE>();
+template TargetInfo *elf::getARMTargetInfo<llvm::object::ELF32BE>();
+
diff --git a/lld/ELF/Driver.cpp b/lld/ELF/Driver.cpp
--- a/lld/ELF/Driver.cpp
+++ b/lld/ELF/Driver.cpp
@@ -161,6 +161,7 @@
           .Cases("aarch64elf", "aarch64linux", {ELF64LEKind, EM_AARCH64})
           .Cases("aarch64elfb", "aarch64linuxb", {ELF64BEKind, EM_AARCH64})
           .Cases("armelf", "armelf_linux_eabi", {ELF32LEKind, EM_ARM})
+          .Cases("armelfb", "armelfb_linux_eabi", {ELF32BEKind, EM_ARM})
           .Case("elf32_x86_64", {ELF32LEKind, EM_X86_64})
           .Cases("elf32btsmip", "elf32btsmipn32", {ELF32BEKind, EM_MIPS})
           .Cases("elf32ltsmip", "elf32ltsmipn32", {ELF32LEKind, EM_MIPS})
@@ -346,6 +347,9 @@
   if (config->fixCortexA8 && config->emachine != EM_ARM)
     error("--fix-cortex-a8 is only supported on ARM targets");
 
+  if (config->fixCortexA8 && !config->isLE)
+    error("--fix-cortex-a8 is not supported on big endian targets");
+  
   if (config->tocOptimize && config->emachine != EM_PPC64)
     error("--toc-optimize is only supported on PowerPC64 targets");
 
diff --git a/lld/ELF/ScriptParser.cpp b/lld/ELF/ScriptParser.cpp
--- a/lld/ELF/ScriptParser.cpp
+++ b/lld/ELF/ScriptParser.cpp
@@ -419,6 +419,7 @@
       .Case("elf32-avr", {ELF32LEKind, EM_AVR})
       .Case("elf32-iamcu", {ELF32LEKind, EM_IAMCU})
       .Case("elf32-littlearm", {ELF32LEKind, EM_ARM})
+      .Case("elf32-bigarm", {ELF32BEKind, EM_ARM})
       .Case("elf32-x86-64", {ELF32LEKind, EM_X86_64})
       .Case("elf64-aarch64", {ELF64LEKind, EM_AARCH64})
       .Case("elf64-littleaarch64", {ELF64LEKind, EM_AARCH64})
diff --git a/lld/ELF/SyntheticSections.cpp b/lld/ELF/SyntheticSections.cpp
--- a/lld/ELF/SyntheticSections.cpp
+++ b/lld/ELF/SyntheticSections.cpp
@@ -3409,17 +3409,12 @@
 // EXIDX_CANTUNWIND entries are represented by nullptr as they do not have an
 // InputSection.
 static bool isDuplicateArmExidxSec(InputSection *prev, InputSection *cur) {
-
-  struct ExidxEntry {
-    ulittle32_t fn;
-    ulittle32_t unwind;
-  };
   // Get the last table Entry from the previous .ARM.exidx section. If Prev is
   // nullptr then it will be a synthesized EXIDX_CANTUNWIND entry.
-  ExidxEntry prevEntry = {ulittle32_t(0), ulittle32_t(1)};
+  uint32_t prevUnwind = 1;
   if (prev)
-    prevEntry = prev->getDataAs<ExidxEntry>().back();
-  if (isExtabRef(prevEntry.unwind))
+    prevUnwind = read32(prev->content().data() + prev->content().size() - 4);
+  if (isExtabRef(prevUnwind))
     return false;
 
   // We consider the unwind instructions of an .ARM.exidx table entry
@@ -3432,12 +3427,13 @@
 
   // If Cur is nullptr then this is synthesized EXIDX_CANTUNWIND entry.
   if (cur == nullptr)
-    return prevEntry.unwind == 1;
+    return prevUnwind == 1;
 
-  for (const ExidxEntry entry : cur->getDataAs<ExidxEntry>())
-    if (isExtabRef(entry.unwind) || entry.unwind != prevEntry.unwind)
+  for (uint32_t offset = 4; offset < (uint32_t)cur->content().size(); offset +=8) {
+    uint32_t curUnwind = read32(cur->content().data() + offset);
+    if (isExtabRef(curUnwind) || curUnwind != prevUnwind)
       return false;
-
+  }
   // All table entries in this .ARM.exidx Section can be merged into the
   // previous Section.
   return true;
@@ -3531,27 +3527,32 @@
 //     the table to terminate the address range of the final entry.
 void ARMExidxSyntheticSection::writeTo(uint8_t *buf) {
 
-  const uint8_t cantUnwindData[8] = {0, 0, 0, 0,  // PREL31 to target
-                                     1, 0, 0, 0}; // EXIDX_CANTUNWIND
-
+  // A linker generated CANTUNWIND entry is made up of two words
+  // 0x0 with R_ARM_PREL31 relocation to target.
+  // 0x1 with EXIDX_CANTUNWIND
   uint64_t offset = 0;
   for (InputSection *isec : executableSections) {
     assert(isec->getParent() != nullptr);
     if (InputSection *d = findExidxSection(isec)) {
-      memcpy(buf + offset, d->content().data(), d->content().size());
+      for (int dataOffset = 0; dataOffset != (int)d->content().size();
+           dataOffset += 4)
+        write32(buf + offset + dataOffset,
+                read32(d->content().data() + dataOffset));
       target->relocateAlloc(*d, buf + d->outSecOff);
       offset += d->getSize();
     } else {
       // A Linker generated CANTUNWIND section.
-      memcpy(buf + offset, cantUnwindData, sizeof(cantUnwindData));
+      write32(buf + offset + 0, 0x0);
+      write32(buf + offset + 4, 0x1);
       uint64_t s = isec->getVA();
       uint64_t p = getVA() + offset;
       target->relocateNoSym(buf + offset, R_ARM_PREL31, s - p);
       offset += 8;
     }
   }
-  // Write Sentinel.
-  memcpy(buf + offset, cantUnwindData, sizeof(cantUnwindData));
+  // Write Sentinel CANTUNWIND entry.
+  write32(buf + offset + 0, 0x0);
+  write32(buf + offset + 4, 0x1);
   uint64_t s = sentinel->getVA(sentinel->getSize());
   uint64_t p = getVA() + offset;
   target->relocateNoSym(buf + offset, R_ARM_PREL31, s - p);
diff --git a/lld/ELF/Target.h b/lld/ELF/Target.h
--- a/lld/ELF/Target.h
+++ b/lld/ELF/Target.h
@@ -169,7 +169,6 @@
 
 TargetInfo *getAArch64TargetInfo();
 TargetInfo *getAMDGPUTargetInfo();
-TargetInfo *getARMTargetInfo();
 TargetInfo *getAVRTargetInfo();
 TargetInfo *getHexagonTargetInfo();
 TargetInfo *getMSP430TargetInfo();
@@ -179,6 +178,7 @@
 TargetInfo *getSPARCV9TargetInfo();
 TargetInfo *getX86TargetInfo();
 TargetInfo *getX86_64TargetInfo();
+template <class ELFT> TargetInfo *getARMTargetInfo();
 template <class ELFT> TargetInfo *getMipsTargetInfo();
 
 struct ErrorPlace {
diff --git a/lld/ELF/Target.cpp b/lld/ELF/Target.cpp
--- a/lld/ELF/Target.cpp
+++ b/lld/ELF/Target.cpp
@@ -57,7 +57,14 @@
   case EM_AMDGPU:
     return getAMDGPUTargetInfo();
   case EM_ARM:
-    return getARMTargetInfo();
+    switch (config->ekind) {
+    case ELF32BEKind:
+      return getARMTargetInfo<ELF32BE>();
+    case ELF32LEKind:
+      return getARMTargetInfo<ELF32LE>();
+    default:
+      llvm_unreachable("unsupported ARM target");
+    }
   case EM_AVR:
     return getAVRTargetInfo();
   case EM_HEXAGON:
diff --git a/lld/ELF/Thunks.cpp b/lld/ELF/Thunks.cpp
--- a/lld/ELF/Thunks.cpp
+++ b/lld/ELF/Thunks.cpp
@@ -586,7 +586,8 @@
   uint64_t s = getARMThunkDestVA(destination);
   uint64_t p = getThunkTargetSym()->getVA();
   int64_t offset = s - p - 4;
-  write32(buf, 0xb000f000); // b.w S
+  write16(buf + 0, 0xf000); // b.w S
+  write16(buf + 2, 0xb000);
   target->relocateNoSym(buf, R_ARM_THM_JUMP24, offset);
 }
 
diff --git a/lld/test/ELF/arm-bl-v4.s b/lld/test/ELF/arm-bl-v4.s
--- a/lld/test/ELF/arm-bl-v4.s
+++ b/lld/test/ELF/arm-bl-v4.s
@@ -10,6 +10,16 @@
 // RUN: ld.lld %t/a.o -pie --script %t/near.lds -o %t/a-near-pie
 // RUN: llvm-objdump --no-print-imm-hex -d --no-show-raw-insn --triple=armv4-none-linux-gnueabi %t/a-near-pie | FileCheck %s --check-prefixes=NEAR
 
+// RUN: llvm-mc -arm-add-build-attributes -filetype=obj -triple=armv4eb-none-linux-gnueabi %t/a.s -o %t/a.o
+// RUN: ld.lld %t/a.o --script %t/far.lds -o %t/a-far
+// RUN: llvm-objdump --no-print-imm-hex -d --no-show-raw-insn --triple=armv4eb-none-linux-gnueabi %t/a-far | FileCheck %s --check-prefixes=FAR-EB
+// RUN: ld.lld %t/a.o --script %t/near.lds -o %t/a-near
+// RUN: llvm-objdump --no-print-imm-hex -d --no-show-raw-insn --triple=armv4eb-none-linux-gnueabi %t/a-near | FileCheck %s --check-prefixes=NEAR
+// RUN: ld.lld %t/a.o -pie --script %t/far.lds -o %t/a-far-pie
+// RUN: llvm-objdump --no-print-imm-hex -d --no-show-raw-insn --triple=armv4eb-none-linux-gnueabi %t/a-far-pie | FileCheck %s --check-prefixes=FAR-EB-PIE
+// RUN: ld.lld %t/a.o -pie --script %t/near.lds -o %t/a-near-pie
+// RUN: llvm-objdump --no-print-imm-hex -d --no-show-raw-insn --triple=armv4eb-none-linux-gnueabi %t/a-near-pie | FileCheck %s --check-prefixes=NEAR
+
 /// On Armv4 there is no blx instruction so long branch/exchange looks slightly
 /// different.
 
@@ -37,6 +47,16 @@
 // FAR-NEXT:  <$d>:
 // FAR-NEXT:   100000c: 00 00 00 06  	.word	0x06000000
 
+// FAR-EB-LABEL: <_start>:
+// FAR-EB-NEXT:   1000000:      	bl	0x1000008 <__ARMv5LongLdrPcThunk_target> @ imm = #0
+// FAR-EB-NEXT:                	mov pc, lr
+// FAR-EB-EMPTY:
+// FAR-EB-NEXT:  <__ARMv5LongLdrPcThunk_target>:
+// FAR-EB-NEXT:   1000008:      	ldr	pc, [pc, #-4]           @ 0x100000c <__ARMv5LongLdrPcThunk_target+0x4>
+// FAR-EB-EMPTY:
+// FAR-EB-NEXT:  <$d>:
+// FAR-EB-NEXT:   100000c: 06 00 00 00  	.word	0x06000000
+
 // FAR-PIE-LABEL: <_start>:
 // FAR-PIE-NEXT:   1000000:      	bl	0x1000008 <__ARMv4PILongThunk_target> @ imm = #0
 // FAR-PIE-NEXT:                	mov pc, lr
@@ -48,6 +68,17 @@
 // FAR-PIE-NEXT:  <$d>:
 // FAR-PIE-NEXT:   1000010: ec ff ff 04  	.word	0x04ffffec
 
+// FAR-EB-PIE-LABEL: <_start>:
+// FAR-EB-PIE-NEXT:   1000000:      	bl	0x1000008 <__ARMv4PILongThunk_target> @ imm = #0
+// FAR-EB-PIE-NEXT:                	mov pc, lr
+// FAR-EB-PIE-EMPTY:
+// FAR-EB-PIE-NEXT:  <__ARMv4PILongThunk_target>:
+// FAR-EB-PIE-NEXT:   1000008:      	ldr	r12, [pc]               @ 0x1000010 <__ARMv4PILongThunk_target+0x8>
+// FAR-EB-PIE-NEXT:                	add	pc, pc, r12
+// FAR-EB-PIE-EMPTY:
+// FAR-EB-PIE-NEXT:  <$d>:
+// FAR-EB-PIE-NEXT:   1000010: 04 ff ff ec  	.word	0x04ffffec
+
 // NEAR-LABEL: <_start>:
 // NEAR-NEXT:  1000000:      	bl 0x1000008 <target> @ imm = #0
 // NEAR-NEXT:               	mov pc, lr
@@ -62,9 +93,15 @@
 // FAR-LABEL: <target>:
 // FAR-NEXT:   6000000:      	mov pc, lr
 
+// FAR-EB-LABEL: <target>:
+// FAR-EB-NEXT:   6000000:      	mov pc, lr
+
 // FAR-PIE-LABEL: <target>:
 // FAR-PIE-NEXT:   6000000:     mov pc, lr
-                                         
+
+// FAR-EB-PIE-LABEL: <target>:
+// FAR-EB-PIE-NEXT:   6000000:     mov pc, lr
+
 // NEAR-LABEL: <target>:
 // NEAR-LABEL:  1000008:      	mov pc, lr
 
diff --git a/lld/test/ELF/arm-bl-v4t.s b/lld/test/ELF/arm-bl-v4t.s
--- a/lld/test/ELF/arm-bl-v4t.s
+++ b/lld/test/ELF/arm-bl-v4t.s
@@ -10,6 +10,16 @@
 // RUN: ld.lld %t/a.o -pie --script %t/near.lds -o %t/a-near-pie
 // RUN: llvm-objdump --no-print-imm-hex -d --no-show-raw-insn --triple=armv4t-none-linux-gnueabi %t/a-near-pie | FileCheck %s --check-prefixes=NEAR
 
+// RUN: llvm-mc -arm-add-build-attributes -filetype=obj -triple=armv4teb-none-linux-gnueabi %t/a.s -o %t/a.o
+// RUN: ld.lld %t/a.o --script %t/far.lds -o %t/a-far
+// RUN: llvm-objdump --no-print-imm-hex -d --no-show-raw-insn --triple=armv4teb-none-linux-gnueabi %t/a-far | FileCheck %s --check-prefixes=FAR-EB
+// RUN: ld.lld %t/a.o --script %t/near.lds -o %t/a-near
+// RUN: llvm-objdump --no-print-imm-hex -d --no-show-raw-insn --triple=armv4teb-none-linux-gnueabi %t/a-near | FileCheck %s --check-prefixes=NEAR
+// RUN: ld.lld %t/a.o -pie --script %t/far.lds -o %t/a-far-pie
+// RUN: llvm-objdump --no-print-imm-hex -d --no-show-raw-insn --triple=armv4teb-none-linux-gnueabi %t/a-far-pie | FileCheck %s --check-prefixes=FAR-EB-PIE
+// RUN: ld.lld %t/a.o -pie --script %t/near.lds -o %t/a-near-pie
+// RUN: llvm-objdump --no-print-imm-hex -d --no-show-raw-insn --triple=armv4teb-none-linux-gnueabi %t/a-near-pie | FileCheck %s --check-prefixes=NEAR
+
 /// On Armv4T there is no blx instruction so long branch/exchange looks slightly
 /// different.
 
@@ -61,6 +71,32 @@
 // FAR-NEXT:  <$d>:
 // FAR-NEXT:   1000024: 05 00 00 06  	.word	0x06000005
 
+// FAR-EB-LABEL: <_start>:
+// FAR-EB-NEXT:   1000000:      	bl	0x1000010 <__ARMv5LongLdrPcThunk_target> @ imm = #8
+// FAR-EB-NEXT:                	bx	lr
+// FAR-EB-EMPTY:
+// FAR-EB-LABEL: <thumb_start>:
+// FAR-EB-NEXT:   1000008:      	bl	0x1000018 <__Thumbv4ABSLongThunk_thumb_target> @ imm = #12
+// FAR-EB-NEXT:                	bx	lr
+// FAR-EB-NEXT:                	bmi	0xffffba                @ imm = #-88
+// FAR-EB-EMPTY:
+// FAR-EB-NEXT:  <__ARMv5LongLdrPcThunk_target>:
+// FAR-EB-NEXT:   1000010:      	ldr	pc, [pc, #-4]           @ 0x1000014 <__ARMv5LongLdrPcThunk_target+0x4>
+// FAR-EB-EMPTY:
+// FAR-EB-NEXT:  <$d>:
+// FAR-EB-NEXT:   1000014: 06 00 00 00  	.word	0x06000000
+// FAR-EB-EMPTY:
+// FAR-EB-NEXT:  <__Thumbv4ABSLongThunk_thumb_target>:
+// FAR-EB-NEXT:   1000018:      	bx	pc
+// FAR-EB-NEXT:                	b	0x1000018 <__Thumbv4ABSLongThunk_thumb_target> @ imm = #-6
+// FAR-EB-EMPTY:
+// FAR-EB-NEXT:  <$a>:
+// FAR-EB-NEXT:   100001c:      	ldr	r12, [pc]               @ 0x1000024 <__Thumbv4ABSLongThunk_thumb_target+0xc>
+// FAR-EB-NEXT:                	bx	r12
+// FAR-EB-EMPTY:
+// FAR-EB-NEXT:  <$d>:
+// FAR-EB-NEXT:   1000024: 06 00 00 05  	.word	0x06000005
+
 // FAR-PIE-LABEL: <_start>:
 // FAR-PIE-NEXT:   1000000:      	bl	0x1000010 <__ARMv4PILongThunk_target> @ imm = #8
 // FAR-PIE-NEXT:                	bx	lr
@@ -89,6 +125,34 @@
 // FAR-PIE-NEXT:  <$d>:
 // FAR-PIE-NEXT:   100002c: d9 ff ff 04  	.word	0x04ffffd9
 
+// FAR-EB-PIE-LABEL: <_start>:
+// FAR-EB-PIE-NEXT:   1000000:      	bl	0x1000010 <__ARMv4PILongThunk_target> @ imm = #8
+// FAR-EB-PIE-NEXT:                	bx	lr
+// FAR-EB-PIE-EMPTY:
+// FAR-EB-PIE-NEXT:  <thumb_start>:
+// FAR-EB-PIE-NEXT:   1000008:      	bl	0x100001c <__Thumbv4PILongThunk_thumb_target> @ imm = #16
+// FAR-EB-PIE-NEXT:                	bx	lr
+// FAR-EB-PIE-NEXT:                	bmi	0xffffba                @ imm = #-88
+// FAR-EB-PIE-EMPTY:
+// FAR-EB-PIE-NEXT:  <__ARMv4PILongThunk_target>:
+// FAR-EB-PIE-NEXT:   1000010:      	ldr	r12, [pc]               @ 0x1000018 <__ARMv4PILongThunk_target+0x8>
+// FAR-EB-PIE-NEXT:                	add	pc, pc, r12
+// FAR-EB-PIE-EMPTY:
+// FAR-EB-PIE-NEXT:  <$d>:
+// FAR-EB-PIE-NEXT:   1000018: 04 ff ff e4  	.word	0x04ffffe4
+// FAR-EB-PIE-EMPTY:
+// FAR-EB-PIE-NEXT:  <__Thumbv4PILongThunk_thumb_target>:
+// FAR-EB-PIE-NEXT:   100001c:      	bx	pc
+// FAR-EB-PIE-NEXT:                	b	0x100001c <__Thumbv4PILongThunk_thumb_target> @ imm = #-6
+// FAR-EB-PIE-EMPTY:
+// FAR-EB-PIE-NEXT:  <$a>:
+// FAR-EB-PIE-NEXT:   1000020:      	ldr	r12, [pc, #4]           @ 0x100002c <__Thumbv4PILongThunk_thumb_target+0x10>
+// FAR-EB-PIE-NEXT:                	add	r12, pc, r12
+// FAR-EB-PIE-NEXT:                	bx	r12
+// FAR-EB-PIE-EMPTY:
+// FAR-EB-PIE-NEXT:  <$d>:
+// FAR-EB-PIE-NEXT:   100002c: 04 ff ff d9  	.word	0x04ffffd9
+
 // NEAR-LABEL: <_start>:
 // NEAR-NEXT:  1000000:      	bl	0x100000c <thumb_start+0x4> @ imm = #4
 // NEAR-NEXT:               	bx	lr
diff --git a/lld/test/ELF/arm-bl-v6.s b/lld/test/ELF/arm-bl-v6.s
--- a/lld/test/ELF/arm-bl-v6.s
+++ b/lld/test/ELF/arm-bl-v6.s
@@ -6,6 +6,13 @@
 // RUN: llvm-objdump --no-print-imm-hex -d --triple=armv6-none-linux-gnueabi --start-address=0x22100c --stop-address=0x221014 %t2 | FileCheck --check-prefix=CHECK-ARM2 %s
 // RUN: llvm-objdump --no-print-imm-hex -d --triple=thumbv6-none-linux-gnueabi %t2 --start-address=0x622000 --stop-address=0x622002 | FileCheck --check-prefix=CHECK-THUMB2 %s
 
+// RUN: llvm-mc -arm-add-build-attributes -filetype=obj -triple=armv6eb-none-linux-gnueabi %s -o %t
+// RUN: ld.lld %t -o %t2
+// RUN: llvm-objdump --no-print-imm-hex -d --triple=armv6eb-none-linux-gnueabi --start-address=0x21000 --stop-address=0x21008 %t2 | FileCheck --check-prefix=CHECK-ARM1 %s
+// RUN: llvm-objdump --no-print-imm-hex -d --triple=thumbv6eb-none-linux-gnueabi %t2 --start-address=0x21008 --stop-address=0x2100c | FileCheck --check-prefix=CHECK-THUMB1 %s
+// RUN: llvm-objdump --no-print-imm-hex -d --triple=armv6eb-none-linux-gnueabi --start-address=0x22100c --stop-address=0x221014 %t2 | FileCheck --check-prefix=CHECK-ARM2-EB %s
+// RUN: llvm-objdump --no-print-imm-hex -d --triple=thumbv6eb-none-linux-gnueabi %t2 --start-address=0x622000 --stop-address=0x622002 | FileCheck --check-prefix=CHECK-THUMB2 %s
+
 /// On Arm v6 the range of a Thumb BL instruction is only 4 megabytes as the
 /// extended range encoding is not supported. The following example has a Thumb
 /// BL that is out of range on ARM v6 and requires a range extension thunk.
@@ -48,6 +55,10 @@
 // CHECK-ARM2-NEXT:   22100c:   e51ff004        ldr     pc, [pc, #-4]
 // CHECK-ARM2: <$d>:
 // CHECK-ARM2-NEXT:   221010:   01 20 62 00     .word   0x00622001
+// CHECK-ARM2-EB: <__ARMv5LongLdrPcThunk_farthumbfunc>:
+// CHECK-ARM2-EB-NEXT:   22100c:   e51ff004        ldr     pc, [pc, #-4]
+// CHECK-ARM2-EB: <$d>:
+// CHECK-ARM2-EB-NEXT:   221010:   00 62 20 01     .word   0x00622001
  .section .text.4, "ax", %progbits
  .space 0x200000
 
diff --git a/lld/test/ELF/arm-bx-v4t.s b/lld/test/ELF/arm-bx-v4t.s
--- a/lld/test/ELF/arm-bx-v4t.s
+++ b/lld/test/ELF/arm-bx-v4t.s
@@ -10,6 +10,16 @@
 // RUN: ld.lld %t/a.o -pie --script %t/near.lds -o %t/a-near-pie
 // RUN: llvm-objdump --no-print-imm-hex -d --no-show-raw-insn --triple=armv4t-none-linux-gnueabi %t/a-near-pie | FileCheck %s --check-prefixes=NEAR-PIE
 
+// RUN: llvm-mc -arm-add-build-attributes -filetype=obj -triple=armv4teb-none-linux-gnueabi %t/a.s -o %t/a.o
+// RUN: ld.lld %t/a.o --script %t/far.lds -o %t/a-far
+// RUN: llvm-objdump --no-print-imm-hex -d --no-show-raw-insn --triple=armv4teb-none-linux-gnueabi %t/a-far | FileCheck %s --check-prefixes=FAR-EB
+// RUN: ld.lld %t/a.o --script %t/near.lds -o %t/a-near
+// RUN: llvm-objdump --no-print-imm-hex -d --no-show-raw-insn --triple=armv4teb-none-linux-gnueabi %t/a-near | FileCheck %s --check-prefixes=NEAR-EB
+// RUN: ld.lld %t/a.o -pie --script %t/far.lds -o %t/a-far-pie
+// RUN: llvm-objdump --no-print-imm-hex -d --no-show-raw-insn --triple=armv4teb-none-linux-gnueabi %t/a-far-pie | FileCheck %s --check-prefixes=FAR-EB-PIE
+// RUN: ld.lld %t/a.o -pie --script %t/near.lds -o %t/a-near-pie
+// RUN: llvm-objdump --no-print-imm-hex -d --no-show-raw-insn --triple=armv4teb-none-linux-gnueabi %t/a-near-pie | FileCheck %s --check-prefixes=NEAR-EB-PIE
+
 /// On Arm v4t there is no blx instruction so all interworking must go via
 /// a thunk.
 
@@ -38,6 +48,17 @@
 // FAR-NEXT:  <$d>:
 // FAR-NEXT:   1000010: 01 00 00 06   .word   0x06000001
 
+// FAR-EB-LABEL: <_start>:
+// FAR-EB-NEXT:   1000000:       bl      0x1000008 <__ARMv4ABSLongBXThunk_target> @ imm = #0
+// FAR-EB-NEXT:                  bx      lr
+// FAR-EB-EMPTY:
+// FAR-EB-NEXT:  <__ARMv4ABSLongBXThunk_target>:
+// FAR-EB-NEXT:   1000008:       ldr     r12, [pc]               @ 0x1000010 <__ARMv4ABSLongBXThunk_target+0x8>
+// FAR-EB-NEXT:                  bx      r12
+// FAR-EB-EMPTY:
+// FAR-EB-NEXT:  <$d>:
+// FAR-EB-NEXT:   1000010: 06 00 00 01   .word   0x06000001
+
 // NEAR-LABEL: <_start>:
 // NEAR-NEXT:   1000000:       bl      0x1000008 <__ARMv4ABSLongBXThunk_target> @ imm = #0
 // NEAR-NEXT:                  bx      lr
@@ -49,6 +70,17 @@
 // NEAR-NEXT:  <$d>:
 // NEAR-NEXT:  1000010: 15 00 00 01   .word   0x01000015
 
+// NEAR-EB-LABEL: <_start>:
+// NEAR-EB-NEXT:   1000000:       bl      0x1000008 <__ARMv4ABSLongBXThunk_target> @ imm = #0
+// NEAR-EB-NEXT:                  bx      lr
+// NEAR-EB-EMPTY:
+// NEAR-EB-NEXT:  <__ARMv4ABSLongBXThunk_target>:
+// NEAR-EB-NEXT:   1000008:       ldr     r12, [pc]               @ 0x1000010 <__ARMv4ABSLongBXThunk_target+0x8>
+// NEAR-EB-NEXT:                  bx      r12
+// NEAR-EB-EMPTY:
+// NEAR-EB-NEXT:  <$d>:
+// NEAR-EB-NEXT:  1000010: 01 00 00 15   .word   0x01000015
+
 // FAR-PIE-LABEL: <_start>:
 // FAR-PIE-NEXT:   1000000:    	bl	0x1000008 <__ARMv4PILongBXThunk_target> @ imm = #0
 // FAR-PIE-NEXT:               	bx	lr
@@ -61,6 +93,18 @@
 // FAR-PIE-NEXT:  <$d>:
 // FAR-PIE-NEXT:   1000014: ed ff ff 04  	.word	0x04ffffed
 
+// FAR-EB-PIE-LABEL: <_start>:
+// FAR-EB-PIE-NEXT:   1000000:    	bl	0x1000008 <__ARMv4PILongBXThunk_target> @ imm = #0
+// FAR-EB-PIE-NEXT:               	bx	lr
+// FAR-EB-PIE-EMPTY:
+// FAR-EB-PIE-NEXT:  <__ARMv4PILongBXThunk_target>:
+// FAR-EB-PIE-NEXT:   1000008:     ldr	r12, [pc, #4]           @ 0x1000014 <__ARMv4PILongBXThunk_target+0xc>
+// FAR-EB-PIE-NEXT:                add	r12, pc, r12
+// FAR-EB-PIE-NEXT:                bx	r12
+// FAR-EB-PIE-EMPTY:
+// FAR-EB-PIE-NEXT:  <$d>:
+// FAR-EB-PIE-NEXT:   1000014: 04 ff ff ed  	.word	0x04ffffed
+
 // NEAR-PIE-LABEL: <_start>:
 // NEAR-PIE-NEXT:   1000000:    bl	0x1000008 <__ARMv4PILongBXThunk_target> @ imm = #0
 // NEAR-PIE-NEXT:               bx	lr
@@ -73,6 +117,18 @@
 // NEAR-PIE-NEXT:  <$d>:
 // NEAR-PIE-NEXT:   1000014: 05 00 00 00  	.word	0x00000005
 
+// NEAR-EB-PIE-LABEL: <_start>:
+// NEAR-EB-PIE-NEXT:   1000000:    bl	0x1000008 <__ARMv4PILongBXThunk_target> @ imm = #0
+// NEAR-EB-PIE-NEXT:               bx	lr
+// NEAR-EB-PIE-EMPTY:
+// NEAR-EB-PIE-NEXT:  <__ARMv4PILongBXThunk_target>:
+// NEAR-EB-PIE-NEXT:   1000008:    ldr	r12, [pc, #4]           @ 0x1000014 <__ARMv4PILongBXThunk_target+0xc>
+// NEAR-EB-PIE-NEXT:               add	r12, pc, r12
+// NEAR-EB-PIE-NEXT:               bx	r12
+// NEAR-EB-PIE-EMPTY:
+// NEAR-EB-PIE-NEXT:  <$d>:
+// NEAR-EB-PIE-NEXT:   1000014: 00 00 00 05  	.word	0x00000005
+
 .section .high, "ax", %progbits
 .thumb
  .globl target
@@ -96,6 +152,21 @@
 // FAR-NEXT: <$d>:
 // FAR-NEXT:  6000010: 00 00 00 01   .word   0x01000000
 
+// FAR-EB-LABEL: <target>:
+// FAR-EB-NEXT:   6000000:       bl      0x6000008 <__Thumbv4ABSLongBXThunk__start> @ imm = #4
+// FAR-EB-NEXT:                  bx      lr
+// FAR-EB-NEXT:                  bmi     0x5ffffb2 <__ARMv4ABSLongBXThunk_target+0x4ffffaa> @ imm = #-88
+// FAR-EB-EMPTY:
+// FAR-EB-NEXT:  <__Thumbv4ABSLongBXThunk__start>:
+// FAR-EB-NEXT:   6000008:       bx      pc
+// FAR-EB-NEXT:                  b       0x6000008 <__Thumbv4ABSLongBXThunk__start> @ imm = #-6
+// FAR-EB-EMPTY:
+// FAR-EB-NEXT:  <$a>:
+// FAR-EB-NEXT:   600000c:       ldr     pc, [pc, #-4]           @ 0x6000010 <__Thumbv4ABSLongBXThunk__start+0x8>
+// FAR-EB-EMPTY:
+// FAR-EB-NEXT: <$d>:
+// FAR-EB-NEXT:  6000010: 01 00 00 00   .word   0x01000000
+
 // NEAR-LABEL: <target>:
 // NEAR-NEXT:   1000014:       bl      0x100001c <__Thumbv4ABSLongBXThunk__start> @ imm = #4
 // NEAR-NEXT:                  bx      lr
@@ -111,6 +182,21 @@
 // NEAR-NEXT:  <$d>:
 // NEAR-NEXT:   1000024: 00 00 00 01   .word   0x01000000
 
+// NEAR-EB-LABEL: <target>:
+// NEAR-EB-NEXT:   1000014:       bl      0x100001c <__Thumbv4ABSLongBXThunk__start> @ imm = #4
+// NEAR-EB-NEXT:                  bx      lr
+// NEAR-EB-NEXT:                  bmi     0xffffc6                @ imm = #-88
+// NEAR-EB-EMPTY:
+// NEAR-EB-NEXT:  <__Thumbv4ABSLongBXThunk__start>:
+// NEAR-EB-NEXT:   100001c:       bx      pc
+// NEAR-EB-NEXT:                  b       0x100001c <__Thumbv4ABSLongBXThunk__start> @ imm = #-6
+// NEAR-EB-EMPTY:
+// NEAR-EB-NEXT:  <$a>:
+// NEAR-EB-NEXT:   1000020:       ldr     pc, [pc, #-4]           @ 0x1000024 <__Thumbv4ABSLongBXThunk__start+0x8>
+// NEAR-EB-EMPTY:
+// NEAR-EB-NEXT:  <$d>:
+// NEAR-EB-NEXT:   1000024: 01 00 00 00   .word   0x01000000
+
 // FAR-PIE-LABEL: <target>:
 // FAR-PIE-NEXT:   6000000:       	bl	0x6000008 <__Thumbv4PILongBXThunk__start> @ imm = #4
 // FAR-PIE-NEXT:                	bx  lr
@@ -127,6 +213,22 @@
 // FAR-PIE-NEXT:  <$d>:
 // FAR-PIE-NEXT:   6000014: e8 ff ff fa  	.word	0xfaffffe8
 
+// FAR-EB-PIE-LABEL: <target>:
+// FAR-EB-PIE-NEXT:   6000000:       	bl	0x6000008 <__Thumbv4PILongBXThunk__start> @ imm = #4
+// FAR-EB-PIE-NEXT:                	bx  lr
+// FAR-EB-PIE-NEXT:                	bmi 0x5ffffb2 <__ARMv4PILongBXThunk_target+0x4ffffaa> @ imm = #-88
+// FAR-EB-PIE-EMPTY:
+// FAR-EB-PIE-NEXT:  <__Thumbv4PILongBXThunk__start>:
+// FAR-EB-PIE-NEXT:   6000008:      	bx	pc
+// FAR-EB-PIE-NEXT:                	b	0x6000008 <__Thumbv4PILongBXThunk__start> @ imm = #-6
+// FAR-EB-PIE-EMPTY:
+// FAR-EB-PIE-NEXT:  <$a>:
+// FAR-EB-PIE-NEXT:   600000c:      	ldr	r12, [pc]               @ 0x6000014 <__Thumbv4PILongBXThunk__start+0xc>
+// FAR-EB-PIE-NEXT:                	add	pc, r12, pc
+// FAR-EB-PIE-EMPTY:
+// FAR-EB-PIE-NEXT:  <$d>:
+// FAR-EB-PIE-NEXT:   6000014: fa ff ff e8  	.word	0xfaffffe8
+
 // NEAR-PIE-LABEL: <target>:
 // NEAR-PIE-NEXT:   1000018:      	bl	0x1000020 <__Thumbv4PILongBXThunk__start> @ imm = #4
 // NEAR-PIE-NEXT:               	bx	lr
@@ -143,6 +245,22 @@
 // NEAR-PIE-NEXT:  <$d>:
 // NEAR-PIE-NEXT:   100002c: d0 ff ff ff  	.word	0xffffffd0
 
+// NEAR-EB-PIE-LABEL: <target>:
+// NEAR-EB-PIE-NEXT:   1000018:      	bl	0x1000020 <__Thumbv4PILongBXThunk__start> @ imm = #4
+// NEAR-EB-PIE-NEXT:               	bx	lr
+// NEAR-EB-PIE-NEXT:               	bmi	0xffffca                @ imm = #-88
+// NEAR-EB-PIE-EMPTY:
+// NEAR-EB-PIE-NEXT:  <__Thumbv4PILongBXThunk__start>:
+// NEAR-EB-PIE-NEXT:   1000020:      	bx	pc
+// NEAR-EB-PIE-NEXT:               	b	0x1000020 <__Thumbv4PILongBXThunk__start> @ imm = #-6
+// NEAR-EB-PIE-EMPTY:
+// NEAR-EB-PIE-NEXT:  <$a>:
+// NEAR-EB-PIE-NEXT:   1000024:      	ldr	r12, [pc]               @ 0x100002c <__Thumbv4PILongBXThunk__start+0xc>
+// NEAR-EB-PIE-NEXT:               	add	pc, r12, pc
+// NEAR-EB-PIE-EMPTY:
+// NEAR-EB-PIE-NEXT:  <$d>:
+// NEAR-EB-PIE-NEXT:   100002c: ff ff ff d0  	.word	0xffffffd0
+
 #--- far.lds
 SECTIONS {
   . = SIZEOF_HEADERS;
diff --git a/lld/test/ELF/arm-data-relocs.s b/lld/test/ELF/arm-data-relocs.s
new file mode 100644
--- /dev/null
+++ b/lld/test/ELF/arm-data-relocs.s
@@ -0,0 +1,27 @@
+// REQUIRES: arm
+// RUN: llvm-mc -filetype=obj -triple=armv7a-none-linux-gnueabi %s -o %t.o
+// RUN: llvm-mc -filetype=obj -triple=armv7a-none-linux-gnueabi %S/Inputs/abs256.s -o %t256.o
+// RUN: ld.lld %t.o %t256.o -o %t
+// RUN: llvm-objdump -s %t | FileCheck %s --check-prefixes=CHECK,LE
+
+// RUN: llvm-mc -filetype=obj -triple=armv7aeb-none-linux-gnueabi %s -o %t.be.o
+// RUN: llvm-mc -filetype=obj -triple=armv7aeb-none-linux-gnueabi %S/Inputs/abs256.s -o %t256.be.o
+// RUN: ld.lld %t.be.o %t256.be.o -o %t.be
+// RUN: llvm-objdump -s %t.be | FileCheck %s --check-prefixes=CHECK,BE
+
+.globl _start
+_start:
+.section .R_ARM_ABS, "ax","progbits"
+  .word foo + 0x24
+
+// CHECK: Contents of section .R_ARM_ABS:
+// LE-NEXT:  200b4 24010000
+// BE-NEXT:  200b4 00000124
+
+.section .R_ARM_PREL, "ax","progbits"
+  .word foo - . + 0x24
+
+// CHECK: Contents of section .R_ARM_PREL:
+// LE-NEXT:  200b8 6c00feff
+// BE-NEXT:  200b8 fffe006c
+
diff --git a/lld/test/ELF/arm-exidx-emit-relocs.s b/lld/test/ELF/arm-exidx-emit-relocs.s
--- a/lld/test/ELF/arm-exidx-emit-relocs.s
+++ b/lld/test/ELF/arm-exidx-emit-relocs.s
@@ -4,6 +4,11 @@
 // RUN: llvm-objdump -s --triple=armv7a-none-linux-gnueabi %t2 | FileCheck %s
 // RUN: llvm-readelf --relocs %t2 | FileCheck -check-prefix=CHECK-RELOCS %s
 
+// RUN: llvm-mc -filetype=obj --arm-add-build-attributes -triple=armv7aeb-none-linux-gnueabi -mcpu=cortex-a8 %s -o %t
+// RUN: ld.lld --emit-relocs %t -o %t2
+// RUN: llvm-objdump -s --triple=armv7aeb-none-linux-gnueabi %t2 | FileCheck -check-prefix=CHECK-EB %s
+// RUN: llvm-readelf --relocs %t2 | FileCheck -check-prefix=CHECK-RELOCS %s
+
 /// LLD does not support --emit-relocs for .ARM.exidx sections as the relocations
 /// from synthetic table entries won't be represented. Given the known use cases
 /// of --emit-relocs, relocating kernels, and binary analysis, the former doesn't
@@ -69,3 +74,9 @@
 // CHECK-NEXT:  100f4 20000100 01000000
 
 // CHECK-RELOCS-NOT: Relocation section '.rel.ARM.exidx'
+
+// CHECK-EB: Contents of section .ARM.exidx:
+// CHECK-EB-NEXT: 100d4 00010028 80978408 00010028 00000001
+// CHECK-EB-NEXT: 100e4 00010028 80978408 00010024 00000001
+// CHECK-EB-NEXT: 100f4 00010020 00000001
+
diff --git a/lld/test/ELF/arm-exidx-relocatable.s b/lld/test/ELF/arm-exidx-relocatable.s
--- a/lld/test/ELF/arm-exidx-relocatable.s
+++ b/lld/test/ELF/arm-exidx-relocatable.s
@@ -5,6 +5,12 @@
 // RUN: ld.lld -r %t %tcantunwind -o %t4
 // RUN: llvm-readobj -S %t4 | FileCheck %s
 
+// RUN: llvm-mc -filetype=obj -triple=armv7aeb-none-linux-gnueabi -mcpu=cortex-a8 %s -o %t
+// RUN: llvm-mc -filetype=obj -triple=armv7aeb-none-linux-gnueabi -mcpu=cortex-a8 %S/Inputs/arm-exidx-cantunwind.s -o %tcantunwind
+// Check that relocatable link maintains SHF_LINK_ORDER for big endian
+// RUN: ld.lld -r %t %tcantunwind -o %t4
+// RUN: llvm-readobj -S %t4 | FileCheck %s
+
 // Each assembler created .ARM.exidx section has the SHF_LINK_ORDER flag set
 // with the sh_link containing the section index of the executable section
 // containing the function it describes. To maintain this property in
diff --git a/lld/test/ELF/arm-exidx-sentinel-norelocatable.s b/lld/test/ELF/arm-exidx-sentinel-norelocatable.s
--- a/lld/test/ELF/arm-exidx-sentinel-norelocatable.s
+++ b/lld/test/ELF/arm-exidx-sentinel-norelocatable.s
@@ -2,6 +2,11 @@
 // RUN: llvm-mc %s -triple=armv7-unknown-linux-gnueabi -filetype=obj -o %t.o
 // RUN: ld.lld -r %t.o -o %t
 // RUN: llvm-readobj -S %t | FileCheck %s
+
+// RUN: llvm-mc %s -triple=armv7eb-unknown-linux-gnueabi -mcpu=cortex-a8 -filetype=obj -o %t.o
+// RUN: ld.lld -r %t.o -o %t
+// RUN: llvm-readobj -S %t | FileCheck %s
+
 // Check that when doing a relocatable link we don't add a terminating entry
 // to the .ARM.exidx section
  .syntax unified
diff --git a/lld/test/ELF/arm-header.s b/lld/test/ELF/arm-header.s
new file mode 100644
--- /dev/null
+++ b/lld/test/ELF/arm-header.s
@@ -0,0 +1,26 @@
+# REQUIRES: arm
+# RUN: llvm-mc -filetype=obj -triple=armv7aeb-none-linux-gnueabi -mcpu=cortex-a8 %s -o %t.o
+# RUN: ld.lld %t.o -o %t1
+# RUN: llvm-readobj -h %t1 | FileCheck %s
+
+# CHECK: Format: elf32-bigarm
+
+# CHECK: ElfHeader {
+# CHECK-NEXT:   Ident {
+# CHECK-NEXT:     Magic: (7F 45 4C 46)
+# CHECK-NEXT:     Class: 32-bit (0x1)
+# CHECK-NEXT:     DataEncoding: BigEndian (0x2)
+# CHECK-NEXT:     FileVersion: 1
+# CHECK-NEXT:     OS/ABI: SystemV (0x0)
+# CHECK-NEXT:     ABIVersion: 0
+# CHECK-NEXT:     Unused: (00 00 00 00 00 00 00)
+# CHECK-NEXT:   }
+
+# CHECK:   Flags [ (0x5000200)
+# CHECK-NEXT:     0x200
+# CHECK-NEXT:     0x1000000
+# CHECK-NEXT:     0x4000000
+# CHECK-NEXT:   ]
+
+# CHECK-NOT: 0x800000
+
diff --git a/lld/test/ELF/arm-mov-relocs.s b/lld/test/ELF/arm-mov-relocs.s
--- a/lld/test/ELF/arm-mov-relocs.s
+++ b/lld/test/ELF/arm-mov-relocs.s
@@ -6,6 +6,13 @@
 // RUN: ld.lld %t3 -o %t4
 // RUN: llvm-objdump --no-print-imm-hex -d %t4 --triple=thumbv7a-unknown-linux-gnueabi --no-show-raw-insn | FileCheck %s
 
+// RUN: llvm-mc -filetype=obj -triple=armv7aeb-unknown-linux-gnueabi -mcpu=cortex-a8 %s -o %t
+// RUN: ld.lld %t -o %t2
+// RUN: llvm-objdump --no-print-imm-hex -d %t2 --triple=armv7aeb-unknown-linux-gnueabi --no-show-raw-insn | FileCheck %s
+// RUN: llvm-mc -filetype=obj -triple=thumbv7aeb-unknown-linux-gnueabi -mcpu=cortex-a8 %s -o %t3
+// RUN: ld.lld %t3 -o %t4
+// RUN: llvm-objdump --no-print-imm-hex -d %t4 --triple=thumbv7aeb-unknown-linux-gnueabi --no-show-raw-insn | FileCheck %s
+
 /// Test the following relocation pairs:
 ///  * R_ARM_MOVW_ABS_NC and R_ARM_MOVT_ABS
 ///  * R_ARM_MOVW_PREL_NC and R_ARM_MOVT_PREL
diff --git a/lld/test/ELF/arm-plt-reloc.s b/lld/test/ELF/arm-plt-reloc.s
--- a/lld/test/ELF/arm-plt-reloc.s
+++ b/lld/test/ELF/arm-plt-reloc.s
@@ -306,3 +306,60 @@
 // DSORELMIX-NEXT:     0x800202C R_ARM_JUMP_SLOT func1
 // DSORELMIX-NEXT:     0x8002030 R_ARM_JUMP_SLOT func2
 // DSORELMIX-NEXT:     0x8002034 R_ARM_JUMP_SLOT func3
+
+// RUN: llvm-mc -filetype=obj -triple=armv7aeb-none-linux-gnueabi -mcpu=cortex-a8 %p/Inputs/arm-plt-reloc.s -o %t1
+// RUN: llvm-mc -filetype=obj -triple=armv7aeb-none-linux-gnueabi -mcpu=cortex-a8 %s -o %t2
+// RUN: ld.lld %t1 %t2 -o %t
+// RUN: llvm-objdump --no-print-imm-hex --triple=armv7aeb-none-linux-gnueabi -d --no-show-raw-insn %t | FileCheck %s
+// RUN: ld.lld -shared %t1 %t2 -o %t3
+// RUN: llvm-objdump --no-print-imm-hex --triple=armv7aeb-none-linux-gnueabi -d --no-show-raw-insn %t3 | FileCheck --check-prefix=DSO %s
+// RUN: llvm-readobj -S -r %t3 | FileCheck -check-prefix=DSOREL %s
+
+// RUN: ld.lld --hash-style=sysv --script %t2.script -shared %t1 %t2 -o %t5
+// RUN: llvm-objdump --no-print-imm-hex --triple=armv7aeb-none-linux-gnueabi -d --no-show-raw-insn %t5 | FileCheck --check-prefix=CHECKLONG-EB %s
+// RUN: llvm-readobj -S -r %t5 | FileCheck --check-prefix=DSORELLONG %s
+
+// CHECKLONG-EB: Disassembly of section .text:
+// CHECKLONG-EB-EMPTY:
+// CHECKLONG-EB-NEXT: <func1>:
+// CHECKLONG-EB-NEXT:     1000:       bx      lr
+// CHECKLONG-EB: <func2>:
+// CHECKLONG-EB-NEXT:     1004:       bx      lr
+// CHECKLONG-EB: <func3>:
+// CHECKLONG-EB-NEXT:     1008:       bx      lr
+// CHECKLONG-EB: <_start>:
+// CHECKLONG-EB-NEXT:     100c:       b       0x2020
+// CHECKLONG-EB-NEXT:     1010:       bl      0x2030
+// CHECKLONG-EB-NEXT:     1014:       beq     0x2040
+// CHECKLONG-EB-EMPTY:
+// CHECKLONG-EB-NEXT: Disassembly of section .plt:
+// CHECKLONG-EB-EMPTY:
+// CHECKLONG-EB-NEXT: <$a>:
+// CHECKLONG-EB-NEXT:     2000:       str     lr, [sp, #-4]!
+// CHECKLONG-EB-NEXT:     2004:       ldr     lr, [pc, #4]
+// CHECKLONG-EB-NEXT:     2008:       add     lr, pc, lr
+// CHECKLONG-EB-NEXT:     200c:       ldr     pc, [lr, #8]!
+// CHECKLONG-EB: <$d>:
+// CHECKLONG-EB-NEXT:     2010:	      11 10 f0 f0     .word   0x1110f0f0
+// CHECKLONG-EB-NEXT:     2014:       d4 d4 d4 d4     .word   0xd4d4d4d4
+// CHECKLONG-EB-NEXT:     2018:       d4 d4 d4 d4     .word   0xd4d4d4d4
+// CHECKLONG-EB-NEXT:     201c:       d4 d4 d4 d4     .word   0xd4d4d4d4
+// CHECKLONG-EB: <$a>:
+// CHECKLONG-EB-NEXT:     2020:       ldr     r12, [pc, #4]
+// CHECKLONG-EB-NEXT:     2024:       add     r12, r12, pc
+// CHECKLONG-EB-NEXT:     2028:       ldr     pc, [r12]
+// CHECKLONG-EB: <$d>:
+// CHECKLONG-EB-NEXT:     202c:       11 10 f0 e0     .word   0x1110f0e0
+// CHECKLONG-EB: <$a>:
+// CHECKLONG-EB-NEXT:     2030:       ldr     r12, [pc, #4]
+// CHECKLONG-EB-NEXT:     2034:       add     r12, r12, pc
+// CHECKLONG-EB-NEXT:     2038:       ldr     pc, [r12]
+// CHECKLONG-EB: <$d>:
+// CHECKLONG-EB-NEXT:     203c:       11 10 f0 d4     .word 0x1110f0d4
+// CHECKLONG-EB: <$a>:
+// CHECKLONG-EB-NEXT:     2040:       ldr     r12, [pc, #4]
+// CHECKLONG-EB-NEXT:     2044:       add     r12, r12, pc
+// CHECKLONG-EB-NEXT:     2048:       ldr     pc, [r12]
+// CHECKLONG-EB: <$d>:
+// CHECKLONG-EB-NEXT:     204c:       11 10 f0 c8     .word   0x1110f0c8
+
diff --git a/lld/test/ELF/arm-thumb-interwork-thunk-v5.s b/lld/test/ELF/arm-thumb-interwork-thunk-v5.s
--- a/lld/test/ELF/arm-thumb-interwork-thunk-v5.s
+++ b/lld/test/ELF/arm-thumb-interwork-thunk-v5.s
@@ -5,6 +5,12 @@
 // RUN: ld.lld %t -o %t3 --shared
 // RUN: llvm-objdump --no-print-imm-hex -d %t3 --triple=armv5-none-linux-gnueabi | FileCheck --check-prefix=CHECK-PI %s
 
+// RUN: llvm-mc -arm-add-build-attributes -filetype=obj -triple=armv5eb-none-linux-gnueabi %s -o %t
+// RUN: ld.lld %t -o %t2
+// RUN: llvm-objdump --no-print-imm-hex -d %t2 --triple=armv5eb-none-linux-gnueabi | FileCheck --check-prefix=CHECK-EB %s
+// RUN: ld.lld %t -o %t3 --shared
+// RUN: llvm-objdump --no-print-imm-hex -d %t3 --triple=armv5eb-none-linux-gnueabi | FileCheck --check-prefix=CHECK-EB-PI %s
+
 // Test ARM Thumb Interworking on older Arm architectures using Thunks that do
 // not use MOVT/MOVW instructions.
 // For pure interworking (not considering range extension) there is only the
@@ -40,6 +46,20 @@
 // CHECK: <$d>:
 // CHECK-NEXT: 21018: 11 10 02 00     .word   0x00021011
 
+// CHECK-EB: <_start>:
+// CHECK-EB-NEXT: 21000: ea000003        b       0x21014 <__ARMv5LongLdrPcThunk_thumb_func>
+// CHECK-EB-NEXT: 21004: fa000001        blx     0x21010 <thumb_func>
+// CHECK-EB-NEXT: 21008: fa000000        blx     0x21010 <thumb_func>
+// CHECK-EB-NEXT: 2100c: e12fff1e        bx      lr
+
+// CHECK-EB: <thumb_func>:
+// CHECK-EB-NEXT: 21010: 4770    bx      lr
+
+// CHECK-EB: <__ARMv5LongLdrPcThunk_thumb_func>:
+// CHECK-EB-NEXT: 21014: e51ff004        ldr     pc, [pc, #-4]
+// CHECK-EB: <$d>:
+// CHECK-EB-NEXT: 21018: 00 02 10 11     .word   0x00021011
+
 // CHECK-PI: <_start>:
 // CHECK-PI-NEXT: 11000: ea000003        b       0x11014 <__ARMv4PILongBXThunk_thumb_func>
 // CHECK-PI-NEXT: 11004: fa000001        blx     0x11010 <thumb_func>
@@ -56,6 +76,21 @@
 // CHECK-PI: <$d>:
 // CHECK-PI-NEXT: 11020: f1 ff ff ff     .word   0xfffffff1
 
+// CHECK-EB-PI: <_start>:
+// CHECK-EB-PI-NEXT: 11000: ea000003        b       0x11014 <__ARMv4PILongBXThunk_thumb_func>
+// CHECK-EB-PI-NEXT: 11004: fa000001        blx     0x11010 <thumb_func>
+// CHECK-EB-PI-NEXT: 11008: fa000000        blx     0x11010 <thumb_func>
+// CHECK-EB-PI-NEXT: 1100c: e12fff1e        bx      lr
+
+// CHECK-EB-PI: <thumb_func>:
+// CHECK-EB-PI-NEXT: 11010: 4770    bx      lr
+
+// CHECK-EB-PI: <__ARMv4PILongBXThunk_thumb_func>:
+// CHECK-EB-PI-NEXT: 11014: e59fc004        ldr     r12, [pc, #4]
+// CHECK-EB-PI-NEXT: 11018: e08fc00c        add     r12, pc, r12
+// CHECK-EB-PI-NEXT: 1101c: e12fff1c        bx      r12
+// CHECK-EB-PI: <$d>:
+// CHECK-EB-PI-NEXT: 11020: ff ff ff f1     .word   0xfffffff1
         .section .text.1, "ax", %progbits
         .thumb
         .hidden thumb_func
diff --git a/lld/test/ELF/arm-thumb-plt-reloc.s b/lld/test/ELF/arm-thumb-plt-reloc.s
--- a/lld/test/ELF/arm-thumb-plt-reloc.s
+++ b/lld/test/ELF/arm-thumb-plt-reloc.s
@@ -6,7 +6,15 @@
 // RUN: ld.lld -shared %t1 %t2 -o %t.so
 // RUN: llvm-objdump --no-print-imm-hex --triple=thumbv7a-none-linux-gnueabi -d %t.so | FileCheck --check-prefix=DSO %s
 // RUN: llvm-readobj -S -r %t.so | FileCheck -check-prefix=DSOREL %s
-//
+
+// RUN: llvm-mc -filetype=obj -triple=thumbv7aeb-none-linux-gnueabi %p/Inputs/arm-plt-reloc.s -o %t1
+// RUN: llvm-mc -filetype=obj -triple=thumbv7aeb-none-linux-gnueabi %s -o %t2
+// RUN: ld.lld %t1 %t2 -o %t
+// RUN: llvm-objdump --no-print-imm-hex --triple=thumbv7aeb-none-linux-gnueabi -d %t | FileCheck %s
+// RUN: ld.lld -shared %t1 %t2 -o %t.so
+// RUN: llvm-objdump --no-print-imm-hex --triple=thumbv7aeb-none-linux-gnueabi -d %t.so | FileCheck --check-prefix=DSO %s
+// RUN: llvm-readobj -S -r %t.so | FileCheck -check-prefix=DSOREL %s
+
 // Test PLT entry generation
  .syntax unified
  .text
diff --git a/lld/test/ELF/arm-thunk-arm-thumb-reuse.s b/lld/test/ELF/arm-thunk-arm-thumb-reuse.s
--- a/lld/test/ELF/arm-thunk-arm-thumb-reuse.s
+++ b/lld/test/ELF/arm-thunk-arm-thumb-reuse.s
@@ -4,6 +4,10 @@
 // RUN: ld.lld --script %t/script %t.o -o %t2
 // RUN: llvm-objdump --no-print-imm-hex --no-show-raw-insn -d %t2 | FileCheck %s
 
+// RUN: llvm-mc -arm-add-build-attributes -filetype=obj -triple=thumbv7aeb-none-linux-gnueabi -mcpu=cortex-a8 %t/test.s -o %t.o
+// RUN: ld.lld --script %t/script %t.o -o %t2
+// RUN: llvm-objdump --no-print-imm-hex --no-show-raw-insn -d %t2 | FileCheck %s
+
 /// Test that we can reuse thunks between Arm and Thumb callers
 /// using a BL. Expect two thunks, one for far, one for far2.
 
diff --git a/lld/test/ELF/arm-thunk-edgecase.s b/lld/test/ELF/arm-thunk-edgecase.s
--- a/lld/test/ELF/arm-thunk-edgecase.s
+++ b/lld/test/ELF/arm-thunk-edgecase.s
@@ -13,6 +13,12 @@
 // RUN: llvm-objdump --no-print-imm-hex --triple=armv7a-none-linux-gnueabi -d %tarm_to_thumb.so | FileCheck --check-prefix=ARM-TO-THUMB %s
 // RUN: llvm-objdump --no-print-imm-hex -d %tthumb_to_arm.so | FileCheck --check-prefix=THUMB-TO-ARM %s
 
+// RUN: llvm-mc -arm-add-build-attributes -filetype=obj -triple=armv7aeb-none-linux-gnueabi -mcpu=cortex-a8 %s -o %t.o
+// RUN: ld.lld -shared -Bsymbolic -script %tarm_to_thumb.script %t.o -o %tarm_to_thumb.so
+// RUN: ld.lld -shared -Bsymbolic -script %tthumb_to_arm.script %t.o -o %tthumb_to_arm.so
+// RUN: llvm-objdump --no-print-imm-hex --triple=armv7aeb-none-linux-gnueabi -d %tarm_to_thumb.so | FileCheck --check-prefix=ARM-TO-THUMB %s
+// RUN: llvm-objdump --no-print-imm-hex -d %tthumb_to_arm.so | FileCheck --check-prefix=THUMB-TO-ARM %s
+
 .syntax unified
 
 .arm
diff --git a/lld/test/ELF/arm-thunk-largesection.s b/lld/test/ELF/arm-thunk-largesection.s
--- a/lld/test/ELF/arm-thunk-largesection.s
+++ b/lld/test/ELF/arm-thunk-largesection.s
@@ -6,6 +6,15 @@
 // RUN: llvm-objdump --no-print-imm-hex -d --no-show-raw-insn --start-address=0x1021ff8 --stop-address=0x1021ffc %t2 | FileCheck --check-prefix=CHECK3 %s
 // RUN: llvm-objdump --no-print-imm-hex -d --no-show-raw-insn --start-address=0x2012ff8 --stop-address=0x2021ffc %t2 | FileCheck --check-prefix=CHECK4 %s
 // RUN: llvm-objdump --no-print-imm-hex -d --no-show-raw-insn --start-address=0x3021fec --stop-address=0x3021ff6 %t2 | FileCheck --check-prefix=CHECK5 %s
+
+// RUN: llvm-mc -arm-add-build-attributes -filetype=obj -triple=thumbv7aeb-none-linux-gnueabi -mcpu=cortex-a8 %s -o %t
+// RUN: ld.lld %t -o %t2
+// RUN: llvm-objdump --no-print-imm-hex -d --no-show-raw-insn --start-address=0x21000 --stop-address=0x21006 %t2 | FileCheck --check-prefix=CHECK1 %s
+// RUN: llvm-objdump --no-print-imm-hex -d --no-show-raw-insn --start-address=0x22004 --stop-address=0x22008 %t2 | FileCheck --check-prefix=CHECK2 %s
+// RUN: llvm-objdump --no-print-imm-hex -d --no-show-raw-insn --start-address=0x1021ff8 --stop-address=0x1021ffc %t2 | FileCheck --check-prefix=CHECK3 %s
+// RUN: llvm-objdump --no-print-imm-hex -d --no-show-raw-insn --start-address=0x2012ff8 --stop-address=0x2021ffc %t2 | FileCheck --check-prefix=CHECK4 %s
+// RUN: llvm-objdump --no-print-imm-hex -d --no-show-raw-insn --start-address=0x3021fec --stop-address=0x3021ff6 %t2 | FileCheck --check-prefix=CHECK5 %s
+
  .syntax unified
  .balign 0x1000
  .thumb
diff --git a/lld/test/ELF/arm-thunk-linkerscript-dotexpr.s b/lld/test/ELF/arm-thunk-linkerscript-dotexpr.s
--- a/lld/test/ELF/arm-thunk-linkerscript-dotexpr.s
+++ b/lld/test/ELF/arm-thunk-linkerscript-dotexpr.s
@@ -7,6 +7,12 @@
 // RUN: ld.lld --no-rosegment --script %t.script %t -o %t2
 // RUN: llvm-objdump --no-print-imm-hex -d %t2 --start-address=0x94 --stop-address=0xbc | FileCheck --check-prefix=CHECK1 %s
 // RUN: llvm-objdump --no-print-imm-hex -d %t2 --start-address=0x20000bc --stop-address=0x20000de | FileCheck --check-prefix=CHECK2 %s
+
+// RUN: llvm-mc -arm-add-build-attributes -filetype=obj -triple=armv7aeb-none-linux-gnueabi -mcpu=cortex-a8 %s -o %t
+// RUN: ld.lld --no-rosegment --script %t.script %t -o %t2
+// RUN: llvm-objdump --no-print-imm-hex -d %t2 --start-address=0x94 --stop-address=0xbc | FileCheck --check-prefix=CHECK1 %s
+// RUN: llvm-objdump --no-print-imm-hex -d %t2 --start-address=0x20000bc --stop-address=0x20000de | FileCheck --check-prefix=CHECK2 %s
+
 // Test that range extension thunks can handle location expressions within
 // a Section Description
  .syntax unified
diff --git a/lld/test/ELF/arm-thunk-linkerscript.s b/lld/test/ELF/arm-thunk-linkerscript.s
--- a/lld/test/ELF/arm-thunk-linkerscript.s
+++ b/lld/test/ELF/arm-thunk-linkerscript.s
@@ -7,6 +7,11 @@
 // RUN:       } " > %t.script
 // RUN: ld.lld --no-rosegment --script %t.script %t -o %t2
 // RUN: llvm-objdump --no-print-imm-hex -d %t2 | FileCheck %s
+
+// RUN: llvm-mc -arm-add-build-attributes -filetype=obj -triple=armv7aeb-none-linux-gnueabi -mcpu=cortex-a8 %s -o %t
+// RUN: ld.lld --no-rosegment --script %t.script %t -o %t2
+// RUN: llvm-objdump --no-print-imm-hex -d %t2 | FileCheck %s
+
 // Simple test that we can support range extension thunks with linker scripts
  .syntax unified
  .section .text_low, "ax", %progbits
diff --git a/lld/test/ELF/arm-thunk-multipass-plt.s b/lld/test/ELF/arm-thunk-multipass-plt.s
--- a/lld/test/ELF/arm-thunk-multipass-plt.s
+++ b/lld/test/ELF/arm-thunk-multipass-plt.s
@@ -4,6 +4,13 @@
 // RUN: llvm-objdump --no-print-imm-hex --no-show-raw-insn --start-address=0x70000c --stop-address=0x700010 --triple=armv5-none-linux-gnueabi -d %t2 | FileCheck %s
 // RUN: llvm-objdump --no-print-imm-hex --no-show-raw-insn --start-address=0x80000c --stop-address=0x800010 -d %t2 | FileCheck %s --check-prefix=CHECK-CALL
 // RUN: llvm-objdump --no-print-imm-hex --no-show-raw-insn --start-address=0xd00020 --stop-address=0xd00060 --triple=armv5-none-linux-gnueabi -d %t2 | FileCheck %s --check-prefix=CHECK-PLT
+
+// RUN: llvm-mc -arm-add-build-attributes -filetype=obj -triple=armv5eb-none-linux-gnueabi %s -o %t
+// RUN: ld.lld %t -o %t2 --shared
+// RUN: llvm-objdump --no-print-imm-hex --no-show-raw-insn --start-address=0x70000c --stop-address=0x700010 --triple=armv5eb-none-linux-gnueabi -d %t2 | FileCheck %s
+// RUN: llvm-objdump --no-print-imm-hex --no-show-raw-insn --start-address=0x80000c --stop-address=0x800010 -d %t2 | FileCheck %s --check-prefix=CHECK-CALL
+// RUN: llvm-objdump --no-print-imm-hex --no-show-raw-insn --start-address=0xd00020 --stop-address=0xd00060 --triple=armv5eb-none-linux-gnueabi -d %t2 | FileCheck %s --check-prefix=CHECK-PLT
+
 /// When we create a thunk to a PLT entry the relocation is redirected to the
 /// Thunk, changing its expression to a non-PLT equivalent. If the thunk
 /// becomes unusable we need to restore the relocation expression to the PLT
diff --git a/lld/test/ELF/arm-thunk-nosuitable.s b/lld/test/ELF/arm-thunk-nosuitable.s
--- a/lld/test/ELF/arm-thunk-nosuitable.s
+++ b/lld/test/ELF/arm-thunk-nosuitable.s
@@ -1,6 +1,10 @@
 // REQUIRES: arm
 // RUN: llvm-mc %s --arm-add-build-attributes --triple=armv7a-linux-gnueabihf --filetype=obj -o %t.o
 // RUN: ld.lld %t.o -o %t
+// RUN: llvm-objdump -d --start-address=0x2200b4 --stop-address=0x2200be %t | FileCheck %s
+
+// RUN: llvm-mc %s --arm-add-build-attributes --triple=armv7aeb-linux-gnueabihf --filetype=obj -mcpu=cortex-a8 -o %t.o
+// RUN: ld.lld %t.o -o %t
 // RUN: llvm-objdump -d --start-address=0x2200b4 --stop-address=0x2200be %t | FileCheck %s
 
         /// Create a conditional branch too far away from a precreated thunk
diff --git a/lld/test/ELF/arm-thunk-re-add.s b/lld/test/ELF/arm-thunk-re-add.s
--- a/lld/test/ELF/arm-thunk-re-add.s
+++ b/lld/test/ELF/arm-thunk-re-add.s
@@ -122,3 +122,12 @@
 // CHECK3-NEXT:  1100058:       e5bcf070        ldr     pc, [r12, #112]!
 // CHECK3: <$d>:
 // CHECK3-NEXT:  110005c:       d4 d4 d4 d4     .word   0xd4d4d4d4
+
+// RUN: llvm-mc -arm-add-build-attributes -filetype=obj -triple=thumbv7aeb-none-linux-gnueabi -mcpu=cortex-a8 %s -o %t
+// RUN: ld.lld %t --shared -o %t.so
+// The output file is large, most of it zeroes. We dissassemble only the
+// parts we need to speed up the test and avoid a large output file
+// RUN: llvm-objdump --no-print-imm-hex -d %t.so --start-address=0x1000004 --stop-address=0x100001c | FileCheck --check-prefix=CHECK1 %s
+// RUN: llvm-objdump --no-print-imm-hex -d %t.so --start-address=0x1100008 --stop-address=0x1100022 | FileCheck --check-prefix=CHECK2 %s
+// RUN: llvm-objdump --no-print-imm-hex -d %t.so --start-address=0x1100020 --stop-address=0x1100064 --triple=armv7aeb-linux-gnueabihf | FileCheck --check-prefix=CHECK3 %s
+
diff --git a/lld/test/ELF/arm-thunk-reuse.s b/lld/test/ELF/arm-thunk-reuse.s
--- a/lld/test/ELF/arm-thunk-reuse.s
+++ b/lld/test/ELF/arm-thunk-reuse.s
@@ -4,6 +4,10 @@
 # RUN: ld.lld -pie -T %t/lds %t/a.o -o %t/a
 # RUN: llvm-objdump --no-print-imm-hex -d --no-show-raw-insn %t/a | FileCheck %s
 
+# RUN: llvm-mc -filetype=obj -triple=armv7eb-a-none-eabi --arm-add-build-attributes -mcpu=cortex-a8 %t/a.s -o %t/a.o
+# RUN: ld.lld -pie -T %t/lds %t/a.o -o %t/a
+# RUN: llvm-objdump --no-print-imm-hex -d --no-show-raw-insn %t/a | FileCheck %s
+
 ## We create a thunk for dest.
 # CHECK-LABEL: <mid>:
 # CHECK-NEXT:   2010004:     b       0x2010008 <__ARMV7PILongThunk_dest>
diff --git a/lld/test/ELF/arm-thunk-section-too-large.s b/lld/test/ELF/arm-thunk-section-too-large.s
--- a/lld/test/ELF/arm-thunk-section-too-large.s
+++ b/lld/test/ELF/arm-thunk-section-too-large.s
@@ -2,6 +2,9 @@
 // RUN: llvm-mc %s -triple=armv7a-linux-gnueabihf -arm-add-build-attributes -filetype=obj -o %t.o
 // RUN: not ld.lld %t.o -o /dev/null 2>&1 | FileCheck %s
 
+// RUN: llvm-mc %s -triple=armv7aeb-linux-gnueabihf -arm-add-build-attributes -filetype=obj -mcpu=cortex-a8 -o %t.o
+// RUN: not ld.lld %t.o -o /dev/null 2>&1 | FileCheck %s
+
 // CHECK: InputSection too large for range extension thunk
         .syntax unified
         .thumb
diff --git a/lld/test/ELF/arm-thunk-toolargesection.s b/lld/test/ELF/arm-thunk-toolargesection.s
--- a/lld/test/ELF/arm-thunk-toolargesection.s
+++ b/lld/test/ELF/arm-thunk-toolargesection.s
@@ -1,6 +1,10 @@
 // REQUIRES: arm
 // RUN: llvm-mc -filetype=obj -triple=thumbv7a-none-linux-gnueabi %s -o %t
 // RUN: not ld.lld %t -o /dev/null 2>&1 | FileCheck %s
+
+// RUN: llvm-mc -filetype=obj -triple=thumbv7aeb-none-linux-gnueabi %s -o %t
+// RUN: not ld.lld %t -o /dev/null 2>&1 | FileCheck %s
+
  .syntax unified
  .balign 0x1000
  .thumb
diff --git a/lld/test/ELF/arm-v5-reloc-error.s b/lld/test/ELF/arm-v5-reloc-error.s
--- a/lld/test/ELF/arm-v5-reloc-error.s
+++ b/lld/test/ELF/arm-v5-reloc-error.s
@@ -7,6 +7,9 @@
 // RUN:       } " > %t.script
 // RUN: not ld.lld --script %t.script %t -o /dev/null 2>&1 | FileCheck %s
 
+// RUN: llvm-mc -filetype=obj -triple=armv7aeb-linux-gnueabi -mcpu=cortex-a8 %s -o %t
+// RUN: not ld.lld --script %t.script %t -o /dev/null 2>&1 | FileCheck %s
+
 // CHECK: error: relocation R_ARM_THM_JUMP24 to far not supported for Armv5 or Armv6 targets
 
 // Lie about our build attributes. Our triple is armv7a-linux-gnueabi but
diff --git a/lld/test/ELF/emulation-arm.s b/lld/test/ELF/emulation-arm.s
--- a/lld/test/ELF/emulation-arm.s
+++ b/lld/test/ELF/emulation-arm.s
@@ -23,5 +23,36 @@
 # ARM-NEXT:   Machine: EM_ARM (0x28)
 # ARM-NEXT:   Version: 1
 
+# RUN: llvm-mc -arm-add-build-attributes -filetype=obj -triple=armv7aeb-none-linux-gnueabi %s -o %t.o
+# RUN: ld.lld -marmelfb_linux_eabi %t.o -o %t1
+# echo 'OUTPUT_FORMAT(elf32-bigarm)' > %t6arm.script
+# ld.lld %tarm -o %t6arm
+# RUN: llvm-readobj -h %t1 | FileCheck %s --check-prefix=ARMEB
+# RUN: llvm-readobj -h %t1 | FileCheck %s --check-prefix=BE8
+
+# ARMEB: ElfHeader {
+# ARMEB-NEXT:   Ident {
+# ARMEB-NEXT:     Magic: (7F 45 4C 46)
+# ARMEB-NEXT:     Class: 32-bit (0x1)
+# ARMEB-NEXT:     DataEncoding: BigEndian (0x2)
+# ARMEB-NEXT:     FileVersion: 1
+# ARMEB-NEXT:     OS/ABI: SystemV (0x0)
+# ARMEB-NEXT:     ABIVersion: 0
+# ARMEB-NEXT:     Unused: (00 00 00 00 00 00 00)
+# ARMEB-NEXT:   }
+# ARMEB-NEXT:   Type: Executable (0x2)
+# ARMEB-NEXT:   Machine: EM_ARM (0x28)
+# ARMEB-NEXT:   Version: 1
+
+## Ensure that the EF_ARM_BE8 flag is not set for be32
+## This will have to be modified on the be8 is implemented
+# ARMEB:   Flags [ (0x5000200)
+# ARMEB-NEXT:     0x200
+# ARMEB-NEXT:     0x1000000
+# ARMEB-NEXT:     0x4000000
+# ARMEB-NEXT:   ]
+
+# BE8-NOT: 0x800000
+
 .globl _start
 _start: