diff --git a/llvm/include/llvm/CodeGen/SelectionDAGISel.h b/llvm/include/llvm/CodeGen/SelectionDAGISel.h --- a/llvm/include/llvm/CodeGen/SelectionDAGISel.h +++ b/llvm/include/llvm/CodeGen/SelectionDAGISel.h @@ -62,9 +62,7 @@ /// Used to report things like combines and FastISel failures. std::unique_ptr ORE; - static char ID; - - explicit SelectionDAGISel(TargetMachine &tm, + explicit SelectionDAGISel(char &ID, TargetMachine &tm, CodeGenOpt::Level OL = CodeGenOpt::Default); ~SelectionDAGISel() override; diff --git a/llvm/lib/CodeGen/SelectionDAG/SelectionDAGISel.cpp b/llvm/lib/CodeGen/SelectionDAG/SelectionDAGISel.cpp --- a/llvm/lib/CodeGen/SelectionDAG/SelectionDAGISel.cpp +++ b/llvm/lib/CodeGen/SelectionDAG/SelectionDAGISel.cpp @@ -313,7 +313,8 @@ // SelectionDAGISel code //===----------------------------------------------------------------------===// -SelectionDAGISel::SelectionDAGISel(TargetMachine &tm, CodeGenOpt::Level OL) +SelectionDAGISel::SelectionDAGISel(char &ID, TargetMachine &tm, + CodeGenOpt::Level OL) : MachineFunctionPass(ID), TM(tm), FuncInfo(new FunctionLoweringInfo()), SwiftError(new SwiftErrorValueTracking()), CurDAG(new SelectionDAG(tm, OL)), @@ -3815,5 +3816,3 @@ } report_fatal_error(Twine(Msg.str())); } - -char SelectionDAGISel::ID = 0; diff --git a/llvm/lib/Target/AArch64/AArch64ISelDAGToDAG.cpp b/llvm/lib/Target/AArch64/AArch64ISelDAGToDAG.cpp --- a/llvm/lib/Target/AArch64/AArch64ISelDAGToDAG.cpp +++ b/llvm/lib/Target/AArch64/AArch64ISelDAGToDAG.cpp @@ -43,9 +43,11 @@ const AArch64Subtarget *Subtarget; public: + static char ID; + explicit AArch64DAGToDAGISel(AArch64TargetMachine &tm, CodeGenOpt::Level OptLevel) - : SelectionDAGISel(tm, OptLevel), Subtarget(nullptr) {} + : SelectionDAGISel(ID, tm, OptLevel), Subtarget(nullptr) {} StringRef getPassName() const override { return "AArch64 Instruction Selection"; @@ -419,6 +421,8 @@ }; } // end anonymous namespace +char AArch64DAGToDAGISel::ID = 0; + /// isIntImmediate - This method tests to see if the node is a constant /// operand. If so Imm will receive the 32-bit value. static bool isIntImmediate(const SDNode *N, uint64_t &Imm) { diff --git a/llvm/lib/Target/AMDGPU/AMDGPUISelDAGToDAG.h b/llvm/lib/Target/AMDGPU/AMDGPUISelDAGToDAG.h --- a/llvm/lib/Target/AMDGPU/AMDGPUISelDAGToDAG.h +++ b/llvm/lib/Target/AMDGPU/AMDGPUISelDAGToDAG.h @@ -91,6 +91,8 @@ bool fp16SrcZerosHighBits(unsigned Opc) const; public: + static char ID; + explicit AMDGPUDAGToDAGISel(TargetMachine *TM = nullptr, CodeGenOpt::Level OptLevel = CodeGenOpt::Default); ~AMDGPUDAGToDAGISel() override = default; diff --git a/llvm/lib/Target/AMDGPU/AMDGPUISelDAGToDAG.cpp b/llvm/lib/Target/AMDGPU/AMDGPUISelDAGToDAG.cpp --- a/llvm/lib/Target/AMDGPU/AMDGPUISelDAGToDAG.cpp +++ b/llvm/lib/Target/AMDGPU/AMDGPUISelDAGToDAG.cpp @@ -119,7 +119,7 @@ AMDGPUDAGToDAGISel::AMDGPUDAGToDAGISel( TargetMachine *TM /*= nullptr*/, CodeGenOpt::Level OptLevel /*= CodeGenOpt::Default*/) - : SelectionDAGISel(*TM, OptLevel) { + : SelectionDAGISel(ID, *TM, OptLevel) { EnableLateStructurizeCFG = AMDGPUTargetMachine::EnableLateStructurizeCFG; } @@ -3001,3 +3001,5 @@ CurDAG->RemoveDeadNodes(); } while (IsModified); } + +char AMDGPUDAGToDAGISel::ID = 0; diff --git a/llvm/lib/Target/ARM/ARMISelDAGToDAG.cpp b/llvm/lib/Target/ARM/ARMISelDAGToDAG.cpp --- a/llvm/lib/Target/ARM/ARMISelDAGToDAG.cpp +++ b/llvm/lib/Target/ARM/ARMISelDAGToDAG.cpp @@ -58,8 +58,10 @@ const ARMSubtarget *Subtarget; public: + static char ID; + explicit ARMDAGToDAGISel(ARMBaseTargetMachine &tm, CodeGenOpt::Level OptLevel) - : SelectionDAGISel(tm, OptLevel) {} + : SelectionDAGISel(ID, tm, OptLevel) {} bool runOnMachineFunction(MachineFunction &MF) override { // Reset the subtarget each time through. @@ -360,6 +362,8 @@ }; } +char ARMDAGToDAGISel::ID = 0; + /// isInt32Immediate - This method tests to see if the node is a 32-bit constant /// operand. If so Imm will receive the 32-bit value. static bool isInt32Immediate(SDNode *N, unsigned &Imm) { diff --git a/llvm/lib/Target/AVR/AVRISelDAGToDAG.cpp b/llvm/lib/Target/AVR/AVRISelDAGToDAG.cpp --- a/llvm/lib/Target/AVR/AVRISelDAGToDAG.cpp +++ b/llvm/lib/Target/AVR/AVRISelDAGToDAG.cpp @@ -26,8 +26,10 @@ /// Lowers LLVM IR (in DAG form) to AVR MC instructions (in DAG form). class AVRDAGToDAGISel : public SelectionDAGISel { public: + static char ID; + AVRDAGToDAGISel(AVRTargetMachine &TM, CodeGenOpt::Level OptLevel) - : SelectionDAGISel(TM, OptLevel), Subtarget(nullptr) {} + : SelectionDAGISel(ID, TM, OptLevel), Subtarget(nullptr) {} StringRef getPassName() const override { return "AVR DAG->DAG Instruction Selection"; @@ -56,6 +58,8 @@ const AVRSubtarget *Subtarget; }; +char AVRDAGToDAGISel::ID = 0; + bool AVRDAGToDAGISel::runOnMachineFunction(MachineFunction &MF) { Subtarget = &MF.getSubtarget(); return SelectionDAGISel::runOnMachineFunction(MF); @@ -581,3 +585,4 @@ } } // end of namespace llvm + diff --git a/llvm/lib/Target/BPF/BPFISelDAGToDAG.cpp b/llvm/lib/Target/BPF/BPFISelDAGToDAG.cpp --- a/llvm/lib/Target/BPF/BPFISelDAGToDAG.cpp +++ b/llvm/lib/Target/BPF/BPFISelDAGToDAG.cpp @@ -45,8 +45,10 @@ const BPFSubtarget *Subtarget; public: + static char ID; + explicit BPFDAGToDAGISel(BPFTargetMachine &TM) - : SelectionDAGISel(TM), Subtarget(nullptr) {} + : SelectionDAGISel(ID, TM), Subtarget(nullptr) {} StringRef getPassName() const override { return "BPF DAG->DAG Pattern Instruction Selection"; @@ -96,6 +98,8 @@ }; } // namespace +char BPFDAGToDAGISel::ID = 0; + // ComplexPattern used on BPF Load/Store instructions bool BPFDAGToDAGISel::SelectAddr(SDValue Addr, SDValue &Base, SDValue &Offset) { // if Address is FI, get the TargetFrameIndex. diff --git a/llvm/lib/Target/Hexagon/HexagonISelDAGToDAG.h b/llvm/lib/Target/Hexagon/HexagonISelDAGToDAG.h --- a/llvm/lib/Target/Hexagon/HexagonISelDAGToDAG.h +++ b/llvm/lib/Target/Hexagon/HexagonISelDAGToDAG.h @@ -31,9 +31,11 @@ const HexagonInstrInfo *HII; const HexagonRegisterInfo *HRI; public: + static char ID; + explicit HexagonDAGToDAGISel(HexagonTargetMachine &tm, CodeGenOpt::Level OptLevel) - : SelectionDAGISel(tm, OptLevel), HST(nullptr), HII(nullptr), + : SelectionDAGISel(ID, tm, OptLevel), HST(nullptr), HII(nullptr), HRI(nullptr) {} bool runOnMachineFunction(MachineFunction &MF) override { diff --git a/llvm/lib/Target/Hexagon/HexagonISelDAGToDAG.cpp b/llvm/lib/Target/Hexagon/HexagonISelDAGToDAG.cpp --- a/llvm/lib/Target/Hexagon/HexagonISelDAGToDAG.cpp +++ b/llvm/lib/Target/Hexagon/HexagonISelDAGToDAG.cpp @@ -63,6 +63,8 @@ } } +char HexagonDAGToDAGISel::ID = 0; + void HexagonDAGToDAGISel::SelectIndexedLoad(LoadSDNode *LD, const SDLoc &dl) { SDValue Chain = LD->getChain(); SDValue Base = LD->getBasePtr(); diff --git a/llvm/lib/Target/Lanai/LanaiISelDAGToDAG.cpp b/llvm/lib/Target/Lanai/LanaiISelDAGToDAG.cpp --- a/llvm/lib/Target/Lanai/LanaiISelDAGToDAG.cpp +++ b/llvm/lib/Target/Lanai/LanaiISelDAGToDAG.cpp @@ -47,8 +47,10 @@ class LanaiDAGToDAGISel : public SelectionDAGISel { public: + static char ID; + explicit LanaiDAGToDAGISel(LanaiTargetMachine &TargetMachine) - : SelectionDAGISel(TargetMachine) {} + : SelectionDAGISel(ID, TargetMachine) {} bool runOnMachineFunction(MachineFunction &MF) override { return SelectionDAGISel::runOnMachineFunction(MF); @@ -98,6 +100,8 @@ } // namespace +char LanaiDAGToDAGISel::ID = 0; + // Helper functions for ComplexPattern used on LanaiInstrInfo // Used on Lanai Load/Store instructions. bool LanaiDAGToDAGISel::selectAddrSls(SDValue Addr, SDValue &Offset) { diff --git a/llvm/lib/Target/MSP430/MSP430ISelDAGToDAG.cpp b/llvm/lib/Target/MSP430/MSP430ISelDAGToDAG.cpp --- a/llvm/lib/Target/MSP430/MSP430ISelDAGToDAG.cpp +++ b/llvm/lib/Target/MSP430/MSP430ISelDAGToDAG.cpp @@ -90,8 +90,10 @@ namespace { class MSP430DAGToDAGISel : public SelectionDAGISel { public: + static char ID; + MSP430DAGToDAGISel(MSP430TargetMachine &TM, CodeGenOpt::Level OptLevel) - : SelectionDAGISel(TM, OptLevel) {} + : SelectionDAGISel(ID, TM, OptLevel) {} private: StringRef getPassName() const override { @@ -119,6 +121,8 @@ }; } // end anonymous namespace +char MSP430DAGToDAGISel::ID; + /// createMSP430ISelDag - This pass converts a legalized DAG into a /// MSP430-specific DAG, ready for instruction scheduling. /// diff --git a/llvm/lib/Target/Mips/MipsISelDAGToDAG.h b/llvm/lib/Target/Mips/MipsISelDAGToDAG.h --- a/llvm/lib/Target/Mips/MipsISelDAGToDAG.h +++ b/llvm/lib/Target/Mips/MipsISelDAGToDAG.h @@ -30,8 +30,10 @@ class MipsDAGToDAGISel : public SelectionDAGISel { public: + static char ID; + explicit MipsDAGToDAGISel(MipsTargetMachine &TM, CodeGenOpt::Level OL) - : SelectionDAGISel(TM, OL), Subtarget(nullptr) {} + : SelectionDAGISel(ID, TM, OL), Subtarget(nullptr) {} // Pass Name StringRef getPassName() const override { diff --git a/llvm/lib/Target/Mips/MipsISelDAGToDAG.cpp b/llvm/lib/Target/Mips/MipsISelDAGToDAG.cpp --- a/llvm/lib/Target/Mips/MipsISelDAGToDAG.cpp +++ b/llvm/lib/Target/Mips/MipsISelDAGToDAG.cpp @@ -322,3 +322,5 @@ } return true; } + +char MipsDAGToDAGISel::ID = 0; diff --git a/llvm/lib/Target/NVPTX/NVPTXISelDAGToDAG.h b/llvm/lib/Target/NVPTX/NVPTXISelDAGToDAG.h --- a/llvm/lib/Target/NVPTX/NVPTXISelDAGToDAG.h +++ b/llvm/lib/Target/NVPTX/NVPTXISelDAGToDAG.h @@ -38,6 +38,8 @@ bool useShortPointers() const; public: + static char ID; + explicit NVPTXDAGToDAGISel(NVPTXTargetMachine &tm, CodeGenOpt::Level OptLevel); diff --git a/llvm/lib/Target/NVPTX/NVPTXISelDAGToDAG.cpp b/llvm/lib/Target/NVPTX/NVPTXISelDAGToDAG.cpp --- a/llvm/lib/Target/NVPTX/NVPTXISelDAGToDAG.cpp +++ b/llvm/lib/Target/NVPTX/NVPTXISelDAGToDAG.cpp @@ -35,9 +35,11 @@ return new NVPTXDAGToDAGISel(TM, OptLevel); } +char NVPTXDAGToDAGISel::ID = 0; + NVPTXDAGToDAGISel::NVPTXDAGToDAGISel(NVPTXTargetMachine &tm, CodeGenOpt::Level OptLevel) - : SelectionDAGISel(tm, OptLevel), TM(tm) { + : SelectionDAGISel(ID, tm, OptLevel), TM(tm) { doMulWide = (OptLevel > 0); } diff --git a/llvm/lib/Target/PowerPC/PPCISelDAGToDAG.cpp b/llvm/lib/Target/PowerPC/PPCISelDAGToDAG.cpp --- a/llvm/lib/Target/PowerPC/PPCISelDAGToDAG.cpp +++ b/llvm/lib/Target/PowerPC/PPCISelDAGToDAG.cpp @@ -145,8 +145,10 @@ unsigned GlobalBaseReg = 0; public: + static char ID; + explicit PPCDAGToDAGISel(PPCTargetMachine &tm, CodeGenOpt::Level OptLevel) - : SelectionDAGISel(tm, OptLevel), TM(tm) {} + : SelectionDAGISel(ID, tm, OptLevel), TM(tm) {} bool runOnMachineFunction(MachineFunction &MF) override { // Make sure we re-emit a set of the global base reg if necessary @@ -445,6 +447,8 @@ } // end anonymous namespace +char PPCDAGToDAGISel::ID = 0; + /// getGlobalBaseReg - Output the instructions required to put the /// base address to use for accessing globals into a register. /// diff --git a/llvm/lib/Target/RISCV/RISCVISelDAGToDAG.h b/llvm/lib/Target/RISCV/RISCVISelDAGToDAG.h --- a/llvm/lib/Target/RISCV/RISCVISelDAGToDAG.h +++ b/llvm/lib/Target/RISCV/RISCVISelDAGToDAG.h @@ -24,9 +24,11 @@ const RISCVSubtarget *Subtarget = nullptr; public: + static char ID; + explicit RISCVDAGToDAGISel(RISCVTargetMachine &TargetMachine, CodeGenOpt::Level OptLevel) - : SelectionDAGISel(TargetMachine, OptLevel) {} + : SelectionDAGISel(ID, TargetMachine, OptLevel) {} StringRef getPassName() const override { return "RISCV DAG->DAG Pattern Instruction Selection"; diff --git a/llvm/lib/Target/RISCV/RISCVISelDAGToDAG.cpp b/llvm/lib/Target/RISCV/RISCVISelDAGToDAG.cpp --- a/llvm/lib/Target/RISCV/RISCVISelDAGToDAG.cpp +++ b/llvm/lib/Target/RISCV/RISCVISelDAGToDAG.cpp @@ -2907,3 +2907,5 @@ CodeGenOpt::Level OptLevel) { return new RISCVDAGToDAGISel(TM, OptLevel); } + +char RISCVDAGToDAGISel::ID = 0; diff --git a/llvm/lib/Target/Sparc/SparcISelDAGToDAG.cpp b/llvm/lib/Target/Sparc/SparcISelDAGToDAG.cpp --- a/llvm/lib/Target/Sparc/SparcISelDAGToDAG.cpp +++ b/llvm/lib/Target/Sparc/SparcISelDAGToDAG.cpp @@ -33,7 +33,9 @@ /// make the right decision when generating code for different targets. const SparcSubtarget *Subtarget = nullptr; public: - explicit SparcDAGToDAGISel(SparcTargetMachine &tm) : SelectionDAGISel(tm) {} + static char ID; + + explicit SparcDAGToDAGISel(SparcTargetMachine &tm) : SelectionDAGISel(ID, tm) {} bool runOnMachineFunction(MachineFunction &MF) override { Subtarget = &MF.getSubtarget(); @@ -65,6 +67,8 @@ }; } // end anonymous namespace +char SparcDAGToDAGISel::ID = 0; + SDNode* SparcDAGToDAGISel::getGlobalBaseReg() { Register GlobalBaseReg = Subtarget->getInstrInfo()->getGlobalBaseReg(MF); return CurDAG->getRegister(GlobalBaseReg, diff --git a/llvm/lib/Target/SystemZ/SystemZISelDAGToDAG.cpp b/llvm/lib/Target/SystemZ/SystemZISelDAGToDAG.cpp --- a/llvm/lib/Target/SystemZ/SystemZISelDAGToDAG.cpp +++ b/llvm/lib/Target/SystemZ/SystemZISelDAGToDAG.cpp @@ -345,8 +345,10 @@ SDValue expandSelectBoolean(SDNode *Node); public: + static char ID; + SystemZDAGToDAGISel(SystemZTargetMachine &TM, CodeGenOpt::Level OptLevel) - : SelectionDAGISel(TM, OptLevel) {} + : SelectionDAGISel(ID, TM, OptLevel) {} bool runOnMachineFunction(MachineFunction &MF) override { const Function &F = MF.getFunction(); @@ -378,6 +380,8 @@ }; } // end anonymous namespace +char SystemZDAGToDAGISel::ID = 0; + FunctionPass *llvm::createSystemZISelDag(SystemZTargetMachine &TM, CodeGenOpt::Level OptLevel) { return new SystemZDAGToDAGISel(TM, OptLevel); diff --git a/llvm/lib/Target/VE/VEISelDAGToDAG.cpp b/llvm/lib/Target/VE/VEISelDAGToDAG.cpp --- a/llvm/lib/Target/VE/VEISelDAGToDAG.cpp +++ b/llvm/lib/Target/VE/VEISelDAGToDAG.cpp @@ -31,7 +31,9 @@ const VESubtarget *Subtarget; public: - explicit VEDAGToDAGISel(VETargetMachine &tm) : SelectionDAGISel(tm) {} + static char ID; + + explicit VEDAGToDAGISel(VETargetMachine &tm) : SelectionDAGISel(ID, tm) {} bool runOnMachineFunction(MachineFunction &MF) override { Subtarget = &MF.getSubtarget(); @@ -69,6 +71,8 @@ }; } // end anonymous namespace +char VEDAGToDAGISel::ID = 0; + bool VEDAGToDAGISel::selectADDRrri(SDValue Addr, SDValue &Base, SDValue &Index, SDValue &Offset) { if (Addr.getOpcode() == ISD::FrameIndex) diff --git a/llvm/lib/Target/WebAssembly/WebAssemblyISelDAGToDAG.cpp b/llvm/lib/Target/WebAssembly/WebAssemblyISelDAGToDAG.cpp --- a/llvm/lib/Target/WebAssembly/WebAssemblyISelDAGToDAG.cpp +++ b/llvm/lib/Target/WebAssembly/WebAssemblyISelDAGToDAG.cpp @@ -41,9 +41,11 @@ const WebAssemblySubtarget *Subtarget; public: + static char ID; + WebAssemblyDAGToDAGISel(WebAssemblyTargetMachine &TM, CodeGenOpt::Level OptLevel) - : SelectionDAGISel(TM, OptLevel), Subtarget(nullptr) {} + : SelectionDAGISel(ID, TM, OptLevel), Subtarget(nullptr) {} StringRef getPassName() const override { return "WebAssembly Instruction Selection"; @@ -82,6 +84,8 @@ }; } // end anonymous namespace +char WebAssemblyDAGToDAGISel::ID; + void WebAssemblyDAGToDAGISel::PreprocessISelDAG() { // Stack objects that should be allocated to locals are hoisted to WebAssembly // locals when they are first used. However for those without uses, we hoist diff --git a/llvm/lib/Target/X86/X86ISelDAGToDAG.cpp b/llvm/lib/Target/X86/X86ISelDAGToDAG.cpp --- a/llvm/lib/Target/X86/X86ISelDAGToDAG.cpp +++ b/llvm/lib/Target/X86/X86ISelDAGToDAG.cpp @@ -168,8 +168,10 @@ bool IndirectTlsSegRefs; public: + static char ID; + explicit X86DAGToDAGISel(X86TargetMachine &tm, CodeGenOpt::Level OptLevel) - : SelectionDAGISel(tm, OptLevel), Subtarget(nullptr), + : SelectionDAGISel(ID, tm, OptLevel), Subtarget(nullptr), OptForMinSize(false), IndirectTlsSegRefs(false) {} StringRef getPassName() const override { @@ -574,6 +576,7 @@ }; } +char X86DAGToDAGISel::ID = 0; // Returns true if this masked compare can be implemented legally with this // type. diff --git a/llvm/lib/Target/XCore/XCoreISelDAGToDAG.cpp b/llvm/lib/Target/XCore/XCoreISelDAGToDAG.cpp --- a/llvm/lib/Target/XCore/XCoreISelDAGToDAG.cpp +++ b/llvm/lib/Target/XCore/XCoreISelDAGToDAG.cpp @@ -38,8 +38,10 @@ class XCoreDAGToDAGISel : public SelectionDAGISel { public: + static char ID; + XCoreDAGToDAGISel(XCoreTargetMachine &TM, CodeGenOpt::Level OptLevel) - : SelectionDAGISel(TM, OptLevel) {} + : SelectionDAGISel(ID, TM, OptLevel) {} void Select(SDNode *N) override; bool tryBRIND(SDNode *N); @@ -76,6 +78,8 @@ }; } // end anonymous namespace +char XCoreDAGToDAGISel::ID = 0; + /// createXCoreISelDag - This pass converts a legalized DAG into a /// XCore-specific DAG, ready for instruction scheduling. ///