diff --git a/llvm/lib/CodeGen/SelectionDAG/FunctionLoweringInfo.cpp b/llvm/lib/CodeGen/SelectionDAG/FunctionLoweringInfo.cpp --- a/llvm/lib/CodeGen/SelectionDAG/FunctionLoweringInfo.cpp +++ b/llvm/lib/CodeGen/SelectionDAG/FunctionLoweringInfo.cpp @@ -13,6 +13,7 @@ #include "llvm/CodeGen/FunctionLoweringInfo.h" #include "llvm/ADT/APInt.h" +#include "llvm/ADT/STLExtras.h" #include "llvm/Analysis/LegacyDivergenceAnalysis.h" #include "llvm/CodeGen/Analysis.h" #include "llvm/CodeGen/MachineFrameInfo.h" @@ -30,7 +31,7 @@ #include "llvm/IR/DerivedTypes.h" #include "llvm/IR/Function.h" #include "llvm/IR/Instructions.h" -#include "llvm/IR/IntrinsicInst.h" +#include "llvm/IR/Intrinsics.h" #include "llvm/IR/Module.h" #include "llvm/Support/Debug.h" #include "llvm/Support/ErrorHandling.h" @@ -40,11 +41,26 @@ #define DEBUG_TYPE "function-lowering-info" +static bool isUsedOutsideOfDefiningBlock(const CallBrInst *CBR) { + return llvm::any_of(CBR->getIndirectDests(), [](BasicBlock *Dest) { + if (const auto *CI = dyn_cast(Dest->begin())) { + if (Function *F = CI->getCalledFunction()) { + return F->getIntrinsicID() == Intrinsic::callbr_landingpad; + } + } + return false; + }); +} + /// isUsedOutsideOfDefiningBlock - Return true if this instruction is used by /// PHI nodes or outside of the basic block that defines it, or used by a /// switch or atomic instruction, which may expand to multiple basic blocks. static bool isUsedOutsideOfDefiningBlock(const Instruction *I) { - if (I->use_empty()) return false; + if (I->use_empty()) { + if (const auto *CBR = dyn_cast(I)) + return isUsedOutsideOfDefiningBlock(CBR); + return false; + } if (isa(I)) return true; const BasicBlock *BB = I->getParent(); for (const User *U : I->users()) diff --git a/llvm/lib/CodeGen/SelectionDAG/SelectionDAGBuilder.h b/llvm/lib/CodeGen/SelectionDAG/SelectionDAGBuilder.h --- a/llvm/lib/CodeGen/SelectionDAG/SelectionDAGBuilder.h +++ b/llvm/lib/CodeGen/SelectionDAG/SelectionDAGBuilder.h @@ -534,6 +534,7 @@ // These all get lowered before this pass. void visitInvoke(const InvokeInst &I); void visitCallBr(const CallBrInst &I); + void visitCallBrLandingPad(const CallInst &I); void visitResume(const ResumeInst &I); void visitUnary(const User &I, unsigned Opcode); diff --git a/llvm/lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp b/llvm/lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp --- a/llvm/lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp +++ b/llvm/lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp @@ -2124,7 +2124,8 @@ DenseMap::iterator VMI = FuncInfo.ValueMap.find(V); if (VMI != FuncInfo.ValueMap.end()) { - assert(!V->use_empty() && "Unused value assigned virtual registers!"); + assert((!V->use_empty() || isa(V)) && + "Unused value assigned virtual registers!"); CopyValueToVirtualRegister(V, VMI->second); } } @@ -7319,6 +7320,9 @@ case Intrinsic::experimental_vector_splice: visitVectorSplice(I); return; + case Intrinsic::callbr_landingpad: + visitCallBrLandingPad(I); + return; } } @@ -11594,3 +11598,91 @@ Mask.push_back(Idx + i); setValue(&I, DAG.getVectorShuffle(VT, DL, V1, V2, Mask)); } + +// Consider the following MIR after SelectionDAG, which produces output in +// phyregs in the first case or virtregs in the second case. +// +// INLINEASM_BR ..., implicit-def $ebx, ..., implicit-def $edx +// %5:gr32 = COPY $ebx +// %6:gr32 = COPY $edx +// %1:gr32 = COPY %6:gr32 +// %0:gr32 = COPY %5:gr32 +// +// INLINEASM_BR ..., def %5:gr32, ..., def %6:gr32 +// %1:gr32 = COPY %6:gr32 +// %0:gr32 = COPY %5:gr32 +// +// Given %0, we'd like to return $ebx in the first case and %5 in the second. +// Given %1, we'd like to return $edx in the first case and %6 in the second. +// +// If a callbr has outputs, it will have a single mapping in FuncInfo.ValueMap +// to a single virtreg (such as %0). The remaining ouputs monotonically +// increase in virtreg number from there. If a callbr has no outputs, then it +// should not have a corresponding callbr landingpad; in fact, the callbr +// landingpad would not even be able to refer to such a callbr. +static Register FollowCopyChain(MachineRegisterInfo &MRI, Register Reg) { + MachineInstr *MI = MRI.def_begin(Reg)->getParent(); + // There is definitely at least one copy. + assert(MI->getOpcode() == TargetOpcode::COPY && + "start of copy chain MUST be COPY"); + Reg = MI->getOperand(1).getReg(); + MI = MRI.def_begin(Reg)->getParent(); + // There may be an optional second copy. + if (MI->getOpcode() == TargetOpcode::COPY) { + assert(Reg.isVirtual() && "expected COPY of virtual register"); + Reg = MI->getOperand(1).getReg(); + assert(Reg.isPhysical() && "expected COPY of physical register"); + MI = MRI.def_begin(Reg)->getParent(); + } + // The start of the chain must be an INLINEASM_BR. + assert(MI->getOpcode() == TargetOpcode::INLINEASM_BR && + "end of copy chain MUST be INLINEASM_BR"); + return Reg; +} + +static size_t PopulateResultValues(const CallBrInst &CBR, SelectionDAG &DAG, + SmallVectorImpl &ResultVTs, + SmallVectorImpl &ResultValues) { + Type *CBRType = CBR.getType(); + assert(!CBRType->isVoidTy() && + "callbr landing pad for callbr without returns"); + ArrayRef ResultTypes = CBRType->isStructTy() + ? cast(CBRType)->elements() + : ArrayRef(CBRType); + size_t NumReturnValues = ResultTypes.size(); + ResultVTs.reserve(NumReturnValues); + ResultValues.reserve(NumReturnValues); + const TargetLowering &TLI = DAG.getTargetLoweringInfo(); + for (Type *T : ResultTypes) + ResultVTs.emplace_back(TLI.getValueType(DAG.getDataLayout(), T)); + return NumReturnValues; +} + +// We must do this walk rather than the simpler +// setValue(&I, getCopyFromRegs(CBR, CBR->getType())); +// otherwise we will end up with copies of virtregs only valid along direct +// edges. +void SelectionDAGBuilder::visitCallBrLandingPad(const CallInst &I) { + SmallVector ResultVTs; + SmallVector ResultValues; + const auto *CBR = + cast(I.getParent()->getUniquePredecessor()->getTerminator()); + const size_t NumReturnValues = + PopulateResultValues(*CBR, DAG, ResultVTs, ResultValues); + MachineRegisterInfo &MRI = DAG.getMachineFunction().getRegInfo(); + unsigned Reg = FuncInfo.ValueMap[CBR]; + SDValue Chain = DAG.getRoot(); + + for (size_t i = 0; i != NumReturnValues; ++i, ++Reg) { + Register Output = FollowCopyChain(MRI, Reg); + + if (Register::isPhysicalRegister(Output)) + FuncInfo.MBB->addLiveIn(Output); + + SDValue V = DAG.getCopyFromReg(Chain, getCurSDLoc(), Output, ResultVTs[i]); + ResultValues.push_back(V); + } + SDValue V = DAG.getNode(ISD::MERGE_VALUES, getCurSDLoc(), + DAG.getVTList(ResultVTs), ResultValues); + setValue(&I, V); +} diff --git a/llvm/test/CodeGen/AArch64/callbr-asm-outputs-indirect-isel.ll b/llvm/test/CodeGen/AArch64/callbr-asm-outputs-indirect-isel.ll new file mode 100644 --- /dev/null +++ b/llvm/test/CodeGen/AArch64/callbr-asm-outputs-indirect-isel.ll @@ -0,0 +1,559 @@ +; NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py + +; RUN: llc -mtriple=aarch64-linux-gnu %s -o - \ +; RUN: -start-before=aarch64-isel -stop-after=finalize-isel \ +; RUN: -global-isel=0 -fast-isel=0 | FileCheck %s + +; This file was initially generated via: +; $ opt -S -callbrprepare llvm/test/CodeGen/AArch64/callbr-prepare.ll -o \ +; llvm/test/CodeGen/AArch64/callbr-asm-outputs-indirect-isel.ll + +; TODO: should we remove test cases that don't use landingpad intrinsic? +; They're not interesting IMO. + +; Removed is the test case for x86 machine specific physreg constraints. + +define i32 @test0() { + ; CHECK-LABEL: name: test0 + ; CHECK: bb.0.entry: + ; CHECK-NEXT: successors: %bb.2(0x80000000), %bb.1(0x00000000) + ; CHECK-NEXT: {{ $}} + ; CHECK-NEXT: INLINEASM_BR &"# $0", 0 /* attdialect */, 1507338 /* regdef:GPR32common */, def %5, 13 /* imm */, %bb.1 + ; CHECK-NEXT: [[COPY:%[0-9]+]]:gpr32all = COPY %5 + ; CHECK-NEXT: B %bb.2 + ; CHECK-NEXT: {{ $}} + ; CHECK-NEXT: bb.1.entry.indirect_crit_edge (machine-block-address-taken, inlineasm-br-indirect-target): + ; CHECK-NEXT: successors: %bb.5(0x80000000) + ; CHECK-NEXT: {{ $}} + ; CHECK-NEXT: [[COPY1:%[0-9]+]]:gpr32all = COPY %5 + ; CHECK-NEXT: B %bb.5 + ; CHECK-NEXT: {{ $}} + ; CHECK-NEXT: bb.2.direct: + ; CHECK-NEXT: successors: %bb.4(0x80000000), %bb.3(0x00000000) + ; CHECK-NEXT: {{ $}} + ; CHECK-NEXT: INLINEASM_BR &"# $0", 0 /* attdialect */, 1507338 /* regdef:GPR32common */, def %6, 13 /* imm */, %bb.3 + ; CHECK-NEXT: [[COPY2:%[0-9]+]]:gpr32all = COPY %6 + ; CHECK-NEXT: B %bb.4 + ; CHECK-NEXT: {{ $}} + ; CHECK-NEXT: bb.3.direct.indirect_crit_edge (machine-block-address-taken, inlineasm-br-indirect-target): + ; CHECK-NEXT: successors: %bb.5(0x80000000) + ; CHECK-NEXT: {{ $}} + ; CHECK-NEXT: [[COPY3:%[0-9]+]]:gpr32all = COPY %6 + ; CHECK-NEXT: B %bb.5 + ; CHECK-NEXT: {{ $}} + ; CHECK-NEXT: bb.4.direct2: + ; CHECK-NEXT: [[COPY4:%[0-9]+]]:gpr32all = COPY $wzr + ; CHECK-NEXT: $w0 = COPY [[COPY4]] + ; CHECK-NEXT: RET_ReallyLR implicit $w0 + ; CHECK-NEXT: {{ $}} + ; CHECK-NEXT: bb.5.indirect: + ; CHECK-NEXT: [[PHI:%[0-9]+]]:gpr32all = PHI [[COPY1]], %bb.1, [[COPY3]], %bb.3 + ; CHECK-NEXT: $w0 = COPY [[PHI]] + ; CHECK-NEXT: RET_ReallyLR implicit $w0 +entry: + %out = callbr i32 asm "# $0", "=r,!i"() + to label %direct [label %entry.indirect_crit_edge] + +entry.indirect_crit_edge: ; preds = %entry + %0 = call i32 @llvm.callbr.landingpad.i32() + br label %indirect + +direct: ; preds = %entry + %out2 = callbr i32 asm "# $0", "=r,!i"() + to label %direct2 [label %direct.indirect_crit_edge] + +direct.indirect_crit_edge: ; preds = %direct + %1 = call i32 @llvm.callbr.landingpad.i32() + br label %indirect + +direct2: ; preds = %direct + ret i32 0 + +indirect: ; preds = %direct.indirect_crit_edge, %entry.indirect_crit_edge + %out3 = phi i32 [ %0, %entry.indirect_crit_edge ], [ %1, %direct.indirect_crit_edge ] + ret i32 %out3 +} + +define i32 @dont_split0() { + ; CHECK-LABEL: name: dont_split0 + ; CHECK: bb.0.entry: + ; CHECK-NEXT: successors: %bb.1(0x80000000), %bb.2(0x00000000) + ; CHECK-NEXT: {{ $}} + ; CHECK-NEXT: INLINEASM_BR &"", 0 /* attdialect */, 13 /* imm */, %bb.2 + ; CHECK-NEXT: B %bb.1 + ; CHECK-NEXT: {{ $}} + ; CHECK-NEXT: bb.1.x: + ; CHECK-NEXT: [[MOVi32imm:%[0-9]+]]:gpr32 = MOVi32imm 42 + ; CHECK-NEXT: $w0 = COPY [[MOVi32imm]] + ; CHECK-NEXT: RET_ReallyLR implicit $w0 + ; CHECK-NEXT: {{ $}} + ; CHECK-NEXT: bb.2.y (machine-block-address-taken, inlineasm-br-indirect-target): + ; CHECK-NEXT: [[COPY:%[0-9]+]]:gpr32all = COPY $wzr + ; CHECK-NEXT: $w0 = COPY [[COPY]] + ; CHECK-NEXT: RET_ReallyLR implicit $w0 +entry: + callbr void asm "", "!i"() + to label %x [label %y] + +x: ; preds = %entry + ret i32 42 + +y: ; preds = %entry + ret i32 0 +} + +define i32 @dont_split1() { + ; CHECK-LABEL: name: dont_split1 + ; CHECK: bb.0.entry: + ; CHECK-NEXT: successors: %bb.1(0x80000000), %bb.2(0x00000000) + ; CHECK-NEXT: {{ $}} + ; CHECK-NEXT: INLINEASM_BR &"", 0 /* attdialect */, 1507338 /* regdef:GPR32common */, def %1, 13 /* imm */, %bb.2 + ; CHECK-NEXT: [[COPY:%[0-9]+]]:gpr32all = COPY %1 + ; CHECK-NEXT: B %bb.1 + ; CHECK-NEXT: {{ $}} + ; CHECK-NEXT: bb.1.x: + ; CHECK-NEXT: [[MOVi32imm:%[0-9]+]]:gpr32 = MOVi32imm 42 + ; CHECK-NEXT: $w0 = COPY [[MOVi32imm]] + ; CHECK-NEXT: RET_ReallyLR implicit $w0 + ; CHECK-NEXT: {{ $}} + ; CHECK-NEXT: bb.2.y (machine-block-address-taken, inlineasm-br-indirect-target): + ; CHECK-NEXT: $w0 = COPY %1 + ; CHECK-NEXT: RET_ReallyLR implicit $w0 +entry: + %0 = callbr i32 asm "", "=r,!i"() + to label %x [label %y] + +x: ; preds = %entry + ret i32 42 + +y: ; preds = %entry + %1 = call i32 @llvm.callbr.landingpad.i32() + ret i32 %1 +} + +define i32 @dont_split2() { + ; CHECK-LABEL: name: dont_split2 + ; CHECK: bb.0.entry: + ; CHECK-NEXT: successors: %bb.1(0x80000000), %bb.2(0x00000000) + ; CHECK-NEXT: {{ $}} + ; CHECK-NEXT: [[MOVi32imm:%[0-9]+]]:gpr32 = MOVi32imm 42 + ; CHECK-NEXT: [[COPY:%[0-9]+]]:gpr32all = COPY [[MOVi32imm]] + ; CHECK-NEXT: INLINEASM_BR &"", 0 /* attdialect */, 13 /* imm */, %bb.2 + ; CHECK-NEXT: B %bb.1 + ; CHECK-NEXT: {{ $}} + ; CHECK-NEXT: bb.1.x: + ; CHECK-NEXT: successors: %bb.2(0x80000000) + ; CHECK-NEXT: {{ $}} + ; CHECK-NEXT: [[COPY1:%[0-9]+]]:gpr32all = COPY $wzr + ; CHECK-NEXT: [[COPY2:%[0-9]+]]:gpr32all = COPY [[COPY1]] + ; CHECK-NEXT: {{ $}} + ; CHECK-NEXT: bb.2.y (machine-block-address-taken, inlineasm-br-indirect-target): + ; CHECK-NEXT: [[PHI:%[0-9]+]]:gpr32all = PHI [[COPY]], %bb.0, [[COPY2]], %bb.1 + ; CHECK-NEXT: $w0 = COPY [[PHI]] + ; CHECK-NEXT: RET_ReallyLR implicit $w0 +entry: + callbr void asm "", "!i"() + to label %x [label %y] + +x: ; preds = %entry + br label %y + +y: ; preds = %x, %entry + %0 = phi i32 [ 0, %x ], [ 42, %entry ] + ret i32 %0 +} + +define i32 @dont_split3() { + ; CHECK-LABEL: name: dont_split3 + ; CHECK: bb.0.entry: + ; CHECK-NEXT: successors: %bb.1(0x80000000), %bb.2(0x00000000) + ; CHECK-NEXT: {{ $}} + ; CHECK-NEXT: INLINEASM_BR &"", 0 /* attdialect */, 1507338 /* regdef:GPR32common */, def %0, 13 /* imm */, %bb.2 + ; CHECK-NEXT: B %bb.1 + ; CHECK-NEXT: {{ $}} + ; CHECK-NEXT: bb.1.x: + ; CHECK-NEXT: successors: %bb.2(0x80000000) + ; CHECK-NEXT: {{ $}} + ; CHECK-NEXT: {{ $}} + ; CHECK-NEXT: bb.2.v (machine-block-address-taken, inlineasm-br-indirect-target): + ; CHECK-NEXT: [[MOVi32imm:%[0-9]+]]:gpr32 = MOVi32imm 42 + ; CHECK-NEXT: $w0 = COPY [[MOVi32imm]] + ; CHECK-NEXT: RET_ReallyLR implicit $w0 +entry: + %0 = callbr i32 asm "", "=r,!i"() + to label %x [label %v] + +x: ; preds = %entry + br label %v + +v: ; preds = %x, %entry + ret i32 42 +} + +define i32 @split_me0() { + ; CHECK-LABEL: name: split_me0 + ; CHECK: bb.0.entry: + ; CHECK-NEXT: successors: %bb.2(0x80000000), %bb.1(0x00000000) + ; CHECK-NEXT: {{ $}} + ; CHECK-NEXT: INLINEASM_BR &"", 0 /* attdialect */, 1507338 /* regdef:GPR32common */, def %3, 13 /* imm */, %bb.1 + ; CHECK-NEXT: [[COPY:%[0-9]+]]:gpr32all = COPY %3 + ; CHECK-NEXT: B %bb.2 + ; CHECK-NEXT: {{ $}} + ; CHECK-NEXT: bb.1.entry.y_crit_edge (machine-block-address-taken, inlineasm-br-indirect-target): + ; CHECK-NEXT: successors: %bb.3(0x80000000) + ; CHECK-NEXT: {{ $}} + ; CHECK-NEXT: [[COPY1:%[0-9]+]]:gpr32all = COPY %3 + ; CHECK-NEXT: B %bb.3 + ; CHECK-NEXT: {{ $}} + ; CHECK-NEXT: bb.2.x: + ; CHECK-NEXT: successors: %bb.3(0x80000000) + ; CHECK-NEXT: {{ $}} + ; CHECK-NEXT: [[MOVi32imm:%[0-9]+]]:gpr32 = MOVi32imm 42 + ; CHECK-NEXT: [[COPY2:%[0-9]+]]:gpr32all = COPY [[MOVi32imm]] + ; CHECK-NEXT: {{ $}} + ; CHECK-NEXT: bb.3.y: + ; CHECK-NEXT: [[PHI:%[0-9]+]]:gpr32all = PHI [[COPY1]], %bb.1, [[COPY2]], %bb.2 + ; CHECK-NEXT: $w0 = COPY [[PHI]] + ; CHECK-NEXT: RET_ReallyLR implicit $w0 +entry: + %0 = callbr i32 asm "", "=r,!i"() + to label %x [label %entry.y_crit_edge] + +entry.y_crit_edge: ; preds = %entry + %1 = call i32 @llvm.callbr.landingpad.i32() + br label %y + +x: ; preds = %entry + br label %y + +y: ; preds = %entry.y_crit_edge, %x + %2 = phi i32 [ %1, %entry.y_crit_edge ], [ 42, %x ] + ret i32 %2 +} + +define i32 @split_me1(i1 %z) { + ; CHECK-LABEL: name: split_me1 + ; CHECK: bb.0.entry: + ; CHECK-NEXT: successors: %bb.1(0x40000000), %bb.4(0x40000000) + ; CHECK-NEXT: liveins: $w0 + ; CHECK-NEXT: {{ $}} + ; CHECK-NEXT: [[COPY:%[0-9]+]]:gpr32 = COPY $w0 + ; CHECK-NEXT: [[DEF:%[0-9]+]]:gpr32all = IMPLICIT_DEF + ; CHECK-NEXT: TBZW [[COPY]], 0, %bb.4 + ; CHECK-NEXT: B %bb.1 + ; CHECK-NEXT: {{ $}} + ; CHECK-NEXT: bb.1.w: + ; CHECK-NEXT: successors: %bb.3(0x80000000), %bb.2(0x00000000) + ; CHECK-NEXT: {{ $}} + ; CHECK-NEXT: INLINEASM_BR &"", 0 /* attdialect */, 1507338 /* regdef:GPR32common */, def %5, 13 /* imm */, %bb.2, 13 /* imm */, %bb.2 + ; CHECK-NEXT: [[COPY1:%[0-9]+]]:gpr32all = COPY %5 + ; CHECK-NEXT: B %bb.3 + ; CHECK-NEXT: {{ $}} + ; CHECK-NEXT: bb.2.w.v_crit_edge (machine-block-address-taken, inlineasm-br-indirect-target): + ; CHECK-NEXT: successors: %bb.4(0x80000000) + ; CHECK-NEXT: {{ $}} + ; CHECK-NEXT: [[COPY2:%[0-9]+]]:gpr32all = COPY %5 + ; CHECK-NEXT: B %bb.4 + ; CHECK-NEXT: {{ $}} + ; CHECK-NEXT: bb.3.x: + ; CHECK-NEXT: [[MOVi32imm:%[0-9]+]]:gpr32 = MOVi32imm 42 + ; CHECK-NEXT: $w0 = COPY [[MOVi32imm]] + ; CHECK-NEXT: RET_ReallyLR implicit $w0 + ; CHECK-NEXT: {{ $}} + ; CHECK-NEXT: bb.4.v: + ; CHECK-NEXT: [[PHI:%[0-9]+]]:gpr32all = PHI [[DEF]], %bb.0, [[COPY2]], %bb.2 + ; CHECK-NEXT: $w0 = COPY [[PHI]] + ; CHECK-NEXT: RET_ReallyLR implicit $w0 +entry: + br i1 %z, label %w, label %v + +w: ; preds = %entry + %0 = callbr i32 asm "", "=r,!i,!i"() + to label %x [label %w.v_crit_edge, label %w.v_crit_edge] + +w.v_crit_edge: ; preds = %w, %w + %1 = call i32 @llvm.callbr.landingpad.i32() + br label %v + +x: ; preds = %w + ret i32 42 + +v: ; preds = %w.v_crit_edge, %entry + %2 = phi i32 [ %1, %w.v_crit_edge ], [ undef, %entry ] + ret i32 %2 +} + +define i32 @split_me2(i1 %z) { + ; CHECK-LABEL: name: split_me2 + ; CHECK: bb.0.entry: + ; CHECK-NEXT: successors: %bb.1(0x40000000), %bb.4(0x40000000) + ; CHECK-NEXT: liveins: $w0 + ; CHECK-NEXT: {{ $}} + ; CHECK-NEXT: [[COPY:%[0-9]+]]:gpr32 = COPY $w0 + ; CHECK-NEXT: [[MOVi32imm:%[0-9]+]]:gpr32 = MOVi32imm 42 + ; CHECK-NEXT: [[COPY1:%[0-9]+]]:gpr32all = COPY [[MOVi32imm]] + ; CHECK-NEXT: TBZW [[COPY]], 0, %bb.4 + ; CHECK-NEXT: B %bb.1 + ; CHECK-NEXT: {{ $}} + ; CHECK-NEXT: bb.1.w: + ; CHECK-NEXT: successors: %bb.3(0x80000000), %bb.2(0x00000000) + ; CHECK-NEXT: {{ $}} + ; CHECK-NEXT: INLINEASM_BR &"", 0 /* attdialect */, 1507338 /* regdef:GPR32common */, def %6, 13 /* imm */, %bb.2, 13 /* imm */, %bb.2 + ; CHECK-NEXT: [[COPY2:%[0-9]+]]:gpr32all = COPY %6 + ; CHECK-NEXT: B %bb.3 + ; CHECK-NEXT: {{ $}} + ; CHECK-NEXT: bb.2.w.v_crit_edge (machine-block-address-taken, inlineasm-br-indirect-target): + ; CHECK-NEXT: successors: %bb.4(0x80000000) + ; CHECK-NEXT: {{ $}} + ; CHECK-NEXT: [[COPY3:%[0-9]+]]:gpr32all = COPY %6 + ; CHECK-NEXT: B %bb.4 + ; CHECK-NEXT: {{ $}} + ; CHECK-NEXT: bb.3.x: + ; CHECK-NEXT: [[MOVi32imm1:%[0-9]+]]:gpr32 = MOVi32imm 42 + ; CHECK-NEXT: $w0 = COPY [[MOVi32imm1]] + ; CHECK-NEXT: RET_ReallyLR implicit $w0 + ; CHECK-NEXT: {{ $}} + ; CHECK-NEXT: bb.4.v: + ; CHECK-NEXT: [[PHI:%[0-9]+]]:gpr32all = PHI [[COPY1]], %bb.0, [[COPY3]], %bb.2 + ; CHECK-NEXT: $w0 = COPY [[PHI]] + ; CHECK-NEXT: RET_ReallyLR implicit $w0 +entry: + br i1 %z, label %w, label %v + +w: ; preds = %entry + %0 = callbr i32 asm "", "=r,!i,!i"() + to label %x [label %w.v_crit_edge, label %w.v_crit_edge] + +w.v_crit_edge: ; preds = %w, %w + %1 = call i32 @llvm.callbr.landingpad.i32() + br label %v + +x: ; preds = %w + ret i32 42 + +v: ; preds = %w.v_crit_edge, %entry + %2 = phi i32 [ %1, %w.v_crit_edge ], [ 42, %entry ] + ret i32 %2 +} + +define i32 @dont_split4() { + ; CHECK-LABEL: name: dont_split4 + ; CHECK: bb.0.entry: + ; CHECK-NEXT: successors: %bb.1(0x80000000), %bb.2(0x00000000) + ; CHECK-NEXT: {{ $}} + ; CHECK-NEXT: INLINEASM_BR &"", 0 /* attdialect */, 1507338 /* regdef:GPR32common */, def %3, 13 /* imm */, %bb.2 + ; CHECK-NEXT: [[COPY:%[0-9]+]]:gpr32all = COPY %3 + ; CHECK-NEXT: B %bb.1 + ; CHECK-NEXT: {{ $}} + ; CHECK-NEXT: bb.1.x: + ; CHECK-NEXT: successors: %bb.3(0x80000000) + ; CHECK-NEXT: {{ $}} + ; CHECK-NEXT: B %bb.3 + ; CHECK-NEXT: {{ $}} + ; CHECK-NEXT: bb.2.y (machine-block-address-taken, inlineasm-br-indirect-target): + ; CHECK-NEXT: successors: %bb.3(0x80000000) + ; CHECK-NEXT: {{ $}} + ; CHECK-NEXT: [[COPY1:%[0-9]+]]:gpr32all = COPY %3 + ; CHECK-NEXT: {{ $}} + ; CHECK-NEXT: bb.3.out: + ; CHECK-NEXT: [[PHI:%[0-9]+]]:gpr32all = PHI [[COPY1]], %bb.2, [[COPY]], %bb.1 + ; CHECK-NEXT: $w0 = COPY [[PHI]] + ; CHECK-NEXT: RET_ReallyLR implicit $w0 +entry: + %0 = callbr i32 asm "", "=r,!i"() + to label %x [label %y] + +x: ; preds = %entry + br label %out + +y: ; preds = %entry + %1 = call i32 @llvm.callbr.landingpad.i32() + br label %out + +out: ; preds = %y, %x + %2 = phi i32 [ %1, %y ], [ %0, %x ] + ret i32 %2 +} + +define i32 @dont_split5() { + ; CHECK-LABEL: name: dont_split5 + ; CHECK: bb.0.entry: + ; CHECK-NEXT: successors: %bb.2(0x80000000), %bb.1(0x00000000) + ; CHECK-NEXT: {{ $}} + ; CHECK-NEXT: INLINEASM_BR &"", 0 /* attdialect */, 1507338 /* regdef:GPR32common */, def %3, 13 /* imm */, %bb.1 + ; CHECK-NEXT: [[COPY:%[0-9]+]]:gpr32all = COPY %3 + ; CHECK-NEXT: B %bb.2 + ; CHECK-NEXT: {{ $}} + ; CHECK-NEXT: bb.1.y (machine-block-address-taken, inlineasm-br-indirect-target): + ; CHECK-NEXT: successors: %bb.2(0x80000000) + ; CHECK-NEXT: {{ $}} + ; CHECK-NEXT: [[COPY1:%[0-9]+]]:gpr32all = COPY %3 + ; CHECK-NEXT: {{ $}} + ; CHECK-NEXT: bb.2.out: + ; CHECK-NEXT: [[PHI:%[0-9]+]]:gpr32all = PHI [[COPY]], %bb.0, [[COPY1]], %bb.1 + ; CHECK-NEXT: $w0 = COPY [[PHI]] + ; CHECK-NEXT: RET_ReallyLR implicit $w0 +entry: + %0 = callbr i32 asm "", "=r,!i"() + to label %out [label %y] + +y: ; preds = %entry + %1 = call i32 @llvm.callbr.landingpad.i32() + br label %out + +out: ; preds = %y, %entry + %2 = phi i32 [ %1, %y ], [ %0, %entry ] + ret i32 %2 +} + +define i32 @split_me3() { + ; CHECK-LABEL: name: split_me3 + ; CHECK: bb.0.entry: + ; CHECK-NEXT: successors: %bb.2(0x80000000), %bb.1(0x00000000) + ; CHECK-NEXT: {{ $}} + ; CHECK-NEXT: INLINEASM_BR &"", 0 /* attdialect */, 1507338 /* regdef:GPR32common */, def %3, 13 /* imm */, %bb.1 + ; CHECK-NEXT: [[COPY:%[0-9]+]]:gpr32all = COPY %3 + ; CHECK-NEXT: B %bb.2 + ; CHECK-NEXT: {{ $}} + ; CHECK-NEXT: bb.1.entry.out_crit_edge (machine-block-address-taken, inlineasm-br-indirect-target): + ; CHECK-NEXT: successors: %bb.3(0x80000000) + ; CHECK-NEXT: {{ $}} + ; CHECK-NEXT: [[COPY1:%[0-9]+]]:gpr32all = COPY %3 + ; CHECK-NEXT: B %bb.3 + ; CHECK-NEXT: {{ $}} + ; CHECK-NEXT: bb.2.y: + ; CHECK-NEXT: successors: %bb.3(0x80000000) + ; CHECK-NEXT: {{ $}} + ; CHECK-NEXT: {{ $}} + ; CHECK-NEXT: bb.3.out: + ; CHECK-NEXT: [[PHI:%[0-9]+]]:gpr32all = PHI [[COPY1]], %bb.1, [[COPY]], %bb.2 + ; CHECK-NEXT: $w0 = COPY [[PHI]] + ; CHECK-NEXT: RET_ReallyLR implicit $w0 +entry: + %0 = callbr i32 asm "", "=r,!i"() + to label %y [label %entry.out_crit_edge] + +entry.out_crit_edge: ; preds = %entry + %1 = call i32 @llvm.callbr.landingpad.i32() + br label %out + +y: ; preds = %entry + br label %out + +out: ; preds = %entry.out_crit_edge, %y + %2 = phi i32 [ %1, %entry.out_crit_edge ], [ %0, %y ] + ret i32 %2 +} + +define i32 @dont_split6(i32 %0) { + ; CHECK-LABEL: name: dont_split6 + ; CHECK: bb.0.entry: + ; CHECK-NEXT: successors: %bb.1(0x80000000) + ; CHECK-NEXT: liveins: $w0 + ; CHECK-NEXT: {{ $}} + ; CHECK-NEXT: [[COPY:%[0-9]+]]:gpr32 = COPY $w0 + ; CHECK-NEXT: {{ $}} + ; CHECK-NEXT: bb.1.loop: + ; CHECK-NEXT: successors: %bb.3(0x80000000), %bb.2(0x00000000) + ; CHECK-NEXT: {{ $}} + ; CHECK-NEXT: [[PHI:%[0-9]+]]:gpr32all = PHI [[COPY]], %bb.0, %2, %bb.2 + ; CHECK-NEXT: [[COPY1:%[0-9]+]]:gpr32common = COPY [[PHI]] + ; CHECK-NEXT: INLINEASM_BR &"", 0 /* attdialect */, 1507338 /* regdef:GPR32common */, def %4, 2147483657 /* reguse tiedto:$0 */, [[COPY1]](tied-def 3), 13 /* imm */, %bb.2 + ; CHECK-NEXT: [[COPY2:%[0-9]+]]:gpr32all = COPY %4 + ; CHECK-NEXT: B %bb.3 + ; CHECK-NEXT: {{ $}} + ; CHECK-NEXT: bb.2.loop.loop_crit_edge (machine-block-address-taken, inlineasm-br-indirect-target): + ; CHECK-NEXT: successors: %bb.1(0x80000000) + ; CHECK-NEXT: {{ $}} + ; CHECK-NEXT: %2:gpr32all = COPY %4 + ; CHECK-NEXT: B %bb.1 + ; CHECK-NEXT: {{ $}} + ; CHECK-NEXT: bb.3.exit: + ; CHECK-NEXT: [[COPY4:%[0-9]+]]:gpr32all = COPY $wzr + ; CHECK-NEXT: $w0 = COPY [[COPY4]] + ; CHECK-NEXT: RET_ReallyLR implicit $w0 +entry: + br label %loop + +loop: ; preds = %loop.loop_crit_edge, %entry + %1 = phi i32 [ %0, %entry ], [ %3, %loop.loop_crit_edge ] + %2 = callbr i32 asm "", "=r,0,!i"(i32 %1) + to label %exit [label %loop.loop_crit_edge] + +loop.loop_crit_edge: ; preds = %loop + %3 = call i32 @llvm.callbr.landingpad.i32() + br label %loop + +exit: ; preds = %loop + ret i32 0 +} + +define i32 @split_me4() { + ; CHECK-LABEL: name: split_me4 + ; CHECK: bb.0.entry: + ; CHECK-NEXT: successors: %bb.2(0x80000000), %bb.1(0x00000000) + ; CHECK-NEXT: {{ $}} + ; CHECK-NEXT: INLINEASM_BR &"", 0 /* attdialect */, 1507338 /* regdef:GPR32common */, def %3, 13 /* imm */, %bb.1 + ; CHECK-NEXT: [[COPY:%[0-9]+]]:gpr32all = COPY %3 + ; CHECK-NEXT: B %bb.2 + ; CHECK-NEXT: {{ $}} + ; CHECK-NEXT: bb.1.entry.same_crit_edge (machine-block-address-taken, inlineasm-br-indirect-target): + ; CHECK-NEXT: successors: %bb.2(0x80000000) + ; CHECK-NEXT: {{ $}} + ; CHECK-NEXT: [[COPY1:%[0-9]+]]:gpr32all = COPY %3 + ; CHECK-NEXT: {{ $}} + ; CHECK-NEXT: bb.2.same: + ; CHECK-NEXT: [[PHI:%[0-9]+]]:gpr32all = PHI [[COPY]], %bb.0, [[COPY1]], %bb.1 + ; CHECK-NEXT: $w0 = COPY [[PHI]] + ; CHECK-NEXT: RET_ReallyLR implicit $w0 +entry: + %0 = callbr i32 asm "", "=r,!i"() + to label %same [label %entry.same_crit_edge] + +entry.same_crit_edge: ; preds = %entry + %1 = call i32 @llvm.callbr.landingpad.i32() + br label %same + +same: ; preds = %entry.same_crit_edge, %entry + %2 = phi i32 [ %1, %entry.same_crit_edge ], [ %0, %entry ] + ret i32 %2 +} + +define i32 @split_me5() { + ; CHECK-LABEL: name: split_me5 + ; CHECK: bb.0.entry: + ; CHECK-NEXT: successors: %bb.2(0x80000000), %bb.1(0x00000000) + ; CHECK-NEXT: {{ $}} + ; CHECK-NEXT: INLINEASM_BR &"", 0 /* attdialect */, 1507338 /* regdef:GPR32common */, def %3, 13 /* imm */, %bb.1 + ; CHECK-NEXT: [[COPY:%[0-9]+]]:gpr32all = COPY %3 + ; CHECK-NEXT: B %bb.2 + ; CHECK-NEXT: {{ $}} + ; CHECK-NEXT: bb.1.entry.same_crit_edge (machine-block-address-taken, inlineasm-br-indirect-target): + ; CHECK-NEXT: successors: %bb.2(0x80000000) + ; CHECK-NEXT: {{ $}} + ; CHECK-NEXT: [[COPY1:%[0-9]+]]:gpr32all = COPY %3 + ; CHECK-NEXT: {{ $}} + ; CHECK-NEXT: bb.2.same: + ; CHECK-NEXT: [[PHI:%[0-9]+]]:gpr32all = PHI [[COPY]], %bb.0, [[COPY1]], %bb.1 + ; CHECK-NEXT: $w0 = COPY [[PHI]] + ; CHECK-NEXT: RET_ReallyLR implicit $w0 +entry: + %0 = callbr i32 asm "", "=r,!i"() + to label %same [label %entry.same_crit_edge] + +entry.same_crit_edge: ; preds = %entry + %1 = call i32 @llvm.callbr.landingpad.i32() + br label %same + +same: ; preds = %entry.same_crit_edge, %entry + %2 = phi i32 [ %1, %entry.same_crit_edge ], [ %0, %entry ] + ret i32 %2 +} + +; Function Attrs: nounwind +declare i32 @llvm.callbr.landingpad.i32() #0 + +; Function Attrs: nounwind +declare i64 @llvm.callbr.landingpad.i64() #0 + +attributes #0 = { nounwind } diff --git a/llvm/test/CodeGen/X86/callbr-asm-outputs-indirect-isel.ll b/llvm/test/CodeGen/X86/callbr-asm-outputs-indirect-isel.ll new file mode 100644 --- /dev/null +++ b/llvm/test/CodeGen/X86/callbr-asm-outputs-indirect-isel.ll @@ -0,0 +1,336 @@ +; NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py +; RUN: llc -mtriple=x86_64-linux-gnu %s -o - -stop-after=finalize-isel \ +; RUN: -start-before=x86-isel | FileCheck %s + +; One virtual register, w/o phi +define i32 @test0() { + ; CHECK-LABEL: name: test0 + ; CHECK: bb.0 (%ir-block.0): + ; CHECK-NEXT: successors: %bb.1(0x80000000), %bb.2(0x00000000) + ; CHECK-NEXT: {{ $}} + ; CHECK-NEXT: INLINEASM_BR &"", 0 /* attdialect */, 2359306 /* regdef:GR32 */, def %1, 13 /* imm */, %bb.2 + ; CHECK-NEXT: [[COPY:%[0-9]+]]:gr32 = COPY %1 + ; CHECK-NEXT: JMP_1 %bb.1 + ; CHECK-NEXT: {{ $}} + ; CHECK-NEXT: bb.1.cleanup: + ; CHECK-NEXT: [[MOV32ri:%[0-9]+]]:gr32 = MOV32ri 42 + ; CHECK-NEXT: $eax = COPY [[MOV32ri]] + ; CHECK-NEXT: RET 0, $eax + ; CHECK-NEXT: {{ $}} + ; CHECK-NEXT: bb.2.z.split (machine-block-address-taken, inlineasm-br-indirect-target): + ; CHECK-NEXT: $eax = COPY %1 + ; CHECK-NEXT: RET 0, $eax + %direct = callbr i32 asm "", "=r,!i"() + to label %cleanup [label %z.split] + +cleanup: + ret i32 42 +z.split: + %indirect = call i32 @llvm.callbr.landingpad.i32() + ret i32 %indirect +} + +; One virtual register, w/ phi +define i32 @test1() { + ; CHECK-LABEL: name: test1 + ; CHECK: bb.0.entry: + ; CHECK-NEXT: successors: %bb.2(0x80000000), %bb.1(0x00000000) + ; CHECK-NEXT: {{ $}} + ; CHECK-NEXT: [[MOV32ri:%[0-9]+]]:gr32 = MOV32ri 42 + ; CHECK-NEXT: INLINEASM_BR &"", 0 /* attdialect */, 2359306 /* regdef:GR32 */, def %4, 13 /* imm */, %bb.1 + ; CHECK-NEXT: [[COPY:%[0-9]+]]:gr32 = COPY %4 + ; CHECK-NEXT: JMP_1 %bb.2 + ; CHECK-NEXT: {{ $}} + ; CHECK-NEXT: bb.1.z.split (machine-block-address-taken, inlineasm-br-indirect-target): + ; CHECK-NEXT: successors: %bb.2(0x80000000) + ; CHECK-NEXT: {{ $}} + ; CHECK-NEXT: [[COPY1:%[0-9]+]]:gr32 = COPY %4 + ; CHECK-NEXT: {{ $}} + ; CHECK-NEXT: bb.2.cleanup: + ; CHECK-NEXT: [[PHI:%[0-9]+]]:gr32 = PHI [[MOV32ri]], %bb.0, [[COPY1]], %bb.1 + ; CHECK-NEXT: $eax = COPY [[PHI]] + ; CHECK-NEXT: RET 0, $eax +entry: + %direct = callbr i32 asm "", "=r,!i"() + to label %cleanup [label %z.split] + +z.split: + %indirect = call i32 @llvm.callbr.landingpad.i32() + br label %cleanup + +cleanup: + %retval.0 = phi i32 [ %indirect, %z.split ], [ 42, %entry ] + ret i32 %retval.0 +} + +; Two virtual registers +define i32 @test2() { + ; CHECK-LABEL: name: test2 + ; CHECK: bb.0.entry: + ; CHECK-NEXT: successors: %bb.2(0x80000000), %bb.1(0x00000000) + ; CHECK-NEXT: {{ $}} + ; CHECK-NEXT: [[MOV32ri:%[0-9]+]]:gr32 = MOV32ri 42 + ; CHECK-NEXT: INLINEASM_BR &"", 0 /* attdialect */, 2359306 /* regdef:GR32 */, def %5, 2359306 /* regdef:GR32 */, def %6, 13 /* imm */, %bb.1 + ; CHECK-NEXT: [[COPY:%[0-9]+]]:gr32 = COPY %6 + ; CHECK-NEXT: [[COPY1:%[0-9]+]]:gr32 = COPY %5 + ; CHECK-NEXT: JMP_1 %bb.2 + ; CHECK-NEXT: {{ $}} + ; CHECK-NEXT: bb.1.z.split (machine-block-address-taken, inlineasm-br-indirect-target): + ; CHECK-NEXT: successors: %bb.2(0x80000000) + ; CHECK-NEXT: {{ $}} + ; CHECK-NEXT: [[COPY2:%[0-9]+]]:gr32 = COPY %5 + ; CHECK-NEXT: {{ $}} + ; CHECK-NEXT: bb.2.cleanup: + ; CHECK-NEXT: [[PHI:%[0-9]+]]:gr32 = PHI [[MOV32ri]], %bb.0, [[COPY2]], %bb.1 + ; CHECK-NEXT: $eax = COPY [[PHI]] + ; CHECK-NEXT: RET 0, $eax +entry: + %direct = callbr { i32, i32 } asm "", "=r,=r,!i"() + to label %cleanup [label %z.split] + +z.split: + %indirect = call { i32, i32 } @llvm.callbr.landingpad.sl_i32i32s() + %asmresult2 = extractvalue { i32, i32 } %indirect, 0 + br label %cleanup + +cleanup: + %retval.0 = phi i32 [ %asmresult2, %z.split ], [ 42, %entry ] + ret i32 %retval.0 +} + +; One physical register +define i32 @test3() { + ; CHECK-LABEL: name: test3 + ; CHECK: bb.0.entry: + ; CHECK-NEXT: successors: %bb.2(0x80000000), %bb.1(0x00000000) + ; CHECK-NEXT: {{ $}} + ; CHECK-NEXT: [[MOV32ri:%[0-9]+]]:gr32 = MOV32ri 42 + ; CHECK-NEXT: INLINEASM_BR &"", 0 /* attdialect */, 10 /* regdef */, implicit-def $ebx, 13 /* imm */, %bb.1 + ; CHECK-NEXT: [[COPY:%[0-9]+]]:gr32 = COPY $ebx + ; CHECK-NEXT: [[COPY1:%[0-9]+]]:gr32 = COPY [[COPY]] + ; CHECK-NEXT: JMP_1 %bb.2 + ; CHECK-NEXT: {{ $}} + ; CHECK-NEXT: bb.1.z.split (machine-block-address-taken, inlineasm-br-indirect-target): + ; CHECK-NEXT: successors: %bb.2(0x80000000) + ; CHECK-NEXT: liveins: $ebx + ; CHECK-NEXT: {{ $}} + ; CHECK-NEXT: [[COPY2:%[0-9]+]]:gr32 = COPY $ebx + ; CHECK-NEXT: [[COPY3:%[0-9]+]]:gr32 = COPY [[COPY2]] + ; CHECK-NEXT: {{ $}} + ; CHECK-NEXT: bb.2.cleanup: + ; CHECK-NEXT: [[PHI:%[0-9]+]]:gr32 = PHI [[MOV32ri]], %bb.0, [[COPY3]], %bb.1 + ; CHECK-NEXT: $eax = COPY [[PHI]] + ; CHECK-NEXT: RET 0, $eax +entry: + %direct = callbr i32 asm "", "={bx},!i"() + to label %cleanup [label %z.split] + +z.split: + %indirect = call i32 @llvm.callbr.landingpad.i32() + br label %cleanup + +cleanup: + %retval.0 = phi i32 [ %indirect, %z.split ], [ 42, %entry ] + ret i32 %retval.0 +} + +; Two physical registers +define i32 @test4() { + ; CHECK-LABEL: name: test4 + ; CHECK: bb.0.entry: + ; CHECK-NEXT: successors: %bb.2(0x80000000), %bb.1(0x00000000) + ; CHECK-NEXT: {{ $}} + ; CHECK-NEXT: [[MOV32ri:%[0-9]+]]:gr32 = MOV32ri 42 + ; CHECK-NEXT: INLINEASM_BR &"", 0 /* attdialect */, 10 /* regdef */, implicit-def $ebx, 10 /* regdef */, implicit-def $edx, 13 /* imm */, %bb.1 + ; CHECK-NEXT: [[COPY:%[0-9]+]]:gr32 = COPY $ebx + ; CHECK-NEXT: [[COPY1:%[0-9]+]]:gr32 = COPY $edx + ; CHECK-NEXT: [[COPY2:%[0-9]+]]:gr32 = COPY [[COPY1]] + ; CHECK-NEXT: [[COPY3:%[0-9]+]]:gr32 = COPY [[COPY]] + ; CHECK-NEXT: JMP_1 %bb.2 + ; CHECK-NEXT: {{ $}} + ; CHECK-NEXT: bb.1.z.split (machine-block-address-taken, inlineasm-br-indirect-target): + ; CHECK-NEXT: successors: %bb.2(0x80000000) + ; CHECK-NEXT: liveins: $ebx, $edx + ; CHECK-NEXT: {{ $}} + ; CHECK-NEXT: [[COPY4:%[0-9]+]]:gr32 = COPY $ebx + ; CHECK-NEXT: [[COPY5:%[0-9]+]]:gr32 = COPY [[COPY4]] + ; CHECK-NEXT: {{ $}} + ; CHECK-NEXT: bb.2.cleanup: + ; CHECK-NEXT: [[PHI:%[0-9]+]]:gr32 = PHI [[MOV32ri]], %bb.0, [[COPY5]], %bb.1 + ; CHECK-NEXT: $eax = COPY [[PHI]] + ; CHECK-NEXT: RET 0, $eax +entry: + %direct = callbr { i32, i32 } asm "", "={bx},={dx},!i"() + to label %cleanup [label %z.split] + +z.split: + %indirect = call { i32, i32 } @llvm.callbr.landingpad.sl_i32i32s() + %asmresult2 = extractvalue { i32, i32 } %indirect, 0 + br label %cleanup + +cleanup: + %retval.0 = phi i32 [ %asmresult2, %z.split ], [ 42, %entry ] + ret i32 %retval.0 +} + +; Test the same destination appearing in the direct/fallthrough branch as the +; indirect branch. Physreg. +define i32 @test5() { + ; CHECK-LABEL: name: test5 + ; CHECK: bb.0.entry: + ; CHECK-NEXT: successors: %bb.1(0x80000000) + ; CHECK-NEXT: {{ $}} + ; CHECK-NEXT: INLINEASM_BR &"# $0", 0 /* attdialect */, 10 /* regdef */, implicit-def $ebx, 13 /* imm */, %bb.1 + ; CHECK-NEXT: [[COPY:%[0-9]+]]:gr32 = COPY $ebx + ; CHECK-NEXT: [[COPY1:%[0-9]+]]:gr32 = COPY [[COPY]] + ; CHECK-NEXT: JMP_1 %bb.1 + ; CHECK-NEXT: {{ $}} + ; CHECK-NEXT: bb.1.cleanup (machine-block-address-taken, inlineasm-br-indirect-target): + ; CHECK-NEXT: liveins: $ebx + ; CHECK-NEXT: {{ $}} + ; CHECK-NEXT: [[COPY2:%[0-9]+]]:gr32 = COPY $ebx + ; CHECK-NEXT: $eax = COPY [[COPY2]] + ; CHECK-NEXT: RET 0, $eax +entry: + %direct = callbr i32 asm "# $0", "={bx},!i"() + to label %cleanup [label %cleanup] + +cleanup: + %indirect = call i32 @llvm.callbr.landingpad.i32() + ret i32 %indirect +} + +; "The Devil's cross" (i.e. two asm goto with conflicting physreg constraints +; going to the same destination) as expressed by clang. +define i64 @test6() { + ; CHECK-LABEL: name: test6 + ; CHECK: bb.0.entry: + ; CHECK-NEXT: successors: %bb.1(0x80000000), %bb.3(0x00000000) + ; CHECK-NEXT: {{ $}} + ; CHECK-NEXT: INLINEASM_BR &"", 0 /* attdialect */, 10 /* regdef */, implicit-def $rdx, 13 /* imm */, %bb.3 + ; CHECK-NEXT: [[COPY:%[0-9]+]]:gr64 = COPY $rdx + ; CHECK-NEXT: [[COPY1:%[0-9]+]]:gr64 = COPY [[COPY]] + ; CHECK-NEXT: JMP_1 %bb.1 + ; CHECK-NEXT: {{ $}} + ; CHECK-NEXT: bb.1.asm.fallthrough: + ; CHECK-NEXT: successors: %bb.2(0x80000000), %bb.4(0x00000000) + ; CHECK-NEXT: {{ $}} + ; CHECK-NEXT: INLINEASM_BR &"", 0 /* attdialect */, 10 /* regdef */, implicit-def $rbx, 13 /* imm */, %bb.4 + ; CHECK-NEXT: [[COPY2:%[0-9]+]]:gr64 = COPY $rbx + ; CHECK-NEXT: [[COPY3:%[0-9]+]]:gr64 = COPY [[COPY2]] + ; CHECK-NEXT: JMP_1 %bb.2 + ; CHECK-NEXT: {{ $}} + ; CHECK-NEXT: bb.2.foo: + ; CHECK-NEXT: [[PHI:%[0-9]+]]:gr64 = PHI %3, %bb.3, [[COPY3]], %bb.1, %4, %bb.4 + ; CHECK-NEXT: $rax = COPY [[PHI]] + ; CHECK-NEXT: RET 0, $rax + ; CHECK-NEXT: {{ $}} + ; CHECK-NEXT: bb.3.foo.split (machine-block-address-taken, inlineasm-br-indirect-target): + ; CHECK-NEXT: successors: %bb.2(0x80000000) + ; CHECK-NEXT: liveins: $rdx + ; CHECK-NEXT: {{ $}} + ; CHECK-NEXT: [[COPY4:%[0-9]+]]:gr64 = COPY $rdx + ; CHECK-NEXT: %3:gr64 = COPY [[COPY4]] + ; CHECK-NEXT: JMP_1 %bb.2 + ; CHECK-NEXT: {{ $}} + ; CHECK-NEXT: bb.4.foo.split2 (machine-block-address-taken, inlineasm-br-indirect-target): + ; CHECK-NEXT: successors: %bb.2(0x80000000) + ; CHECK-NEXT: liveins: $rbx + ; CHECK-NEXT: {{ $}} + ; CHECK-NEXT: [[COPY6:%[0-9]+]]:gr64 = COPY $rbx + ; CHECK-NEXT: %4:gr64 = COPY [[COPY6]] + ; CHECK-NEXT: JMP_1 %bb.2 +entry: + %0 = callbr i64 asm "", "={dx},!i"() + to label %asm.fallthrough [label %foo.split] + +asm.fallthrough: + %1 = callbr i64 asm "", "={bx},!i"() + to label %foo [label %foo.split2] + +foo: + %x.0 = phi i64 [ %3, %foo.split2 ], [ %2, %foo.split ], [ %1, %asm.fallthrough ] + ret i64 %x.0 + +foo.split: + %2 = call i64 @llvm.callbr.landingpad.i64() + br label %foo + +foo.split2: + %3 = call i64 @llvm.callbr.landingpad.i64() + br label %foo +} + + +; Test a callbr looping back on itself. +define i32 @test7() { + ; CHECK-LABEL: name: test7 + ; CHECK: bb.0.entry: + ; CHECK-NEXT: successors: %bb.1(0x80000000) + ; CHECK-NEXT: {{ $}} + ; CHECK-NEXT: [[DEF:%[0-9]+]]:gr32 = IMPLICIT_DEF + ; CHECK-NEXT: {{ $}} + ; CHECK-NEXT: bb.1.retry: + ; CHECK-NEXT: successors: %bb.2(0x80000000), %bb.3(0x00000000) + ; CHECK-NEXT: {{ $}} + ; CHECK-NEXT: [[PHI:%[0-9]+]]:gr32 = PHI [[DEF]], %bb.0, %2, %bb.3 + ; CHECK-NEXT: [[COPY:%[0-9]+]]:gr32 = COPY [[PHI]] + ; CHECK-NEXT: INLINEASM_BR &"", 0 /* attdialect */, 10 /* regdef */, implicit-def $edx, 2147483657 /* reguse tiedto:$0 */, [[COPY]](tied-def 3), 13 /* imm */, %bb.3 + ; CHECK-NEXT: [[COPY1:%[0-9]+]]:gr32 = COPY $edx + ; CHECK-NEXT: [[COPY2:%[0-9]+]]:gr32 = COPY [[COPY1]] + ; CHECK-NEXT: JMP_1 %bb.2 + ; CHECK-NEXT: {{ $}} + ; CHECK-NEXT: bb.2.asm.fallthrough: + ; CHECK-NEXT: $eax = COPY [[COPY2]] + ; CHECK-NEXT: RET 0, $eax + ; CHECK-NEXT: {{ $}} + ; CHECK-NEXT: bb.3.retry.split (machine-block-address-taken, inlineasm-br-indirect-target): + ; CHECK-NEXT: successors: %bb.1(0x80000000) + ; CHECK-NEXT: liveins: $edx + ; CHECK-NEXT: {{ $}} + ; CHECK-NEXT: [[COPY3:%[0-9]+]]:gr32 = COPY $edx + ; CHECK-NEXT: %2:gr32 = COPY [[COPY3]] + ; CHECK-NEXT: JMP_1 %bb.1 +entry: + br label %retry + +retry: + %x.0 = phi i32 [ undef, %entry ], [ %1, %retry.split ] + %0 = callbr i32 asm "", "={dx},0,!i"(i32 %x.0) + to label %asm.fallthrough [label %retry.split] + +asm.fallthrough: + ret i32 %0 + +retry.split: + %1 = call i32 @llvm.callbr.landingpad.i32() + br label %retry +} + +; Test the same destination appearing in the direct/fallthrough branch as the +; indirect branch. Same as test5 but with a virtreg rather than a physreg +; constraint. +define i32 @test8() { + ; CHECK-LABEL: name: test8 + ; CHECK: bb.0.entry: + ; CHECK-NEXT: successors: %bb.1(0x80000000) + ; CHECK-NEXT: {{ $}} + ; CHECK-NEXT: INLINEASM_BR &"# $0", 0 /* attdialect */, 2359306 /* regdef:GR32 */, def %1, 13 /* imm */, %bb.1 + ; CHECK-NEXT: %0:gr32 = COPY %1 + ; CHECK-NEXT: JMP_1 %bb.1 + ; CHECK-NEXT: {{ $}} + ; CHECK-NEXT: bb.1.cleanup (machine-block-address-taken, inlineasm-br-indirect-target): + ; CHECK-NEXT: $eax = COPY %1 + ; CHECK-NEXT: RET 0, $eax +entry: + %direct = callbr i32 asm "# $0", "=r,!i"() + to label %cleanup [label %cleanup] + +cleanup: + %indirect = call i32 @llvm.callbr.landingpad.i32() + ret i32 %indirect +} + +declare i64 @llvm.callbr.landingpad.i64() +declare i32 @llvm.callbr.landingpad.i32() +declare { i32, i32 } @llvm.callbr.landingpad.sl_i32i32s()