diff --git a/llvm/lib/Target/AMDGPU/AsmParser/AMDGPUAsmParser.cpp b/llvm/lib/Target/AMDGPU/AsmParser/AMDGPUAsmParser.cpp --- a/llvm/lib/Target/AMDGPU/AsmParser/AMDGPUAsmParser.cpp +++ b/llvm/lib/Target/AMDGPU/AsmParser/AMDGPUAsmParser.cpp @@ -1253,7 +1253,6 @@ bool ForcedDPP = false; bool ForcedSDWA = false; KernelScopeInfo KernelScope; - unsigned CPolSeen; /// @name Auto-generated Match Functions /// { @@ -1553,6 +1552,7 @@ OperandMatchResultTy parseNamedBit(StringRef Name, OperandVector &Operands, AMDGPUOperand::ImmTy ImmTy = AMDGPUOperand::ImmTyNone); + unsigned parseCPolId(StringRef Id, StringRef Mnemo, bool &Disabling) const; OperandMatchResultTy parseCPol(OperandVector &Operands); OperandMatchResultTy parseStringWithPrefix(StringRef Prefix, StringRef &Value, @@ -1683,6 +1683,7 @@ bool isId(const StringRef Id) const; bool isId(const AsmToken &Token, const StringRef Id) const; bool isToken(const AsmToken::TokenKind Kind) const; + StringRef getId() const; bool trySkipId(const StringRef Id); bool trySkipId(const StringRef Pref, const StringRef Id); bool trySkipId(const StringRef Id, const AsmToken::TokenKind Kind); @@ -5867,7 +5868,6 @@ OperandMode Mode = OperandMode_Default; if (IsMIMG && isGFX10Plus() && Operands.size() == 2) Mode = OperandMode_NSA; - CPolSeen = 0; OperandMatchResultTy Res = parseOperand(Operands, Name, Mode); if (Res != MatchOperand_Success) { @@ -6010,86 +6010,71 @@ return MatchOperand_Success; } +unsigned AMDGPUAsmParser::parseCPolId(StringRef Id, StringRef Mnemo, + bool &Disabling) const { + Disabling = Id.startswith("no"); + + if (isGFX940() && !Mnemo.startswith("s_")) { + return StringSwitch(Id) + .Case("nt", AMDGPU::CPol::NT) + .Case("nont", AMDGPU::CPol::NT) + .Case("sc0", AMDGPU::CPol::SC0) + .Case("nosc0", AMDGPU::CPol::SC0) + .Case("sc1", AMDGPU::CPol::SC1) + .Case("nosc1", AMDGPU::CPol::SC1) + .Default(0); + } + + return StringSwitch(Id) + .Case("dlc", AMDGPU::CPol::DLC) + .Case("nodlc", AMDGPU::CPol::DLC) + .Case("glc", AMDGPU::CPol::GLC) + .Case("noglc", AMDGPU::CPol::GLC) + .Case("scc", AMDGPU::CPol::SCC) + .Case("noscc", AMDGPU::CPol::SCC) + .Case("slc", AMDGPU::CPol::SLC) + .Case("noslc", AMDGPU::CPol::SLC) + .Default(0); +} + OperandMatchResultTy AMDGPUAsmParser::parseCPol(OperandVector &Operands) { - OperandMatchResultTy Res = MatchOperand_NoMatch; - + StringRef Mnemo = ((AMDGPUOperand &)*Operands[0]).getToken(); + unsigned Enabled = 0, Seen = 0; + SMLoc S = getLoc(); for (;;) { - unsigned CPolOn = 0; - unsigned CPolOff = 0; - SMLoc S = getLoc(); - - StringRef Mnemo = ((AMDGPUOperand &)*Operands[0]).getToken(); - if (isGFX940() && !Mnemo.startswith("s_")) { - if (trySkipId("sc0")) - CPolOn = AMDGPU::CPol::SC0; - else if (trySkipId("nosc0")) - CPolOff = AMDGPU::CPol::SC0; - else if (trySkipId("nt")) - CPolOn = AMDGPU::CPol::NT; - else if (trySkipId("nont")) - CPolOff = AMDGPU::CPol::NT; - else if (trySkipId("sc1")) - CPolOn = AMDGPU::CPol::SC1; - else if (trySkipId("nosc1")) - CPolOff = AMDGPU::CPol::SC1; - else - break; - } else if (trySkipId("glc")) - CPolOn = AMDGPU::CPol::GLC; - else if (trySkipId("noglc")) - CPolOff = AMDGPU::CPol::GLC; - else if (trySkipId("slc")) - CPolOn = AMDGPU::CPol::SLC; - else if (trySkipId("noslc")) - CPolOff = AMDGPU::CPol::SLC; - else if (trySkipId("dlc")) - CPolOn = AMDGPU::CPol::DLC; - else if (trySkipId("nodlc")) - CPolOff = AMDGPU::CPol::DLC; - else if (trySkipId("scc")) - CPolOn = AMDGPU::CPol::SCC; - else if (trySkipId("noscc")) - CPolOff = AMDGPU::CPol::SCC; - else + bool Disabling; + unsigned P = parseCPolId(getId(), Mnemo, Disabling); + if (!P) break; - if (!isGFX10Plus() && ((CPolOn | CPolOff) & AMDGPU::CPol::DLC)) { + if (!isGFX10Plus() && P == AMDGPU::CPol::DLC) { Error(S, "dlc modifier is not supported on this GPU"); return MatchOperand_ParseFail; } - if (!isGFX90A() && ((CPolOn | CPolOff) & AMDGPU::CPol::SCC)) { + if (!isGFX90A() && P == AMDGPU::CPol::SCC) { Error(S, "scc modifier is not supported on this GPU"); return MatchOperand_ParseFail; } - if (CPolSeen & (CPolOn | CPolOff)) { + if (Seen & P) { Error(S, "duplicate cache policy modifier"); return MatchOperand_ParseFail; } - CPolSeen |= (CPolOn | CPolOff); - Res = MatchOperand_Success; + if (!Disabling) + Enabled |= P; - AMDGPUOperand *CPolOp = nullptr; - for (unsigned I = 1; I != Operands.size(); ++I) { - AMDGPUOperand &Op = ((AMDGPUOperand &)*Operands[I]); - if (Op.isCPol()) { - CPolOp = &Op; - break; - } - } - - if (CPolOp) { - CPolOp->setImm((CPolOp->getImm() | CPolOn) & ~CPolOff); - } else { - Operands.push_back( - AMDGPUOperand::CreateImm(this, CPolOn, S, AMDGPUOperand::ImmTyCPol)); - } + Seen |= P; } - return Res; + if (!Seen) + return MatchOperand_NoMatch; + + Operands.push_back( + AMDGPUOperand::CreateImm(this, Enabled, S, AMDGPUOperand::ImmTyCPol)); + return MatchOperand_Success; } static void addOptionalImmOperand( @@ -7119,6 +7104,10 @@ return getTokenKind() == Kind; } +StringRef AMDGPUAsmParser::getId() const { + return isToken(AsmToken::Identifier) ? getTokenStr() : StringRef(); +} + bool AMDGPUAsmParser::trySkipId(const StringRef Id) { if (isId(Id)) {