Index: llvm/lib/Target/SPIRV/SPIRVTargetMachine.cpp
===================================================================
--- llvm/lib/Target/SPIRV/SPIRVTargetMachine.cpp
+++ llvm/lib/Target/SPIRV/SPIRVTargetMachine.cpp
@@ -124,7 +124,8 @@
   disablePass(&PatchableFunctionID);
   disablePass(&ShrinkWrapID);
   disablePass(&LiveDebugValuesID);
-
+  disablePass(&MachineLateInstrsCleanupID);
+  
   // Do not work with OpPhi.
   disablePass(&BranchFolderPassID);
   disablePass(&MachineBlockPlacementID);
Index: llvm/test/CodeGen/SPIRV/instructions/atomic.ll
===================================================================
--- llvm/test/CodeGen/SPIRV/instructions/atomic.ll
+++ llvm/test/CodeGen/SPIRV/instructions/atomic.ll
@@ -1,4 +1,4 @@
-; RUN: llc -mtriple=spirv32-unknown-unknown %s -o - | FileCheck %s
+; RUN: llc -O0 -mtriple=spirv32-unknown-unknown %s -o - | FileCheck %s
 
 ; CHECK-DAG: OpName [[ADD:%.*]] "test_add"
 ; CHECK-DAG: OpName [[SUB:%.*]] "test_sub"
Index: llvm/test/CodeGen/SPIRV/instructions/atomic_acqrel.ll
===================================================================
--- llvm/test/CodeGen/SPIRV/instructions/atomic_acqrel.ll
+++ llvm/test/CodeGen/SPIRV/instructions/atomic_acqrel.ll
@@ -1,4 +1,4 @@
-; RUN: llc -mtriple=spirv32-unknown-unknown %s -o - | FileCheck %s
+; RUN: llc -O0 -mtriple=spirv32-unknown-unknown %s -o - | FileCheck %s
 
 ; CHECK-DAG: OpName [[ADD:%.*]] "test_add"
 ; CHECK-DAG: OpName [[SUB:%.*]] "test_sub"
Index: llvm/test/CodeGen/SPIRV/instructions/atomic_seq.ll
===================================================================
--- llvm/test/CodeGen/SPIRV/instructions/atomic_seq.ll
+++ llvm/test/CodeGen/SPIRV/instructions/atomic_seq.ll
@@ -1,4 +1,4 @@
-; RUN: llc -mtriple=spirv32-unknown-unknown %s -o - | FileCheck %s
+; RUN: llc -O0 -mtriple=spirv32-unknown-unknown %s -o - | FileCheck %s
 
 ; CHECK-DAG: OpName [[ADD:%.*]] "test_add"
 ; CHECK-DAG: OpName [[SUB:%.*]] "test_sub"
Index: llvm/test/CodeGen/SPIRV/instructions/fcmp.ll
===================================================================
--- llvm/test/CodeGen/SPIRV/instructions/fcmp.ll
+++ llvm/test/CodeGen/SPIRV/instructions/fcmp.ll
@@ -1,4 +1,4 @@
-; RUN: llc -mtriple=spirv32-unknown-unknown %s -o - | FileCheck %s
+; RUN: llc -O0 -mtriple=spirv32-unknown-unknown %s -o - | FileCheck %s
 
 ; CHECK-DAG: OpName [[UEQ:%.*]] "test_ueq"
 ; CHECK-DAG: OpName [[OEQ:%.*]] "test_oeq"
Index: llvm/test/CodeGen/SPIRV/instructions/float-casts.ll
===================================================================
--- llvm/test/CodeGen/SPIRV/instructions/float-casts.ll
+++ llvm/test/CodeGen/SPIRV/instructions/float-casts.ll
@@ -1,4 +1,4 @@
-; RUN: llc -mtriple=spirv32-unknown-unknown %s -o - | FileCheck %s
+; RUN: llc -O0 -mtriple=spirv32-unknown-unknown %s -o - | FileCheck %s
 
 ; CHECK-DAG: OpName [[TRUNC32_16:%.*]] "f32tof16"
 ; CHECK-DAG: OpName [[EXT16_32:%.*]] "f16tof32"
Index: llvm/test/CodeGen/SPIRV/instructions/icmp.ll
===================================================================
--- llvm/test/CodeGen/SPIRV/instructions/icmp.ll
+++ llvm/test/CodeGen/SPIRV/instructions/icmp.ll
@@ -1,4 +1,4 @@
-; RUN: llc -mtriple=spirv32-unknown-unknown %s -o - | FileCheck %s
+; RUN: llc -O0 -mtriple=spirv32-unknown-unknown %s -o - | FileCheck %s
 
 ; CHECK-DAG: OpName [[EQ:%.*]] "test_eq"
 ; CHECK-DAG: OpName [[NE:%.*]] "test_ne"
Index: llvm/test/CodeGen/SPIRV/instructions/integer-casts.ll
===================================================================
--- llvm/test/CodeGen/SPIRV/instructions/integer-casts.ll
+++ llvm/test/CodeGen/SPIRV/instructions/integer-casts.ll
@@ -1,4 +1,4 @@
-; RUN: llc -mtriple=spirv32-unknown-unknown %s -o - | FileCheck %s
+; RUN: llc -O0 -mtriple=spirv32-unknown-unknown %s -o - | FileCheck %s
 
 ; CHECK-DAG: OpName [[TRUNC32_16:%.*]] "i32toi16"
 ; CHECK-DAG: OpName [[TRUNC32_8:%.*]] "i32toi8"
Index: llvm/test/CodeGen/SPIRV/instructions/intrinsics.ll
===================================================================
--- llvm/test/CodeGen/SPIRV/instructions/intrinsics.ll
+++ llvm/test/CodeGen/SPIRV/instructions/intrinsics.ll
@@ -1,4 +1,4 @@
-; RUN: llc %s -mtriple=spirv32-unknown-unknown -o - | FileCheck %s
+; RUN: llc -O0 %s -mtriple=spirv32-unknown-unknown -o - | FileCheck %s
 
 declare float @llvm.fabs.f32(float)
 declare float @llvm.rint.f32(float)
Index: llvm/test/CodeGen/SPIRV/instructions/ptrcmp.ll
===================================================================
--- llvm/test/CodeGen/SPIRV/instructions/ptrcmp.ll
+++ llvm/test/CodeGen/SPIRV/instructions/ptrcmp.ll
@@ -1,4 +1,4 @@
-; RUN: llc -mtriple=spirv32-unknown-unknown %s -o - | FileCheck %s
+; RUN: llc -O0 -mtriple=spirv32-unknown-unknown %s -o - | FileCheck %s
 
 ; CHECK-DAG: OpName [[EQ:%.*]] "test_eq"
 ; CHECK-DAG: OpName [[NE:%.*]] "test_ne"
Index: llvm/test/CodeGen/SPIRV/instructions/vector-shuffle.ll
===================================================================
--- llvm/test/CodeGen/SPIRV/instructions/vector-shuffle.ll
+++ llvm/test/CodeGen/SPIRV/instructions/vector-shuffle.ll
@@ -1,4 +1,4 @@
-; RUN: llc -mtriple=spirv32-unknown-unknown %s -o - | FileCheck %s
+; RUN: llc -O0 -mtriple=spirv32-unknown-unknown %s -o - | FileCheck %s
 
 ; CHECK-DAG: OpName [[SHFv4:%.+]] "shuffle_v4"
 ; CHECK-DAG: OpName [[INSv4:%.+]] "insert_v4"