Index: lldb/source/Plugins/Instruction/RISCV/EmulateInstructionRISCV.h
===================================================================
--- lldb/source/Plugins/Instruction/RISCV/EmulateInstructionRISCV.h
+++ lldb/source/Plugins/Instruction/RISCV/EmulateInstructionRISCV.h
@@ -18,12 +18,14 @@
 #include "lldb/Utility/Status.h"
 
 namespace lldb_private {
+using namespace llvm;
+using namespace lldb;
 
 class EmulateInstructionRISCV : public EmulateInstruction {
 public:
-  static llvm::StringRef GetPluginNameStatic() { return "riscv"; }
+  static StringRef GetPluginNameStatic() { return "riscv"; }
 
-  static llvm::StringRef GetPluginDescriptionStatic() {
+  static StringRef GetPluginDescriptionStatic() {
     return "Emulate instructions for the RISC-V architecture.";
   }
 
@@ -51,7 +53,7 @@
 public:
   EmulateInstructionRISCV(const ArchSpec &arch) : EmulateInstruction(arch) {}
 
-  llvm::StringRef GetPluginName() override { return GetPluginNameStatic(); }
+  StringRef GetPluginName() override { return GetPluginNameStatic(); }
 
   bool SupportsEmulatingInstructionsOfType(InstructionType inst_type) override {
     return SupportsThisInstructionType(inst_type);
@@ -62,19 +64,18 @@
   bool EvaluateInstruction(uint32_t options) override;
   bool TestEmulation(Stream *out_stream, ArchSpec &arch,
                      OptionValueDictionary *test_data) override;
-  llvm::Optional<RegisterInfo> GetRegisterInfo(lldb::RegisterKind reg_kind,
-                                               uint32_t reg_num) override;
+  Optional<RegisterInfo> GetRegisterInfo(RegisterKind reg_kind,
+                                         uint32_t reg_num) override;
 
-  llvm::Optional<lldb::addr_t> ReadPC();
-  bool WritePC(lldb::addr_t pc);
+  Optional<addr_t> ReadPC();
+  bool WritePC(addr_t pc);
 
-  llvm::Optional<DecodeResult> ReadInstructionAt(lldb::addr_t addr);
-  llvm::Optional<DecodeResult> Decode(uint32_t inst);
+  Optional<DecodeResult> ReadInstructionAt(addr_t addr);
+  Optional<DecodeResult> Decode(uint32_t inst);
   bool Execute(DecodeResult inst, bool ignore_cond);
 
   template <typename T>
-  std::enable_if_t<std::is_integral_v<T>, llvm::Optional<T>>
-  ReadMem(uint64_t addr) {
+  std::enable_if_t<std::is_integral_v<T>, Optional<T>> ReadMem(uint64_t addr) {
     EmulateInstructionRISCV::Context ctx;
     ctx.type = EmulateInstruction::eContextRegisterLoad;
     ctx.SetNoArgs();
@@ -92,8 +93,8 @@
     return WriteMemoryUnsigned(ctx, addr, value, sizeof(T));
   }
 
-  llvm::RoundingMode GetRoundingMode();
-  bool SetAccruedExceptions(llvm::APFloatBase::opStatus);
+  RoundingMode GetRoundingMode();
+  bool SetAccruedExceptions(APFloatBase::opStatus);
 
 private:
   /// Last decoded instruction from m_opcode
Index: lldb/source/Plugins/Instruction/RISCV/EmulateInstructionRISCV.cpp
===================================================================
--- lldb/source/Plugins/Instruction/RISCV/EmulateInstructionRISCV.cpp
+++ lldb/source/Plugins/Instruction/RISCV/EmulateInstructionRISCV.cpp
@@ -24,6 +24,7 @@
 #include "llvm/ADT/STLExtras.h"
 #include "llvm/Support/MathExtras.h"
 
+using namespace llvm;
 using namespace lldb;
 using namespace lldb_private;
 
@@ -34,10 +35,9 @@
 /// Returns all values wrapped in Optional, or std::nullopt if any of the values
 /// is std::nullopt.
 template <typename... Ts>
-static llvm::Optional<std::tuple<Ts...>> zipOpt(llvm::Optional<Ts> &&...ts) {
+static Optional<std::tuple<Ts...>> zipOpt(Optional<Ts> &&...ts) {
   if ((ts.has_value() && ...))
-    return llvm::Optional<std::tuple<Ts...>>(
-        std::make_tuple(std::move(*ts)...));
+    return Optional<std::tuple<Ts...>>(std::make_tuple(std::move(*ts)...));
   else
     return std::nullopt;
 }
@@ -118,7 +118,7 @@
                                 registerValue);
 }
 
-bool Rd::WriteAPFloat(EmulateInstructionRISCV &emulator, llvm::APFloat value) {
+bool Rd::WriteAPFloat(EmulateInstructionRISCV &emulator, APFloat value) {
   uint32_t lldb_reg = FPREncodingToLLDB(rd);
   EmulateInstruction::Context ctx;
   ctx.type = EmulateInstruction::eContextRegisterStore;
@@ -129,39 +129,39 @@
                                 registerValue);
 }
 
-llvm::Optional<uint64_t> Rs::Read(EmulateInstructionRISCV &emulator) {
+Optional<uint64_t> Rs::Read(EmulateInstructionRISCV &emulator) {
   uint32_t lldbReg = GPREncodingToLLDB(rs);
   RegisterValue value;
   return emulator.ReadRegister(eRegisterKindLLDB, lldbReg, value)
-             ? llvm::Optional<uint64_t>(value.GetAsUInt64())
+             ? Optional<uint64_t>(value.GetAsUInt64())
              : std::nullopt;
 }
 
-llvm::Optional<int32_t> Rs::ReadI32(EmulateInstructionRISCV &emulator) {
+Optional<int32_t> Rs::ReadI32(EmulateInstructionRISCV &emulator) {
   return Read(emulator).transform(
       [](uint64_t value) { return int32_t(uint32_t(value)); });
 }
 
-llvm::Optional<int64_t> Rs::ReadI64(EmulateInstructionRISCV &emulator) {
+Optional<int64_t> Rs::ReadI64(EmulateInstructionRISCV &emulator) {
   return Read(emulator).transform(
       [](uint64_t value) { return int64_t(value); });
 }
 
-llvm::Optional<uint32_t> Rs::ReadU32(EmulateInstructionRISCV &emulator) {
+Optional<uint32_t> Rs::ReadU32(EmulateInstructionRISCV &emulator) {
   return Read(emulator).transform(
       [](uint64_t value) { return uint32_t(value); });
 }
 
-llvm::Optional<llvm::APFloat> Rs::ReadAPFloat(EmulateInstructionRISCV &emulator,
-                                              bool isDouble) {
+Optional<APFloat> Rs::ReadAPFloat(EmulateInstructionRISCV &emulator,
+                                  bool isDouble) {
   uint32_t lldbReg = FPREncodingToLLDB(rs);
   RegisterValue value;
   if (!emulator.ReadRegister(eRegisterKindLLDB, lldbReg, value))
     return std::nullopt;
   uint64_t bits = value.GetAsUInt64();
-  llvm::APInt api(64, bits, false);
-  return llvm::APFloat(isDouble ? llvm::APFloat(api.bitsToDouble())
-                                : llvm::APFloat(api.bitsToFloat()));
+  APInt api(64, bits, false);
+  return APFloat(isDouble ? APFloat(api.bitsToDouble())
+                          : APFloat(api.bitsToFloat()));
 }
 
 static bool CompareB(uint64_t rs1, uint64_t rs2, uint32_t funct3) {
@@ -215,7 +215,7 @@
     std::is_same_v<T, AMOMAXU_W> || std::is_same_v<T, AMOMAXU_D>;
 
 template <typename I>
-static std::enable_if_t<is_load<I> || is_store<I>, llvm::Optional<uint64_t>>
+static std::enable_if_t<is_load<I> || is_store<I>, Optional<uint64_t>>
 LoadStoreAddr(EmulateInstructionRISCV &emulator, I inst) {
   return inst.rs1.Read(emulator).transform(
       [&](uint64_t rs1) { return rs1 + uint64_t(SignExt(inst.imm)); });
@@ -247,11 +247,11 @@
 template <typename I>
 static std::enable_if_t<is_amo_add<I> || is_amo_bit_op<I> || is_amo_swap<I> ||
                             is_amo_cmp<I>,
-                        llvm::Optional<uint64_t>>
+                        Optional<uint64_t>>
 AtomicAddr(EmulateInstructionRISCV &emulator, I inst, unsigned int align) {
   return inst.rs1.Read(emulator)
       .transform([&](uint64_t rs1) {
-        return rs1 % align == 0 ? llvm::Optional<uint64_t>(rs1) : std::nullopt;
+        return rs1 % align == 0 ? Optional<uint64_t>(rs1) : std::nullopt;
       })
       .value_or(std::nullopt);
 }
@@ -567,7 +567,7 @@
     {"FCVT_S_LU", 0xFFF0007F, 0xD0300053, DecodeIType<FCVT_S_LU>},
 };
 
-llvm::Optional<DecodeResult> EmulateInstructionRISCV::Decode(uint32_t inst) {
+Optional<DecodeResult> EmulateInstructionRISCV::Decode(uint32_t inst) {
   Log *log = GetLog(LLDBLog::Unwind);
 
   uint16_t try_rvc = uint16_t(inst & 0x0000ffff);
@@ -897,7 +897,7 @@
         .transform([&](auto &&tup) {
           auto [rs1, rs2] = tup;
           // signed * signed
-          auto mul = llvm::APInt(128, rs1, true) * llvm::APInt(128, rs2, true);
+          auto mul = APInt(128, rs1, true) * APInt(128, rs2, true);
           return inst.rd.Write(m_emu, mul.ashr(64).trunc(64).getZExtValue());
         })
         .value_or(false);
@@ -907,8 +907,7 @@
         .transform([&](auto &&tup) {
           auto [rs1, rs2] = tup;
           // signed * unsigned
-          auto mul = llvm::APInt(128, rs1, true).zext(128) *
-                     llvm::APInt(128, rs2, false);
+          auto mul = APInt(128, rs1, true).zext(128) * APInt(128, rs2, false);
           return inst.rd.Write(m_emu, mul.lshr(64).trunc(64).getZExtValue());
         })
         .value_or(false);
@@ -918,8 +917,7 @@
         .transform([&](auto &&tup) {
           auto [rs1, rs2] = tup;
           // unsigned * unsigned
-          auto mul =
-              llvm::APInt(128, rs1, false) * llvm::APInt(128, rs2, false);
+          auto mul = APInt(128, rs1, false) * APInt(128, rs2, false);
           return inst.rd.Write(m_emu, mul.lshr(64).trunc(64).getZExtValue());
         })
         .value_or(false);
@@ -1134,7 +1132,7 @@
         .transform([&](auto &&rs1) {
           uint64_t addr = rs1 + uint64_t(inst.imm);
           uint64_t bits = m_emu.ReadMem<uint64_t>(addr).value();
-          llvm::APFloat f(llvm::APFloat::IEEEsingle(), llvm::APInt(32, bits));
+          APFloat f(APFloat::IEEEsingle(), APInt(32, bits));
           return inst.rd.WriteAPFloat(m_emu, f);
         })
         .value_or(false);
@@ -1294,9 +1292,9 @@
           // Signaling NaN inputs set the invalid operation exception flag, even
           // when the result is not NaN.
           if (rs1.isNaN() || rs2.isNaN())
-            m_emu.SetAccruedExceptions(llvm::APFloat::opInvalidOp);
+            m_emu.SetAccruedExceptions(APFloat::opInvalidOp);
           if (rs1.isNaN() && rs2.isNaN()) {
-            auto canonicalNaN = llvm::APFloat::getQNaN(rs1.getSemantics());
+            auto canonicalNaN = APFloat::getQNaN(rs1.getSemantics());
             return inst.rd.WriteAPFloat(m_emu, canonicalNaN);
           }
           return inst.rd.WriteAPFloat(m_emu, minnum(rs1, rs2));
@@ -1309,9 +1307,9 @@
         .transform([&](auto &&tup) {
           auto [rs1, rs2] = tup;
           if (rs1.isNaN() || rs2.isNaN())
-            m_emu.SetAccruedExceptions(llvm::APFloat::opInvalidOp);
+            m_emu.SetAccruedExceptions(APFloat::opInvalidOp);
           if (rs1.isNaN() && rs2.isNaN()) {
-            auto canonicalNaN = llvm::APFloat::getQNaN(rs1.getSemantics());
+            auto canonicalNaN = APFloat::getQNaN(rs1.getSemantics());
             return inst.rd.WriteAPFloat(m_emu, canonicalNaN);
           }
           return inst.rd.WriteAPFloat(m_emu, maxnum(rs1, rs2));
@@ -1351,11 +1349,10 @@
           auto [rs1, rs2] = tup;
           if (rs1.isNaN() || rs2.isNaN()) {
             if (rs1.isSignaling() || rs2.isSignaling())
-              m_emu.SetAccruedExceptions(llvm::APFloat::opInvalidOp);
+              m_emu.SetAccruedExceptions(APFloat::opInvalidOp);
             return inst.rd.Write(m_emu, 0);
           }
-          return inst.rd.Write(m_emu,
-                               rs1.compare(rs2) == llvm::APFloat::cmpEqual);
+          return inst.rd.Write(m_emu, rs1.compare(rs2) == APFloat::cmpEqual);
         })
         .value_or(false);
   }
@@ -1365,11 +1362,10 @@
         .transform([&](auto &&tup) {
           auto [rs1, rs2] = tup;
           if (rs1.isNaN() || rs2.isNaN()) {
-            m_emu.SetAccruedExceptions(llvm::APFloat::opInvalidOp);
+            m_emu.SetAccruedExceptions(APFloat::opInvalidOp);
             return inst.rd.Write(m_emu, 0);
           }
-          return inst.rd.Write(m_emu,
-                               rs1.compare(rs2) == llvm::APFloat::cmpLessThan);
+          return inst.rd.Write(m_emu, rs1.compare(rs2) == APFloat::cmpLessThan);
         })
         .value_or(false);
   }
@@ -1379,11 +1375,11 @@
         .transform([&](auto &&tup) {
           auto [rs1, rs2] = tup;
           if (rs1.isNaN() || rs2.isNaN()) {
-            m_emu.SetAccruedExceptions(llvm::APFloat::opInvalidOp);
+            m_emu.SetAccruedExceptions(APFloat::opInvalidOp);
             return inst.rd.Write(m_emu, 0);
           }
-          return inst.rd.Write(m_emu, rs1.compare(rs2) !=
-                                          llvm::APFloat::cmpGreaterThan);
+          return inst.rd.Write(m_emu,
+                               rs1.compare(rs2) != APFloat::cmpGreaterThan);
         })
         .value_or(false);
   }
@@ -1424,7 +1420,7 @@
   bool operator()(FCVT_S_W inst) {
     return inst.rs1.ReadI32(m_emu)
         .transform([&](auto &&rs1) {
-          llvm::APFloat apf(llvm::APFloat::IEEEsingle(), rs1);
+          APFloat apf(APFloat::IEEEsingle(), rs1);
           return inst.rd.WriteAPFloat(m_emu, apf);
         })
         .value_or(false);
@@ -1432,7 +1428,7 @@
   bool operator()(FCVT_S_WU inst) {
     return inst.rs1.ReadU32(m_emu)
         .transform([&](auto &&rs1) {
-          llvm::APFloat apf(llvm::APFloat::IEEEsingle(), rs1);
+          APFloat apf(APFloat::IEEEsingle(), rs1);
           return inst.rd.WriteAPFloat(m_emu, apf);
         })
         .value_or(false);
@@ -1440,8 +1436,8 @@
   bool operator()(FMV_W_X inst) {
     return inst.rs1.Read(m_emu)
         .transform([&](auto &&rs1) {
-          llvm::APInt apInt(32, NanUnBoxing(rs1));
-          llvm::APFloat apf(apInt.bitsToFloat());
+          APInt apInt(32, NanUnBoxing(rs1));
+          APFloat apf(apInt.bitsToFloat());
           return inst.rd.WriteAPFloat(m_emu, apf);
         })
         .value_or(false);
@@ -1465,7 +1461,7 @@
   bool operator()(FCVT_S_L inst) {
     return inst.rs1.ReadI64(m_emu)
         .transform([&](auto &&rs1) {
-          llvm::APFloat apf(llvm::APFloat::IEEEsingle(), rs1);
+          APFloat apf(APFloat::IEEEsingle(), rs1);
           return inst.rd.WriteAPFloat(m_emu, apf);
         })
         .value_or(false);
@@ -1473,7 +1469,7 @@
   bool operator()(FCVT_S_LU inst) {
     return inst.rs1.Read(m_emu)
         .transform([&](auto &&rs1) {
-          llvm::APFloat apf(llvm::APFloat::IEEEsingle(), rs1);
+          APFloat apf(APFloat::IEEEsingle(), rs1);
           return inst.rd.WriteAPFloat(m_emu, apf);
         })
         .value_or(false);
@@ -1513,8 +1509,8 @@
          WritePC(*old_pc + Executor::size(m_decoded.is_rvc));
 }
 
-llvm::Optional<DecodeResult>
-EmulateInstructionRISCV::ReadInstructionAt(lldb::addr_t addr) {
+Optional<DecodeResult>
+EmulateInstructionRISCV::ReadInstructionAt(addr_t addr) {
   return ReadMem<uint32_t>(addr)
       .transform([&](uint32_t inst) { return Decode(inst); })
       .value_or(std::nullopt);
@@ -1536,14 +1532,14 @@
   return true;
 }
 
-llvm::Optional<lldb::addr_t> EmulateInstructionRISCV::ReadPC() {
+Optional<addr_t> EmulateInstructionRISCV::ReadPC() {
   bool success = false;
   auto addr = ReadRegisterUnsigned(eRegisterKindGeneric, LLDB_REGNUM_GENERIC_PC,
                                    LLDB_INVALID_ADDRESS, &success);
-  return success ? llvm::Optional<lldb::addr_t>(addr) : std::nullopt;
+  return success ? Optional<addr_t>(addr) : std::nullopt;
 }
 
-bool EmulateInstructionRISCV::WritePC(lldb::addr_t pc) {
+bool EmulateInstructionRISCV::WritePC(addr_t pc) {
   EmulateInstruction::Context ctx;
   ctx.type = eContextAdvancePC;
   ctx.SetNoArgs();
@@ -1551,54 +1547,54 @@
                                LLDB_REGNUM_GENERIC_PC, pc);
 }
 
-llvm::RoundingMode EmulateInstructionRISCV::GetRoundingMode() {
+RoundingMode EmulateInstructionRISCV::GetRoundingMode() {
   bool success = false;
   auto fcsr = ReadRegisterUnsigned(eRegisterKindLLDB, fpr_fcsr_riscv,
                                    LLDB_INVALID_ADDRESS, &success);
   if (!success)
-    return llvm::RoundingMode::Invalid;
+    return RoundingMode::Invalid;
   auto frm = (fcsr >> 5) & 0x7;
   switch (frm) {
   case 0b000:
-    return llvm::RoundingMode::NearestTiesToEven;
+    return RoundingMode::NearestTiesToEven;
   case 0b001:
-    return llvm::RoundingMode::TowardZero;
+    return RoundingMode::TowardZero;
   case 0b010:
-    return llvm::RoundingMode::TowardNegative;
+    return RoundingMode::TowardNegative;
   case 0b011:
-    return llvm::RoundingMode::TowardPositive;
+    return RoundingMode::TowardPositive;
   case 0b111:
-    return llvm::RoundingMode::Dynamic;
+    return RoundingMode::Dynamic;
   default:
     // Reserved for future use.
-    return llvm::RoundingMode::Invalid;
+    return RoundingMode::Invalid;
   }
 }
 
 bool EmulateInstructionRISCV::SetAccruedExceptions(
-    llvm::APFloatBase::opStatus opStatus) {
+    APFloatBase::opStatus opStatus) {
   bool success = false;
   auto fcsr = ReadRegisterUnsigned(eRegisterKindLLDB, fpr_fcsr_riscv,
                                    LLDB_INVALID_ADDRESS, &success);
   if (!success)
     return false;
   switch (opStatus) {
-  case llvm::APFloatBase::opInvalidOp:
+  case APFloatBase::opInvalidOp:
     fcsr |= 1 << 4;
     break;
-  case llvm::APFloatBase::opDivByZero:
+  case APFloatBase::opDivByZero:
     fcsr |= 1 << 3;
     break;
-  case llvm::APFloatBase::opOverflow:
+  case APFloatBase::opOverflow:
     fcsr |= 1 << 2;
     break;
-  case llvm::APFloatBase::opUnderflow:
+  case APFloatBase::opUnderflow:
     fcsr |= 1 << 1;
     break;
-  case llvm::APFloatBase::opInexact:
+  case APFloatBase::opInexact:
     fcsr |= 1 << 0;
     break;
-  case llvm::APFloatBase::opOK:
+  case APFloatBase::opOK:
     break;
   }
   EmulateInstruction::Context ctx;
@@ -1607,8 +1603,8 @@
   return WriteRegisterUnsigned(ctx, eRegisterKindLLDB, fpr_fcsr_riscv, fcsr);
 }
 
-llvm::Optional<RegisterInfo>
-EmulateInstructionRISCV::GetRegisterInfo(lldb::RegisterKind reg_kind,
+Optional<RegisterInfo>
+EmulateInstructionRISCV::GetRegisterInfo(RegisterKind reg_kind,
                                          uint32_t reg_index) {
   if (reg_kind == eRegisterKindGeneric) {
     switch (reg_index) {
Index: lldb/source/Plugins/Instruction/RISCV/RISCVInstructions.h
===================================================================
--- lldb/source/Plugins/Instruction/RISCV/RISCVInstructions.h
+++ lldb/source/Plugins/Instruction/RISCV/RISCVInstructions.h
@@ -16,23 +16,24 @@
 #include "llvm/ADT/Optional.h"
 
 namespace lldb_private {
+using namespace llvm;
 
 class EmulateInstructionRISCV;
 
 struct Rd {
   uint32_t rd;
   bool Write(EmulateInstructionRISCV &emulator, uint64_t value);
-  bool WriteAPFloat(EmulateInstructionRISCV &emulator, llvm::APFloat value);
+  bool WriteAPFloat(EmulateInstructionRISCV &emulator, APFloat value);
 };
 
 struct Rs {
   uint32_t rs;
-  llvm::Optional<uint64_t> Read(EmulateInstructionRISCV &emulator);
-  llvm::Optional<int32_t> ReadI32(EmulateInstructionRISCV &emulator);
-  llvm::Optional<int64_t> ReadI64(EmulateInstructionRISCV &emulator);
-  llvm::Optional<uint32_t> ReadU32(EmulateInstructionRISCV &emulator);
-  llvm::Optional<llvm::APFloat> ReadAPFloat(EmulateInstructionRISCV &emulator,
-                                            bool isDouble);
+  Optional<uint64_t> Read(EmulateInstructionRISCV &emulator);
+  Optional<int32_t> ReadI32(EmulateInstructionRISCV &emulator);
+  Optional<int64_t> ReadI64(EmulateInstructionRISCV &emulator);
+  Optional<uint32_t> ReadU32(EmulateInstructionRISCV &emulator);
+  Optional<APFloat> ReadAPFloat(EmulateInstructionRISCV &emulator,
+                                bool isDouble);
 };
 
 #define I_TYPE_INST(NAME)                                                      \
Index: lldb/unittests/Instruction/RISCV/TestRISCVEmulator.cpp
===================================================================
--- lldb/unittests/Instruction/RISCV/TestRISCVEmulator.cpp
+++ lldb/unittests/Instruction/RISCV/TestRISCVEmulator.cpp
@@ -19,6 +19,7 @@
 #include "Plugins/Process/Utility/RegisterInfoPOSIX_riscv64.h"
 #include "Plugins/Process/Utility/lldb-riscv-register-enums.h"
 
+using namespace llvm;
 using namespace lldb;
 using namespace lldb_private;
 
@@ -69,7 +70,7 @@
   }
 
   static size_t ReadMemoryCallback(EmulateInstruction *instruction, void *baton,
-                                   const Context &context, lldb::addr_t addr,
+                                   const Context &context, addr_t addr,
                                    void *dst, size_t length) {
     RISCVEmulatorTester *tester = (RISCVEmulatorTester *)instruction;
     assert(addr + length < sizeof(tester->memory));
@@ -79,7 +80,7 @@
 
   static size_t WriteMemoryCallback(EmulateInstruction *instruction,
                                     void *baton, const Context &context,
-                                    lldb::addr_t addr, const void *dst,
+                                    addr_t addr, const void *dst,
                                     size_t length) {
     RISCVEmulatorTester *tester = (RISCVEmulatorTester *)instruction;
     assert(addr + length < sizeof(tester->memory));
@@ -101,7 +102,7 @@
 };
 
 TEST_F(RISCVEmulatorTester, testJAL) {
-  lldb::addr_t old_pc = 0x114514;
+  addr_t old_pc = 0x114514;
   WritePC(old_pc);
   // jal x1, -6*4
   uint32_t inst = 0b11111110100111111111000011101111;
@@ -123,8 +124,8 @@
 }
 
 TEST_F(RISCVEmulatorTester, testJALR) {
-  lldb::addr_t old_pc = 0x114514;
-  lldb::addr_t old_x2 = 0x1024;
+  addr_t old_pc = 0x114514;
+  addr_t old_x2 = 0x1024;
   WritePC(old_pc);
   gpr.gpr[2] = old_x2;
   // jalr x1, x2(-255)
@@ -175,7 +176,7 @@
 static void testBranch(RISCVEmulatorTester *tester, EncoderB encoder,
                        bool branched, uint64_t rs1, uint64_t rs2) {
   // prepare test registers
-  lldb::addr_t old_pc = 0x114514;
+  addr_t old_pc = 0x114514;
   tester->WritePC(old_pc);
   tester->gpr.gpr[1] = rs1;
   tester->gpr.gpr[2] = rs2;
@@ -215,7 +216,7 @@
 static void TestInst(RISCVEmulatorTester *tester, DecodeResult inst,
                      bool has_rs2, RDComputer rd_val) {
 
-  lldb::addr_t old_pc = 0x114514;
+  addr_t old_pc = 0x114514;
   tester->WritePC(old_pc);
   uint32_t rd = DecodeRD(inst.inst);
   uint32_t rs1 = DecodeRS1(inst.inst);
@@ -503,9 +504,9 @@
   uint32_t rs1 = DecodeRS1(inst.inst);
   uint32_t rs2 = DecodeRS2(inst.inst);
 
-  llvm::APFloat ap_rs1_val(rs1_val);
-  llvm::APFloat ap_rs2_val(rs2_val);
-  llvm::APFloat ap_rs3_val(0.5f);
+  APFloat ap_rs1_val(rs1_val);
+  APFloat ap_rs2_val(rs2_val);
+  APFloat ap_rs3_val(0.5f);
 
   if (rs1)
     tester->fpr.fpr[rs1] = ap_rs1_val.bitcastToAPInt().getZExtValue();
@@ -525,8 +526,8 @@
     }
   }
 
-  llvm::APInt apInt(32, tester->fpr.fpr[rd]);
-  llvm::APFloat rd_val(apInt.bitsToFloat());
+  APInt apInt(32, tester->fpr.fpr[rd]);
+  APFloat rd_val(apInt.bitsToFloat());
   ASSERT_EQ(rd_val.convertToFloat(), rd_exp);
 }
 
@@ -577,7 +578,7 @@
 
   for (auto i : FloatToInt) {
     if (inst.pattern.name == i) {
-      llvm::APFloat apf_rs1_val(12.0f);
+      APFloat apf_rs1_val(12.0f);
       tester->fpr.fpr[rs1] = apf_rs1_val.bitcastToAPInt().getZExtValue();
       ASSERT_TRUE(tester->Execute(inst, false));
       ASSERT_EQ(tester->gpr.gpr[rd], uint64_t(12));
@@ -589,8 +590,8 @@
     if (inst.pattern.name == i) {
       tester->gpr.gpr[rs1] = 12;
       ASSERT_TRUE(tester->Execute(inst, false));
-      llvm::APInt apInt(32, tester->fpr.fpr[rd]);
-      llvm::APFloat rd_val(apInt.bitsToFloat());
+      APInt apInt(32, tester->fpr.fpr[rd]);
+      APFloat rd_val(apInt.bitsToFloat());
       ASSERT_EQ(rd_val.convertToFloat(), 12.0f);
       return;
     }
@@ -622,7 +623,7 @@
   uint32_t FLWInst = 0x1A207;  // imm = 0
   uint32_t FSWInst = 0x21A827; // imm = 16
 
-  llvm::APFloat apf(12.0f);
+  APFloat apf(12.0f);
   uint64_t bits = apf.bitcastToAPInt().getZExtValue();
 
   *(uint64_t *)this->memory = bits;
@@ -645,7 +646,7 @@
 TEST_F(RISCVEmulatorTester, TestFMV_X_WInst) {
   auto FMV_X_WInst = 0xE0018253;
 
-  llvm::APFloat apf(12.0f);
+  APFloat apf(12.0f);
   auto bits = NanBoxing(apf.bitcastToAPInt().getZExtValue());
   this->fpr.fpr[DecodeRS1(FMV_X_WInst)] = bits;
   auto decode = this->Decode(FMV_X_WInst);
@@ -659,7 +660,7 @@
 TEST_F(RISCVEmulatorTester, TestFMV_W_XInst) {
   auto FMV_W_XInst = 0xF0018253;
 
-  llvm::APFloat apf(12.0f);
+  APFloat apf(12.0f);
   uint64_t bits = NanUnBoxing(apf.bitcastToAPInt().getZExtValue());
   this->gpr.gpr[DecodeRS1(FMV_W_XInst)] = bits;
   auto decode = this->Decode(FMV_W_XInst);