diff --git a/llvm/lib/Target/RISCV/RISCVRegisterInfo.td b/llvm/lib/Target/RISCV/RISCVRegisterInfo.td
--- a/llvm/lib/Target/RISCV/RISCVRegisterInfo.td
+++ b/llvm/lib/Target/RISCV/RISCVRegisterInfo.td
@@ -490,54 +490,47 @@
   int Size = !mul(Vlmul, 64);
 }
 
-def VR : VReg<[vint8m1_t, vint16m1_t, vint32m1_t, vint64m1_t,
-               vfloat16m1_t, vfloat32m1_t, vfloat64m1_t,
-               vint8mf2_t, vint8mf4_t, vint8mf8_t,
-               vint16mf2_t, vint16mf4_t, vint32mf2_t,
-               vfloat16mf4_t, vfloat16mf2_t, vfloat32mf2_t,
-               vbool64_t, vbool32_t, vbool16_t, vbool8_t, vbool4_t,
-               vbool2_t, vbool1_t],
-           (add (sequence "V%u", 8, 31),
-                (sequence "V%u", 0, 7)), 1>;
+defvar VMaskVTs = [vbool1_t, vbool2_t, vbool4_t, vbool8_t, vbool16_t,
+                   vbool32_t, vbool64_t];
+
+defvar VM1VTs = [vint8m1_t, vint16m1_t, vint32m1_t, vint64m1_t,
+                 vfloat16m1_t, vfloat32m1_t, vfloat64m1_t,
+                 vint8mf2_t, vint8mf4_t, vint8mf8_t,
+                 vint16mf2_t, vint16mf4_t, vint32mf2_t,
+                 vfloat16mf4_t, vfloat16mf2_t, vfloat32mf2_t];
+
+defvar VM2VTs = [vint8m2_t, vint16m2_t, vint32m2_t, vint64m2_t,
+                 vfloat16m2_t, vfloat32m2_t, vfloat64m2_t];
+
+defvar VM4VTs = [vint8m4_t, vint16m4_t, vint32m4_t, vint64m4_t,
+                 vfloat16m4_t, vfloat32m4_t, vfloat64m4_t];
+
+defvar VM8VTs = [vint8m8_t, vint16m8_t, vint32m8_t, vint64m8_t,
+                 vfloat16m8_t, vfloat32m8_t, vfloat64m8_t];
 
-def VRNoV0 : VReg<[vint8m1_t, vint16m1_t, vint32m1_t, vint64m1_t,
-                   vfloat16m1_t, vfloat32m1_t, vfloat64m1_t,
-                   vint8mf2_t, vint8mf4_t, vint8mf8_t,
-                   vint16mf2_t, vint16mf4_t, vint32mf2_t,
-                   vfloat16mf4_t, vfloat16mf2_t, vfloat32mf2_t,
-                   vbool64_t, vbool32_t, vbool16_t, vbool8_t, vbool4_t,
-                   vbool2_t, vbool1_t],
-               (add (sequence "V%u", 8, 31),
-                    (sequence "V%u", 1, 7)), 1>;
-
-def VRM2 : VReg<[vint8m2_t, vint16m2_t, vint32m2_t, vint64m2_t,
-                 vfloat16m2_t, vfloat32m2_t, vfloat64m2_t],
-             (add (sequence "V%uM2", 8, 31, 2),
-                  (sequence "V%uM2", 0, 7, 2)), 2>;
-
-def VRM2NoV0 : VReg<[vint8m2_t, vint16m2_t, vint32m2_t, vint64m2_t,
-                     vfloat16m2_t, vfloat32m2_t, vfloat64m2_t],
-             (add (sequence "V%uM2", 8, 31, 2),
-                  (sequence "V%uM2", 2, 7, 2)), 2>;
-
-def VRM4 : VReg<[vint8m4_t, vint16m4_t, vint32m4_t, vint64m4_t,
-                 vfloat16m4_t, vfloat32m4_t, vfloat64m4_t],
+def VR : VReg<!listconcat(VM1VTs, VMaskVTs),
+              (add (sequence "V%u", 8, 31),
+                   (sequence "V%u", 0, 7)), 1>;
+
+def VRNoV0 : VReg<!listconcat(VM1VTs, VMaskVTs),
+                  (add (sequence "V%u", 8, 31),
+                       (sequence "V%u", 1, 7)), 1>;
+
+def VRM2 : VReg<VM2VTs, (add (sequence "V%uM2", 8, 31, 2),
+                             (sequence "V%uM2", 0, 7, 2)), 2>;
+
+def VRM2NoV0 : VReg<VM2VTs, (add (sequence "V%uM2", 8, 31, 2),
+                                 (sequence "V%uM2", 2, 7, 2)), 2>;
+
+def VRM4 : VReg<VM4VTs,
              (add V8M4, V12M4, V16M4, V20M4, V24M4, V28M4, V0M4, V4M4), 4>;
 
-def VRM4NoV0 : VReg<[vint8m4_t, vint16m4_t, vint32m4_t, vint64m4_t,
-                     vfloat16m4_t, vfloat32m4_t, vfloat64m4_t],
+def VRM4NoV0 : VReg<VM4VTs,
              (add V8M4, V12M4, V16M4, V20M4, V24M4, V28M4, V4M4), 4>;
 
-def VRM8 : VReg<[vint8m8_t, vint16m8_t, vint32m8_t, vint64m8_t,
-                 vfloat16m8_t, vfloat32m8_t, vfloat64m8_t],
-             (add V8M8, V16M8, V24M8, V0M8), 8>;
+def VRM8 : VReg<VM8VTs, (add V8M8, V16M8, V24M8, V0M8), 8>;
 
-def VRM8NoV0 : VReg<[vint8m8_t, vint16m8_t, vint32m8_t, vint64m8_t,
-                     vfloat16m8_t, vfloat32m8_t, vfloat64m8_t],
-             (add V8M8, V16M8, V24M8), 8>;
-
-defvar VMaskVTs = [vbool1_t, vbool2_t, vbool4_t, vbool8_t, vbool16_t,
-                   vbool32_t, vbool64_t];
+def VRM8NoV0 : VReg<VM8VTs, (add V8M8, V16M8, V24M8), 8>;
 
 def VMV0 : RegisterClass<"RISCV", VMaskVTs, 64, (add V0)> {
   let Size = 64;