diff --git a/mlir/test/mlir-tblgen/enums-gen.td b/mlir/test/mlir-tblgen/enums-gen.td --- a/mlir/test/mlir-tblgen/enums-gen.td +++ b/mlir/test/mlir-tblgen/enums-gen.td @@ -5,7 +5,7 @@ include "mlir/IR/OpBase.td" // Test bit enums -def None: I32BitEnumAttrCaseNone<"None">; +def None: I32BitEnumAttrCaseNone<"None", "none">; def Bit0: I32BitEnumAttrCaseBit<"Bit0", 0, "tagged">; def Bit1: I32BitEnumAttrCaseBit<"Bit1", 1>; def Bit2: I32BitEnumAttrCaseBit<"Bit2", 2>; @@ -60,14 +60,14 @@ // DEF-LABEL: std::string stringifyMyBitEnum // DEF: auto val = static_cast -// DEF: if (val == 0) return "None"; +// DEF: if (val == 0) return "none"; // DEF: if (1u == (1u & val)) // DEF-NEXT: push_back("tagged") // DEF: if (2u == (2u & val)) // DEF-NEXT: push_back("Bit1") // DEF-LABEL: ::llvm::Optional symbolizeMyBitEnum(::llvm::StringRef str) -// DEF: if (str == "None") return MyBitEnum::None; +// DEF: if (str == "none") return MyBitEnum::None; // DEF: .Case("tagged", 1) // DEF: .Case("Bit1", 2) diff --git a/mlir/tools/mlir-tblgen/EnumsGen.cpp b/mlir/tools/mlir-tblgen/EnumsGen.cpp --- a/mlir/tools/mlir-tblgen/EnumsGen.cpp +++ b/mlir/tools/mlir-tblgen/EnumsGen.cpp @@ -128,8 +128,7 @@ continue; StringRef symbol = it.value().getSymbol(); os << llvm::formatv(" case {0}::{1}:\n", qualName, - llvm::isDigit(symbol.front()) ? ("_" + symbol) - : symbol); + makeIdentifier(symbol)); } os << " break;\n" " default:\n" @@ -326,7 +325,7 @@ if (allBitsUnsetCase) { os << " // Special case for all bits unset.\n"; os << formatv(" if (val == 0) return \"{0}\";\n\n", - allBitsUnsetCase->getSymbol()); + allBitsUnsetCase->getStr()); } os << " ::llvm::SmallVector<::llvm::StringRef, 2> strs;\n"; @@ -413,7 +412,7 @@ os << " // Special case for all bits unset.\n"; StringRef caseSymbol = allBitsUnsetCase->getSymbol(); os << formatv(" if (str == \"{1}\") return {0}::{2};\n\n", enumName, - caseSymbol, makeIdentifier(caseSymbol)); + allBitsUnsetCase->getStr(), makeIdentifier(caseSymbol)); } // Split the string to get symbols for all the bits.