diff --git a/clang/lib/CodeGen/CGBuiltin.cpp b/clang/lib/CodeGen/CGBuiltin.cpp --- a/clang/lib/CodeGen/CGBuiltin.cpp +++ b/clang/lib/CodeGen/CGBuiltin.cpp @@ -3325,7 +3325,7 @@ } case Builtin::BI__builtin_flt_rounds: { - Function *F = CGM.getIntrinsic(Intrinsic::flt_rounds); + Function *F = CGM.getIntrinsic(Intrinsic::get_rounding); llvm::Type *ResultType = ConvertType(E->getType()); Value *Result = Builder.CreateCall(F); diff --git a/clang/test/CodeGen/builtins-msp430.c b/clang/test/CodeGen/builtins-msp430.c --- a/clang/test/CodeGen/builtins-msp430.c +++ b/clang/test/CodeGen/builtins-msp430.c @@ -2,7 +2,7 @@ // RUN: %clang_cc1 -triple msp430-unknown-unknown -emit-llvm %s -o - | FileCheck %s int test_builtin_flt_rounds() { - // CHECK: [[V0:[%A-Za-z0-9.]+]] = call i32 @llvm.flt.rounds() + // CHECK: [[V0:[%A-Za-z0-9.]+]] = call i32 @llvm.get.rounding() // CHECK-DAG: [[V1:[%A-Za-z0-9.]+]] = trunc i32 [[V0]] to i16 // CHECK-DAG: ret i16 [[V1]] return __builtin_flt_rounds(); diff --git a/clang/test/CodeGen/builtins.c b/clang/test/CodeGen/builtins.c --- a/clang/test/CodeGen/builtins.c +++ b/clang/test/CodeGen/builtins.c @@ -277,7 +277,7 @@ // CHECK: and i1 res = __builtin_flt_rounds(); - // CHECK: call i32 @llvm.flt.rounds( + // CHECK: call i32 @llvm.get.rounding( } // CHECK-LABEL: define{{.*}} void @test_float_builtin_ops diff --git a/llvm/docs/LangRef.rst b/llvm/docs/LangRef.rst --- a/llvm/docs/LangRef.rst +++ b/llvm/docs/LangRef.rst @@ -24598,7 +24598,7 @@ mode or state of floating point exceptions. Altering the floating point environment requires special care. See :ref:`Floating Point Environment `. -'``llvm.flt.rounds``' Intrinsic +'``llvm.get.rounding``' Intrinsic ^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ Syntax: @@ -24606,17 +24606,17 @@ :: - declare i32 @llvm.flt.rounds() + declare i32 @llvm.get.rounding() Overview: """"""""" -The '``llvm.flt.rounds``' intrinsic reads the current rounding mode. +The '``llvm.get.rounding``' intrinsic reads the current rounding mode. Semantics: """""""""" -The '``llvm.flt.rounds``' intrinsic returns the current rounding mode. +The '``llvm.get.rounding``' intrinsic returns the current rounding mode. Encoding of the returned values is same as the result of ``FLT_ROUNDS``, specified by C standard: @@ -24631,7 +24631,6 @@ Other values may be used to represent additional rounding modes, supported by a target. These values are target-specific. - '``llvm.set.rounding``' Intrinsic ^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ @@ -24651,7 +24650,7 @@ """""""""" The argument is the required rounding mode. Encoding of rounding mode is -the same as used by '``llvm.flt.rounds``'. +the same as used by '``llvm.get.rounding``'. Semantics: """""""""" diff --git a/llvm/include/llvm/CodeGen/ISDOpcodes.h b/llvm/include/llvm/CodeGen/ISDOpcodes.h --- a/llvm/include/llvm/CodeGen/ISDOpcodes.h +++ b/llvm/include/llvm/CodeGen/ISDOpcodes.h @@ -859,12 +859,11 @@ /// 3 Round to -inf /// 4 Round to nearest, ties to zero /// Result is rounding mode and chain. Input is a chain. - /// TODO: Rename this node to GET_ROUNDING. - FLT_ROUNDS_, + GET_ROUNDING, /// Set rounding mode. /// The first operand is a chain pointer. The second specifies the required - /// rounding mode, encoded in the same way as used in '``FLT_ROUNDS_``'. + /// rounding mode, encoded in the same way as used in '``GET_ROUNDING``'. SET_ROUNDING, /// X = FP_EXTEND(Y) - Extend a smaller FP type into a larger FP type. diff --git a/llvm/include/llvm/IR/Intrinsics.td b/llvm/include/llvm/IR/Intrinsics.td --- a/llvm/include/llvm/IR/Intrinsics.td +++ b/llvm/include/llvm/IR/Intrinsics.td @@ -755,7 +755,7 @@ // let IntrProperties = [IntrInaccessibleMemOnly, IntrWillReturn] in { - def int_flt_rounds : DefaultAttrsIntrinsic<[llvm_i32_ty], []>; + def int_get_rounding : DefaultAttrsIntrinsic<[llvm_i32_ty], []>; def int_set_rounding : DefaultAttrsIntrinsic<[], [llvm_i32_ty]>; } diff --git a/llvm/lib/CodeGen/IntrinsicLowering.cpp b/llvm/lib/CodeGen/IntrinsicLowering.cpp --- a/llvm/lib/CodeGen/IntrinsicLowering.cpp +++ b/llvm/lib/CodeGen/IntrinsicLowering.cpp @@ -430,7 +430,7 @@ ReplaceFPIntrinsicWithCall(CI, "copysignf", "copysign", "copysignl"); break; } - case Intrinsic::flt_rounds: + case Intrinsic::get_rounding: // Lower to "round to the nearest" if (!CI->getType()->isVoidTy()) CI->replaceAllUsesWith(ConstantInt::get(CI->getType(), 1)); diff --git a/llvm/lib/CodeGen/SelectionDAG/LegalizeDAG.cpp b/llvm/lib/CodeGen/SelectionDAG/LegalizeDAG.cpp --- a/llvm/lib/CodeGen/SelectionDAG/LegalizeDAG.cpp +++ b/llvm/lib/CodeGen/SelectionDAG/LegalizeDAG.cpp @@ -1078,7 +1078,7 @@ SimpleFinishLegalizing = false; break; case ISD::EXTRACT_ELEMENT: - case ISD::FLT_ROUNDS_: + case ISD::GET_ROUNDING: case ISD::MERGE_VALUES: case ISD::EH_RETURN: case ISD::FRAME_TO_ARGS_OFFSET: @@ -2741,7 +2741,7 @@ FA, Offset)); break; } - case ISD::FLT_ROUNDS_: + case ISD::GET_ROUNDING: Results.push_back(DAG.getConstant(1, dl, Node->getValueType(0))); Results.push_back(Node->getOperand(0)); break; diff --git a/llvm/lib/CodeGen/SelectionDAG/LegalizeIntegerTypes.cpp b/llvm/lib/CodeGen/SelectionDAG/LegalizeIntegerTypes.cpp --- a/llvm/lib/CodeGen/SelectionDAG/LegalizeIntegerTypes.cpp +++ b/llvm/lib/CodeGen/SelectionDAG/LegalizeIntegerTypes.cpp @@ -153,7 +153,7 @@ Res = PromoteIntRes_FP_TO_FP16_BF16(N); break; - case ISD::FLT_ROUNDS_: Res = PromoteIntRes_FLT_ROUNDS(N); break; + case ISD::GET_ROUNDING: Res = PromoteIntRes_GET_ROUNDING(N); break; case ISD::AND: case ISD::OR: @@ -730,7 +730,7 @@ return DAG.getNode(N->getOpcode(), dl, NVT, N->getOperand(0)); } -SDValue DAGTypeLegalizer::PromoteIntRes_FLT_ROUNDS(SDNode *N) { +SDValue DAGTypeLegalizer::PromoteIntRes_GET_ROUNDING(SDNode *N) { EVT NVT = TLI.getTypeToTransformTo(*DAG.getContext(), N->getValueType(0)); SDLoc dl(N); @@ -2428,7 +2428,7 @@ case ISD::CTPOP: ExpandIntRes_CTPOP(N, Lo, Hi); break; case ISD::CTTZ_ZERO_UNDEF: case ISD::CTTZ: ExpandIntRes_CTTZ(N, Lo, Hi); break; - case ISD::FLT_ROUNDS_: ExpandIntRes_FLT_ROUNDS(N, Lo, Hi); break; + case ISD::GET_ROUNDING:ExpandIntRes_GET_ROUNDING(N, Lo, Hi); break; case ISD::STRICT_FP_TO_SINT: case ISD::FP_TO_SINT: ExpandIntRes_FP_TO_SINT(N, Lo, Hi); break; case ISD::STRICT_FP_TO_UINT: @@ -3388,15 +3388,15 @@ Hi = DAG.getConstant(0, dl, NVT); } -void DAGTypeLegalizer::ExpandIntRes_FLT_ROUNDS(SDNode *N, SDValue &Lo, +void DAGTypeLegalizer::ExpandIntRes_GET_ROUNDING(SDNode *N, SDValue &Lo, SDValue &Hi) { SDLoc dl(N); EVT NVT = TLI.getTypeToTransformTo(*DAG.getContext(), N->getValueType(0)); unsigned NBitWidth = NVT.getSizeInBits(); - Lo = DAG.getNode(ISD::FLT_ROUNDS_, dl, {NVT, MVT::Other}, N->getOperand(0)); + Lo = DAG.getNode(ISD::GET_ROUNDING, dl, {NVT, MVT::Other}, N->getOperand(0)); SDValue Chain = Lo.getValue(1); - // The high part is the sign of Lo, as -1 is a valid value for FLT_ROUNDS + // The high part is the sign of Lo, as -1 is a valid value for GET_ROUNDING Hi = DAG.getNode(ISD::SRA, dl, NVT, Lo, DAG.getShiftAmountConstant(NBitWidth - 1, NVT, dl)); diff --git a/llvm/lib/CodeGen/SelectionDAG/LegalizeTypes.h b/llvm/lib/CodeGen/SelectionDAG/LegalizeTypes.h --- a/llvm/lib/CodeGen/SelectionDAG/LegalizeTypes.h +++ b/llvm/lib/CodeGen/SelectionDAG/LegalizeTypes.h @@ -354,7 +354,7 @@ SDValue PromoteIntRes_ADDSUBSHLSAT(SDNode *N); SDValue PromoteIntRes_MULFIX(SDNode *N); SDValue PromoteIntRes_DIVFIX(SDNode *N); - SDValue PromoteIntRes_FLT_ROUNDS(SDNode *N); + SDValue PromoteIntRes_GET_ROUNDING(SDNode *N); SDValue PromoteIntRes_VECREDUCE(SDNode *N); SDValue PromoteIntRes_VP_REDUCE(SDNode *N); SDValue PromoteIntRes_ABS(SDNode *N); @@ -437,7 +437,7 @@ void ExpandIntRes_SIGN_EXTEND_INREG (SDNode *N, SDValue &Lo, SDValue &Hi); void ExpandIntRes_TRUNCATE (SDNode *N, SDValue &Lo, SDValue &Hi); void ExpandIntRes_ZERO_EXTEND (SDNode *N, SDValue &Lo, SDValue &Hi); - void ExpandIntRes_FLT_ROUNDS (SDNode *N, SDValue &Lo, SDValue &Hi); + void ExpandIntRes_GET_ROUNDING (SDNode *N, SDValue &Lo, SDValue &Hi); void ExpandIntRes_FP_TO_SINT (SDNode *N, SDValue &Lo, SDValue &Hi); void ExpandIntRes_FP_TO_UINT (SDNode *N, SDValue &Lo, SDValue &Hi); void ExpandIntRes_FP_TO_XINT_SAT (SDNode *N, SDValue &Lo, SDValue &Hi); diff --git a/llvm/lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp b/llvm/lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp --- a/llvm/lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp +++ b/llvm/lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp @@ -6826,8 +6826,8 @@ case Intrinsic::gcread: case Intrinsic::gcwrite: llvm_unreachable("GC failed to lower gcread/gcwrite intrinsics!"); - case Intrinsic::flt_rounds: - Res = DAG.getNode(ISD::FLT_ROUNDS_, sdl, {MVT::i32, MVT::Other}, getRoot()); + case Intrinsic::get_rounding: + Res = DAG.getNode(ISD::GET_ROUNDING, sdl, {MVT::i32, MVT::Other}, getRoot()); setValue(&I, Res); DAG.setRoot(Res.getValue(1)); return; diff --git a/llvm/lib/CodeGen/SelectionDAG/SelectionDAGDumper.cpp b/llvm/lib/CodeGen/SelectionDAG/SelectionDAGDumper.cpp --- a/llvm/lib/CodeGen/SelectionDAG/SelectionDAGDumper.cpp +++ b/llvm/lib/CodeGen/SelectionDAG/SelectionDAGDumper.cpp @@ -422,7 +422,7 @@ return "call_alloc"; // Floating point environment manipulation - case ISD::FLT_ROUNDS_: return "flt_rounds"; + case ISD::GET_ROUNDING: return "get_rounding"; case ISD::SET_ROUNDING: return "set_rounding"; // Bit manipulation diff --git a/llvm/lib/IR/AutoUpgrade.cpp b/llvm/lib/IR/AutoUpgrade.cpp --- a/llvm/lib/IR/AutoUpgrade.cpp +++ b/llvm/lib/IR/AutoUpgrade.cpp @@ -908,6 +908,13 @@ } break; } + case 'f': + if (Name.startswith("flt.rounds")) { + rename(F); + NewFn = Intrinsic::getDeclaration(F->getParent(), Intrinsic::get_rounding); + return true; + } + break; case 'i': case 'l': { bool IsLifetimeStart = Name.startswith("lifetime.start"); diff --git a/llvm/lib/Target/AArch64/AArch64ISelLowering.h b/llvm/lib/Target/AArch64/AArch64ISelLowering.h --- a/llvm/lib/Target/AArch64/AArch64ISelLowering.h +++ b/llvm/lib/Target/AArch64/AArch64ISelLowering.h @@ -1033,7 +1033,7 @@ SDValue LowerFRAMEADDR(SDValue Op, SelectionDAG &DAG) const; SDValue LowerSPONENTRY(SDValue Op, SelectionDAG &DAG) const; SDValue LowerRETURNADDR(SDValue Op, SelectionDAG &DAG) const; - SDValue LowerFLT_ROUNDS_(SDValue Op, SelectionDAG &DAG) const; + SDValue LowerGET_ROUNDING(SDValue Op, SelectionDAG &DAG) const; SDValue LowerSET_ROUNDING(SDValue Op, SelectionDAG &DAG) const; SDValue LowerINSERT_VECTOR_ELT(SDValue Op, SelectionDAG &DAG) const; SDValue LowerEXTRACT_VECTOR_ELT(SDValue Op, SelectionDAG &DAG) const; diff --git a/llvm/lib/Target/AArch64/AArch64ISelLowering.cpp b/llvm/lib/Target/AArch64/AArch64ISelLowering.cpp --- a/llvm/lib/Target/AArch64/AArch64ISelLowering.cpp +++ b/llvm/lib/Target/AArch64/AArch64ISelLowering.cpp @@ -740,7 +740,7 @@ setOperationAction(ISD::PREFETCH, MVT::Other, Custom); - setOperationAction(ISD::FLT_ROUNDS_, MVT::i32, Custom); + setOperationAction(ISD::GET_ROUNDING, MVT::i32, Custom); setOperationAction(ISD::SET_ROUNDING, MVT::Other, Custom); setOperationAction(ISD::ATOMIC_CMP_SWAP, MVT::i128, Custom); @@ -4468,8 +4468,8 @@ return false; } -SDValue AArch64TargetLowering::LowerFLT_ROUNDS_(SDValue Op, - SelectionDAG &DAG) const { +SDValue AArch64TargetLowering::LowerGET_ROUNDING(SDValue Op, + SelectionDAG &DAG) const { // The rounding mode is in bits 23:22 of the FPSCR. // The ARM rounding mode value to FLT_ROUNDS mapping is 0->1, 1->2, 2->3, 3->0 // The formula we use to implement this is (((FPSCR + 1 << 22) >> 22) & 3) @@ -5934,8 +5934,8 @@ return LowerFP_TO_INT_SAT(Op, DAG); case ISD::FSINCOS: return LowerFSINCOS(Op, DAG); - case ISD::FLT_ROUNDS_: - return LowerFLT_ROUNDS_(Op, DAG); + case ISD::GET_ROUNDING: + return LowerGET_ROUNDING(Op, DAG); case ISD::SET_ROUNDING: return LowerSET_ROUNDING(Op, DAG); case ISD::MUL: diff --git a/llvm/lib/Target/ARM/ARMISelLowering.h b/llvm/lib/Target/ARM/ARMISelLowering.h --- a/llvm/lib/Target/ARM/ARMISelLowering.h +++ b/llvm/lib/Target/ARM/ARMISelLowering.h @@ -829,7 +829,7 @@ SDValue LowerFRAMEADDR(SDValue Op, SelectionDAG &DAG) const; SDValue LowerShiftRightParts(SDValue Op, SelectionDAG &DAG) const; SDValue LowerShiftLeftParts(SDValue Op, SelectionDAG &DAG) const; - SDValue LowerFLT_ROUNDS_(SDValue Op, SelectionDAG &DAG) const; + SDValue LowerGET_ROUNDING(SDValue Op, SelectionDAG &DAG) const; SDValue LowerSET_ROUNDING(SDValue Op, SelectionDAG &DAG) const; SDValue LowerConstantFP(SDValue Op, SelectionDAG &DAG, const ARMSubtarget *ST) const; diff --git a/llvm/lib/Target/ARM/ARMISelLowering.cpp b/llvm/lib/Target/ARM/ARMISelLowering.cpp --- a/llvm/lib/Target/ARM/ARMISelLowering.cpp +++ b/llvm/lib/Target/ARM/ARMISelLowering.cpp @@ -1397,7 +1397,7 @@ // Turn f64->i64 into VMOVRRD, i64 -> f64 to VMOVDRR // iff target supports vfp2. setOperationAction(ISD::BITCAST, MVT::i64, Custom); - setOperationAction(ISD::FLT_ROUNDS_, MVT::i32, Custom); + setOperationAction(ISD::GET_ROUNDING, MVT::i32, Custom); setOperationAction(ISD::SET_ROUNDING, MVT::Other, Custom); } @@ -6372,8 +6372,8 @@ return DAG.getMergeValues(Ops, dl); } -SDValue ARMTargetLowering::LowerFLT_ROUNDS_(SDValue Op, - SelectionDAG &DAG) const { +SDValue ARMTargetLowering::LowerGET_ROUNDING(SDValue Op, + SelectionDAG &DAG) const { // The rounding mode is in bits 23:22 of the FPSCR. // The ARM rounding mode value to FLT_ROUNDS mapping is 0->1, 1->2, 2->3, 3->0 // The formula we use to implement this is (((FPSCR + 1 << 22) >> 22) & 3) @@ -10416,7 +10416,7 @@ case ISD::TRUNCATE: return LowerTruncate(Op.getNode(), DAG, Subtarget); case ISD::SIGN_EXTEND: case ISD::ZERO_EXTEND: return LowerVectorExtend(Op.getNode(), DAG, Subtarget); - case ISD::FLT_ROUNDS_: return LowerFLT_ROUNDS_(Op, DAG); + case ISD::GET_ROUNDING: return LowerGET_ROUNDING(Op, DAG); case ISD::SET_ROUNDING: return LowerSET_ROUNDING(Op, DAG); case ISD::MUL: return LowerMUL(Op, DAG); case ISD::SDIV: diff --git a/llvm/lib/Target/PowerPC/PPCISelLowering.h b/llvm/lib/Target/PowerPC/PPCISelLowering.h --- a/llvm/lib/Target/PowerPC/PPCISelLowering.h +++ b/llvm/lib/Target/PowerPC/PPCISelLowering.h @@ -1285,7 +1285,7 @@ SDValue LowerFP_TO_INT(SDValue Op, SelectionDAG &DAG, const SDLoc &dl) const; SDValue LowerINT_TO_FP(SDValue Op, SelectionDAG &DAG) const; - SDValue LowerFLT_ROUNDS_(SDValue Op, SelectionDAG &DAG) const; + SDValue LowerGET_ROUNDING(SDValue Op, SelectionDAG &DAG) const; SDValue LowerSHL_PARTS(SDValue Op, SelectionDAG &DAG) const; SDValue LowerSRL_PARTS(SDValue Op, SelectionDAG &DAG) const; SDValue LowerSRA_PARTS(SDValue Op, SelectionDAG &DAG) const; diff --git a/llvm/lib/Target/PowerPC/PPCISelLowering.cpp b/llvm/lib/Target/PowerPC/PPCISelLowering.cpp --- a/llvm/lib/Target/PowerPC/PPCISelLowering.cpp +++ b/llvm/lib/Target/PowerPC/PPCISelLowering.cpp @@ -419,7 +419,7 @@ if (Subtarget.hasSPE()) setLoadExtAction(ISD::EXTLOAD, MVT::f64, MVT::f32, Expand); - setOperationAction(ISD::FLT_ROUNDS_, MVT::i32, Custom); + setOperationAction(ISD::GET_ROUNDING, MVT::i32, Custom); // If we're enabling GP optimizations, use hardware square root if (!Subtarget.hasFSQRT() && @@ -8752,8 +8752,8 @@ return FP; } -SDValue PPCTargetLowering::LowerFLT_ROUNDS_(SDValue Op, - SelectionDAG &DAG) const { +SDValue PPCTargetLowering::LowerGET_ROUNDING(SDValue Op, + SelectionDAG &DAG) const { SDLoc dl(Op); /* The rounding mode is in bits 30:31 of FPSR, and has the following @@ -8763,7 +8763,7 @@ 10 Round to +inf 11 Round to -inf - FLT_ROUNDS, on the other hand, expects the following: + GET_ROUNDING, on the other hand, expects the following: -1 Undefined 0 Round to 0 1 Round to nearest @@ -11339,7 +11339,7 @@ case ISD::STRICT_SINT_TO_FP: case ISD::UINT_TO_FP: case ISD::SINT_TO_FP: return LowerINT_TO_FP(Op, DAG); - case ISD::FLT_ROUNDS_: return LowerFLT_ROUNDS_(Op, DAG); + case ISD::GET_ROUNDING: return LowerGET_ROUNDING(Op, DAG); // Lower 64-bit shifts. case ISD::SHL_PARTS: return LowerSHL_PARTS(Op, DAG); diff --git a/llvm/lib/Target/RISCV/RISCVISelLowering.cpp b/llvm/lib/Target/RISCV/RISCVISelLowering.cpp --- a/llvm/lib/Target/RISCV/RISCVISelLowering.cpp +++ b/llvm/lib/Target/RISCV/RISCVISelLowering.cpp @@ -439,7 +439,7 @@ ISD::STRICT_UINT_TO_FP, ISD::STRICT_SINT_TO_FP}, XLenVT, Legal); - setOperationAction(ISD::FLT_ROUNDS_, XLenVT, Custom); + setOperationAction(ISD::GET_ROUNDING, XLenVT, Custom); setOperationAction(ISD::SET_ROUNDING, MVT::Other, Custom); } @@ -4175,7 +4175,7 @@ case ISD::MSCATTER: case ISD::VP_SCATTER: return lowerMaskedScatter(Op, DAG); - case ISD::FLT_ROUNDS_: + case ISD::GET_ROUNDING: return lowerGET_ROUNDING(Op, DAG); case ISD::SET_ROUNDING: return lowerSET_ROUNDING(Op, DAG); @@ -8028,9 +8028,9 @@ if (SDValue V = lowerVPREDUCE(SDValue(N, 0), DAG)) Results.push_back(V); break; - case ISD::FLT_ROUNDS_: { + case ISD::GET_ROUNDING: { SDVTList VTs = DAG.getVTList(Subtarget.getXLenVT(), MVT::Other); - SDValue Res = DAG.getNode(ISD::FLT_ROUNDS_, DL, VTs, N->getOperand(0)); + SDValue Res = DAG.getNode(ISD::GET_ROUNDING, DL, VTs, N->getOperand(0)); Results.push_back(Res.getValue(0)); Results.push_back(Res.getValue(1)); break; diff --git a/llvm/lib/Target/X86/X86ISelLowering.h b/llvm/lib/Target/X86/X86ISelLowering.h --- a/llvm/lib/Target/X86/X86ISelLowering.h +++ b/llvm/lib/Target/X86/X86ISelLowering.h @@ -1619,7 +1619,7 @@ SDValue lowerEH_SJLJ_LONGJMP(SDValue Op, SelectionDAG &DAG) const; SDValue lowerEH_SJLJ_SETUP_DISPATCH(SDValue Op, SelectionDAG &DAG) const; SDValue LowerINIT_TRAMPOLINE(SDValue Op, SelectionDAG &DAG) const; - SDValue LowerFLT_ROUNDS_(SDValue Op, SelectionDAG &DAG) const; + SDValue LowerGET_ROUNDING(SDValue Op, SelectionDAG &DAG) const; SDValue LowerSET_ROUNDING(SDValue Op, SelectionDAG &DAG) const; SDValue LowerWin64_i128OP(SDValue Op, SelectionDAG &DAG) const; SDValue LowerWin64_FP_TO_INT128(SDValue Op, SelectionDAG &DAG, diff --git a/llvm/lib/Target/X86/X86ISelLowering.cpp b/llvm/lib/Target/X86/X86ISelLowering.cpp --- a/llvm/lib/Target/X86/X86ISelLowering.cpp +++ b/llvm/lib/Target/X86/X86ISelLowering.cpp @@ -364,7 +364,7 @@ setOperationAction(ISD::FREM , MVT::f128 , Expand); if (!Subtarget.useSoftFloat() && Subtarget.hasX87()) { - setOperationAction(ISD::FLT_ROUNDS_ , MVT::i32 , Custom); + setOperationAction(ISD::GET_ROUNDING , MVT::i32 , Custom); setOperationAction(ISD::SET_ROUNDING , MVT::Other, Custom); } @@ -28953,8 +28953,8 @@ } } -SDValue X86TargetLowering::LowerFLT_ROUNDS_(SDValue Op, - SelectionDAG &DAG) const { +SDValue X86TargetLowering::LowerGET_ROUNDING(SDValue Op, + SelectionDAG &DAG) const { /* The rounding mode is in bits 11:10 of FPSR, and has the following settings: @@ -28963,7 +28963,7 @@ 10 Round to +inf 11 Round to 0 - FLT_ROUNDS, on the other hand, expects the following: + GET_ROUNDING, on the other hand, expects the following: -1 Undefined 0 Round to 0 1 Round to nearest @@ -32986,7 +32986,7 @@ return lowerEH_SJLJ_SETUP_DISPATCH(Op, DAG); case ISD::INIT_TRAMPOLINE: return LowerINIT_TRAMPOLINE(Op, DAG); case ISD::ADJUST_TRAMPOLINE: return LowerADJUST_TRAMPOLINE(Op, DAG); - case ISD::FLT_ROUNDS_: return LowerFLT_ROUNDS_(Op, DAG); + case ISD::GET_ROUNDING: return LowerGET_ROUNDING(Op, DAG); case ISD::SET_ROUNDING: return LowerSET_ROUNDING(Op, DAG); case ISD::CTLZ: case ISD::CTLZ_ZERO_UNDEF: return LowerCTLZ(Op, Subtarget, DAG); diff --git a/llvm/test/Bitcode/Inputs/auto_upgrade_flt_rounds.bc b/llvm/test/Bitcode/Inputs/auto_upgrade_flt_rounds.bc new file mode 100644 index 0000000000000000000000000000000000000000..0000000000000000000000000000000000000000 GIT binary patch literal 0 Hc$@:4 ; preds = %3 - %5 = call i32 @llvm.flt.rounds() + %5 = call i32 @llvm.get.rounding() %6 = icmp eq i32 %5, 1 br i1 %6, label %8, label %7 @@ -33,4 +33,4 @@ ret void } -declare i32 @llvm.flt.rounds() nounwind +declare i32 @llvm.get.rounding() nounwind diff --git a/llvm/test/CodeGen/ARM/fpscr-intrinsics.ll b/llvm/test/CodeGen/ARM/fpscr-intrinsics.ll --- a/llvm/test/CodeGen/ARM/fpscr-intrinsics.ll +++ b/llvm/test/CodeGen/ARM/fpscr-intrinsics.ll @@ -7,7 +7,7 @@ define void @strtod() { entry: ; CHECK: vmrs r{{[0-9]+}}, fpscr - %0 = call i32 @llvm.flt.rounds() + %0 = call i32 @llvm.get.rounding() %tobool = icmp ne i32 %0, 0 br i1 %tobool, label %if.then, label %if.end @@ -41,4 +41,4 @@ declare void @llvm.arm.set.fpscr(i32) ; Function Attrs: nounwind -declare i32 @llvm.flt.rounds() +declare i32 @llvm.get.rounding() diff --git a/llvm/test/CodeGen/ARM/no-fpscr-liveness.ll b/llvm/test/CodeGen/ARM/no-fpscr-liveness.ll --- a/llvm/test/CodeGen/ARM/no-fpscr-liveness.ll +++ b/llvm/test/CodeGen/ARM/no-fpscr-liveness.ll @@ -22,7 +22,7 @@ bb: %tmp = alloca %struct.wibble, align 4 %tmp1 = bitcast %struct.wibble* %tmp to i8* - %tmp2 = tail call i32 @llvm.flt.rounds() + %tmp2 = tail call i32 @llvm.get.rounding() %tmp3 = ptrtoint %struct.wibble* %tmp to i32 %tmp4 = sitofp i32 %tmp3 to double %tmp5 = fmul double %tmp4, 0x0123456789ABCDEF @@ -47,5 +47,5 @@ ret i32 undef } -declare i32 @llvm.flt.rounds() +declare i32 @llvm.get.rounding() declare i32 @zot(...) diff --git a/llvm/test/CodeGen/MSP430/flt_rounds.ll b/llvm/test/CodeGen/MSP430/flt_rounds.ll --- a/llvm/test/CodeGen/MSP430/flt_rounds.ll +++ b/llvm/test/CodeGen/MSP430/flt_rounds.ll @@ -2,9 +2,9 @@ define i16 @foo() { entry: - %0 = call i32 @llvm.flt.rounds() + %0 = call i32 @llvm.get.rounding() %1 = trunc i32 %0 to i16 ret i16 %1 } -declare i32 @llvm.flt.rounds() nounwind +declare i32 @llvm.get.rounding() nounwind diff --git a/llvm/test/CodeGen/PowerPC/frounds.ll b/llvm/test/CodeGen/PowerPC/frounds.ll --- a/llvm/test/CodeGen/PowerPC/frounds.ll +++ b/llvm/test/CodeGen/PowerPC/frounds.ll @@ -66,7 +66,7 @@ %retval = alloca i32 ; [#uses=2] %tmp = alloca i32 ; [#uses=2] %"alloca point" = bitcast i32 0 to i32 ; [#uses=0] - %tmp1 = call i32 @llvm.flt.rounds( ) ; [#uses=1] + %tmp1 = call i32 @llvm.get.rounding( ) ; [#uses=1] store i32 %tmp1, ptr %tmp, align 4 %tmp2 = load i32, ptr %tmp, align 4 ; [#uses=1] store i32 %tmp2, ptr %retval, align 4 @@ -77,4 +77,4 @@ ret i32 %retval3 } -declare i32 @llvm.flt.rounds() nounwind +declare i32 @llvm.get.rounding() nounwind diff --git a/llvm/test/CodeGen/RISCV/flt-rounds.ll b/llvm/test/CodeGen/RISCV/flt-rounds.ll --- a/llvm/test/CodeGen/RISCV/flt-rounds.ll +++ b/llvm/test/CodeGen/RISCV/flt-rounds.ll @@ -4,7 +4,7 @@ ; RUN: llc -mtriple=riscv64 -verify-machineinstrs < %s \ ; RUN: | FileCheck -check-prefix=RV64I %s -declare i32 @llvm.flt.rounds() +declare i32 @llvm.get.rounding() define i32 @test_flt_rounds() nounwind { ; RV32I-LABEL: test_flt_rounds: @@ -16,6 +16,6 @@ ; RV64I: # %bb.0: ; RV64I-NEXT: li a0, 1 ; RV64I-NEXT: ret - %1 = call i32 @llvm.flt.rounds() + %1 = call i32 @llvm.get.rounding() ret i32 %1 } diff --git a/llvm/test/CodeGen/RISCV/fpenv.ll b/llvm/test/CodeGen/RISCV/fpenv.ll --- a/llvm/test/CodeGen/RISCV/fpenv.ll +++ b/llvm/test/CodeGen/RISCV/fpenv.ll @@ -22,7 +22,7 @@ ; RV64IF-NEXT: srl a0, a1, a0 ; RV64IF-NEXT: andi a0, a0, 7 ; RV64IF-NEXT: ret - %rm = call i32 @llvm.flt.rounds() + %rm = call i32 @llvm.get.rounding() ret i32 %rm } @@ -122,4 +122,4 @@ } declare void @llvm.set.rounding(i32) -declare i32 @llvm.flt.rounds() +declare i32 @llvm.get.rounding() diff --git a/llvm/test/CodeGen/X86/flt-rounds.ll b/llvm/test/CodeGen/X86/flt-rounds.ll --- a/llvm/test/CodeGen/X86/flt-rounds.ll +++ b/llvm/test/CodeGen/X86/flt-rounds.ll @@ -3,7 +3,7 @@ ; RUN: llc -mtriple=i686-unknown-linux-gnu -mattr=-sse2 -verify-machineinstrs < %s | FileCheck %s --check-prefix=X86 ; RUN: llc -mtriple=x86_64-unknown-linux-gnu -verify-machineinstrs < %s | FileCheck %s --check-prefix=X64 -declare i32 @llvm.flt.rounds() +declare i32 @llvm.get.rounding() define i32 @test_flt_rounds() nounwind { ; X86-LABEL: test_flt_rounds: @@ -31,7 +31,7 @@ ; X64-NEXT: shrl %cl, %eax ; X64-NEXT: andl $3, %eax ; X64-NEXT: retq - %1 = call i32 @llvm.flt.rounds() + %1 = call i32 @llvm.get.rounding() ret i32 %1 } @@ -172,21 +172,21 @@ ; X64-NEXT: retq entry: %call = tail call i32 @fesetround(i32 1024) - %0 = tail call i32 @llvm.flt.rounds() + %0 = tail call i32 @llvm.get.rounding() %cmp = icmp ne i32 %0, 3 %spec.select = zext i1 %cmp to i32 %call1 = tail call i32 @fesetround(i32 0) - %1 = tail call i32 @llvm.flt.rounds() + %1 = tail call i32 @llvm.get.rounding() %cmp2 = icmp eq i32 %1, 1 %inc4 = select i1 %cmp, i32 2, i32 1 %errs.1 = select i1 %cmp2, i32 %spec.select, i32 %inc4 %call6 = tail call i32 @fesetround(i32 3072) - %2 = tail call i32 @llvm.flt.rounds() + %2 = tail call i32 @llvm.get.rounding() %cmp7 = icmp ne i32 %2, 0 %inc9 = zext i1 %cmp7 to i32 %spec.select22 = add nuw nsw i32 %errs.1, %inc9 %call11 = tail call i32 @fesetround(i32 2048) - %3 = tail call i32 @llvm.flt.rounds() + %3 = tail call i32 @llvm.get.rounding() %cmp12 = icmp ne i32 %3, 2 %inc14.neg = sext i1 %cmp12 to i32 %cmp16 = icmp ne i32 %spec.select22, %inc14.neg