Index: clang/include/clang/Basic/riscv_thead_vector.td =================================================================== --- /dev/null +++ clang/include/clang/Basic/riscv_thead_vector.td @@ -0,0 +1,22 @@ +multiclass TH_VdotOutOp1Op2BuiltinSet> suffixes_prototypes> { + let OverloadedName = NAME in + defm "" : RVVBuiltinSet; +} + +let UnMaskedPolicyScheme = HasPolicyOperand, + IsPrototypeDefaultTU = true, + HasMaskedOffOperand = false, + Log2LMUL = [-1, 0, 1, 2, 3] in { +defm th_vmaqau : TH_VdotOutOp1Op2BuiltinSet<"th_vmaqau", "c", + [["vv", "Uh", "UhUhUvUv"], + ["vx", "Uh", "UhUhUeUv"]]>; +defm th_vmaqa : TH_VdotOutOp1Op2BuiltinSet<"th_vmaqa", "c", + [["vv", "h", "hhvv"], + ["vx", "h", "hhev"]]>; +defm th_vmaqasu : TH_VdotOutOp1Op2BuiltinSet<"th_vmaqasu", "c", + [["vv", "h", "hhvUv"], + ["vx", "h", "hheUv"]]>; +defm th_vmaqaus : TH_VdotOutOp1Op2BuiltinSet<"th_vmaqaus", "c", + [["vx", "h", "hhUev"]]>; +} Index: clang/include/clang/Basic/riscv_vector.td =================================================================== --- clang/include/clang/Basic/riscv_vector.td +++ clang/include/clang/Basic/riscv_vector.td @@ -61,6 +61,9 @@ // element type which is four times as wide as the element type of 'v' // o: computes a vector type identical to what 'v' computes except for the // element type which is eight times as wide as the element type of 'v' +// h: computes a vector type identical to what 'v' computes except for the +// element type which is four times as wide as the element type of 'v', +// and keep LMUL same with the original vector type // m: computes a vector type identical to what 'v' computes except for the // element type which is bool // 0: void type, ignores "t" @@ -2390,3 +2393,8 @@ } } } + +//===----------------------------------------------------------------------===// +// Vendor extensions +//===----------------------------------------------------------------------===// +include "clang/Basic/riscv_thead_vector.td" Index: clang/include/clang/Support/RISCVVIntrinsicUtils.h =================================================================== --- clang/include/clang/Support/RISCVVIntrinsicUtils.h +++ clang/include/clang/Support/RISCVVIntrinsicUtils.h @@ -35,6 +35,7 @@ Widening2XVector, Widening4XVector, Widening8XVector, + Widening4XSEW, MaskVector, Log2EEW3, Log2EEW4, Index: clang/lib/Support/RISCVVIntrinsicUtils.cpp =================================================================== --- clang/lib/Support/RISCVVIntrinsicUtils.cpp +++ clang/lib/Support/RISCVVIntrinsicUtils.cpp @@ -392,6 +392,10 @@ PT = BaseTypeModifier::Vector; VTM = VectorTypeModifier::Widening8XVector; break; + case 'h': + PT = BaseTypeModifier::Vector; + VTM = VectorTypeModifier::Widening4XSEW; + break; case 'm': PT = BaseTypeModifier::Vector; VTM = VectorTypeModifier::MaskVector; @@ -629,6 +633,10 @@ LMUL.MulLog2LMUL(3); Scale = LMUL.getScale(ElementBitwidth); break; + case VectorTypeModifier::Widening4XSEW: + ElementBitwidth *= 4; + Scale = LMUL.getScale(ElementBitwidth); + break; case VectorTypeModifier::MaskVector: ScalarType = ScalarTypeKind::Boolean; Scale = LMUL.getScale(ElementBitwidth); @@ -1084,7 +1092,7 @@ SmallVector parsePrototypes(StringRef Prototypes) { SmallVector PrototypeDescriptors; - const StringRef Primaries("evwqom0ztul"); + const StringRef Primaries("evwqohm0ztul"); while (!Prototypes.empty()) { size_t Idx = 0; // Skip over complex prototype because it could contain primitive type Index: clang/test/CodeGen/RISCV/Vendor/THEAD/vdot-intrinsics-overloaded/vmaqa.c =================================================================== --- /dev/null +++ clang/test/CodeGen/RISCV/Vendor/THEAD/vdot-intrinsics-overloaded/vmaqa.c @@ -0,0 +1,574 @@ +// NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py +// REQUIRES: riscv-registered-target +// RUN: %clang_cc1 -triple riscv64 -target-feature +v -target-feature +xtheadvdot -disable-O0-optnone -emit-llvm %s -o - | opt -S -passes=mem2reg | FileCheck %s + +#include + +// CHECK-LABEL: @test_th_vmaqa_vv_i32mf2( +// CHECK-NEXT: entry: +// CHECK-NEXT: [[TMP0:%.*]] = call @llvm.riscv.th.vmaqa.nxv1i32.nxv4i8.nxv4i8.i64( [[ACC:%.*]], [[OP1:%.*]], [[OP2:%.*]], i64 [[VL:%.*]], i64 0) +// CHECK-NEXT: ret [[TMP0]] +// +vint32mf2_t test_th_vmaqa_vv_i32mf2(vint32mf2_t acc, vint8mf2_t op1, vint8mf2_t op2, + size_t vl) { + return th_vmaqa(acc, op1, op2, vl); +} + +// CHECK-LABEL: @test_th_vmaqa_vx_i32mf2( +// CHECK-NEXT: entry: +// CHECK-NEXT: [[TMP0:%.*]] = call @llvm.riscv.th.vmaqa.nxv1i32.i8.nxv4i8.i64( [[ACC:%.*]], i8 [[OP1:%.*]], [[OP2:%.*]], i64 [[VL:%.*]], i64 0) +// CHECK-NEXT: ret [[TMP0]] +// +vint32mf2_t test_th_vmaqa_vx_i32mf2(vint32mf2_t acc, int8_t op1, vint8mf2_t op2, + size_t vl) { + return th_vmaqa(acc, op1, op2, vl); +} + +// CHECK-LABEL: @test_th_vmaqa_vv_i32m1( +// CHECK-NEXT: entry: +// CHECK-NEXT: [[TMP0:%.*]] = call @llvm.riscv.th.vmaqa.nxv2i32.nxv8i8.nxv8i8.i64( [[ACC:%.*]], [[OP1:%.*]], [[OP2:%.*]], i64 [[VL:%.*]], i64 0) +// CHECK-NEXT: ret [[TMP0]] +// +vint32m1_t test_th_vmaqa_vv_i32m1(vint32m1_t acc, vint8m1_t op1, vint8m1_t op2, + size_t vl) { + return th_vmaqa(acc, op1, op2, vl); +} + +// CHECK-LABEL: @test_th_vmaqa_vx_i32m1( +// CHECK-NEXT: entry: +// CHECK-NEXT: [[TMP0:%.*]] = call @llvm.riscv.th.vmaqa.nxv2i32.i8.nxv8i8.i64( [[ACC:%.*]], i8 [[OP1:%.*]], [[OP2:%.*]], i64 [[VL:%.*]], i64 0) +// CHECK-NEXT: ret [[TMP0]] +// +vint32m1_t test_th_vmaqa_vx_i32m1(vint32m1_t acc, int8_t op1, vint8m1_t op2, + size_t vl) { + return th_vmaqa(acc, op1, op2, vl); +} + +// CHECK-LABEL: @test_th_vmaqa_vv_i32m2( +// CHECK-NEXT: entry: +// CHECK-NEXT: [[TMP0:%.*]] = call @llvm.riscv.th.vmaqa.nxv4i32.nxv16i8.nxv16i8.i64( [[ACC:%.*]], [[OP1:%.*]], [[OP2:%.*]], i64 [[VL:%.*]], i64 0) +// CHECK-NEXT: ret [[TMP0]] +// +vint32m2_t test_th_vmaqa_vv_i32m2(vint32m2_t acc, vint8m2_t op1, vint8m2_t op2, + size_t vl) { + return th_vmaqa(acc, op1, op2, vl); +} + +// CHECK-LABEL: @test_th_vmaqa_vx_i32m2( +// CHECK-NEXT: entry: +// CHECK-NEXT: [[TMP0:%.*]] = call @llvm.riscv.th.vmaqa.nxv4i32.i8.nxv16i8.i64( [[ACC:%.*]], i8 [[OP1:%.*]], [[OP2:%.*]], i64 [[VL:%.*]], i64 0) +// CHECK-NEXT: ret [[TMP0]] +// +vint32m2_t test_th_vmaqa_vx_i32m2(vint32m2_t acc, int8_t op1, vint8m2_t op2, + size_t vl) { + return th_vmaqa(acc, op1, op2, vl); +} + +// CHECK-LABEL: @test_th_vmaqa_vv_i32m4( +// CHECK-NEXT: entry: +// CHECK-NEXT: [[TMP0:%.*]] = call @llvm.riscv.th.vmaqa.nxv8i32.nxv32i8.nxv32i8.i64( [[ACC:%.*]], [[OP1:%.*]], [[OP2:%.*]], i64 [[VL:%.*]], i64 0) +// CHECK-NEXT: ret [[TMP0]] +// +vint32m4_t test_th_vmaqa_vv_i32m4(vint32m4_t acc, vint8m4_t op1, vint8m4_t op2, + size_t vl) { + return th_vmaqa(acc, op1, op2, vl); +} + +// CHECK-LABEL: @test_th_vmaqa_vx_i32m4( +// CHECK-NEXT: entry: +// CHECK-NEXT: [[TMP0:%.*]] = call @llvm.riscv.th.vmaqa.nxv8i32.i8.nxv32i8.i64( [[ACC:%.*]], i8 [[OP1:%.*]], [[OP2:%.*]], i64 [[VL:%.*]], i64 0) +// CHECK-NEXT: ret [[TMP0]] +// +vint32m4_t test_th_vmaqa_vx_i32m4(vint32m4_t acc, int8_t op1, vint8m4_t op2, + size_t vl) { + return th_vmaqa(acc, op1, op2, vl); +} + + +// CHECK-LABEL: @test_th_vmaqau_vv_u32mf2( +// CHECK-NEXT: entry: +// CHECK-NEXT: [[TMP0:%.*]] = call @llvm.riscv.th.vmaqau.nxv1i32.nxv4i8.nxv4i8.i64( [[ACC:%.*]], [[OP1:%.*]], [[OP2:%.*]], i64 [[VL:%.*]], i64 0) +// CHECK-NEXT: ret [[TMP0]] +// +vuint32mf2_t test_th_vmaqau_vv_u32mf2(vuint32mf2_t acc, vuint8mf2_t op1, + vuint8mf2_t op2, size_t vl) { + return th_vmaqau(acc, op1, op2, vl); +} + +// CHECK-LABEL: @test_th_vmaqau_vx_u32mf2( +// CHECK-NEXT: entry: +// CHECK-NEXT: [[TMP0:%.*]] = call @llvm.riscv.th.vmaqau.nxv1i32.i8.nxv4i8.i64( [[ACC:%.*]], i8 [[OP1:%.*]], [[OP2:%.*]], i64 [[VL:%.*]], i64 0) +// CHECK-NEXT: ret [[TMP0]] +// +vuint32mf2_t test_th_vmaqau_vx_u32mf2(vuint32mf2_t acc, uint8_t op1, vuint8mf2_t op2, + size_t vl) { + return th_vmaqau(acc, op1, op2, vl); +} + +// CHECK-LABEL: @test_th_vmaqau_vv_u32m1( +// CHECK-NEXT: entry: +// CHECK-NEXT: [[TMP0:%.*]] = call @llvm.riscv.th.vmaqau.nxv2i32.nxv8i8.nxv8i8.i64( [[ACC:%.*]], [[OP1:%.*]], [[OP2:%.*]], i64 [[VL:%.*]], i64 0) +// CHECK-NEXT: ret [[TMP0]] +// +vuint32m1_t test_th_vmaqau_vv_u32m1(vuint32m1_t acc, vuint8m1_t op1, + vuint8m1_t op2, size_t vl) { + return th_vmaqau(acc, op1, op2, vl); +} + +// CHECK-LABEL: @test_th_vmaqau_vx_u32m1( +// CHECK-NEXT: entry: +// CHECK-NEXT: [[TMP0:%.*]] = call @llvm.riscv.th.vmaqau.nxv2i32.i8.nxv8i8.i64( [[ACC:%.*]], i8 [[OP1:%.*]], [[OP2:%.*]], i64 [[VL:%.*]], i64 0) +// CHECK-NEXT: ret [[TMP0]] +// +vuint32m1_t test_th_vmaqau_vx_u32m1(vuint32m1_t acc, uint8_t op1, vuint8m1_t op2, + size_t vl) { + return th_vmaqau(acc, op1, op2, vl); +} + +// CHECK-LABEL: @test_th_vmaqau_vv_u32m2( +// CHECK-NEXT: entry: +// CHECK-NEXT: [[TMP0:%.*]] = call @llvm.riscv.th.vmaqau.nxv4i32.nxv16i8.nxv16i8.i64( [[ACC:%.*]], [[OP1:%.*]], [[OP2:%.*]], i64 [[VL:%.*]], i64 0) +// CHECK-NEXT: ret [[TMP0]] +// +vuint32m2_t test_th_vmaqau_vv_u32m2(vuint32m2_t acc, vuint8m2_t op1, + vuint8m2_t op2, size_t vl) { + return th_vmaqau(acc, op1, op2, vl); +} + +// CHECK-LABEL: @test_th_vmaqau_vx_u32m2( +// CHECK-NEXT: entry: +// CHECK-NEXT: [[TMP0:%.*]] = call @llvm.riscv.th.vmaqau.nxv4i32.i8.nxv16i8.i64( [[ACC:%.*]], i8 [[OP1:%.*]], [[OP2:%.*]], i64 [[VL:%.*]], i64 0) +// CHECK-NEXT: ret [[TMP0]] +// +vuint32m2_t test_th_vmaqau_vx_u32m2(vuint32m2_t acc, uint8_t op1, vuint8m2_t op2, + size_t vl) { + return th_vmaqau(acc, op1, op2, vl); +} + +// CHECK-LABEL: @test_th_vmaqau_vv_u32m4( +// CHECK-NEXT: entry: +// CHECK-NEXT: [[TMP0:%.*]] = call @llvm.riscv.th.vmaqau.nxv8i32.nxv32i8.nxv32i8.i64( [[ACC:%.*]], [[OP1:%.*]], [[OP2:%.*]], i64 [[VL:%.*]], i64 0) +// CHECK-NEXT: ret [[TMP0]] +// +vuint32m4_t test_th_vmaqau_vv_u32m4(vuint32m4_t acc, vuint8m4_t op1, + vuint8m4_t op2, size_t vl) { + return th_vmaqau(acc, op1, op2, vl); +} + +// CHECK-LABEL: @test_th_vmaqau_vx_u32m4( +// CHECK-NEXT: entry: +// CHECK-NEXT: [[TMP0:%.*]] = call @llvm.riscv.th.vmaqau.nxv8i32.i8.nxv32i8.i64( [[ACC:%.*]], i8 [[OP1:%.*]], [[OP2:%.*]], i64 [[VL:%.*]], i64 0) +// CHECK-NEXT: ret [[TMP0]] +// +vuint32m4_t test_th_vmaqau_vx_u32m4(vuint32m4_t acc, uint8_t op1, vuint8m4_t op2, + size_t vl) { + return th_vmaqau(acc, op1, op2, vl); +} + + +// CHECK-LABEL: @test_th_vmaqasu_vv_i32mf2( +// CHECK-NEXT: entry: +// CHECK-NEXT: [[TMP0:%.*]] = call @llvm.riscv.th.vmaqasu.nxv1i32.nxv4i8.nxv4i8.i64( [[ACC:%.*]], [[OP1:%.*]], [[OP2:%.*]], i64 [[VL:%.*]], i64 0) +// CHECK-NEXT: ret [[TMP0]] +// +vint32mf2_t test_th_vmaqasu_vv_i32mf2(vint32mf2_t acc, vint8mf2_t op1, + vuint8mf2_t op2, size_t vl) { + return th_vmaqasu(acc, op1, op2, vl); +} + +// CHECK-LABEL: @test_th_vmaqasu_vx_i32mf2( +// CHECK-NEXT: entry: +// CHECK-NEXT: [[TMP0:%.*]] = call @llvm.riscv.th.vmaqasu.nxv1i32.i8.nxv4i8.i64( [[ACC:%.*]], i8 [[OP1:%.*]], [[OP2:%.*]], i64 [[VL:%.*]], i64 0) +// CHECK-NEXT: ret [[TMP0]] +// +vint32mf2_t test_th_vmaqasu_vx_i32mf2(vint32mf2_t acc, int8_t op1, vuint8mf2_t op2, + size_t vl) { + return th_vmaqasu(acc, op1, op2, vl); +} + +// CHECK-LABEL: @test_th_vmaqasu_vv_i32m1( +// CHECK-NEXT: entry: +// CHECK-NEXT: [[TMP0:%.*]] = call @llvm.riscv.th.vmaqasu.nxv2i32.nxv8i8.nxv8i8.i64( [[ACC:%.*]], [[OP1:%.*]], [[OP2:%.*]], i64 [[VL:%.*]], i64 0) +// CHECK-NEXT: ret [[TMP0]] +// +vint32m1_t test_th_vmaqasu_vv_i32m1(vint32m1_t acc, vint8m1_t op1, vuint8m1_t op2, + size_t vl) { + return th_vmaqasu(acc, op1, op2, vl); +} + +// CHECK-LABEL: @test_th_vmaqasu_vx_i32m1( +// CHECK-NEXT: entry: +// CHECK-NEXT: [[TMP0:%.*]] = call @llvm.riscv.th.vmaqasu.nxv2i32.i8.nxv8i8.i64( [[ACC:%.*]], i8 [[OP1:%.*]], [[OP2:%.*]], i64 [[VL:%.*]], i64 0) +// CHECK-NEXT: ret [[TMP0]] +// +vint32m1_t test_th_vmaqasu_vx_i32m1(vint32m1_t acc, int8_t op1, vuint8m1_t op2, + size_t vl) { + return th_vmaqasu(acc, op1, op2, vl); +} + +// CHECK-LABEL: @test_th_vmaqasu_vv_i32m2( +// CHECK-NEXT: entry: +// CHECK-NEXT: [[TMP0:%.*]] = call @llvm.riscv.th.vmaqasu.nxv4i32.nxv16i8.nxv16i8.i64( [[ACC:%.*]], [[OP1:%.*]], [[OP2:%.*]], i64 [[VL:%.*]], i64 0) +// CHECK-NEXT: ret [[TMP0]] +// +vint32m2_t test_th_vmaqasu_vv_i32m2(vint32m2_t acc, vint8m2_t op1, vuint8m2_t op2, + size_t vl) { + return th_vmaqasu(acc, op1, op2, vl); +} + +// CHECK-LABEL: @test_th_vmaqasu_vx_i32m2( +// CHECK-NEXT: entry: +// CHECK-NEXT: [[TMP0:%.*]] = call @llvm.riscv.th.vmaqasu.nxv4i32.i8.nxv16i8.i64( [[ACC:%.*]], i8 [[OP1:%.*]], [[OP2:%.*]], i64 [[VL:%.*]], i64 0) +// CHECK-NEXT: ret [[TMP0]] +// +vint32m2_t test_th_vmaqasu_vx_i32m2(vint32m2_t acc, int8_t op1, vuint8m2_t op2, + size_t vl) { + return th_vmaqasu(acc, op1, op2, vl); +} + +// CHECK-LABEL: @test_th_vmaqasu_vv_i32m4( +// CHECK-NEXT: entry: +// CHECK-NEXT: [[TMP0:%.*]] = call @llvm.riscv.th.vmaqasu.nxv8i32.nxv32i8.nxv32i8.i64( [[ACC:%.*]], [[OP1:%.*]], [[OP2:%.*]], i64 [[VL:%.*]], i64 0) +// CHECK-NEXT: ret [[TMP0]] +// +vint32m4_t test_th_vmaqasu_vv_i32m4(vint32m4_t acc, vint8m4_t op1, vuint8m4_t op2, + size_t vl) { + return th_vmaqasu(acc, op1, op2, vl); +} + +// CHECK-LABEL: @test_th_vmaqasu_vx_i32m4( +// CHECK-NEXT: entry: +// CHECK-NEXT: [[TMP0:%.*]] = call @llvm.riscv.th.vmaqasu.nxv8i32.i8.nxv32i8.i64( [[ACC:%.*]], i8 [[OP1:%.*]], [[OP2:%.*]], i64 [[VL:%.*]], i64 0) +// CHECK-NEXT: ret [[TMP0]] +// +vint32m4_t test_th_vmaqasu_vx_i32m4(vint32m4_t acc, int8_t op1, vuint8m4_t op2, + size_t vl) { + return th_vmaqasu(acc, op1, op2, vl); +} + + +// CHECK-LABEL: @test_th_vmaqaus_vx_i32mf2( +// CHECK-NEXT: entry: +// CHECK-NEXT: [[TMP0:%.*]] = call @llvm.riscv.th.vmaqaus.nxv1i32.i8.nxv4i8.i64( [[ACC:%.*]], i8 [[OP1:%.*]], [[OP2:%.*]], i64 [[VL:%.*]], i64 0) +// CHECK-NEXT: ret [[TMP0]] +// +vint32mf2_t test_th_vmaqaus_vx_i32mf2(vint32mf2_t acc, uint8_t op1, vint8mf2_t op2, + size_t vl) { + return th_vmaqaus(acc, op1, op2, vl); +} + +// CHECK-LABEL: @test_th_vmaqaus_vx_i32m1( +// CHECK-NEXT: entry: +// CHECK-NEXT: [[TMP0:%.*]] = call @llvm.riscv.th.vmaqaus.nxv2i32.i8.nxv8i8.i64( [[ACC:%.*]], i8 [[OP1:%.*]], [[OP2:%.*]], i64 [[VL:%.*]], i64 0) +// CHECK-NEXT: ret [[TMP0]] +// +vint32m1_t test_th_vmaqaus_vx_i32m1(vint32m1_t acc, uint8_t op1, vint8m1_t op2, + size_t vl) { + return th_vmaqaus(acc, op1, op2, vl); +} + +// CHECK-LABEL: @test_th_vmaqaus_vx_i32m2( +// CHECK-NEXT: entry: +// CHECK-NEXT: [[TMP0:%.*]] = call @llvm.riscv.th.vmaqaus.nxv4i32.i8.nxv16i8.i64( [[ACC:%.*]], i8 [[OP1:%.*]], [[OP2:%.*]], i64 [[VL:%.*]], i64 0) +// CHECK-NEXT: ret [[TMP0]] +// +vint32m2_t test_th_vmaqaus_vx_i32m2(vint32m2_t acc, uint8_t op1, vint8m2_t op2, + size_t vl) { + return th_vmaqaus(acc, op1, op2, vl); +} + +// CHECK-LABEL: @test_th_vmaqaus_vx_i32m4( +// CHECK-NEXT: entry: +// CHECK-NEXT: [[TMP0:%.*]] = call @llvm.riscv.th.vmaqaus.nxv8i32.i8.nxv32i8.i64( [[ACC:%.*]], i8 [[OP1:%.*]], [[OP2:%.*]], i64 [[VL:%.*]], i64 0) +// CHECK-NEXT: ret [[TMP0]] +// +vint32m4_t test_th_vmaqaus_vx_i32m4(vint32m4_t acc, uint8_t op1, vint8m4_t op2, + size_t vl) { + return th_vmaqaus(acc, op1, op2, vl); +} + + +// CHECK-LABEL: @test_th_vmaqa_vv_i32mf2_m( +// CHECK-NEXT: entry: +// CHECK-NEXT: [[TMP0:%.*]] = call @llvm.riscv.th.vmaqa.mask.nxv1i32.nxv4i8.nxv4i8.i64( [[ACC:%.*]], [[OP1:%.*]], [[OP2:%.*]], [[MASK:%.*]], i64 [[VL:%.*]], i64 0) +// CHECK-NEXT: ret [[TMP0]] +// +vint32mf2_t test_th_vmaqa_vv_i32mf2_m(vbool16_t mask, vint32mf2_t acc, + vint8mf2_t op1, vint8mf2_t op2, size_t vl) { + return th_vmaqa(mask, acc, op1, op2, vl); +} + +// CHECK-LABEL: @test_th_vmaqa_vx_i32mf2_m( +// CHECK-NEXT: entry: +// CHECK-NEXT: [[TMP0:%.*]] = call @llvm.riscv.th.vmaqa.mask.nxv1i32.i8.nxv4i8.i64( [[ACC:%.*]], i8 [[OP1:%.*]], [[OP2:%.*]], [[MASK:%.*]], i64 [[VL:%.*]], i64 0) +// CHECK-NEXT: ret [[TMP0]] +// +vint32mf2_t test_th_vmaqa_vx_i32mf2_m(vbool16_t mask, vint32mf2_t acc, int8_t op1, + vint8mf2_t op2, size_t vl) { + return th_vmaqa(mask, acc, op1, op2, vl); +} + +// CHECK-LABEL: @test_th_vmaqa_vv_i32m1_m( +// CHECK-NEXT: entry: +// CHECK-NEXT: [[TMP0:%.*]] = call @llvm.riscv.th.vmaqa.mask.nxv2i32.nxv8i8.nxv8i8.i64( [[ACC:%.*]], [[OP1:%.*]], [[OP2:%.*]], [[MASK:%.*]], i64 [[VL:%.*]], i64 0) +// CHECK-NEXT: ret [[TMP0]] +// +vint32m1_t test_th_vmaqa_vv_i32m1_m(vbool8_t mask, vint32m1_t acc, vint8m1_t op1, + vint8m1_t op2, size_t vl) { + return th_vmaqa(mask, acc, op1, op2, vl); +} + +// CHECK-LABEL: @test_th_vmaqa_vx_i32m1_m( +// CHECK-NEXT: entry: +// CHECK-NEXT: [[TMP0:%.*]] = call @llvm.riscv.th.vmaqa.mask.nxv2i32.i8.nxv8i8.i64( [[ACC:%.*]], i8 [[OP1:%.*]], [[OP2:%.*]], [[MASK:%.*]], i64 [[VL:%.*]], i64 0) +// CHECK-NEXT: ret [[TMP0]] +// +vint32m1_t test_th_vmaqa_vx_i32m1_m(vbool8_t mask, vint32m1_t acc, int8_t op1, + vint8m1_t op2, size_t vl) { + return th_vmaqa(mask, acc, op1, op2, vl); +} + +// CHECK-LABEL: @test_th_vmaqa_vv_i32m2_m( +// CHECK-NEXT: entry: +// CHECK-NEXT: [[TMP0:%.*]] = call @llvm.riscv.th.vmaqa.mask.nxv4i32.nxv16i8.nxv16i8.i64( [[ACC:%.*]], [[OP1:%.*]], [[OP2:%.*]], [[MASK:%.*]], i64 [[VL:%.*]], i64 0) +// CHECK-NEXT: ret [[TMP0]] +// +vint32m2_t test_th_vmaqa_vv_i32m2_m(vbool4_t mask, vint32m2_t acc, vint8m2_t op1, + vint8m2_t op2, size_t vl) { + return th_vmaqa(mask, acc, op1, op2, vl); +} + +// CHECK-LABEL: @test_th_vmaqa_vx_i32m2_m( +// CHECK-NEXT: entry: +// CHECK-NEXT: [[TMP0:%.*]] = call @llvm.riscv.th.vmaqa.mask.nxv4i32.i8.nxv16i8.i64( [[ACC:%.*]], i8 [[OP1:%.*]], [[OP2:%.*]], [[MASK:%.*]], i64 [[VL:%.*]], i64 0) +// CHECK-NEXT: ret [[TMP0]] +// +vint32m2_t test_th_vmaqa_vx_i32m2_m(vbool4_t mask, vint32m2_t acc, int8_t op1, + vint8m2_t op2, size_t vl) { + return th_vmaqa(mask, acc, op1, op2, vl); +} + +// CHECK-LABEL: @test_th_vmaqa_vv_i32m4_m( +// CHECK-NEXT: entry: +// CHECK-NEXT: [[TMP0:%.*]] = call @llvm.riscv.th.vmaqa.mask.nxv8i32.nxv32i8.nxv32i8.i64( [[ACC:%.*]], [[OP1:%.*]], [[OP2:%.*]], [[MASK:%.*]], i64 [[VL:%.*]], i64 0) +// CHECK-NEXT: ret [[TMP0]] +// +vint32m4_t test_th_vmaqa_vv_i32m4_m(vbool2_t mask, vint32m4_t acc, vint8m4_t op1, + vint8m4_t op2, size_t vl) { + return th_vmaqa(mask, acc, op1, op2, vl); +} + +// CHECK-LABEL: @test_th_vmaqa_vx_i32m4_m( +// CHECK-NEXT: entry: +// CHECK-NEXT: [[TMP0:%.*]] = call @llvm.riscv.th.vmaqa.mask.nxv8i32.i8.nxv32i8.i64( [[ACC:%.*]], i8 [[OP1:%.*]], [[OP2:%.*]], [[MASK:%.*]], i64 [[VL:%.*]], i64 0) +// CHECK-NEXT: ret [[TMP0]] +// +vint32m4_t test_th_vmaqa_vx_i32m4_m(vbool2_t mask, vint32m4_t acc, int8_t op1, + vint8m4_t op2, size_t vl) { + return th_vmaqa(mask, acc, op1, op2, vl); +} + + +// CHECK-LABEL: @test_th_vmaqau_vv_u32mf2_m( +// CHECK-NEXT: entry: +// CHECK-NEXT: [[TMP0:%.*]] = call @llvm.riscv.th.vmaqau.mask.nxv1i32.nxv4i8.nxv4i8.i64( [[ACC:%.*]], [[OP1:%.*]], [[OP2:%.*]], [[MASK:%.*]], i64 [[VL:%.*]], i64 0) +// CHECK-NEXT: ret [[TMP0]] +// +vuint32mf2_t test_th_vmaqau_vv_u32mf2_m(vbool16_t mask, vuint32mf2_t acc, + vuint8mf2_t op1, vuint8mf2_t op2, + size_t vl) { + return th_vmaqau(mask, acc, op1, op2, vl); +} + +// CHECK-LABEL: @test_th_vmaqau_vx_u32mf2_m( +// CHECK-NEXT: entry: +// CHECK-NEXT: [[TMP0:%.*]] = call @llvm.riscv.th.vmaqau.mask.nxv1i32.i8.nxv4i8.i64( [[ACC:%.*]], i8 [[OP1:%.*]], [[OP2:%.*]], [[MASK:%.*]], i64 [[VL:%.*]], i64 0) +// CHECK-NEXT: ret [[TMP0]] +// +vuint32mf2_t test_th_vmaqau_vx_u32mf2_m(vbool16_t mask, vuint32mf2_t acc, + uint8_t op1, vuint8mf2_t op2, size_t vl) { + return th_vmaqau(mask, acc, op1, op2, vl); +} + +// CHECK-LABEL: @test_th_vmaqau_vv_u32m1_m( +// CHECK-NEXT: entry: +// CHECK-NEXT: [[TMP0:%.*]] = call @llvm.riscv.th.vmaqau.mask.nxv2i32.nxv8i8.nxv8i8.i64( [[ACC:%.*]], [[OP1:%.*]], [[OP2:%.*]], [[MASK:%.*]], i64 [[VL:%.*]], i64 0) +// CHECK-NEXT: ret [[TMP0]] +// +vuint32m1_t test_th_vmaqau_vv_u32m1_m(vbool8_t mask, vuint32m1_t acc, + vuint8m1_t op1, vuint8m1_t op2, size_t vl) { + return th_vmaqau(mask, acc, op1, op2, vl); +} + +// CHECK-LABEL: @test_th_vmaqau_vx_u32m1_m( +// CHECK-NEXT: entry: +// CHECK-NEXT: [[TMP0:%.*]] = call @llvm.riscv.th.vmaqau.mask.nxv2i32.i8.nxv8i8.i64( [[ACC:%.*]], i8 [[OP1:%.*]], [[OP2:%.*]], [[MASK:%.*]], i64 [[VL:%.*]], i64 0) +// CHECK-NEXT: ret [[TMP0]] +// +vuint32m1_t test_th_vmaqau_vx_u32m1_m(vbool8_t mask, vuint32m1_t acc, uint8_t op1, + vuint8m1_t op2, size_t vl) { + return th_vmaqau(mask, acc, op1, op2, vl); +} + +// CHECK-LABEL: @test_th_vmaqau_vv_u32m2_m( +// CHECK-NEXT: entry: +// CHECK-NEXT: [[TMP0:%.*]] = call @llvm.riscv.th.vmaqau.mask.nxv4i32.nxv16i8.nxv16i8.i64( [[ACC:%.*]], [[OP1:%.*]], [[OP2:%.*]], [[MASK:%.*]], i64 [[VL:%.*]], i64 0) +// CHECK-NEXT: ret [[TMP0]] +// +vuint32m2_t test_th_vmaqau_vv_u32m2_m(vbool4_t mask, vuint32m2_t acc, + vuint8m2_t op1, vuint8m2_t op2, size_t vl) { + return th_vmaqau(mask, acc, op1, op2, vl); +} + +// CHECK-LABEL: @test_th_vmaqau_vx_u32m2_m( +// CHECK-NEXT: entry: +// CHECK-NEXT: [[TMP0:%.*]] = call @llvm.riscv.th.vmaqau.mask.nxv4i32.i8.nxv16i8.i64( [[ACC:%.*]], i8 [[OP1:%.*]], [[OP2:%.*]], [[MASK:%.*]], i64 [[VL:%.*]], i64 0) +// CHECK-NEXT: ret [[TMP0]] +// +vuint32m2_t test_th_vmaqau_vx_u32m2_m(vbool4_t mask, vuint32m2_t acc, uint8_t op1, + vuint8m2_t op2, size_t vl) { + return th_vmaqau(mask, acc, op1, op2, vl); +} + +// CHECK-LABEL: @test_th_vmaqau_vv_u32m4_m( +// CHECK-NEXT: entry: +// CHECK-NEXT: [[TMP0:%.*]] = call @llvm.riscv.th.vmaqau.mask.nxv8i32.nxv32i8.nxv32i8.i64( [[ACC:%.*]], [[OP1:%.*]], [[OP2:%.*]], [[MASK:%.*]], i64 [[VL:%.*]], i64 0) +// CHECK-NEXT: ret [[TMP0]] +// +vuint32m4_t test_th_vmaqau_vv_u32m4_m(vbool2_t mask, vuint32m4_t acc, + vuint8m4_t op1, vuint8m4_t op2, size_t vl) { + return th_vmaqau(mask, acc, op1, op2, vl); +} + +// CHECK-LABEL: @test_th_vmaqau_vx_u32m4_m( +// CHECK-NEXT: entry: +// CHECK-NEXT: [[TMP0:%.*]] = call @llvm.riscv.th.vmaqau.mask.nxv8i32.i8.nxv32i8.i64( [[ACC:%.*]], i8 [[OP1:%.*]], [[OP2:%.*]], [[MASK:%.*]], i64 [[VL:%.*]], i64 0) +// CHECK-NEXT: ret [[TMP0]] +// +vuint32m4_t test_th_vmaqau_vx_u32m4_m(vbool2_t mask, vuint32m4_t acc, uint8_t op1, + vuint8m4_t op2, size_t vl) { + return th_vmaqau(mask, acc, op1, op2, vl); +} + + +// CHECK-LABEL: @test_th_vmaqasu_vv_i32mf2_m( +// CHECK-NEXT: entry: +// CHECK-NEXT: [[TMP0:%.*]] = call @llvm.riscv.th.vmaqasu.mask.nxv1i32.nxv4i8.nxv4i8.i64( [[ACC:%.*]], [[OP1:%.*]], [[OP2:%.*]], [[MASK:%.*]], i64 [[VL:%.*]], i64 0) +// CHECK-NEXT: ret [[TMP0]] +// +vint32mf2_t test_th_vmaqasu_vv_i32mf2_m(vbool16_t mask, vint32mf2_t acc, + vint8mf2_t op1, vuint8mf2_t op2, + size_t vl) { + return th_vmaqasu(mask, acc, op1, op2, vl); +} + +// CHECK-LABEL: @test_th_vmaqasu_vx_i32mf2_m( +// CHECK-NEXT: entry: +// CHECK-NEXT: [[TMP0:%.*]] = call @llvm.riscv.th.vmaqasu.mask.nxv1i32.i8.nxv4i8.i64( [[ACC:%.*]], i8 [[OP1:%.*]], [[OP2:%.*]], [[MASK:%.*]], i64 [[VL:%.*]], i64 0) +// CHECK-NEXT: ret [[TMP0]] +// +vint32mf2_t test_th_vmaqasu_vx_i32mf2_m(vbool16_t mask, vint32mf2_t acc, int8_t op1, + vuint8mf2_t op2, size_t vl) { + return th_vmaqasu(mask, acc, op1, op2, vl); +} + +// CHECK-LABEL: @test_th_vmaqasu_vv_i32m1_m( +// CHECK-NEXT: entry: +// CHECK-NEXT: [[TMP0:%.*]] = call @llvm.riscv.th.vmaqasu.mask.nxv2i32.nxv8i8.nxv8i8.i64( [[ACC:%.*]], [[OP1:%.*]], [[OP2:%.*]], [[MASK:%.*]], i64 [[VL:%.*]], i64 0) +// CHECK-NEXT: ret [[TMP0]] +// +vint32m1_t test_th_vmaqasu_vv_i32m1_m(vbool8_t mask, vint32m1_t acc, + vint8m1_t op1, vuint8m1_t op2, size_t vl) { + return th_vmaqasu(mask, acc, op1, op2, vl); +} + +// CHECK-LABEL: @test_th_vmaqasu_vx_i32m1_m( +// CHECK-NEXT: entry: +// CHECK-NEXT: [[TMP0:%.*]] = call @llvm.riscv.th.vmaqasu.mask.nxv2i32.i8.nxv8i8.i64( [[ACC:%.*]], i8 [[OP1:%.*]], [[OP2:%.*]], [[MASK:%.*]], i64 [[VL:%.*]], i64 0) +// CHECK-NEXT: ret [[TMP0]] +// +vint32m1_t test_th_vmaqasu_vx_i32m1_m(vbool8_t mask, vint32m1_t acc, int8_t op1, + vuint8m1_t op2, size_t vl) { + return th_vmaqasu(mask, acc, op1, op2, vl); +} + +// CHECK-LABEL: @test_th_vmaqasu_vv_i32m2_m( +// CHECK-NEXT: entry: +// CHECK-NEXT: [[TMP0:%.*]] = call @llvm.riscv.th.vmaqasu.mask.nxv4i32.nxv16i8.nxv16i8.i64( [[ACC:%.*]], [[OP1:%.*]], [[OP2:%.*]], [[MASK:%.*]], i64 [[VL:%.*]], i64 0) +// CHECK-NEXT: ret [[TMP0]] +// +vint32m2_t test_th_vmaqasu_vv_i32m2_m(vbool4_t mask, vint32m2_t acc, + vint8m2_t op1, vuint8m2_t op2, size_t vl) { + return th_vmaqasu(mask, acc, op1, op2, vl); +} + +// CHECK-LABEL: @test_th_vmaqasu_vx_i32m2_m( +// CHECK-NEXT: entry: +// CHECK-NEXT: [[TMP0:%.*]] = call @llvm.riscv.th.vmaqasu.mask.nxv4i32.i8.nxv16i8.i64( [[ACC:%.*]], i8 [[OP1:%.*]], [[OP2:%.*]], [[MASK:%.*]], i64 [[VL:%.*]], i64 0) +// CHECK-NEXT: ret [[TMP0]] +// +vint32m2_t test_th_vmaqasu_vx_i32m2_m(vbool4_t mask, vint32m2_t acc, int8_t op1, + vuint8m2_t op2, size_t vl) { + return th_vmaqasu(mask, acc, op1, op2, vl); +} + +// CHECK-LABEL: @test_th_vmaqasu_vv_i32m4_m( +// CHECK-NEXT: entry: +// CHECK-NEXT: [[TMP0:%.*]] = call @llvm.riscv.th.vmaqasu.mask.nxv8i32.nxv32i8.nxv32i8.i64( [[ACC:%.*]], [[OP1:%.*]], [[OP2:%.*]], [[MASK:%.*]], i64 [[VL:%.*]], i64 0) +// CHECK-NEXT: ret [[TMP0]] +// +vint32m4_t test_th_vmaqasu_vv_i32m4_m(vbool2_t mask, vint32m4_t acc, + vint8m4_t op1, vuint8m4_t op2, size_t vl) { + return th_vmaqasu(mask, acc, op1, op2, vl); +} + +// CHECK-LABEL: @test_th_vmaqasu_vx_i32m4_m( +// CHECK-NEXT: entry: +// CHECK-NEXT: [[TMP0:%.*]] = call @llvm.riscv.th.vmaqasu.mask.nxv8i32.i8.nxv32i8.i64( [[ACC:%.*]], i8 [[OP1:%.*]], [[OP2:%.*]], [[MASK:%.*]], i64 [[VL:%.*]], i64 0) +// CHECK-NEXT: ret [[TMP0]] +// +vint32m4_t test_th_vmaqasu_vx_i32m4_m(vbool2_t mask, vint32m4_t acc, int8_t op1, + vuint8m4_t op2, size_t vl) { + return th_vmaqasu(mask, acc, op1, op2, vl); +} + + +// CHECK-LABEL: @test_th_vmaqaus_vx_i32mf2_m( +// CHECK-NEXT: entry: +// CHECK-NEXT: [[TMP0:%.*]] = call @llvm.riscv.th.vmaqaus.mask.nxv1i32.i8.nxv4i8.i64( [[ACC:%.*]], i8 [[OP1:%.*]], [[OP2:%.*]], [[MASK:%.*]], i64 [[VL:%.*]], i64 0) +// CHECK-NEXT: ret [[TMP0]] +// +vint32mf2_t test_th_vmaqaus_vx_i32mf2_m(vbool16_t mask, vint32mf2_t acc, uint8_t op1, + vint8mf2_t op2, size_t vl) { + return th_vmaqaus(mask, acc, op1, op2, vl); +} + +// CHECK-LABEL: @test_th_vmaqaus_vx_i32m1_m( +// CHECK-NEXT: entry: +// CHECK-NEXT: [[TMP0:%.*]] = call @llvm.riscv.th.vmaqaus.mask.nxv2i32.i8.nxv8i8.i64( [[ACC:%.*]], i8 [[OP1:%.*]], [[OP2:%.*]], [[MASK:%.*]], i64 [[VL:%.*]], i64 0) +// CHECK-NEXT: ret [[TMP0]] +// +vint32m1_t test_th_vmaqaus_vx_i32m1_m(vbool8_t mask, vint32m1_t acc, uint8_t op1, + vint8m1_t op2, size_t vl) { + return th_vmaqaus(mask, acc, op1, op2, vl); +} + +// CHECK-LABEL: @test_th_vmaqaus_vx_i32m2_m( +// CHECK-NEXT: entry: +// CHECK-NEXT: [[TMP0:%.*]] = call @llvm.riscv.th.vmaqaus.mask.nxv4i32.i8.nxv16i8.i64( [[ACC:%.*]], i8 [[OP1:%.*]], [[OP2:%.*]], [[MASK:%.*]], i64 [[VL:%.*]], i64 0) +// CHECK-NEXT: ret [[TMP0]] +// +vint32m2_t test_th_vmaqaus_vx_i32m2_m(vbool4_t mask, vint32m2_t acc, uint8_t op1, + vint8m2_t op2, size_t vl) { + return th_vmaqaus(mask, acc, op1, op2, vl); +} + +// CHECK-LABEL: @test_th_vmaqaus_vx_i32m4_m( +// CHECK-NEXT: entry: +// CHECK-NEXT: [[TMP0:%.*]] = call @llvm.riscv.th.vmaqaus.mask.nxv8i32.i8.nxv32i8.i64( [[ACC:%.*]], i8 [[OP1:%.*]], [[OP2:%.*]], [[MASK:%.*]], i64 [[VL:%.*]], i64 0) +// CHECK-NEXT: ret [[TMP0]] +// +vint32m4_t test_th_vmaqaus_vx_i32m4_m(vbool2_t mask, vint32m4_t acc, uint8_t op1, + vint8m4_t op2, size_t vl) { + return th_vmaqaus(mask, acc, op1, op2, vl); +} Index: clang/test/CodeGen/RISCV/Vendor/THEAD/vdot-intrinsics/vmaqa.c =================================================================== --- /dev/null +++ clang/test/CodeGen/RISCV/Vendor/THEAD/vdot-intrinsics/vmaqa.c @@ -0,0 +1,574 @@ +// NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py +// REQUIRES: riscv-registered-target +// RUN: %clang_cc1 -triple riscv64 -target-feature +v -target-feature +xtheadvdot -disable-O0-optnone -emit-llvm %s -o - | opt -S -passes=mem2reg | FileCheck %s + +#include + +// CHECK-LABEL: @test_th_vmaqa_vv_i32mf2( +// CHECK-NEXT: entry: +// CHECK-NEXT: [[TMP0:%.*]] = call @llvm.riscv.th.vmaqa.nxv1i32.nxv4i8.nxv4i8.i64( [[ACC:%.*]], [[OP1:%.*]], [[OP2:%.*]], i64 [[VL:%.*]], i64 0) +// CHECK-NEXT: ret [[TMP0]] +// +vint32mf2_t test_th_vmaqa_vv_i32mf2(vint32mf2_t acc, vint8mf2_t op1, vint8mf2_t op2, + size_t vl) { + return th_vmaqa_vv_i32mf2(acc, op1, op2, vl); +} + +// CHECK-LABEL: @test_th_vmaqa_vx_i32mf2( +// CHECK-NEXT: entry: +// CHECK-NEXT: [[TMP0:%.*]] = call @llvm.riscv.th.vmaqa.nxv1i32.i8.nxv4i8.i64( [[ACC:%.*]], i8 [[OP1:%.*]], [[OP2:%.*]], i64 [[VL:%.*]], i64 0) +// CHECK-NEXT: ret [[TMP0]] +// +vint32mf2_t test_th_vmaqa_vx_i32mf2(vint32mf2_t acc, int8_t op1, vint8mf2_t op2, + size_t vl) { + return th_vmaqa_vx_i32mf2(acc, op1, op2, vl); +} + +// CHECK-LABEL: @test_th_vmaqa_vv_i32m1( +// CHECK-NEXT: entry: +// CHECK-NEXT: [[TMP0:%.*]] = call @llvm.riscv.th.vmaqa.nxv2i32.nxv8i8.nxv8i8.i64( [[ACC:%.*]], [[OP1:%.*]], [[OP2:%.*]], i64 [[VL:%.*]], i64 0) +// CHECK-NEXT: ret [[TMP0]] +// +vint32m1_t test_th_vmaqa_vv_i32m1(vint32m1_t acc, vint8m1_t op1, vint8m1_t op2, + size_t vl) { + return th_vmaqa_vv_i32m1(acc, op1, op2, vl); +} + +// CHECK-LABEL: @test_th_vmaqa_vx_i32m1( +// CHECK-NEXT: entry: +// CHECK-NEXT: [[TMP0:%.*]] = call @llvm.riscv.th.vmaqa.nxv2i32.i8.nxv8i8.i64( [[ACC:%.*]], i8 [[OP1:%.*]], [[OP2:%.*]], i64 [[VL:%.*]], i64 0) +// CHECK-NEXT: ret [[TMP0]] +// +vint32m1_t test_th_vmaqa_vx_i32m1(vint32m1_t acc, int8_t op1, vint8m1_t op2, + size_t vl) { + return th_vmaqa_vx_i32m1(acc, op1, op2, vl); +} + +// CHECK-LABEL: @test_th_vmaqa_vv_i32m2( +// CHECK-NEXT: entry: +// CHECK-NEXT: [[TMP0:%.*]] = call @llvm.riscv.th.vmaqa.nxv4i32.nxv16i8.nxv16i8.i64( [[ACC:%.*]], [[OP1:%.*]], [[OP2:%.*]], i64 [[VL:%.*]], i64 0) +// CHECK-NEXT: ret [[TMP0]] +// +vint32m2_t test_th_vmaqa_vv_i32m2(vint32m2_t acc, vint8m2_t op1, vint8m2_t op2, + size_t vl) { + return th_vmaqa_vv_i32m2(acc, op1, op2, vl); +} + +// CHECK-LABEL: @test_th_vmaqa_vx_i32m2( +// CHECK-NEXT: entry: +// CHECK-NEXT: [[TMP0:%.*]] = call @llvm.riscv.th.vmaqa.nxv4i32.i8.nxv16i8.i64( [[ACC:%.*]], i8 [[OP1:%.*]], [[OP2:%.*]], i64 [[VL:%.*]], i64 0) +// CHECK-NEXT: ret [[TMP0]] +// +vint32m2_t test_th_vmaqa_vx_i32m2(vint32m2_t acc, int8_t op1, vint8m2_t op2, + size_t vl) { + return th_vmaqa_vx_i32m2(acc, op1, op2, vl); +} + +// CHECK-LABEL: @test_th_vmaqa_vv_i32m4( +// CHECK-NEXT: entry: +// CHECK-NEXT: [[TMP0:%.*]] = call @llvm.riscv.th.vmaqa.nxv8i32.nxv32i8.nxv32i8.i64( [[ACC:%.*]], [[OP1:%.*]], [[OP2:%.*]], i64 [[VL:%.*]], i64 0) +// CHECK-NEXT: ret [[TMP0]] +// +vint32m4_t test_th_vmaqa_vv_i32m4(vint32m4_t acc, vint8m4_t op1, vint8m4_t op2, + size_t vl) { + return th_vmaqa_vv_i32m4(acc, op1, op2, vl); +} + +// CHECK-LABEL: @test_th_vmaqa_vx_i32m4( +// CHECK-NEXT: entry: +// CHECK-NEXT: [[TMP0:%.*]] = call @llvm.riscv.th.vmaqa.nxv8i32.i8.nxv32i8.i64( [[ACC:%.*]], i8 [[OP1:%.*]], [[OP2:%.*]], i64 [[VL:%.*]], i64 0) +// CHECK-NEXT: ret [[TMP0]] +// +vint32m4_t test_th_vmaqa_vx_i32m4(vint32m4_t acc, int8_t op1, vint8m4_t op2, + size_t vl) { + return th_vmaqa_vx_i32m4(acc, op1, op2, vl); +} + + +// CHECK-LABEL: @test_th_vmaqau_vv_u32mf2( +// CHECK-NEXT: entry: +// CHECK-NEXT: [[TMP0:%.*]] = call @llvm.riscv.th.vmaqau.nxv1i32.nxv4i8.nxv4i8.i64( [[ACC:%.*]], [[OP1:%.*]], [[OP2:%.*]], i64 [[VL:%.*]], i64 0) +// CHECK-NEXT: ret [[TMP0]] +// +vuint32mf2_t test_th_vmaqau_vv_u32mf2(vuint32mf2_t acc, vuint8mf2_t op1, + vuint8mf2_t op2, size_t vl) { + return th_vmaqau_vv_u32mf2(acc, op1, op2, vl); +} + +// CHECK-LABEL: @test_th_vmaqau_vx_u32mf2( +// CHECK-NEXT: entry: +// CHECK-NEXT: [[TMP0:%.*]] = call @llvm.riscv.th.vmaqau.nxv1i32.i8.nxv4i8.i64( [[ACC:%.*]], i8 [[OP1:%.*]], [[OP2:%.*]], i64 [[VL:%.*]], i64 0) +// CHECK-NEXT: ret [[TMP0]] +// +vuint32mf2_t test_th_vmaqau_vx_u32mf2(vuint32mf2_t acc, uint8_t op1, vuint8mf2_t op2, + size_t vl) { + return th_vmaqau_vx_u32mf2(acc, op1, op2, vl); +} + +// CHECK-LABEL: @test_th_vmaqau_vv_u32m1( +// CHECK-NEXT: entry: +// CHECK-NEXT: [[TMP0:%.*]] = call @llvm.riscv.th.vmaqau.nxv2i32.nxv8i8.nxv8i8.i64( [[ACC:%.*]], [[OP1:%.*]], [[OP2:%.*]], i64 [[VL:%.*]], i64 0) +// CHECK-NEXT: ret [[TMP0]] +// +vuint32m1_t test_th_vmaqau_vv_u32m1(vuint32m1_t acc, vuint8m1_t op1, + vuint8m1_t op2, size_t vl) { + return th_vmaqau_vv_u32m1(acc, op1, op2, vl); +} + +// CHECK-LABEL: @test_th_vmaqau_vx_u32m1( +// CHECK-NEXT: entry: +// CHECK-NEXT: [[TMP0:%.*]] = call @llvm.riscv.th.vmaqau.nxv2i32.i8.nxv8i8.i64( [[ACC:%.*]], i8 [[OP1:%.*]], [[OP2:%.*]], i64 [[VL:%.*]], i64 0) +// CHECK-NEXT: ret [[TMP0]] +// +vuint32m1_t test_th_vmaqau_vx_u32m1(vuint32m1_t acc, uint8_t op1, vuint8m1_t op2, + size_t vl) { + return th_vmaqau_vx_u32m1(acc, op1, op2, vl); +} + +// CHECK-LABEL: @test_th_vmaqau_vv_u32m2( +// CHECK-NEXT: entry: +// CHECK-NEXT: [[TMP0:%.*]] = call @llvm.riscv.th.vmaqau.nxv4i32.nxv16i8.nxv16i8.i64( [[ACC:%.*]], [[OP1:%.*]], [[OP2:%.*]], i64 [[VL:%.*]], i64 0) +// CHECK-NEXT: ret [[TMP0]] +// +vuint32m2_t test_th_vmaqau_vv_u32m2(vuint32m2_t acc, vuint8m2_t op1, + vuint8m2_t op2, size_t vl) { + return th_vmaqau_vv_u32m2(acc, op1, op2, vl); +} + +// CHECK-LABEL: @test_th_vmaqau_vx_u32m2( +// CHECK-NEXT: entry: +// CHECK-NEXT: [[TMP0:%.*]] = call @llvm.riscv.th.vmaqau.nxv4i32.i8.nxv16i8.i64( [[ACC:%.*]], i8 [[OP1:%.*]], [[OP2:%.*]], i64 [[VL:%.*]], i64 0) +// CHECK-NEXT: ret [[TMP0]] +// +vuint32m2_t test_th_vmaqau_vx_u32m2(vuint32m2_t acc, uint8_t op1, vuint8m2_t op2, + size_t vl) { + return th_vmaqau_vx_u32m2(acc, op1, op2, vl); +} + +// CHECK-LABEL: @test_th_vmaqau_vv_u32m4( +// CHECK-NEXT: entry: +// CHECK-NEXT: [[TMP0:%.*]] = call @llvm.riscv.th.vmaqau.nxv8i32.nxv32i8.nxv32i8.i64( [[ACC:%.*]], [[OP1:%.*]], [[OP2:%.*]], i64 [[VL:%.*]], i64 0) +// CHECK-NEXT: ret [[TMP0]] +// +vuint32m4_t test_th_vmaqau_vv_u32m4(vuint32m4_t acc, vuint8m4_t op1, + vuint8m4_t op2, size_t vl) { + return th_vmaqau_vv_u32m4(acc, op1, op2, vl); +} + +// CHECK-LABEL: @test_th_vmaqau_vx_u32m4( +// CHECK-NEXT: entry: +// CHECK-NEXT: [[TMP0:%.*]] = call @llvm.riscv.th.vmaqau.nxv8i32.i8.nxv32i8.i64( [[ACC:%.*]], i8 [[OP1:%.*]], [[OP2:%.*]], i64 [[VL:%.*]], i64 0) +// CHECK-NEXT: ret [[TMP0]] +// +vuint32m4_t test_th_vmaqau_vx_u32m4(vuint32m4_t acc, uint8_t op1, vuint8m4_t op2, + size_t vl) { + return th_vmaqau_vx_u32m4(acc, op1, op2, vl); +} + + +// CHECK-LABEL: @test_th_vmaqasu_vv_i32mf2( +// CHECK-NEXT: entry: +// CHECK-NEXT: [[TMP0:%.*]] = call @llvm.riscv.th.vmaqasu.nxv1i32.nxv4i8.nxv4i8.i64( [[ACC:%.*]], [[OP1:%.*]], [[OP2:%.*]], i64 [[VL:%.*]], i64 0) +// CHECK-NEXT: ret [[TMP0]] +// +vint32mf2_t test_th_vmaqasu_vv_i32mf2(vint32mf2_t acc, vint8mf2_t op1, + vuint8mf2_t op2, size_t vl) { + return th_vmaqasu_vv_i32mf2(acc, op1, op2, vl); +} + +// CHECK-LABEL: @test_th_vmaqasu_vx_i32mf2( +// CHECK-NEXT: entry: +// CHECK-NEXT: [[TMP0:%.*]] = call @llvm.riscv.th.vmaqasu.nxv1i32.i8.nxv4i8.i64( [[ACC:%.*]], i8 [[OP1:%.*]], [[OP2:%.*]], i64 [[VL:%.*]], i64 0) +// CHECK-NEXT: ret [[TMP0]] +// +vint32mf2_t test_th_vmaqasu_vx_i32mf2(vint32mf2_t acc, int8_t op1, vuint8mf2_t op2, + size_t vl) { + return th_vmaqasu_vx_i32mf2(acc, op1, op2, vl); +} + +// CHECK-LABEL: @test_th_vmaqasu_vv_i32m1( +// CHECK-NEXT: entry: +// CHECK-NEXT: [[TMP0:%.*]] = call @llvm.riscv.th.vmaqasu.nxv2i32.nxv8i8.nxv8i8.i64( [[ACC:%.*]], [[OP1:%.*]], [[OP2:%.*]], i64 [[VL:%.*]], i64 0) +// CHECK-NEXT: ret [[TMP0]] +// +vint32m1_t test_th_vmaqasu_vv_i32m1(vint32m1_t acc, vint8m1_t op1, vuint8m1_t op2, + size_t vl) { + return th_vmaqasu_vv_i32m1(acc, op1, op2, vl); +} + +// CHECK-LABEL: @test_th_vmaqasu_vx_i32m1( +// CHECK-NEXT: entry: +// CHECK-NEXT: [[TMP0:%.*]] = call @llvm.riscv.th.vmaqasu.nxv2i32.i8.nxv8i8.i64( [[ACC:%.*]], i8 [[OP1:%.*]], [[OP2:%.*]], i64 [[VL:%.*]], i64 0) +// CHECK-NEXT: ret [[TMP0]] +// +vint32m1_t test_th_vmaqasu_vx_i32m1(vint32m1_t acc, int8_t op1, vuint8m1_t op2, + size_t vl) { + return th_vmaqasu_vx_i32m1(acc, op1, op2, vl); +} + +// CHECK-LABEL: @test_th_vmaqasu_vv_i32m2( +// CHECK-NEXT: entry: +// CHECK-NEXT: [[TMP0:%.*]] = call @llvm.riscv.th.vmaqasu.nxv4i32.nxv16i8.nxv16i8.i64( [[ACC:%.*]], [[OP1:%.*]], [[OP2:%.*]], i64 [[VL:%.*]], i64 0) +// CHECK-NEXT: ret [[TMP0]] +// +vint32m2_t test_th_vmaqasu_vv_i32m2(vint32m2_t acc, vint8m2_t op1, vuint8m2_t op2, + size_t vl) { + return th_vmaqasu_vv_i32m2(acc, op1, op2, vl); +} + +// CHECK-LABEL: @test_th_vmaqasu_vx_i32m2( +// CHECK-NEXT: entry: +// CHECK-NEXT: [[TMP0:%.*]] = call @llvm.riscv.th.vmaqasu.nxv4i32.i8.nxv16i8.i64( [[ACC:%.*]], i8 [[OP1:%.*]], [[OP2:%.*]], i64 [[VL:%.*]], i64 0) +// CHECK-NEXT: ret [[TMP0]] +// +vint32m2_t test_th_vmaqasu_vx_i32m2(vint32m2_t acc, int8_t op1, vuint8m2_t op2, + size_t vl) { + return th_vmaqasu_vx_i32m2(acc, op1, op2, vl); +} + +// CHECK-LABEL: @test_th_vmaqasu_vv_i32m4( +// CHECK-NEXT: entry: +// CHECK-NEXT: [[TMP0:%.*]] = call @llvm.riscv.th.vmaqasu.nxv8i32.nxv32i8.nxv32i8.i64( [[ACC:%.*]], [[OP1:%.*]], [[OP2:%.*]], i64 [[VL:%.*]], i64 0) +// CHECK-NEXT: ret [[TMP0]] +// +vint32m4_t test_th_vmaqasu_vv_i32m4(vint32m4_t acc, vint8m4_t op1, vuint8m4_t op2, + size_t vl) { + return th_vmaqasu_vv_i32m4(acc, op1, op2, vl); +} + +// CHECK-LABEL: @test_th_vmaqasu_vx_i32m4( +// CHECK-NEXT: entry: +// CHECK-NEXT: [[TMP0:%.*]] = call @llvm.riscv.th.vmaqasu.nxv8i32.i8.nxv32i8.i64( [[ACC:%.*]], i8 [[OP1:%.*]], [[OP2:%.*]], i64 [[VL:%.*]], i64 0) +// CHECK-NEXT: ret [[TMP0]] +// +vint32m4_t test_th_vmaqasu_vx_i32m4(vint32m4_t acc, int8_t op1, vuint8m4_t op2, + size_t vl) { + return th_vmaqasu_vx_i32m4(acc, op1, op2, vl); +} + + +// CHECK-LABEL: @test_th_vmaqaus_vx_i32mf2( +// CHECK-NEXT: entry: +// CHECK-NEXT: [[TMP0:%.*]] = call @llvm.riscv.th.vmaqaus.nxv1i32.i8.nxv4i8.i64( [[ACC:%.*]], i8 [[OP1:%.*]], [[OP2:%.*]], i64 [[VL:%.*]], i64 0) +// CHECK-NEXT: ret [[TMP0]] +// +vint32mf2_t test_th_vmaqaus_vx_i32mf2(vint32mf2_t acc, uint8_t op1, vint8mf2_t op2, + size_t vl) { + return th_vmaqaus_vx_i32mf2(acc, op1, op2, vl); +} + +// CHECK-LABEL: @test_th_vmaqaus_vx_i32m1( +// CHECK-NEXT: entry: +// CHECK-NEXT: [[TMP0:%.*]] = call @llvm.riscv.th.vmaqaus.nxv2i32.i8.nxv8i8.i64( [[ACC:%.*]], i8 [[OP1:%.*]], [[OP2:%.*]], i64 [[VL:%.*]], i64 0) +// CHECK-NEXT: ret [[TMP0]] +// +vint32m1_t test_th_vmaqaus_vx_i32m1(vint32m1_t acc, uint8_t op1, vint8m1_t op2, + size_t vl) { + return th_vmaqaus_vx_i32m1(acc, op1, op2, vl); +} + +// CHECK-LABEL: @test_th_vmaqaus_vx_i32m2( +// CHECK-NEXT: entry: +// CHECK-NEXT: [[TMP0:%.*]] = call @llvm.riscv.th.vmaqaus.nxv4i32.i8.nxv16i8.i64( [[ACC:%.*]], i8 [[OP1:%.*]], [[OP2:%.*]], i64 [[VL:%.*]], i64 0) +// CHECK-NEXT: ret [[TMP0]] +// +vint32m2_t test_th_vmaqaus_vx_i32m2(vint32m2_t acc, uint8_t op1, vint8m2_t op2, + size_t vl) { + return th_vmaqaus_vx_i32m2(acc, op1, op2, vl); +} + +// CHECK-LABEL: @test_th_vmaqaus_vx_i32m4( +// CHECK-NEXT: entry: +// CHECK-NEXT: [[TMP0:%.*]] = call @llvm.riscv.th.vmaqaus.nxv8i32.i8.nxv32i8.i64( [[ACC:%.*]], i8 [[OP1:%.*]], [[OP2:%.*]], i64 [[VL:%.*]], i64 0) +// CHECK-NEXT: ret [[TMP0]] +// +vint32m4_t test_th_vmaqaus_vx_i32m4(vint32m4_t acc, uint8_t op1, vint8m4_t op2, + size_t vl) { + return th_vmaqaus_vx_i32m4(acc, op1, op2, vl); +} + + +// CHECK-LABEL: @test_th_vmaqa_vv_i32mf2_m( +// CHECK-NEXT: entry: +// CHECK-NEXT: [[TMP0:%.*]] = call @llvm.riscv.th.vmaqa.mask.nxv1i32.nxv4i8.nxv4i8.i64( [[ACC:%.*]], [[OP1:%.*]], [[OP2:%.*]], [[MASK:%.*]], i64 [[VL:%.*]], i64 0) +// CHECK-NEXT: ret [[TMP0]] +// +vint32mf2_t test_th_vmaqa_vv_i32mf2_m(vbool16_t mask, vint32mf2_t acc, + vint8mf2_t op1, vint8mf2_t op2, size_t vl) { + return th_vmaqa_vv_i32mf2_m(mask, acc, op1, op2, vl); +} + +// CHECK-LABEL: @test_th_vmaqa_vx_i32mf2_m( +// CHECK-NEXT: entry: +// CHECK-NEXT: [[TMP0:%.*]] = call @llvm.riscv.th.vmaqa.mask.nxv1i32.i8.nxv4i8.i64( [[ACC:%.*]], i8 [[OP1:%.*]], [[OP2:%.*]], [[MASK:%.*]], i64 [[VL:%.*]], i64 0) +// CHECK-NEXT: ret [[TMP0]] +// +vint32mf2_t test_th_vmaqa_vx_i32mf2_m(vbool16_t mask, vint32mf2_t acc, int8_t op1, + vint8mf2_t op2, size_t vl) { + return th_vmaqa_vx_i32mf2_m(mask, acc, op1, op2, vl); +} + +// CHECK-LABEL: @test_th_vmaqa_vv_i32m1_m( +// CHECK-NEXT: entry: +// CHECK-NEXT: [[TMP0:%.*]] = call @llvm.riscv.th.vmaqa.mask.nxv2i32.nxv8i8.nxv8i8.i64( [[ACC:%.*]], [[OP1:%.*]], [[OP2:%.*]], [[MASK:%.*]], i64 [[VL:%.*]], i64 0) +// CHECK-NEXT: ret [[TMP0]] +// +vint32m1_t test_th_vmaqa_vv_i32m1_m(vbool8_t mask, vint32m1_t acc, vint8m1_t op1, + vint8m1_t op2, size_t vl) { + return th_vmaqa_vv_i32m1_m(mask, acc, op1, op2, vl); +} + +// CHECK-LABEL: @test_th_vmaqa_vx_i32m1_m( +// CHECK-NEXT: entry: +// CHECK-NEXT: [[TMP0:%.*]] = call @llvm.riscv.th.vmaqa.mask.nxv2i32.i8.nxv8i8.i64( [[ACC:%.*]], i8 [[OP1:%.*]], [[OP2:%.*]], [[MASK:%.*]], i64 [[VL:%.*]], i64 0) +// CHECK-NEXT: ret [[TMP0]] +// +vint32m1_t test_th_vmaqa_vx_i32m1_m(vbool8_t mask, vint32m1_t acc, int8_t op1, + vint8m1_t op2, size_t vl) { + return th_vmaqa_vx_i32m1_m(mask, acc, op1, op2, vl); +} + +// CHECK-LABEL: @test_th_vmaqa_vv_i32m2_m( +// CHECK-NEXT: entry: +// CHECK-NEXT: [[TMP0:%.*]] = call @llvm.riscv.th.vmaqa.mask.nxv4i32.nxv16i8.nxv16i8.i64( [[ACC:%.*]], [[OP1:%.*]], [[OP2:%.*]], [[MASK:%.*]], i64 [[VL:%.*]], i64 0) +// CHECK-NEXT: ret [[TMP0]] +// +vint32m2_t test_th_vmaqa_vv_i32m2_m(vbool4_t mask, vint32m2_t acc, vint8m2_t op1, + vint8m2_t op2, size_t vl) { + return th_vmaqa_vv_i32m2_m(mask, acc, op1, op2, vl); +} + +// CHECK-LABEL: @test_th_vmaqa_vx_i32m2_m( +// CHECK-NEXT: entry: +// CHECK-NEXT: [[TMP0:%.*]] = call @llvm.riscv.th.vmaqa.mask.nxv4i32.i8.nxv16i8.i64( [[ACC:%.*]], i8 [[OP1:%.*]], [[OP2:%.*]], [[MASK:%.*]], i64 [[VL:%.*]], i64 0) +// CHECK-NEXT: ret [[TMP0]] +// +vint32m2_t test_th_vmaqa_vx_i32m2_m(vbool4_t mask, vint32m2_t acc, int8_t op1, + vint8m2_t op2, size_t vl) { + return th_vmaqa_vx_i32m2_m(mask, acc, op1, op2, vl); +} + +// CHECK-LABEL: @test_th_vmaqa_vv_i32m4_m( +// CHECK-NEXT: entry: +// CHECK-NEXT: [[TMP0:%.*]] = call @llvm.riscv.th.vmaqa.mask.nxv8i32.nxv32i8.nxv32i8.i64( [[ACC:%.*]], [[OP1:%.*]], [[OP2:%.*]], [[MASK:%.*]], i64 [[VL:%.*]], i64 0) +// CHECK-NEXT: ret [[TMP0]] +// +vint32m4_t test_th_vmaqa_vv_i32m4_m(vbool2_t mask, vint32m4_t acc, vint8m4_t op1, + vint8m4_t op2, size_t vl) { + return th_vmaqa_vv_i32m4_m(mask, acc, op1, op2, vl); +} + +// CHECK-LABEL: @test_th_vmaqa_vx_i32m4_m( +// CHECK-NEXT: entry: +// CHECK-NEXT: [[TMP0:%.*]] = call @llvm.riscv.th.vmaqa.mask.nxv8i32.i8.nxv32i8.i64( [[ACC:%.*]], i8 [[OP1:%.*]], [[OP2:%.*]], [[MASK:%.*]], i64 [[VL:%.*]], i64 0) +// CHECK-NEXT: ret [[TMP0]] +// +vint32m4_t test_th_vmaqa_vx_i32m4_m(vbool2_t mask, vint32m4_t acc, int8_t op1, + vint8m4_t op2, size_t vl) { + return th_vmaqa_vx_i32m4_m(mask, acc, op1, op2, vl); +} + + +// CHECK-LABEL: @test_th_vmaqau_vv_u32mf2_m( +// CHECK-NEXT: entry: +// CHECK-NEXT: [[TMP0:%.*]] = call @llvm.riscv.th.vmaqau.mask.nxv1i32.nxv4i8.nxv4i8.i64( [[ACC:%.*]], [[OP1:%.*]], [[OP2:%.*]], [[MASK:%.*]], i64 [[VL:%.*]], i64 0) +// CHECK-NEXT: ret [[TMP0]] +// +vuint32mf2_t test_th_vmaqau_vv_u32mf2_m(vbool16_t mask, vuint32mf2_t acc, + vuint8mf2_t op1, vuint8mf2_t op2, + size_t vl) { + return th_vmaqau_vv_u32mf2_m(mask, acc, op1, op2, vl); +} + +// CHECK-LABEL: @test_th_vmaqau_vx_u32mf2_m( +// CHECK-NEXT: entry: +// CHECK-NEXT: [[TMP0:%.*]] = call @llvm.riscv.th.vmaqau.mask.nxv1i32.i8.nxv4i8.i64( [[ACC:%.*]], i8 [[OP1:%.*]], [[OP2:%.*]], [[MASK:%.*]], i64 [[VL:%.*]], i64 0) +// CHECK-NEXT: ret [[TMP0]] +// +vuint32mf2_t test_th_vmaqau_vx_u32mf2_m(vbool16_t mask, vuint32mf2_t acc, + uint8_t op1, vuint8mf2_t op2, size_t vl) { + return th_vmaqau_vx_u32mf2_m(mask, acc, op1, op2, vl); +} + +// CHECK-LABEL: @test_th_vmaqau_vv_u32m1_m( +// CHECK-NEXT: entry: +// CHECK-NEXT: [[TMP0:%.*]] = call @llvm.riscv.th.vmaqau.mask.nxv2i32.nxv8i8.nxv8i8.i64( [[ACC:%.*]], [[OP1:%.*]], [[OP2:%.*]], [[MASK:%.*]], i64 [[VL:%.*]], i64 0) +// CHECK-NEXT: ret [[TMP0]] +// +vuint32m1_t test_th_vmaqau_vv_u32m1_m(vbool8_t mask, vuint32m1_t acc, + vuint8m1_t op1, vuint8m1_t op2, size_t vl) { + return th_vmaqau_vv_u32m1_m(mask, acc, op1, op2, vl); +} + +// CHECK-LABEL: @test_th_vmaqau_vx_u32m1_m( +// CHECK-NEXT: entry: +// CHECK-NEXT: [[TMP0:%.*]] = call @llvm.riscv.th.vmaqau.mask.nxv2i32.i8.nxv8i8.i64( [[ACC:%.*]], i8 [[OP1:%.*]], [[OP2:%.*]], [[MASK:%.*]], i64 [[VL:%.*]], i64 0) +// CHECK-NEXT: ret [[TMP0]] +// +vuint32m1_t test_th_vmaqau_vx_u32m1_m(vbool8_t mask, vuint32m1_t acc, uint8_t op1, + vuint8m1_t op2, size_t vl) { + return th_vmaqau_vx_u32m1_m(mask, acc, op1, op2, vl); +} + +// CHECK-LABEL: @test_th_vmaqau_vv_u32m2_m( +// CHECK-NEXT: entry: +// CHECK-NEXT: [[TMP0:%.*]] = call @llvm.riscv.th.vmaqau.mask.nxv4i32.nxv16i8.nxv16i8.i64( [[ACC:%.*]], [[OP1:%.*]], [[OP2:%.*]], [[MASK:%.*]], i64 [[VL:%.*]], i64 0) +// CHECK-NEXT: ret [[TMP0]] +// +vuint32m2_t test_th_vmaqau_vv_u32m2_m(vbool4_t mask, vuint32m2_t acc, + vuint8m2_t op1, vuint8m2_t op2, size_t vl) { + return th_vmaqau_vv_u32m2_m(mask, acc, op1, op2, vl); +} + +// CHECK-LABEL: @test_th_vmaqau_vx_u32m2_m( +// CHECK-NEXT: entry: +// CHECK-NEXT: [[TMP0:%.*]] = call @llvm.riscv.th.vmaqau.mask.nxv4i32.i8.nxv16i8.i64( [[ACC:%.*]], i8 [[OP1:%.*]], [[OP2:%.*]], [[MASK:%.*]], i64 [[VL:%.*]], i64 0) +// CHECK-NEXT: ret [[TMP0]] +// +vuint32m2_t test_th_vmaqau_vx_u32m2_m(vbool4_t mask, vuint32m2_t acc, uint8_t op1, + vuint8m2_t op2, size_t vl) { + return th_vmaqau_vx_u32m2_m(mask, acc, op1, op2, vl); +} + +// CHECK-LABEL: @test_th_vmaqau_vv_u32m4_m( +// CHECK-NEXT: entry: +// CHECK-NEXT: [[TMP0:%.*]] = call @llvm.riscv.th.vmaqau.mask.nxv8i32.nxv32i8.nxv32i8.i64( [[ACC:%.*]], [[OP1:%.*]], [[OP2:%.*]], [[MASK:%.*]], i64 [[VL:%.*]], i64 0) +// CHECK-NEXT: ret [[TMP0]] +// +vuint32m4_t test_th_vmaqau_vv_u32m4_m(vbool2_t mask, vuint32m4_t acc, + vuint8m4_t op1, vuint8m4_t op2, size_t vl) { + return th_vmaqau_vv_u32m4_m(mask, acc, op1, op2, vl); +} + +// CHECK-LABEL: @test_th_vmaqau_vx_u32m4_m( +// CHECK-NEXT: entry: +// CHECK-NEXT: [[TMP0:%.*]] = call @llvm.riscv.th.vmaqau.mask.nxv8i32.i8.nxv32i8.i64( [[ACC:%.*]], i8 [[OP1:%.*]], [[OP2:%.*]], [[MASK:%.*]], i64 [[VL:%.*]], i64 0) +// CHECK-NEXT: ret [[TMP0]] +// +vuint32m4_t test_th_vmaqau_vx_u32m4_m(vbool2_t mask, vuint32m4_t acc, uint8_t op1, + vuint8m4_t op2, size_t vl) { + return th_vmaqau_vx_u32m4_m(mask, acc, op1, op2, vl); +} + + +// CHECK-LABEL: @test_th_vmaqasu_vv_i32mf2_m( +// CHECK-NEXT: entry: +// CHECK-NEXT: [[TMP0:%.*]] = call @llvm.riscv.th.vmaqasu.mask.nxv1i32.nxv4i8.nxv4i8.i64( [[ACC:%.*]], [[OP1:%.*]], [[OP2:%.*]], [[MASK:%.*]], i64 [[VL:%.*]], i64 0) +// CHECK-NEXT: ret [[TMP0]] +// +vint32mf2_t test_th_vmaqasu_vv_i32mf2_m(vbool16_t mask, vint32mf2_t acc, + vint8mf2_t op1, vuint8mf2_t op2, + size_t vl) { + return th_vmaqasu_vv_i32mf2_m(mask, acc, op1, op2, vl); +} + +// CHECK-LABEL: @test_th_vmaqasu_vx_i32mf2_m( +// CHECK-NEXT: entry: +// CHECK-NEXT: [[TMP0:%.*]] = call @llvm.riscv.th.vmaqasu.mask.nxv1i32.i8.nxv4i8.i64( [[ACC:%.*]], i8 [[OP1:%.*]], [[OP2:%.*]], [[MASK:%.*]], i64 [[VL:%.*]], i64 0) +// CHECK-NEXT: ret [[TMP0]] +// +vint32mf2_t test_th_vmaqasu_vx_i32mf2_m(vbool16_t mask, vint32mf2_t acc, int8_t op1, + vuint8mf2_t op2, size_t vl) { + return th_vmaqasu_vx_i32mf2_m(mask, acc, op1, op2, vl); +} + +// CHECK-LABEL: @test_th_vmaqasu_vv_i32m1_m( +// CHECK-NEXT: entry: +// CHECK-NEXT: [[TMP0:%.*]] = call @llvm.riscv.th.vmaqasu.mask.nxv2i32.nxv8i8.nxv8i8.i64( [[ACC:%.*]], [[OP1:%.*]], [[OP2:%.*]], [[MASK:%.*]], i64 [[VL:%.*]], i64 0) +// CHECK-NEXT: ret [[TMP0]] +// +vint32m1_t test_th_vmaqasu_vv_i32m1_m(vbool8_t mask, vint32m1_t acc, + vint8m1_t op1, vuint8m1_t op2, size_t vl) { + return th_vmaqasu_vv_i32m1_m(mask, acc, op1, op2, vl); +} + +// CHECK-LABEL: @test_th_vmaqasu_vx_i32m1_m( +// CHECK-NEXT: entry: +// CHECK-NEXT: [[TMP0:%.*]] = call @llvm.riscv.th.vmaqasu.mask.nxv2i32.i8.nxv8i8.i64( [[ACC:%.*]], i8 [[OP1:%.*]], [[OP2:%.*]], [[MASK:%.*]], i64 [[VL:%.*]], i64 0) +// CHECK-NEXT: ret [[TMP0]] +// +vint32m1_t test_th_vmaqasu_vx_i32m1_m(vbool8_t mask, vint32m1_t acc, int8_t op1, + vuint8m1_t op2, size_t vl) { + return th_vmaqasu_vx_i32m1_m(mask, acc, op1, op2, vl); +} + +// CHECK-LABEL: @test_th_vmaqasu_vv_i32m2_m( +// CHECK-NEXT: entry: +// CHECK-NEXT: [[TMP0:%.*]] = call @llvm.riscv.th.vmaqasu.mask.nxv4i32.nxv16i8.nxv16i8.i64( [[ACC:%.*]], [[OP1:%.*]], [[OP2:%.*]], [[MASK:%.*]], i64 [[VL:%.*]], i64 0) +// CHECK-NEXT: ret [[TMP0]] +// +vint32m2_t test_th_vmaqasu_vv_i32m2_m(vbool4_t mask, vint32m2_t acc, + vint8m2_t op1, vuint8m2_t op2, size_t vl) { + return th_vmaqasu_vv_i32m2_m(mask, acc, op1, op2, vl); +} + +// CHECK-LABEL: @test_th_vmaqasu_vx_i32m2_m( +// CHECK-NEXT: entry: +// CHECK-NEXT: [[TMP0:%.*]] = call @llvm.riscv.th.vmaqasu.mask.nxv4i32.i8.nxv16i8.i64( [[ACC:%.*]], i8 [[OP1:%.*]], [[OP2:%.*]], [[MASK:%.*]], i64 [[VL:%.*]], i64 0) +// CHECK-NEXT: ret [[TMP0]] +// +vint32m2_t test_th_vmaqasu_vx_i32m2_m(vbool4_t mask, vint32m2_t acc, int8_t op1, + vuint8m2_t op2, size_t vl) { + return th_vmaqasu_vx_i32m2_m(mask, acc, op1, op2, vl); +} + +// CHECK-LABEL: @test_th_vmaqasu_vv_i32m4_m( +// CHECK-NEXT: entry: +// CHECK-NEXT: [[TMP0:%.*]] = call @llvm.riscv.th.vmaqasu.mask.nxv8i32.nxv32i8.nxv32i8.i64( [[ACC:%.*]], [[OP1:%.*]], [[OP2:%.*]], [[MASK:%.*]], i64 [[VL:%.*]], i64 0) +// CHECK-NEXT: ret [[TMP0]] +// +vint32m4_t test_th_vmaqasu_vv_i32m4_m(vbool2_t mask, vint32m4_t acc, + vint8m4_t op1, vuint8m4_t op2, size_t vl) { + return th_vmaqasu_vv_i32m4_m(mask, acc, op1, op2, vl); +} + +// CHECK-LABEL: @test_th_vmaqasu_vx_i32m4_m( +// CHECK-NEXT: entry: +// CHECK-NEXT: [[TMP0:%.*]] = call @llvm.riscv.th.vmaqasu.mask.nxv8i32.i8.nxv32i8.i64( [[ACC:%.*]], i8 [[OP1:%.*]], [[OP2:%.*]], [[MASK:%.*]], i64 [[VL:%.*]], i64 0) +// CHECK-NEXT: ret [[TMP0]] +// +vint32m4_t test_th_vmaqasu_vx_i32m4_m(vbool2_t mask, vint32m4_t acc, int8_t op1, + vuint8m4_t op2, size_t vl) { + return th_vmaqasu_vx_i32m4_m(mask, acc, op1, op2, vl); +} + + +// CHECK-LABEL: @test_th_vmaqaus_vx_i32mf2_m( +// CHECK-NEXT: entry: +// CHECK-NEXT: [[TMP0:%.*]] = call @llvm.riscv.th.vmaqaus.mask.nxv1i32.i8.nxv4i8.i64( [[ACC:%.*]], i8 [[OP1:%.*]], [[OP2:%.*]], [[MASK:%.*]], i64 [[VL:%.*]], i64 0) +// CHECK-NEXT: ret [[TMP0]] +// +vint32mf2_t test_th_vmaqaus_vx_i32mf2_m(vbool16_t mask, vint32mf2_t acc, uint8_t op1, + vint8mf2_t op2, size_t vl) { + return th_vmaqaus_vx_i32mf2_m(mask, acc, op1, op2, vl); +} + +// CHECK-LABEL: @test_th_vmaqaus_vx_i32m1_m( +// CHECK-NEXT: entry: +// CHECK-NEXT: [[TMP0:%.*]] = call @llvm.riscv.th.vmaqaus.mask.nxv2i32.i8.nxv8i8.i64( [[ACC:%.*]], i8 [[OP1:%.*]], [[OP2:%.*]], [[MASK:%.*]], i64 [[VL:%.*]], i64 0) +// CHECK-NEXT: ret [[TMP0]] +// +vint32m1_t test_th_vmaqaus_vx_i32m1_m(vbool8_t mask, vint32m1_t acc, uint8_t op1, + vint8m1_t op2, size_t vl) { + return th_vmaqaus_vx_i32m1_m(mask, acc, op1, op2, vl); +} + +// CHECK-LABEL: @test_th_vmaqaus_vx_i32m2_m( +// CHECK-NEXT: entry: +// CHECK-NEXT: [[TMP0:%.*]] = call @llvm.riscv.th.vmaqaus.mask.nxv4i32.i8.nxv16i8.i64( [[ACC:%.*]], i8 [[OP1:%.*]], [[OP2:%.*]], [[MASK:%.*]], i64 [[VL:%.*]], i64 0) +// CHECK-NEXT: ret [[TMP0]] +// +vint32m2_t test_th_vmaqaus_vx_i32m2_m(vbool4_t mask, vint32m2_t acc, uint8_t op1, + vint8m2_t op2, size_t vl) { + return th_vmaqaus_vx_i32m2_m(mask, acc, op1, op2, vl); +} + +// CHECK-LABEL: @test_th_vmaqaus_vx_i32m4_m( +// CHECK-NEXT: entry: +// CHECK-NEXT: [[TMP0:%.*]] = call @llvm.riscv.th.vmaqaus.mask.nxv8i32.i8.nxv32i8.i64( [[ACC:%.*]], i8 [[OP1:%.*]], [[OP2:%.*]], [[MASK:%.*]], i64 [[VL:%.*]], i64 0) +// CHECK-NEXT: ret [[TMP0]] +// +vint32m4_t test_th_vmaqaus_vx_i32m4_m(vbool2_t mask, vint32m4_t acc, uint8_t op1, + vint8m4_t op2, size_t vl) { + return th_vmaqaus_vx_i32m4_m(mask, acc, op1, op2, vl); +} Index: clang/test/Preprocessor/riscv-target-thead-features.c =================================================================== --- /dev/null +++ clang/test/Preprocessor/riscv-target-thead-features.c @@ -0,0 +1,3 @@ +// RUN: %clang -target riscv64 -march=rv64ixtheadvdot -x c -E -dM %s \ +// RUN: -o - | FileCheck --check-prefix=CHECK-XTHEADVDOT-EXT %s +// CHECK-XTHEADVDOT-EXT: __riscv_xtheadvdot 1000000{{$}} Index: llvm/include/llvm/IR/IntrinsicsRISCV.td =================================================================== --- llvm/include/llvm/IR/IntrinsicsRISCV.td +++ llvm/include/llvm/IR/IntrinsicsRISCV.td @@ -1582,3 +1582,8 @@ def int_riscv_sm3p0 : ScalarCryptoGprIntrinsicAny; def int_riscv_sm3p1 : ScalarCryptoGprIntrinsicAny; } // TargetPrefix = "riscv" + +//===----------------------------------------------------------------------===// +// Vendor extensions +//===----------------------------------------------------------------------===// +include "llvm/IR/IntrinsicsRISCV_THEAD.td" Index: llvm/include/llvm/IR/IntrinsicsRISCV_THEAD.td =================================================================== --- /dev/null +++ llvm/include/llvm/IR/IntrinsicsRISCV_THEAD.td @@ -0,0 +1,22 @@ +let TargetPrefix = "riscv" in { + + class TH_VdotTernaryWideMasked + : Intrinsic< [llvm_anyvector_ty], + [LLVMMatchType<0>, llvm_any_ty, llvm_anyvector_ty, + LLVMScalarOrSameVectorWidth<2, llvm_i1_ty>, + llvm_anyint_ty, LLVMMatchType<3>], + [ImmArg>, IntrNoMem]>, RISCVVIntrinsic { + let ScalarOperand = 1; + let VLOperand = 4; + } + + multiclass TH_VdotTernaryWide { + def "int_riscv_" # NAME : RISCVTernaryWideUnMasked; + def "int_riscv_" # NAME # "_mask" : TH_VdotTernaryWideMasked; + } + + defm th_vmaqa : TH_VdotTernaryWide; + defm th_vmaqau : TH_VdotTernaryWide; + defm th_vmaqasu : TH_VdotTernaryWide; + defm th_vmaqaus : TH_VdotTernaryWide; +} Index: llvm/lib/Support/RISCVISAInfo.cpp =================================================================== --- llvm/lib/Support/RISCVISAInfo.cpp +++ llvm/lib/Support/RISCVISAInfo.cpp @@ -105,6 +105,7 @@ {"svnapot", RISCVExtensionVersion{1, 0}}, {"svinval", RISCVExtensionVersion{1, 0}}, {"xventanacondops", RISCVExtensionVersion{1, 0}}, + {"xtheadvdot", RISCVExtensionVersion{1, 0}}, }; static const RISCVSupportedExtension SupportedExperimentalExtensions[] = { Index: llvm/lib/Target/RISCV/CMakeLists.txt =================================================================== --- llvm/lib/Target/RISCV/CMakeLists.txt +++ llvm/lib/Target/RISCV/CMakeLists.txt @@ -70,3 +70,5 @@ add_subdirectory(MCTargetDesc) add_subdirectory(MCA) add_subdirectory(TargetInfo) + +add_subdirectory(Vendor) Index: llvm/lib/Target/RISCV/RISCV.td =================================================================== --- llvm/lib/Target/RISCV/RISCV.td +++ llvm/lib/Target/RISCV/RISCV.td @@ -525,6 +525,11 @@ def HasAtomicLdSt : Predicate<"Subtarget->hasStdExtA() || Subtarget->hasForcedAtomics()">; +//===----------------------------------------------------------------------===// +// RISC-V vendor subtarget features and instruction predicates. +//===----------------------------------------------------------------------===// +include "Vendor/THEAD/THEAD.td" + //===----------------------------------------------------------------------===// // Named operands for CSR instructions. //===----------------------------------------------------------------------===// Index: llvm/lib/Target/RISCV/RISCVInstrInfoV.td =================================================================== --- llvm/lib/Target/RISCV/RISCVInstrInfoV.td +++ llvm/lib/Target/RISCV/RISCVInstrInfoV.td @@ -1767,4 +1767,6 @@ } } // Predicates = [HasVInstructionsI64, IsRV64] +include "Vendor/THEAD/THEADInstrInfoV.td" include "RISCVInstrInfoVPseudos.td" +include "Vendor/THEAD/THEADInstrInfoVPseudo.td" Index: llvm/lib/Target/RISCV/RISCVSubtarget.h =================================================================== --- llvm/lib/Target/RISCV/RISCVSubtarget.h +++ llvm/lib/Target/RISCV/RISCVSubtarget.h @@ -33,6 +33,8 @@ class StringRef; class RISCVSubtarget : public RISCVGenSubtargetInfo { +#include "Vendor/THEAD/THEADSubtarget.h" + public: enum RISCVProcFamilyEnum : uint8_t { Others, Index: llvm/lib/Target/RISCV/Vendor/CMakeLists.txt =================================================================== --- /dev/null +++ llvm/lib/Target/RISCV/Vendor/CMakeLists.txt @@ -0,0 +1 @@ +add_subdirectory(THEAD) Index: llvm/lib/Target/RISCV/Vendor/THEAD/THEAD.td =================================================================== --- /dev/null +++ llvm/lib/Target/RISCV/Vendor/THEAD/THEAD.td @@ -0,0 +1,6 @@ +def FeatureTHeadVdot + : SubtargetFeature<"xtheadvdot", "HasTHeadVdot", "true", + "'xtheadvdot' (THEAD Vector Extensions for Dot)">; +def HasTHeadVdot : Predicate<"Subtarget->hasTHeadVdot()">, + AssemblerPredicate<(all_of FeatureTHeadVdot), + "'xtheadvdot' (THEAD Vector Extensions for Dot)">; Index: llvm/lib/Target/RISCV/Vendor/THEAD/THEADInstrInfoV.td =================================================================== --- /dev/null +++ llvm/lib/Target/RISCV/Vendor/THEAD/THEADInstrInfoV.td @@ -0,0 +1,57 @@ +//===----------------------------------------------------------------------===// +// Instruction class templates +//===----------------------------------------------------------------------===// +class THInstVdotVV funct6, RISCVVFormat opv, dag outs, dag ins, + string opcodestr, string argstr> + : RVInstVV { + let Inst{26} = 0; + let Opcode = OPC_CUSTOM_0.Value; +} + +class THInstVdotVX funct6, RISCVVFormat opv, dag outs, dag ins, + string opcodestr, string argstr> + : RVInstVX { + let Inst{26} = 1; + let Opcode = OPC_CUSTOM_0.Value; +} + +let hasSideEffects = 0, mayLoad = 0, mayStore = 0 in { +// op vd, vs1, vs2, vm (reverse the order of vs1 and vs2) +class THVdotALUrVV funct6, RISCVVFormat opv, string opcodestr> + : THInstVdotVV; + +// op vd, rs1, vs2, vm (reverse the order of rs1 and vs2) +class THVdotALUrVX funct6, RISCVVFormat opv, string opcodestr> + : THInstVdotVX; +} // hasSideEffects = 0, mayLoad = 0, mayStore = 0 + +//===----------------------------------------------------------------------===// +// Combination of instruction classes. +// Use these multiclasses to define instructions more easily. +//===----------------------------------------------------------------------===// +multiclass THVdotVMAQA_VX funct6> { + def _VX : THVdotALUrVX; +} + +multiclass THVdotVMAQA funct6> { + def _VV : THVdotALUrVV; + defm "" : THVdotVMAQA_VX; +} + +//===----------------------------------------------------------------------===// +// Instructions +//===----------------------------------------------------------------------===// +let Predicates = [HasTHeadVdot] in { +let Constraints = "@earlyclobber $vd" in { +let RVVConstraint = WidenV in { +defm THVdotVMAQA : THVdotVMAQA<"th.vmaqa", 0b100000>; +defm THVdotVMAQAU : THVdotVMAQA<"th.vmaqau", 0b100010>; +defm THVdotVMAQASU : THVdotVMAQA<"th.vmaqasu", 0b100100>; +defm THVdotVMAQAUS : THVdotVMAQA_VX<"th.vmaqaus",0b100110>; +} // RVVConstraint = WidenV +} // Constraints = "@earlyclobber $vd" +} // Predicates = [HasTHeadVdot] Index: llvm/lib/Target/RISCV/Vendor/THEAD/THEADInstrInfoVPseudo.td =================================================================== --- /dev/null +++ llvm/lib/Target/RISCV/Vendor/THEAD/THEADInstrInfoVPseudo.td @@ -0,0 +1,77 @@ +// Associate LMUL with tablegen records of register classes. +def THVdotV_M1 : LMULInfo<0b000, 8, VR, VR, VR, VR, VR, "M1">; +def THVdotV_M2 : LMULInfo<0b001, 16, VRM2, VRM2, VR, VR, VR, "M2">; +def THVdotV_M4 : LMULInfo<0b010, 32, VRM4, VRM4, VRM2, VR, VR, "M4">; +def THVdotV_M8 : LMULInfo<0b011, 64, VRM8, VRM8, VRM4, VRM2, VR, "M8">; + +defvar MxListTHVdot = [V_MF2, THVdotV_M1, THVdotV_M2, THVdotV_M4, THVdotV_M8]; + +defset list AllQuadenableInt8NoVLMulVectors = { + def : VTypeInfoToWide; + def : VTypeInfoToWide; + def : VTypeInfoToWide; + def : VTypeInfoToWide; + def : VTypeInfoToWide; +} + +//===----------------------------------------------------------------------===// +// Combination of instruction classes. +// Use these multiclasses to define instructions more easily. +//===----------------------------------------------------------------------===// +multiclass VPseudoVMAQA_VV_VX { + foreach m = MxListTHVdot in { + defm "" : VPseudoTernaryW_VV; + defm "" : VPseudoTernaryW_VX; + } +} + +multiclass VPseudoVMAQA_VX { + foreach m = MxListTHVdot in { + defm "" : VPseudoTernaryW_VX; + } +} + +multiclass VPatTernaryVMAQA_VV vtilist> { + foreach vtiToWti = vtilist in { + defvar vti = vtiToWti.Vti; + defvar wti = vtiToWti.Wti; + defm : VPatTernaryWithPolicy; + } +} + +multiclass VPatTernaryVMAQA_VX vtilist> { + foreach vtiToWti = vtilist in { + defvar vti = vtiToWti.Vti; + defvar wti = vtiToWti.Wti; + defm : VPatTernaryWithPolicy; + } +} + +multiclass VPatTernaryVMAQA_VV_VX vtilist> + : VPatTernaryVMAQA_VV, + VPatTernaryVMAQA_VX; + +//===----------------------------------------------------------------------===// +// Pseudo-instructions and codegen patterns +//===----------------------------------------------------------------------===// +defm PseudoTHVdotVMAQA : VPseudoVMAQA_VV_VX; +defm PseudoTHVdotVMAQAU : VPseudoVMAQA_VV_VX; +defm PseudoTHVdotVMAQASU : VPseudoVMAQA_VV_VX; +defm PseudoTHVdotVMAQAUS : VPseudoVMAQA_VX; + +let Predicates = [HasTHeadVdot] in { +defm : VPatTernaryVMAQA_VV_VX<"int_riscv_th_vmaqa", "PseudoTHVdotVMAQA", AllQuadenableInt8NoVLMulVectors>; +defm : VPatTernaryVMAQA_VV_VX<"int_riscv_th_vmaqau", "PseudoTHVdotVMAQAU", AllQuadenableInt8NoVLMulVectors>; +defm : VPatTernaryVMAQA_VV_VX<"int_riscv_th_vmaqasu","PseudoTHVdotVMAQASU",AllQuadenableInt8NoVLMulVectors>; +defm : VPatTernaryVMAQA_VX<"int_riscv_th_vmaqaus", "PseudoTHVdotVMAQAUS",AllQuadenableInt8NoVLMulVectors>; +} Index: llvm/lib/Target/RISCV/Vendor/THEAD/THEADSubtarget.h =================================================================== --- /dev/null +++ llvm/lib/Target/RISCV/Vendor/THEAD/THEADSubtarget.h @@ -0,0 +1,5 @@ +private: + bool HasTHeadVdot = false; + +public: + bool hasTHeadVdot() const { return HasTHeadVdot; } Index: llvm/test/CodeGen/RISCV/Vendor/THEAD/attributes.ll =================================================================== --- /dev/null +++ llvm/test/CodeGen/RISCV/Vendor/THEAD/attributes.ll @@ -0,0 +1,10 @@ +;; Generate ELF attributes from llc. + +; RUN: llc -mtriple=riscv64 -mattr=+xtheadvdot %s -o - | FileCheck --check-prefix=RV64XTHEADVDOT %s + +; RV64XTHEADVDOT: .attribute 5, "rv64i2p0_xtheadvdot1p0" + +define i32 @addi(i32 %a) { + %1 = add i32 %a, 1 + ret i32 %1 +} Index: llvm/test/CodeGen/RISCV/Vendor/THEAD/vdot/vmaqa.ll =================================================================== --- /dev/null +++ llvm/test/CodeGen/RISCV/Vendor/THEAD/vdot/vmaqa.ll @@ -0,0 +1,381 @@ +; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py +; RUN: sed 's/iXLen/i32/g' %s | llc -mtriple=riscv32 -mattr=+v,+xtheadvdot \ +; RUN: -verify-machineinstrs | FileCheck %s +; RUN: sed 's/iXLen/i64/g' %s | llc -mtriple=riscv64 -mattr=+v,+xtheadvdot \ +; RUN: -verify-machineinstrs | FileCheck %s +declare @llvm.riscv.th.vmaqa.nxv1i32.nxv4i8( + , + , + , + iXLen, + iXLen); + +define @intrinsic_th_vmaqa_vv_nxv1i32_nxv4i8_nxv4i8( %0, %1, %2, iXLen %3) nounwind { +; CHECK-LABEL: intrinsic_th_vmaqa_vv_nxv1i32_nxv4i8_nxv4i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli zero, a0, e32, mf2, tu, ma +; CHECK-NEXT: th.vmaqa.vv v8, v9, v10 +; CHECK-NEXT: ret +entry: + %a = call @llvm.riscv.th.vmaqa.nxv1i32.nxv4i8( + %0, + %1, + %2, + iXLen %3, iXLen 0) + + ret %a +} + +declare @llvm.riscv.th.vmaqa.mask.nxv1i32.nxv4i8( + , + , + , + , + iXLen, iXLen); + +define @intrinsic_th_vmaqa_mask_vv_nxv1i32_nxv4i8_nxv4i8( %0, %1, %2, %3, iXLen %4) nounwind { +; CHECK-LABEL: intrinsic_th_vmaqa_mask_vv_nxv1i32_nxv4i8_nxv4i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli zero, a0, e32, mf2, tu, mu +; CHECK-NEXT: th.vmaqa.vv v8, v9, v10, v0.t +; CHECK-NEXT: ret +entry: + %a = call @llvm.riscv.th.vmaqa.mask.nxv1i32.nxv4i8( + %0, + %1, + %2, + %3, + iXLen %4, iXLen 0) + + ret %a +} + +declare @llvm.riscv.th.vmaqa.nxv2i32.nxv8i8( + , + , + , + iXLen, + iXLen); + +define @intrinsic_th_vmaqa_vv_nxv2i32_nxv8i8_nxv8i8( %0, %1, %2, iXLen %3) nounwind { +; CHECK-LABEL: intrinsic_th_vmaqa_vv_nxv2i32_nxv8i8_nxv8i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli zero, a0, e32, m1, tu, ma +; CHECK-NEXT: th.vmaqa.vv v8, v9, v10 +; CHECK-NEXT: ret +entry: + %a = call @llvm.riscv.th.vmaqa.nxv2i32.nxv8i8( + %0, + %1, + %2, + iXLen %3, iXLen 0) + + ret %a +} + +declare @llvm.riscv.th.vmaqa.mask.nxv2i32.nxv8i8( + , + , + , + , + iXLen, iXLen); + +define @intrinsic_th_vmaqa_mask_vv_nxv2i32_nxv8i8_nxv8i8( %0, %1, %2, %3, iXLen %4) nounwind { +; CHECK-LABEL: intrinsic_th_vmaqa_mask_vv_nxv2i32_nxv8i8_nxv8i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli zero, a0, e32, m1, tu, mu +; CHECK-NEXT: th.vmaqa.vv v8, v9, v10, v0.t +; CHECK-NEXT: ret +entry: + %a = call @llvm.riscv.th.vmaqa.mask.nxv2i32.nxv8i8( + %0, + %1, + %2, + %3, + iXLen %4, iXLen 0) + + ret %a +} + +declare @llvm.riscv.th.vmaqa.nxv4i32.nxv16i8( + , + , + , + iXLen, + iXLen); + +define @intrinsic_th_vmaqa_vv_nxv4i32_nxv16i8_nxv16i8( %0, %1, %2, iXLen %3) nounwind { +; CHECK-LABEL: intrinsic_th_vmaqa_vv_nxv4i32_nxv16i8_nxv16i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli zero, a0, e32, m2, tu, ma +; CHECK-NEXT: th.vmaqa.vv v8, v10, v12 +; CHECK-NEXT: ret +entry: + %a = call @llvm.riscv.th.vmaqa.nxv4i32.nxv16i8( + %0, + %1, + %2, + iXLen %3, iXLen 0) + + ret %a +} + +declare @llvm.riscv.th.vmaqa.mask.nxv4i32.nxv16i8( + , + , + , + , + iXLen, iXLen); + +define @intrinsic_th_vmaqa_mask_vv_nxv4i32_nxv16i8_nxv16i8( %0, %1, %2, %3, iXLen %4) nounwind { +; CHECK-LABEL: intrinsic_th_vmaqa_mask_vv_nxv4i32_nxv16i8_nxv16i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli zero, a0, e32, m2, tu, mu +; CHECK-NEXT: th.vmaqa.vv v8, v10, v12, v0.t +; CHECK-NEXT: ret +entry: + %a = call @llvm.riscv.th.vmaqa.mask.nxv4i32.nxv16i8( + %0, + %1, + %2, + %3, + iXLen %4, iXLen 0) + + ret %a +} + +declare @llvm.riscv.th.vmaqa.nxv8i32.nxv32i8( + , + , + , + iXLen, + iXLen); + +define @intrinsic_th_vmaqa_vv_nxv8i32_nxv32i8_nxv32i8( %0, %1, %2, iXLen %3) nounwind { +; CHECK-LABEL: intrinsic_th_vmaqa_vv_nxv8i32_nxv32i8_nxv32i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli zero, a0, e32, m4, tu, ma +; CHECK-NEXT: th.vmaqa.vv v8, v12, v16 +; CHECK-NEXT: ret +entry: + %a = call @llvm.riscv.th.vmaqa.nxv8i32.nxv32i8( + %0, + %1, + %2, + iXLen %3, iXLen 0) + + ret %a +} + +declare @llvm.riscv.th.vmaqa.mask.nxv8i32.nxv32i8( + , + , + , + , + iXLen, iXLen); + +define @intrinsic_th_vmaqa_mask_vv_nxv8i32_nxv32i8_nxv32i8( %0, %1, %2, %3, iXLen %4) nounwind { +; CHECK-LABEL: intrinsic_th_vmaqa_mask_vv_nxv8i32_nxv32i8_nxv32i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli zero, a0, e32, m4, tu, mu +; CHECK-NEXT: th.vmaqa.vv v8, v12, v16, v0.t +; CHECK-NEXT: ret +entry: + %a = call @llvm.riscv.th.vmaqa.mask.nxv8i32.nxv32i8( + %0, + %1, + %2, + %3, + iXLen %4, iXLen 0) + + ret %a +} + + +declare @llvm.riscv.th.vmaqa.nxv1i32.i8( + , + i8, + , + iXLen, + iXLen); + +define @intrinsic_th_vmaqa_vx_nxv1i32_i8_nxv4i8( %0, i8 %1, %2, iXLen %3) nounwind { +; CHECK-LABEL: intrinsic_th_vmaqa_vx_nxv1i32_i8_nxv4i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli zero, a1, e32, mf2, tu, ma +; CHECK-NEXT: th.vmaqa.vx v8, a0, v9 +; CHECK-NEXT: ret +entry: + %a = call @llvm.riscv.th.vmaqa.nxv1i32.i8( + %0, + i8 %1, + %2, + iXLen %3, iXLen 0) + + ret %a +} + +declare @llvm.riscv.th.vmaqa.mask.nxv1i32.i8( + , + i8, + , + , + iXLen, iXLen); + +define @intrinsic_th_vmaqa_mask_vx_nxv1i32_i8_nxv4i8( %0, i8 %1, %2, %3, iXLen %4) nounwind { +; CHECK-LABEL: intrinsic_th_vmaqa_mask_vx_nxv1i32_i8_nxv4i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli zero, a1, e32, mf2, tu, mu +; CHECK-NEXT: th.vmaqa.vx v8, a0, v9, v0.t +; CHECK-NEXT: ret +entry: + %a = call @llvm.riscv.th.vmaqa.mask.nxv1i32.i8( + %0, + i8 %1, + %2, + %3, + iXLen %4, iXLen 0) + + ret %a +} + +declare @llvm.riscv.th.vmaqa.nxv2i32.i8( + , + i8, + , + iXLen, + iXLen); + +define @intrinsic_th_vmaqa_vx_nxv2i32_i8_nxv8i8( %0, i8 %1, %2, iXLen %3) nounwind { +; CHECK-LABEL: intrinsic_th_vmaqa_vx_nxv2i32_i8_nxv8i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli zero, a1, e32, m1, tu, ma +; CHECK-NEXT: th.vmaqa.vx v8, a0, v9 +; CHECK-NEXT: ret +entry: + %a = call @llvm.riscv.th.vmaqa.nxv2i32.i8( + %0, + i8 %1, + %2, + iXLen %3, iXLen 0) + + ret %a +} + +declare @llvm.riscv.th.vmaqa.mask.nxv2i32.i8( + , + i8, + , + , + iXLen, iXLen); + +define @intrinsic_th_vmaqa_mask_vx_nxv2i32_i8_nxv8i8( %0, i8 %1, %2, %3, iXLen %4) nounwind { +; CHECK-LABEL: intrinsic_th_vmaqa_mask_vx_nxv2i32_i8_nxv8i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli zero, a1, e32, m1, tu, mu +; CHECK-NEXT: th.vmaqa.vx v8, a0, v9, v0.t +; CHECK-NEXT: ret +entry: + %a = call @llvm.riscv.th.vmaqa.mask.nxv2i32.i8( + %0, + i8 %1, + %2, + %3, + iXLen %4, iXLen 0) + + ret %a +} + +declare @llvm.riscv.th.vmaqa.nxv4i32.i8( + , + i8, + , + iXLen, + iXLen); + +define @intrinsic_th_vmaqa_vx_nxv4i32_i8_nxv16i8( %0, i8 %1, %2, iXLen %3) nounwind { +; CHECK-LABEL: intrinsic_th_vmaqa_vx_nxv4i32_i8_nxv16i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli zero, a1, e32, m2, tu, ma +; CHECK-NEXT: th.vmaqa.vx v8, a0, v10 +; CHECK-NEXT: ret +entry: + %a = call @llvm.riscv.th.vmaqa.nxv4i32.i8( + %0, + i8 %1, + %2, + iXLen %3, iXLen 0) + + ret %a +} + +declare @llvm.riscv.th.vmaqa.mask.nxv4i32.i8( + , + i8, + , + , + iXLen, iXLen); + +define @intrinsic_th_vmaqa_mask_vx_nxv4i32_i8_nxv16i8( %0, i8 %1, %2, %3, iXLen %4) nounwind { +; CHECK-LABEL: intrinsic_th_vmaqa_mask_vx_nxv4i32_i8_nxv16i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli zero, a1, e32, m2, tu, mu +; CHECK-NEXT: th.vmaqa.vx v8, a0, v10, v0.t +; CHECK-NEXT: ret +entry: + %a = call @llvm.riscv.th.vmaqa.mask.nxv4i32.i8( + %0, + i8 %1, + %2, + %3, + iXLen %4, iXLen 0) + + ret %a +} + +declare @llvm.riscv.th.vmaqa.nxv8i32.i8( + , + i8, + , + iXLen, + iXLen); + +define @intrinsic_th_vmaqa_vx_nxv8i32_i8_nxv32i8( %0, i8 %1, %2, iXLen %3) nounwind { +; CHECK-LABEL: intrinsic_th_vmaqa_vx_nxv8i32_i8_nxv32i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli zero, a1, e32, m4, tu, ma +; CHECK-NEXT: th.vmaqa.vx v8, a0, v12 +; CHECK-NEXT: ret +entry: + %a = call @llvm.riscv.th.vmaqa.nxv8i32.i8( + %0, + i8 %1, + %2, + iXLen %3, iXLen 0) + + ret %a +} + +declare @llvm.riscv.th.vmaqa.mask.nxv8i32.i8( + , + i8, + , + , + iXLen, iXLen); + +define @intrinsic_th_vmaqa_mask_vx_nxv8i32_i8_nxv32i8( %0, i8 %1, %2, %3, iXLen %4) nounwind { +; CHECK-LABEL: intrinsic_th_vmaqa_mask_vx_nxv8i32_i8_nxv32i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli zero, a1, e32, m4, tu, mu +; CHECK-NEXT: th.vmaqa.vx v8, a0, v12, v0.t +; CHECK-NEXT: ret +entry: + %a = call @llvm.riscv.th.vmaqa.mask.nxv8i32.i8( + %0, + i8 %1, + %2, + %3, + iXLen %4, iXLen 0) + + ret %a +} Index: llvm/test/CodeGen/RISCV/Vendor/THEAD/vdot/vmaqasu.ll =================================================================== --- /dev/null +++ llvm/test/CodeGen/RISCV/Vendor/THEAD/vdot/vmaqasu.ll @@ -0,0 +1,381 @@ +; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py +; RUN: sed 's/iXLen/i32/g' %s | llc -mtriple=riscv32 -mattr=+v,+xtheadvdot \ +; RUN: -verify-machineinstrs | FileCheck %s +; RUN: sed 's/iXLen/i64/g' %s | llc -mtriple=riscv64 -mattr=+v,+xtheadvdot \ +; RUN: -verify-machineinstrs | FileCheck %s +declare @llvm.riscv.th.vmaqasu.nxv1i32.nxv4i8( + , + , + , + iXLen, + iXLen); + +define @intrinsic_th_vmaqasu_vv_nxv1i32_nxv4i8_nxv4i8( %0, %1, %2, iXLen %3) nounwind { +; CHECK-LABEL: intrinsic_th_vmaqasu_vv_nxv1i32_nxv4i8_nxv4i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli zero, a0, e32, mf2, tu, ma +; CHECK-NEXT: th.vmaqasu.vv v8, v9, v10 +; CHECK-NEXT: ret +entry: + %a = call @llvm.riscv.th.vmaqasu.nxv1i32.nxv4i8( + %0, + %1, + %2, + iXLen %3, iXLen 0) + + ret %a +} + +declare @llvm.riscv.th.vmaqasu.mask.nxv1i32.nxv4i8( + , + , + , + , + iXLen, iXLen); + +define @intrinsic_th_vmaqasu_mask_vv_nxv1i32_nxv4i8_nxv4i8( %0, %1, %2, %3, iXLen %4) nounwind { +; CHECK-LABEL: intrinsic_th_vmaqasu_mask_vv_nxv1i32_nxv4i8_nxv4i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli zero, a0, e32, mf2, tu, mu +; CHECK-NEXT: th.vmaqasu.vv v8, v9, v10, v0.t +; CHECK-NEXT: ret +entry: + %a = call @llvm.riscv.th.vmaqasu.mask.nxv1i32.nxv4i8( + %0, + %1, + %2, + %3, + iXLen %4, iXLen 0) + + ret %a +} + +declare @llvm.riscv.th.vmaqasu.nxv2i32.nxv8i8( + , + , + , + iXLen, + iXLen); + +define @intrinsic_th_vmaqasu_vv_nxv2i32_nxv8i8_nxv8i8( %0, %1, %2, iXLen %3) nounwind { +; CHECK-LABEL: intrinsic_th_vmaqasu_vv_nxv2i32_nxv8i8_nxv8i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli zero, a0, e32, m1, tu, ma +; CHECK-NEXT: th.vmaqasu.vv v8, v9, v10 +; CHECK-NEXT: ret +entry: + %a = call @llvm.riscv.th.vmaqasu.nxv2i32.nxv8i8( + %0, + %1, + %2, + iXLen %3, iXLen 0) + + ret %a +} + +declare @llvm.riscv.th.vmaqasu.mask.nxv2i32.nxv8i8( + , + , + , + , + iXLen, iXLen); + +define @intrinsic_th_vmaqasu_mask_vv_nxv2i32_nxv8i8_nxv8i8( %0, %1, %2, %3, iXLen %4) nounwind { +; CHECK-LABEL: intrinsic_th_vmaqasu_mask_vv_nxv2i32_nxv8i8_nxv8i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli zero, a0, e32, m1, tu, mu +; CHECK-NEXT: th.vmaqasu.vv v8, v9, v10, v0.t +; CHECK-NEXT: ret +entry: + %a = call @llvm.riscv.th.vmaqasu.mask.nxv2i32.nxv8i8( + %0, + %1, + %2, + %3, + iXLen %4, iXLen 0) + + ret %a +} + +declare @llvm.riscv.th.vmaqasu.nxv4i32.nxv16i8( + , + , + , + iXLen, + iXLen); + +define @intrinsic_th_vmaqasu_vv_nxv4i32_nxv16i8_nxv16i8( %0, %1, %2, iXLen %3) nounwind { +; CHECK-LABEL: intrinsic_th_vmaqasu_vv_nxv4i32_nxv16i8_nxv16i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli zero, a0, e32, m2, tu, ma +; CHECK-NEXT: th.vmaqasu.vv v8, v10, v12 +; CHECK-NEXT: ret +entry: + %a = call @llvm.riscv.th.vmaqasu.nxv4i32.nxv16i8( + %0, + %1, + %2, + iXLen %3, iXLen 0) + + ret %a +} + +declare @llvm.riscv.th.vmaqasu.mask.nxv4i32.nxv16i8( + , + , + , + , + iXLen, iXLen); + +define @intrinsic_th_vmaqasu_mask_vv_nxv4i32_nxv16i8_nxv16i8( %0, %1, %2, %3, iXLen %4) nounwind { +; CHECK-LABEL: intrinsic_th_vmaqasu_mask_vv_nxv4i32_nxv16i8_nxv16i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli zero, a0, e32, m2, tu, mu +; CHECK-NEXT: th.vmaqasu.vv v8, v10, v12, v0.t +; CHECK-NEXT: ret +entry: + %a = call @llvm.riscv.th.vmaqasu.mask.nxv4i32.nxv16i8( + %0, + %1, + %2, + %3, + iXLen %4, iXLen 0) + + ret %a +} + +declare @llvm.riscv.th.vmaqasu.nxv8i32.nxv32i8( + , + , + , + iXLen, + iXLen); + +define @intrinsic_th_vmaqasu_vv_nxv8i32_nxv32i8_nxv32i8( %0, %1, %2, iXLen %3) nounwind { +; CHECK-LABEL: intrinsic_th_vmaqasu_vv_nxv8i32_nxv32i8_nxv32i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli zero, a0, e32, m4, tu, ma +; CHECK-NEXT: th.vmaqasu.vv v8, v12, v16 +; CHECK-NEXT: ret +entry: + %a = call @llvm.riscv.th.vmaqasu.nxv8i32.nxv32i8( + %0, + %1, + %2, + iXLen %3, iXLen 0) + + ret %a +} + +declare @llvm.riscv.th.vmaqasu.mask.nxv8i32.nxv32i8( + , + , + , + , + iXLen, iXLen); + +define @intrinsic_th_vmaqasu_mask_vv_nxv8i32_nxv32i8_nxv32i8( %0, %1, %2, %3, iXLen %4) nounwind { +; CHECK-LABEL: intrinsic_th_vmaqasu_mask_vv_nxv8i32_nxv32i8_nxv32i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli zero, a0, e32, m4, tu, mu +; CHECK-NEXT: th.vmaqasu.vv v8, v12, v16, v0.t +; CHECK-NEXT: ret +entry: + %a = call @llvm.riscv.th.vmaqasu.mask.nxv8i32.nxv32i8( + %0, + %1, + %2, + %3, + iXLen %4, iXLen 0) + + ret %a +} + + +declare @llvm.riscv.th.vmaqasu.nxv1i32.i8( + , + i8, + , + iXLen, + iXLen); + +define @intrinsic_th_vmaqasu_vx_nxv1i32_i8_nxv4i8( %0, i8 %1, %2, iXLen %3) nounwind { +; CHECK-LABEL: intrinsic_th_vmaqasu_vx_nxv1i32_i8_nxv4i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli zero, a1, e32, mf2, tu, ma +; CHECK-NEXT: th.vmaqasu.vx v8, a0, v9 +; CHECK-NEXT: ret +entry: + %a = call @llvm.riscv.th.vmaqasu.nxv1i32.i8( + %0, + i8 %1, + %2, + iXLen %3, iXLen 0) + + ret %a +} + +declare @llvm.riscv.th.vmaqasu.mask.nxv1i32.i8( + , + i8, + , + , + iXLen, iXLen); + +define @intrinsic_th_vmaqasu_mask_vx_nxv1i32_i8_nxv4i8( %0, i8 %1, %2, %3, iXLen %4) nounwind { +; CHECK-LABEL: intrinsic_th_vmaqasu_mask_vx_nxv1i32_i8_nxv4i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli zero, a1, e32, mf2, tu, mu +; CHECK-NEXT: th.vmaqasu.vx v8, a0, v9, v0.t +; CHECK-NEXT: ret +entry: + %a = call @llvm.riscv.th.vmaqasu.mask.nxv1i32.i8( + %0, + i8 %1, + %2, + %3, + iXLen %4, iXLen 0) + + ret %a +} + +declare @llvm.riscv.th.vmaqasu.nxv2i32.i8( + , + i8, + , + iXLen, + iXLen); + +define @intrinsic_th_vmaqasu_vx_nxv2i32_i8_nxv8i8( %0, i8 %1, %2, iXLen %3) nounwind { +; CHECK-LABEL: intrinsic_th_vmaqasu_vx_nxv2i32_i8_nxv8i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli zero, a1, e32, m1, tu, ma +; CHECK-NEXT: th.vmaqasu.vx v8, a0, v9 +; CHECK-NEXT: ret +entry: + %a = call @llvm.riscv.th.vmaqasu.nxv2i32.i8( + %0, + i8 %1, + %2, + iXLen %3, iXLen 0) + + ret %a +} + +declare @llvm.riscv.th.vmaqasu.mask.nxv2i32.i8( + , + i8, + , + , + iXLen, iXLen); + +define @intrinsic_th_vmaqasu_mask_vx_nxv2i32_i8_nxv8i8( %0, i8 %1, %2, %3, iXLen %4) nounwind { +; CHECK-LABEL: intrinsic_th_vmaqasu_mask_vx_nxv2i32_i8_nxv8i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli zero, a1, e32, m1, tu, mu +; CHECK-NEXT: th.vmaqasu.vx v8, a0, v9, v0.t +; CHECK-NEXT: ret +entry: + %a = call @llvm.riscv.th.vmaqasu.mask.nxv2i32.i8( + %0, + i8 %1, + %2, + %3, + iXLen %4, iXLen 0) + + ret %a +} + +declare @llvm.riscv.th.vmaqasu.nxv4i32.i8( + , + i8, + , + iXLen, + iXLen); + +define @intrinsic_th_vmaqasu_vx_nxv4i32_i8_nxv16i8( %0, i8 %1, %2, iXLen %3) nounwind { +; CHECK-LABEL: intrinsic_th_vmaqasu_vx_nxv4i32_i8_nxv16i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli zero, a1, e32, m2, tu, ma +; CHECK-NEXT: th.vmaqasu.vx v8, a0, v10 +; CHECK-NEXT: ret +entry: + %a = call @llvm.riscv.th.vmaqasu.nxv4i32.i8( + %0, + i8 %1, + %2, + iXLen %3, iXLen 0) + + ret %a +} + +declare @llvm.riscv.th.vmaqasu.mask.nxv4i32.i8( + , + i8, + , + , + iXLen, iXLen); + +define @intrinsic_th_vmaqasu_mask_vx_nxv4i32_i8_nxv16i8( %0, i8 %1, %2, %3, iXLen %4) nounwind { +; CHECK-LABEL: intrinsic_th_vmaqasu_mask_vx_nxv4i32_i8_nxv16i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli zero, a1, e32, m2, tu, mu +; CHECK-NEXT: th.vmaqasu.vx v8, a0, v10, v0.t +; CHECK-NEXT: ret +entry: + %a = call @llvm.riscv.th.vmaqasu.mask.nxv4i32.i8( + %0, + i8 %1, + %2, + %3, + iXLen %4, iXLen 0) + + ret %a +} + +declare @llvm.riscv.th.vmaqasu.nxv8i32.i8( + , + i8, + , + iXLen, + iXLen); + +define @intrinsic_th_vmaqasu_vx_nxv8i32_i8_nxv32i8( %0, i8 %1, %2, iXLen %3) nounwind { +; CHECK-LABEL: intrinsic_th_vmaqasu_vx_nxv8i32_i8_nxv32i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli zero, a1, e32, m4, tu, ma +; CHECK-NEXT: th.vmaqasu.vx v8, a0, v12 +; CHECK-NEXT: ret +entry: + %a = call @llvm.riscv.th.vmaqasu.nxv8i32.i8( + %0, + i8 %1, + %2, + iXLen %3, iXLen 0) + + ret %a +} + +declare @llvm.riscv.th.vmaqasu.mask.nxv8i32.i8( + , + i8, + , + , + iXLen, iXLen); + +define @intrinsic_th_vmaqasu_mask_vx_nxv8i32_i8_nxv32i8( %0, i8 %1, %2, %3, iXLen %4) nounwind { +; CHECK-LABEL: intrinsic_th_vmaqasu_mask_vx_nxv8i32_i8_nxv32i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli zero, a1, e32, m4, tu, mu +; CHECK-NEXT: th.vmaqasu.vx v8, a0, v12, v0.t +; CHECK-NEXT: ret +entry: + %a = call @llvm.riscv.th.vmaqasu.mask.nxv8i32.i8( + %0, + i8 %1, + %2, + %3, + iXLen %4, iXLen 0) + + ret %a +} Index: llvm/test/CodeGen/RISCV/Vendor/THEAD/vdot/vmaqau.ll =================================================================== --- /dev/null +++ llvm/test/CodeGen/RISCV/Vendor/THEAD/vdot/vmaqau.ll @@ -0,0 +1,381 @@ +; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py +; RUN: sed 's/iXLen/i32/g' %s | llc -mtriple=riscv32 -mattr=+v,+xtheadvdot \ +; RUN: -verify-machineinstrs | FileCheck %s +; RUN: sed 's/iXLen/i64/g' %s | llc -mtriple=riscv64 -mattr=+v,+xtheadvdot \ +; RUN: -verify-machineinstrs | FileCheck %s +declare @llvm.riscv.th.vmaqau.nxv1i32.nxv4i8( + , + , + , + iXLen, + iXLen); + +define @intrinsic_th_vmaqau_vv_nxv1i32_nxv4i8_nxv4i8( %0, %1, %2, iXLen %3) nounwind { +; CHECK-LABEL: intrinsic_th_vmaqau_vv_nxv1i32_nxv4i8_nxv4i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli zero, a0, e32, mf2, tu, ma +; CHECK-NEXT: th.vmaqau.vv v8, v9, v10 +; CHECK-NEXT: ret +entry: + %a = call @llvm.riscv.th.vmaqau.nxv1i32.nxv4i8( + %0, + %1, + %2, + iXLen %3, iXLen 0) + + ret %a +} + +declare @llvm.riscv.th.vmaqau.mask.nxv1i32.nxv4i8( + , + , + , + , + iXLen, iXLen); + +define @intrinsic_th_vmaqau_mask_vv_nxv1i32_nxv4i8_nxv4i8( %0, %1, %2, %3, iXLen %4) nounwind { +; CHECK-LABEL: intrinsic_th_vmaqau_mask_vv_nxv1i32_nxv4i8_nxv4i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli zero, a0, e32, mf2, tu, mu +; CHECK-NEXT: th.vmaqau.vv v8, v9, v10, v0.t +; CHECK-NEXT: ret +entry: + %a = call @llvm.riscv.th.vmaqau.mask.nxv1i32.nxv4i8( + %0, + %1, + %2, + %3, + iXLen %4, iXLen 0) + + ret %a +} + +declare @llvm.riscv.th.vmaqau.nxv2i32.nxv8i8( + , + , + , + iXLen, + iXLen); + +define @intrinsic_th_vmaqau_vv_nxv2i32_nxv8i8_nxv8i8( %0, %1, %2, iXLen %3) nounwind { +; CHECK-LABEL: intrinsic_th_vmaqau_vv_nxv2i32_nxv8i8_nxv8i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli zero, a0, e32, m1, tu, ma +; CHECK-NEXT: th.vmaqau.vv v8, v9, v10 +; CHECK-NEXT: ret +entry: + %a = call @llvm.riscv.th.vmaqau.nxv2i32.nxv8i8( + %0, + %1, + %2, + iXLen %3, iXLen 0) + + ret %a +} + +declare @llvm.riscv.th.vmaqau.mask.nxv2i32.nxv8i8( + , + , + , + , + iXLen, iXLen); + +define @intrinsic_th_vmaqau_mask_vv_nxv2i32_nxv8i8_nxv8i8( %0, %1, %2, %3, iXLen %4) nounwind { +; CHECK-LABEL: intrinsic_th_vmaqau_mask_vv_nxv2i32_nxv8i8_nxv8i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli zero, a0, e32, m1, tu, mu +; CHECK-NEXT: th.vmaqau.vv v8, v9, v10, v0.t +; CHECK-NEXT: ret +entry: + %a = call @llvm.riscv.th.vmaqau.mask.nxv2i32.nxv8i8( + %0, + %1, + %2, + %3, + iXLen %4, iXLen 0) + + ret %a +} + +declare @llvm.riscv.th.vmaqau.nxv4i32.nxv16i8( + , + , + , + iXLen, + iXLen); + +define @intrinsic_th_vmaqau_vv_nxv4i32_nxv16i8_nxv16i8( %0, %1, %2, iXLen %3) nounwind { +; CHECK-LABEL: intrinsic_th_vmaqau_vv_nxv4i32_nxv16i8_nxv16i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli zero, a0, e32, m2, tu, ma +; CHECK-NEXT: th.vmaqau.vv v8, v10, v12 +; CHECK-NEXT: ret +entry: + %a = call @llvm.riscv.th.vmaqau.nxv4i32.nxv16i8( + %0, + %1, + %2, + iXLen %3, iXLen 0) + + ret %a +} + +declare @llvm.riscv.th.vmaqau.mask.nxv4i32.nxv16i8( + , + , + , + , + iXLen, iXLen); + +define @intrinsic_th_vmaqau_mask_vv_nxv4i32_nxv16i8_nxv16i8( %0, %1, %2, %3, iXLen %4) nounwind { +; CHECK-LABEL: intrinsic_th_vmaqau_mask_vv_nxv4i32_nxv16i8_nxv16i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli zero, a0, e32, m2, tu, mu +; CHECK-NEXT: th.vmaqau.vv v8, v10, v12, v0.t +; CHECK-NEXT: ret +entry: + %a = call @llvm.riscv.th.vmaqau.mask.nxv4i32.nxv16i8( + %0, + %1, + %2, + %3, + iXLen %4, iXLen 0) + + ret %a +} + +declare @llvm.riscv.th.vmaqau.nxv8i32.nxv32i8( + , + , + , + iXLen, + iXLen); + +define @intrinsic_th_vmaqau_vv_nxv8i32_nxv32i8_nxv32i8( %0, %1, %2, iXLen %3) nounwind { +; CHECK-LABEL: intrinsic_th_vmaqau_vv_nxv8i32_nxv32i8_nxv32i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli zero, a0, e32, m4, tu, ma +; CHECK-NEXT: th.vmaqau.vv v8, v12, v16 +; CHECK-NEXT: ret +entry: + %a = call @llvm.riscv.th.vmaqau.nxv8i32.nxv32i8( + %0, + %1, + %2, + iXLen %3, iXLen 0) + + ret %a +} + +declare @llvm.riscv.th.vmaqau.mask.nxv8i32.nxv32i8( + , + , + , + , + iXLen, iXLen); + +define @intrinsic_th_vmaqau_mask_vv_nxv8i32_nxv32i8_nxv32i8( %0, %1, %2, %3, iXLen %4) nounwind { +; CHECK-LABEL: intrinsic_th_vmaqau_mask_vv_nxv8i32_nxv32i8_nxv32i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli zero, a0, e32, m4, tu, mu +; CHECK-NEXT: th.vmaqau.vv v8, v12, v16, v0.t +; CHECK-NEXT: ret +entry: + %a = call @llvm.riscv.th.vmaqau.mask.nxv8i32.nxv32i8( + %0, + %1, + %2, + %3, + iXLen %4, iXLen 0) + + ret %a +} + + +declare @llvm.riscv.th.vmaqau.nxv1i32.i8( + , + i8, + , + iXLen, + iXLen); + +define @intrinsic_th_vmaqau_vx_nxv1i32_i8_nxv4i8( %0, i8 %1, %2, iXLen %3) nounwind { +; CHECK-LABEL: intrinsic_th_vmaqau_vx_nxv1i32_i8_nxv4i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli zero, a1, e32, mf2, tu, ma +; CHECK-NEXT: th.vmaqau.vx v8, a0, v9 +; CHECK-NEXT: ret +entry: + %a = call @llvm.riscv.th.vmaqau.nxv1i32.i8( + %0, + i8 %1, + %2, + iXLen %3, iXLen 0) + + ret %a +} + +declare @llvm.riscv.th.vmaqau.mask.nxv1i32.i8( + , + i8, + , + , + iXLen, iXLen); + +define @intrinsic_th_vmaqau_mask_vx_nxv1i32_i8_nxv4i8( %0, i8 %1, %2, %3, iXLen %4) nounwind { +; CHECK-LABEL: intrinsic_th_vmaqau_mask_vx_nxv1i32_i8_nxv4i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli zero, a1, e32, mf2, tu, mu +; CHECK-NEXT: th.vmaqau.vx v8, a0, v9, v0.t +; CHECK-NEXT: ret +entry: + %a = call @llvm.riscv.th.vmaqau.mask.nxv1i32.i8( + %0, + i8 %1, + %2, + %3, + iXLen %4, iXLen 0) + + ret %a +} + +declare @llvm.riscv.th.vmaqau.nxv2i32.i8( + , + i8, + , + iXLen, + iXLen); + +define @intrinsic_th_vmaqau_vx_nxv2i32_i8_nxv8i8( %0, i8 %1, %2, iXLen %3) nounwind { +; CHECK-LABEL: intrinsic_th_vmaqau_vx_nxv2i32_i8_nxv8i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli zero, a1, e32, m1, tu, ma +; CHECK-NEXT: th.vmaqau.vx v8, a0, v9 +; CHECK-NEXT: ret +entry: + %a = call @llvm.riscv.th.vmaqau.nxv2i32.i8( + %0, + i8 %1, + %2, + iXLen %3, iXLen 0) + + ret %a +} + +declare @llvm.riscv.th.vmaqau.mask.nxv2i32.i8( + , + i8, + , + , + iXLen, iXLen); + +define @intrinsic_th_vmaqau_mask_vx_nxv2i32_i8_nxv8i8( %0, i8 %1, %2, %3, iXLen %4) nounwind { +; CHECK-LABEL: intrinsic_th_vmaqau_mask_vx_nxv2i32_i8_nxv8i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli zero, a1, e32, m1, tu, mu +; CHECK-NEXT: th.vmaqau.vx v8, a0, v9, v0.t +; CHECK-NEXT: ret +entry: + %a = call @llvm.riscv.th.vmaqau.mask.nxv2i32.i8( + %0, + i8 %1, + %2, + %3, + iXLen %4, iXLen 0) + + ret %a +} + +declare @llvm.riscv.th.vmaqau.nxv4i32.i8( + , + i8, + , + iXLen, + iXLen); + +define @intrinsic_th_vmaqau_vx_nxv4i32_i8_nxv16i8( %0, i8 %1, %2, iXLen %3) nounwind { +; CHECK-LABEL: intrinsic_th_vmaqau_vx_nxv4i32_i8_nxv16i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli zero, a1, e32, m2, tu, ma +; CHECK-NEXT: th.vmaqau.vx v8, a0, v10 +; CHECK-NEXT: ret +entry: + %a = call @llvm.riscv.th.vmaqau.nxv4i32.i8( + %0, + i8 %1, + %2, + iXLen %3, iXLen 0) + + ret %a +} + +declare @llvm.riscv.th.vmaqau.mask.nxv4i32.i8( + , + i8, + , + , + iXLen, iXLen); + +define @intrinsic_th_vmaqau_mask_vx_nxv4i32_i8_nxv16i8( %0, i8 %1, %2, %3, iXLen %4) nounwind { +; CHECK-LABEL: intrinsic_th_vmaqau_mask_vx_nxv4i32_i8_nxv16i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli zero, a1, e32, m2, tu, mu +; CHECK-NEXT: th.vmaqau.vx v8, a0, v10, v0.t +; CHECK-NEXT: ret +entry: + %a = call @llvm.riscv.th.vmaqau.mask.nxv4i32.i8( + %0, + i8 %1, + %2, + %3, + iXLen %4, iXLen 0) + + ret %a +} + +declare @llvm.riscv.th.vmaqau.nxv8i32.i8( + , + i8, + , + iXLen, + iXLen); + +define @intrinsic_th_vmaqau_vx_nxv8i32_i8_nxv32i8( %0, i8 %1, %2, iXLen %3) nounwind { +; CHECK-LABEL: intrinsic_th_vmaqau_vx_nxv8i32_i8_nxv32i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli zero, a1, e32, m4, tu, ma +; CHECK-NEXT: th.vmaqau.vx v8, a0, v12 +; CHECK-NEXT: ret +entry: + %a = call @llvm.riscv.th.vmaqau.nxv8i32.i8( + %0, + i8 %1, + %2, + iXLen %3, iXLen 0) + + ret %a +} + +declare @llvm.riscv.th.vmaqau.mask.nxv8i32.i8( + , + i8, + , + , + iXLen, iXLen); + +define @intrinsic_th_vmaqau_mask_vx_nxv8i32_i8_nxv32i8( %0, i8 %1, %2, %3, iXLen %4) nounwind { +; CHECK-LABEL: intrinsic_th_vmaqau_mask_vx_nxv8i32_i8_nxv32i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli zero, a1, e32, m4, tu, mu +; CHECK-NEXT: th.vmaqau.vx v8, a0, v12, v0.t +; CHECK-NEXT: ret +entry: + %a = call @llvm.riscv.th.vmaqau.mask.nxv8i32.i8( + %0, + i8 %1, + %2, + %3, + iXLen %4, iXLen 0) + + ret %a +} Index: llvm/test/CodeGen/RISCV/Vendor/THEAD/vdot/vmaqaus.ll =================================================================== --- /dev/null +++ llvm/test/CodeGen/RISCV/Vendor/THEAD/vdot/vmaqaus.ll @@ -0,0 +1,192 @@ +; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py +; RUN: sed 's/iXLen/i32/g' %s | llc -mtriple=riscv32 -mattr=+v,+xtheadvdot \ +; RUN: -verify-machineinstrs | FileCheck %s +; RUN: sed 's/iXLen/i64/g' %s | llc -mtriple=riscv64 -mattr=+v,+xtheadvdot \ +; RUN: -verify-machineinstrs | FileCheck %s +declare @llvm.riscv.th.vmaqaus.nxv1i32.i8( + , + i8, + , + iXLen, + iXLen); + +define @intrinsic_th_vmaqaus_vx_nxv1i32_i8_nxv4i8( %0, i8 %1, %2, iXLen %3) nounwind { +; CHECK-LABEL: intrinsic_th_vmaqaus_vx_nxv1i32_i8_nxv4i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli zero, a1, e32, mf2, tu, ma +; CHECK-NEXT: th.vmaqaus.vx v8, a0, v9 +; CHECK-NEXT: ret +entry: + %a = call @llvm.riscv.th.vmaqaus.nxv1i32.i8( + %0, + i8 %1, + %2, + iXLen %3, iXLen 0) + + ret %a +} + +declare @llvm.riscv.th.vmaqaus.mask.nxv1i32.i8( + , + i8, + , + , + iXLen, iXLen); + +define @intrinsic_th_vmaqaus_mask_vx_nxv1i32_i8_nxv4i8( %0, i8 %1, %2, %3, iXLen %4) nounwind { +; CHECK-LABEL: intrinsic_th_vmaqaus_mask_vx_nxv1i32_i8_nxv4i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli zero, a1, e32, mf2, tu, mu +; CHECK-NEXT: th.vmaqaus.vx v8, a0, v9, v0.t +; CHECK-NEXT: ret +entry: + %a = call @llvm.riscv.th.vmaqaus.mask.nxv1i32.i8( + %0, + i8 %1, + %2, + %3, + iXLen %4, iXLen 0) + + ret %a +} + +declare @llvm.riscv.th.vmaqaus.nxv2i32.i8( + , + i8, + , + iXLen, + iXLen); + +define @intrinsic_th_vmaqaus_vx_nxv2i32_i8_nxv8i8( %0, i8 %1, %2, iXLen %3) nounwind { +; CHECK-LABEL: intrinsic_th_vmaqaus_vx_nxv2i32_i8_nxv8i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli zero, a1, e32, m1, tu, ma +; CHECK-NEXT: th.vmaqaus.vx v8, a0, v9 +; CHECK-NEXT: ret +entry: + %a = call @llvm.riscv.th.vmaqaus.nxv2i32.i8( + %0, + i8 %1, + %2, + iXLen %3, iXLen 0) + + ret %a +} + +declare @llvm.riscv.th.vmaqaus.mask.nxv2i32.i8( + , + i8, + , + , + iXLen, iXLen); + +define @intrinsic_th_vmaqaus_mask_vx_nxv2i32_i8_nxv8i8( %0, i8 %1, %2, %3, iXLen %4) nounwind { +; CHECK-LABEL: intrinsic_th_vmaqaus_mask_vx_nxv2i32_i8_nxv8i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli zero, a1, e32, m1, tu, mu +; CHECK-NEXT: th.vmaqaus.vx v8, a0, v9, v0.t +; CHECK-NEXT: ret +entry: + %a = call @llvm.riscv.th.vmaqaus.mask.nxv2i32.i8( + %0, + i8 %1, + %2, + %3, + iXLen %4, iXLen 0) + + ret %a +} + +declare @llvm.riscv.th.vmaqaus.nxv4i32.i8( + , + i8, + , + iXLen, + iXLen); + +define @intrinsic_th_vmaqaus_vx_nxv4i32_i8_nxv16i8( %0, i8 %1, %2, iXLen %3) nounwind { +; CHECK-LABEL: intrinsic_th_vmaqaus_vx_nxv4i32_i8_nxv16i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli zero, a1, e32, m2, tu, ma +; CHECK-NEXT: th.vmaqaus.vx v8, a0, v10 +; CHECK-NEXT: ret +entry: + %a = call @llvm.riscv.th.vmaqaus.nxv4i32.i8( + %0, + i8 %1, + %2, + iXLen %3, iXLen 0) + + ret %a +} + +declare @llvm.riscv.th.vmaqaus.mask.nxv4i32.i8( + , + i8, + , + , + iXLen, iXLen); + +define @intrinsic_th_vmaqaus_mask_vx_nxv4i32_i8_nxv16i8( %0, i8 %1, %2, %3, iXLen %4) nounwind { +; CHECK-LABEL: intrinsic_th_vmaqaus_mask_vx_nxv4i32_i8_nxv16i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli zero, a1, e32, m2, tu, mu +; CHECK-NEXT: th.vmaqaus.vx v8, a0, v10, v0.t +; CHECK-NEXT: ret +entry: + %a = call @llvm.riscv.th.vmaqaus.mask.nxv4i32.i8( + %0, + i8 %1, + %2, + %3, + iXLen %4, iXLen 0) + + ret %a +} + +declare @llvm.riscv.th.vmaqaus.nxv8i32.i8( + , + i8, + , + iXLen, + iXLen); + +define @intrinsic_th_vmaqaus_vx_nxv8i32_i8_nxv32i8( %0, i8 %1, %2, iXLen %3) nounwind { +; CHECK-LABEL: intrinsic_th_vmaqaus_vx_nxv8i32_i8_nxv32i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli zero, a1, e32, m4, tu, ma +; CHECK-NEXT: th.vmaqaus.vx v8, a0, v12 +; CHECK-NEXT: ret +entry: + %a = call @llvm.riscv.th.vmaqaus.nxv8i32.i8( + %0, + i8 %1, + %2, + iXLen %3, iXLen 0) + + ret %a +} + +declare @llvm.riscv.th.vmaqaus.mask.nxv8i32.i8( + , + i8, + , + , + iXLen, iXLen); + +define @intrinsic_th_vmaqaus_mask_vx_nxv8i32_i8_nxv32i8( %0, i8 %1, %2, %3, iXLen %4) nounwind { +; CHECK-LABEL: intrinsic_th_vmaqaus_mask_vx_nxv8i32_i8_nxv32i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli zero, a1, e32, m4, tu, mu +; CHECK-NEXT: th.vmaqaus.vx v8, a0, v12, v0.t +; CHECK-NEXT: ret +entry: + %a = call @llvm.riscv.th.vmaqaus.mask.nxv8i32.i8( + %0, + i8 %1, + %2, + %3, + iXLen %4, iXLen 0) + + ret %a +} Index: llvm/test/MC/RISCV/Vendor/THEAD/vdot/vmaqa.s =================================================================== --- /dev/null +++ llvm/test/MC/RISCV/Vendor/THEAD/vdot/vmaqa.s @@ -0,0 +1,93 @@ +# RUN: llvm-mc -triple=riscv64 -show-encoding --mattr=+v,+xtheadvdot %s \ +# RUN: | FileCheck %s --check-prefixes=CHECK-ENCODING,CHECK-INST +# RUN: not llvm-mc -triple=riscv64 -show-encoding %s 2>&1 \ +# RUN: | FileCheck %s --check-prefix=CHECK-ERROR +# RUN: llvm-mc -triple=riscv64 -filetype=obj --mattr=+v,+xtheadvdot %s \ +# RUN: | llvm-objdump -d --mattr=+v,+xtheadvdot - \ +# RUN: | FileCheck %s --check-prefix=CHECK-INST +# RUN: llvm-mc -triple=riscv64 -filetype=obj --mattr=+v,+xtheadvdot %s \ +# RUN: | llvm-objdump -d - | FileCheck %s --check-prefix=CHECK-UNKNOWN + +th.vmaqau.vv v8, v20, v4, v0.t +# CHECK-INST: th.vmaqau.vv v8, v20, v4, v0.t +# CHECK-ENCODING: [0x0b,0x64,0x4a,0x88] +# CHECK-ERROR: instruction requires the following: 'xtheadvdot' (THEAD Vector Extensions for Dot){{$}} +# CHECK-UNKNOWN: 0b 64 4a 88 + +th.vmaqau.vv v8, v20, v4 +# CHECK-INST: th.vmaqau.vv v8, v20, v4 +# CHECK-ENCODING: [0x0b,0x64,0x4a,0x8a] +# CHECK-ERROR: instruction requires the following: 'xtheadvdot' (THEAD Vector Extensions for Dot){{$}} +# CHECK-UNKNOWN: 0b 64 4a 8a + +th.vmaqau.vx v8, a0, v4, v0.t +# CHECK-INST: th.vmaqau.vx v8, a0, v4, v0.t +# CHECK-ENCODING: [0x0b,0x64,0x45,0x8c] +# CHECK-ERROR: instruction requires the following: 'xtheadvdot' (THEAD Vector Extensions for Dot){{$}} +# CHECK-UNKNOWN: 0b 64 45 8c + +th.vmaqau.vx v8, a0, v4 +# CHECK-INST: th.vmaqau.vx v8, a0, v4 +# CHECK-ENCODING: [0x0b,0x64,0x45,0x8e] +# CHECK-ERROR: instruction requires the following: 'xtheadvdot' (THEAD Vector Extensions for Dot){{$}} +# CHECK-UNKNOWN: 0b 64 45 8e + +th.vmaqa.vv v8, v20, v4, v0.t +# CHECK-INST: th.vmaqa.vv v8, v20, v4, v0.t +# CHECK-ENCODING: [0x0b,0x64,0x4a,0x80] +# CHECK-ERROR: instruction requires the following: 'xtheadvdot' (THEAD Vector Extensions for Dot){{$}} +# CHECK-UNKNOWN: 0b 64 4a 80 + +th.vmaqa.vv v8, v20, v4 +# CHECK-INST: th.vmaqa.vv v8, v20, v4 +# CHECK-ENCODING: [0x0b,0x64,0x4a,0x82] +# CHECK-ERROR: instruction requires the following: 'xtheadvdot' (THEAD Vector Extensions for Dot){{$}} +# CHECK-UNKNOWN: 0b 64 4a 82 + +th.vmaqa.vx v8, a0, v4, v0.t +# CHECK-INST: th.vmaqa.vx v8, a0, v4, v0.t +# CHECK-ENCODING: [0x0b,0x64,0x45,0x84] +# CHECK-ERROR: instruction requires the following: 'xtheadvdot' (THEAD Vector Extensions for Dot){{$}} +# CHECK-UNKNOWN: 0b 64 45 84 + +th.vmaqa.vx v8, a0, v4 +# CHECK-INST: th.vmaqa.vx v8, a0, v4 +# CHECK-ENCODING: [0x0b,0x64,0x45,0x86] +# CHECK-ERROR: instruction requires the following: 'xtheadvdot' (THEAD Vector Extensions for Dot){{$}} +# CHECK-UNKNOWN: 0b 64 45 86 + +th.vmaqasu.vv v8, v20, v4, v0.t +# CHECK-INST: th.vmaqasu.vv v8, v20, v4, v0.t +# CHECK-ENCODING: [0x0b,0x64,0x4a,0x90] +# CHECK-ERROR: instruction requires the following: 'xtheadvdot' (THEAD Vector Extensions for Dot){{$}} +# CHECK-UNKNOWN: 0b 64 4a 90 + +th.vmaqasu.vv v8, v20, v4 +# CHECK-INST: th.vmaqasu.vv v8, v20, v4 +# CHECK-ENCODING: [0x0b,0x64,0x4a,0x92] +# CHECK-ERROR: instruction requires the following: 'xtheadvdot' (THEAD Vector Extensions for Dot){{$}} +# CHECK-UNKNOWN: 0b 64 4a 92 + +th.vmaqasu.vx v8, a0, v4, v0.t +# CHECK-INST: th.vmaqasu.vx v8, a0, v4, v0.t +# CHECK-ENCODING: [0x0b,0x64,0x45,0x94] +# CHECK-ERROR: instruction requires the following: 'xtheadvdot' (THEAD Vector Extensions for Dot){{$}} +# CHECK-UNKNOWN: 0b 64 45 94 + +th.vmaqasu.vx v8, a0, v4 +# CHECK-INST: th.vmaqasu.vx v8, a0, v4 +# CHECK-ENCODING: [0x0b,0x64,0x45,0x96] +# CHECK-ERROR: instruction requires the following: 'xtheadvdot' (THEAD Vector Extensions for Dot){{$}} +# CHECK-UNKNOWN: 0b 64 45 96 + +th.vmaqaus.vx v8, a0, v4, v0.t +# CHECK-INST: th.vmaqaus.vx v8, a0, v4, v0.t +# CHECK-ENCODING: [0x0b,0x64,0x45,0x9c] +# CHECK-ERROR: instruction requires the following: 'xtheadvdot' (THEAD Vector Extensions for Dot){{$}} +# CHECK-UNKNOWN: 0b 64 45 9c + +th.vmaqaus.vx v8, a0, v4 +# CHECK-INST: th.vmaqaus.vx v8, a0, v4 +# CHECK-ENCODING: [0x0b,0x64,0x45,0x9e] +# CHECK-ERROR: instruction requires the following: 'xtheadvdot' (THEAD Vector Extensions for Dot){{$}} +# CHECK-UNKNOWN: 0b 64 45 9e