diff --git a/llvm/lib/Target/ARM/ARMISelLowering.cpp b/llvm/lib/Target/ARM/ARMISelLowering.cpp
--- a/llvm/lib/Target/ARM/ARMISelLowering.cpp
+++ b/llvm/lib/Target/ARM/ARMISelLowering.cpp
@@ -13774,6 +13774,8 @@
   APInt C1Int = C1ShlC2->getAPIntValue();
 
   // Check that performing a lshr will not lose any information.
+  if (C2Int.getBitWidth() <= C2->getZExtValue()) 
+    return SDValue();
   APInt Mask = APInt::getHighBitsSet(C2Int.getBitWidth(),
                                      C2Int.getBitWidth() - C2->getZExtValue());
   if ((C1Int & Mask) != C1Int)
diff --git a/llvm/test/CodeGen/ARM/pr59317.ll b/llvm/test/CodeGen/ARM/pr59317.ll
new file mode 100644
--- /dev/null
+++ b/llvm/test/CodeGen/ARM/pr59317.ll
@@ -0,0 +1,25 @@
+; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
+; RUN: llc -mtriple=arm %s -o - | FileCheck --check-prefix=arm %s
+; RUN: llc -mtriple=armeb %s -o - | FileCheck --check-prefix=armeb %s
+
+define i1 @pr59317(i16 %F) {
+; arm-LABEL: pr59317:
+; arm:       @ %bb.0: @ %BB
+; arm-NEXT:    sub sp, sp, #8
+; arm-NEXT:    mov r0, #0
+; arm-NEXT:    add sp, sp, #8
+; arm-NEXT:    mov pc, lr
+;
+; armeb-LABEL: pr59317:
+; armeb:       @ %bb.0: @ %BB
+; armeb-NEXT:    sub sp, sp, #8
+; armeb-NEXT:    mov r0, #0
+; armeb-NEXT:    add sp, sp, #8
+; armeb-NEXT:    mov pc, lr
+BB:
+  %E = extractelement <1 x i16> <i16 -1>, i16 %F
+  %RP = alloca i64, align 8
+  %B = shl i16 %E, %E
+  %C1 = icmp ugt i16 %B, %F
+  ret i1 %C1
+}