Index: llvm/lib/Target/AMDGPU/AsmParser/AMDGPUAsmParser.cpp =================================================================== --- llvm/lib/Target/AMDGPU/AsmParser/AMDGPUAsmParser.cpp +++ llvm/lib/Target/AMDGPU/AsmParser/AMDGPUAsmParser.cpp @@ -2091,8 +2091,10 @@ } void AMDGPUOperand::addImmOperands(MCInst &Inst, unsigned N, bool ApplyModifiers) const { - if (AMDGPU::isSISrcOperand(AsmParser->getMII()->get(Inst.getOpcode()), - Inst.getNumOperands())) { + const auto &InstDesc = AsmParser->getMII()->get(Inst.getOpcode()); + auto OpNum = Inst.getNumOperands(); + if (AMDGPU::isSISrcOperand(InstDesc, OpNum) || + AMDGPU::isKImmOperand(InstDesc, OpNum)) { addLiteralImmOperand(Inst, Imm.Val, ApplyModifiers & isImmTy(ImmTyNone) && Imm.Mods.hasFPModifiers()); @@ -2107,7 +2109,8 @@ const auto& InstDesc = AsmParser->getMII()->get(Inst.getOpcode()); auto OpNum = Inst.getNumOperands(); // Check that this operand accepts literals - assert(AMDGPU::isSISrcOperand(InstDesc, OpNum)); + assert(AMDGPU::isSISrcOperand(InstDesc, OpNum) || + AMDGPU::isKImmOperand(InstDesc, OpNum)); if (ApplyModifiers) { assert(AMDGPU::isSISrcFPOperand(InstDesc, OpNum)); @@ -3382,8 +3385,7 @@ unsigned OpIdx) const { const MCInstrDesc &Desc = MII.get(Inst.getOpcode()); - if (!AMDGPU::isSISrcOperand(Desc, OpIdx) || - AMDGPU::isKImmOperand(Desc, OpIdx)) { + if (!AMDGPU::isSISrcOperand(Desc, OpIdx)) { return false; } @@ -4329,7 +4331,7 @@ const MCOperand &MO = Inst.getOperand(OpIdx); if (!MO.isImm() && !MO.isExpr()) continue; - if (!isSISrcOperand(Desc, OpIdx)) + if (!isSISrcOperand(Desc, OpIdx) && !isKImmOperand(Desc, OpIdx)) continue; if (MO.isImm() && !isInlineConstant(Inst, OpIdx)) { Index: llvm/lib/Target/AMDGPU/SIDefines.h =================================================================== --- llvm/lib/Target/AMDGPU/SIDefines.h +++ llvm/lib/Target/AMDGPU/SIDefines.h @@ -176,10 +176,6 @@ OPERAND_REG_INLINE_C_V2INT32, OPERAND_REG_INLINE_C_V2FP32, - /// Operand with 32-bit immediate that uses the constant bus. - OPERAND_KIMM32, - OPERAND_KIMM16, - /// Operands with an AccVGPR register or inline constant OPERAND_REG_INLINE_AC_INT16, OPERAND_REG_INLINE_AC_INT32, @@ -191,6 +187,10 @@ OPERAND_REG_INLINE_AC_V2INT32, OPERAND_REG_INLINE_AC_V2FP32, + /// Operand with 32-bit immediate that uses the constant bus. + OPERAND_KIMM32, + OPERAND_KIMM16, + OPERAND_REG_IMM_FIRST = OPERAND_REG_IMM_INT32, OPERAND_REG_IMM_LAST = OPERAND_REG_IMM_V2FP32, Index: llvm/lib/Target/AMDGPU/SIFoldOperands.cpp =================================================================== --- llvm/lib/Target/AMDGPU/SIFoldOperands.cpp +++ llvm/lib/Target/AMDGPU/SIFoldOperands.cpp @@ -499,10 +499,8 @@ return false; uint8_t OpTy = OpInfo[UseOpIdx].OperandType; - if ((OpTy < AMDGPU::OPERAND_REG_INLINE_AC_FIRST || - OpTy > AMDGPU::OPERAND_REG_INLINE_AC_LAST) && - (OpTy < AMDGPU::OPERAND_REG_INLINE_C_FIRST || - OpTy > AMDGPU::OPERAND_REG_INLINE_C_LAST)) + if (OpTy < AMDGPU::OPERAND_REG_INLINE_C_FIRST || + OpTy > AMDGPU::OPERAND_REG_INLINE_C_LAST) return false; if (OpToFold.isImm() && TII->isInlineConstant(OpToFold, OpTy) && Index: llvm/lib/Target/AMDGPU/SIInstrInfo.cpp =================================================================== --- llvm/lib/Target/AMDGPU/SIInstrInfo.cpp +++ llvm/lib/Target/AMDGPU/SIInstrInfo.cpp @@ -3796,9 +3796,6 @@ uint32_t Trunc = static_cast(Imm); return AMDGPU::isInlinableLiteralV216(Trunc, ST.hasInv2PiInlineImm()); } - case AMDGPU::OPERAND_KIMM32: - case AMDGPU::OPERAND_KIMM16: - return false; default: llvm_unreachable("invalid bitwidth"); } @@ -5098,7 +5095,7 @@ return false; SGPRsUsed.insert(SGPR); } - } else if (InstDesc.OpInfo[i].OperandType == AMDGPU::OPERAND_KIMM32 || + } else if (AMDGPU::isKImmOperand(InstDesc, i) || (AMDGPU::isSISrcOperand(InstDesc, i) && !isInlineConstant(Op, InstDesc.OpInfo[i]))) { if (!LiteralLimit--)