diff --git a/llvm/test/CodeGen/AArch64/sve-streaming-mode-fixed-length-ld2-alloca.ll b/llvm/test/CodeGen/AArch64/sve-streaming-mode-fixed-length-ld2-alloca.ll new file mode 100644 --- /dev/null +++ b/llvm/test/CodeGen/AArch64/sve-streaming-mode-fixed-length-ld2-alloca.ll @@ -0,0 +1,37 @@ +; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py +; RUN: llc -force-streaming-compatible-sve < %s | FileCheck %s + +target triple = "aarch64-unknown-linux-gnu" + +declare void @def(ptr) + +define void @st1d_fixed(ptr %st_ptr) #0 { +; CHECK-LABEL: st1d_fixed: +; CHECK: // %bb.0: +; CHECK-NEXT: sub sp, sp, #160 +; CHECK-NEXT: .cfi_def_cfa_offset 160 +; CHECK-NEXT: str x30, [sp, #128] // 8-byte Folded Spill +; CHECK-NEXT: stp x20, x19, [sp, #144] // 16-byte Folded Spill +; CHECK-NEXT: .cfi_offset w19, -8 +; CHECK-NEXT: .cfi_offset w20, -16 +; CHECK-NEXT: .cfi_offset w30, -32 +; CHECK-NEXT: mov x19, x0 +; CHECK-NEXT: mov x0, sp +; CHECK-NEXT: mov x20, sp +; CHECK-NEXT: bl def +; CHECK-NEXT: ld2 { v0.2d, v1.2d }, [x20], #32 +; CHECK-NEXT: ldr x30, [sp, #128] // 8-byte Folded Reload +; CHECK-NEXT: ld2 { v2.2d, v3.2d }, [x20] +; CHECK-NEXT: stp q0, q2, [x19] +; CHECK-NEXT: ldp x20, x19, [sp, #144] // 16-byte Folded Reload +; CHECK-NEXT: add sp, sp, #160 +; CHECK-NEXT: ret + %alloc = alloca [16 x double] + call void @def(ptr %alloc) + %load = load <8 x double>, ptr %alloc + %strided.vec = shufflevector <8 x double> %load, <8 x double> poison, <4 x i32> + store <4 x double> %strided.vec, ptr %st_ptr + ret void +} + +attributes #0 = { "target-features"="+sve" } diff --git a/llvm/test/CodeGen/AArch64/sve-streaming-mode-fixed-length-limit-duplane.ll b/llvm/test/CodeGen/AArch64/sve-streaming-mode-fixed-length-limit-duplane.ll new file mode 100644 --- /dev/null +++ b/llvm/test/CodeGen/AArch64/sve-streaming-mode-fixed-length-limit-duplane.ll @@ -0,0 +1,52 @@ +; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py +; RUN: llc -mattr=+sve -force-streaming-compatible-sve < %s | FileCheck %s + +target triple = "aarch64-unknown-linux-gnu" + +define <4 x i32> @test(<16 x i32>* %arg1, <16 x i32>* %arg2) { +; CHECK-LABEL: test: +; CHECK: // %bb.0: // %entry +; CHECK-NEXT: ldp q2, q1, [x0, #32] +; CHECK-NEXT: add z2.s, z2.s, z2.s +; CHECK-NEXT: ldp q3, q4, [x0] +; CHECK-NEXT: mov z0.s, z1.s[2] +; CHECK-NEXT: add z1.s, z1.s, z1.s +; CHECK-NEXT: stp q2, q1, [x0, #32] +; CHECK-NEXT: // kill: def $q0 killed $q0 killed $z0 +; CHECK-NEXT: add z2.s, z3.s, z3.s +; CHECK-NEXT: add z1.s, z4.s, z4.s +; CHECK-NEXT: stp q2, q1, [x0] +; CHECK-NEXT: ret +entry: + %0 = load <16 x i32>, <16 x i32>* %arg1, align 256 + %1 = load <16 x i32>, <16 x i32>* %arg2, align 256 + %shvec = shufflevector <16 x i32> %0, <16 x i32> %1, <4 x i32> + %2 = add <16 x i32> %0, %0 + store <16 x i32> %2, <16 x i32>* %arg1, align 256 + ret <4 x i32> %shvec +} + +define <2 x i32> @test2(<16 x i32>* %arg1, <16 x i32>* %arg2) { +; CHECK-LABEL: test2: +; CHECK: // %bb.0: // %entry +; CHECK-NEXT: ldp q2, q0, [x0, #32] +; CHECK-NEXT: ldp q4, q5, [x0] +; CHECK-NEXT: mov z1.d, z0.d +; CHECK-NEXT: add z3.s, z0.s, z0.s +; CHECK-NEXT: ext z1.b, z1.b, z0.b, #8 +; CHECK-NEXT: mov z0.s, s1 +; CHECK-NEXT: add z1.s, z2.s, z2.s +; CHECK-NEXT: stp q1, q3, [x0, #32] +; CHECK-NEXT: add z1.s, z4.s, z4.s +; CHECK-NEXT: // kill: def $d0 killed $d0 killed $z0 +; CHECK-NEXT: add z2.s, z5.s, z5.s +; CHECK-NEXT: stp q1, q2, [x0] +; CHECK-NEXT: ret +entry: + %0 = load <16 x i32>, <16 x i32>* %arg1, align 256 + %1 = load <16 x i32>, <16 x i32>* %arg2, align 256 + %shvec = shufflevector <16 x i32> %0, <16 x i32> %1, <2 x i32> + %2 = add <16 x i32> %0, %0 + store <16 x i32> %2, <16 x i32>* %arg1, align 256 + ret <2 x i32> %shvec +} diff --git a/llvm/test/CodeGen/AArch64/sve-streaming-mode-fixed-length-optimize-ptrue.ll b/llvm/test/CodeGen/AArch64/sve-streaming-mode-fixed-length-optimize-ptrue.ll new file mode 100644 --- /dev/null +++ b/llvm/test/CodeGen/AArch64/sve-streaming-mode-fixed-length-optimize-ptrue.ll @@ -0,0 +1,368 @@ +; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py +; RUN: llc -force-streaming-compatible-sve < %s | FileCheck %s + +target triple = "aarch64-unknown-linux-gnu" + +define void @add_v4i8(<4 x i8>* %a, <4 x i8>* %b) #0 { +; CHECK-LABEL: add_v4i8: +; CHECK: // %bb.0: +; CHECK-NEXT: ldr s0, [x0] +; CHECK-NEXT: ptrue p0.h, vl4 +; CHECK-NEXT: ldr s1, [x1] +; CHECK-NEXT: uunpklo z0.h, z0.b +; CHECK-NEXT: uunpklo z1.h, z1.b +; CHECK-NEXT: add z0.h, z0.h, z1.h +; CHECK-NEXT: st1b { z0.h }, p0, [x0] +; CHECK-NEXT: ret + %op1 = load <4 x i8>, <4 x i8>* %a + %op2 = load <4 x i8>, <4 x i8>* %b + %res = add <4 x i8> %op1, %op2 + store <4 x i8> %res, <4 x i8>* %a + ret void +} + +define void @add_v8i8(<8 x i8>* %a, <8 x i8>* %b) #0 { +; CHECK-LABEL: add_v8i8: +; CHECK: // %bb.0: +; CHECK-NEXT: ldr d0, [x0] +; CHECK-NEXT: ldr d1, [x1] +; CHECK-NEXT: add z0.b, z0.b, z1.b +; CHECK-NEXT: str d0, [x0] +; CHECK-NEXT: ret + %op1 = load <8 x i8>, <8 x i8>* %a + %op2 = load <8 x i8>, <8 x i8>* %b + %res = add <8 x i8> %op1, %op2 + store <8 x i8> %res, <8 x i8>* %a + ret void +} + +define void @add_v16i8(<16 x i8>* %a, <16 x i8>* %b) #0 { +; CHECK-LABEL: add_v16i8: +; CHECK: // %bb.0: +; CHECK-NEXT: ldr q0, [x0] +; CHECK-NEXT: ldr q1, [x1] +; CHECK-NEXT: add z0.b, z0.b, z1.b +; CHECK-NEXT: str q0, [x0] +; CHECK-NEXT: ret + %op1 = load <16 x i8>, <16 x i8>* %a + %op2 = load <16 x i8>, <16 x i8>* %b + %res = add <16 x i8> %op1, %op2 + store <16 x i8> %res, <16 x i8>* %a + ret void +} + +define void @add_v32i8(<32 x i8>* %a, <32 x i8>* %b) #0 { +; CHECK-LABEL: add_v32i8: +; CHECK: // %bb.0: +; CHECK-NEXT: ldp q0, q1, [x0] +; CHECK-NEXT: ldp q2, q3, [x1] +; CHECK-NEXT: add z0.b, z0.b, z2.b +; CHECK-NEXT: add z1.b, z1.b, z3.b +; CHECK-NEXT: stp q0, q1, [x0] +; CHECK-NEXT: ret + %op1 = load <32 x i8>, <32 x i8>* %a + %op2 = load <32 x i8>, <32 x i8>* %b + %res = add <32 x i8> %op1, %op2 + store <32 x i8> %res, <32 x i8>* %a + ret void +} + +define void @add_v2i16(<2 x i16>* %a, <2 x i16>* %b, <2 x i16>* %c) #0 { +; CHECK-LABEL: add_v2i16: +; CHECK: // %bb.0: +; CHECK-NEXT: sub sp, sp, #16 +; CHECK-NEXT: .cfi_def_cfa_offset 16 +; CHECK-NEXT: ldrh w8, [x0, #2] +; CHECK-NEXT: ptrue p0.s, vl2 +; CHECK-NEXT: str w8, [sp, #4] +; CHECK-NEXT: ldrh w8, [x0] +; CHECK-NEXT: str w8, [sp] +; CHECK-NEXT: ldrh w8, [x1, #2] +; CHECK-NEXT: str w8, [sp, #12] +; CHECK-NEXT: ldrh w8, [x1] +; CHECK-NEXT: str w8, [sp, #8] +; CHECK-NEXT: ldp d0, d1, [sp] +; CHECK-NEXT: add z0.s, z0.s, z1.s +; CHECK-NEXT: st1h { z0.s }, p0, [x0] +; CHECK-NEXT: add sp, sp, #16 +; CHECK-NEXT: ret + %op1 = load <2 x i16>, <2 x i16>* %a + %op2 = load <2 x i16>, <2 x i16>* %b + %res = add <2 x i16> %op1, %op2 + store <2 x i16> %res, <2 x i16>* %a + ret void +} + +define void @add_v4i16(<4 x i16>* %a, <4 x i16>* %b, <4 x i16>* %c) #0 { +; CHECK-LABEL: add_v4i16: +; CHECK: // %bb.0: +; CHECK-NEXT: ldr d0, [x0] +; CHECK-NEXT: ldr d1, [x1] +; CHECK-NEXT: add z0.h, z0.h, z1.h +; CHECK-NEXT: str d0, [x0] +; CHECK-NEXT: ret + %op1 = load <4 x i16>, <4 x i16>* %a + %op2 = load <4 x i16>, <4 x i16>* %b + %res = add <4 x i16> %op1, %op2 + store <4 x i16> %res, <4 x i16>* %a + ret void +} + +define void @add_v8i16(<8 x i16>* %a, <8 x i16>* %b, <8 x i16>* %c) #0 { +; CHECK-LABEL: add_v8i16: +; CHECK: // %bb.0: +; CHECK-NEXT: ldr q0, [x0] +; CHECK-NEXT: ldr q1, [x1] +; CHECK-NEXT: add z0.h, z0.h, z1.h +; CHECK-NEXT: str q0, [x0] +; CHECK-NEXT: ret + %op1 = load <8 x i16>, <8 x i16>* %a + %op2 = load <8 x i16>, <8 x i16>* %b + %res = add <8 x i16> %op1, %op2 + store <8 x i16> %res, <8 x i16>* %a + ret void +} + +define void @add_v16i16(<16 x i16>* %a, <16 x i16>* %b, <16 x i16>* %c) #0 { +; CHECK-LABEL: add_v16i16: +; CHECK: // %bb.0: +; CHECK-NEXT: ldp q0, q1, [x0] +; CHECK-NEXT: ldp q2, q3, [x1] +; CHECK-NEXT: add z0.h, z0.h, z2.h +; CHECK-NEXT: add z1.h, z1.h, z3.h +; CHECK-NEXT: stp q0, q1, [x0] +; CHECK-NEXT: ret + %op1 = load <16 x i16>, <16 x i16>* %a + %op2 = load <16 x i16>, <16 x i16>* %b + %res = add <16 x i16> %op1, %op2 + store <16 x i16> %res, <16 x i16>* %a + ret void +} + +define void @abs_v2i32(<2 x i32>* %a) #0 { +; CHECK-LABEL: abs_v2i32: +; CHECK: // %bb.0: +; CHECK-NEXT: ldr d0, [x0] +; CHECK-NEXT: ptrue p0.s, vl2 +; CHECK-NEXT: abs z0.s, p0/m, z0.s +; CHECK-NEXT: str d0, [x0] +; CHECK-NEXT: ret + %op1 = load <2 x i32>, <2 x i32>* %a + %res = call <2 x i32> @llvm.abs.v2i32(<2 x i32> %op1, i1 false) + store <2 x i32> %res, <2 x i32>* %a + ret void +} + +define void @abs_v4i32(<4 x i32>* %a) #0 { +; CHECK-LABEL: abs_v4i32: +; CHECK: // %bb.0: +; CHECK-NEXT: ldr q0, [x0] +; CHECK-NEXT: ptrue p0.s, vl4 +; CHECK-NEXT: abs z0.s, p0/m, z0.s +; CHECK-NEXT: str q0, [x0] +; CHECK-NEXT: ret + %op1 = load <4 x i32>, <4 x i32>* %a + %res = call <4 x i32> @llvm.abs.v4i32(<4 x i32> %op1, i1 false) + store <4 x i32> %res, <4 x i32>* %a + ret void +} + +define void @abs_v8i32(<8 x i32>* %a) #0 { +; CHECK-LABEL: abs_v8i32: +; CHECK: // %bb.0: +; CHECK-NEXT: ldp q0, q1, [x0] +; CHECK-NEXT: ptrue p0.s, vl4 +; CHECK-NEXT: abs z0.s, p0/m, z0.s +; CHECK-NEXT: abs z1.s, p0/m, z1.s +; CHECK-NEXT: stp q0, q1, [x0] +; CHECK-NEXT: ret + %op1 = load <8 x i32>, <8 x i32>* %a + %res = call <8 x i32> @llvm.abs.v8i32(<8 x i32> %op1, i1 false) + store <8 x i32> %res, <8 x i32>* %a + ret void +} + +define void @abs_v2i64(<2 x i64>* %a) #0 { +; CHECK-LABEL: abs_v2i64: +; CHECK: // %bb.0: +; CHECK-NEXT: ldr q0, [x0] +; CHECK-NEXT: ptrue p0.d, vl2 +; CHECK-NEXT: abs z0.d, p0/m, z0.d +; CHECK-NEXT: str q0, [x0] +; CHECK-NEXT: ret + %op1 = load <2 x i64>, <2 x i64>* %a + %res = call <2 x i64> @llvm.abs.v2i64(<2 x i64> %op1, i1 false) + store <2 x i64> %res, <2 x i64>* %a + ret void +} + +define void @abs_v4i64(<4 x i64>* %a) #0 { +; CHECK-LABEL: abs_v4i64: +; CHECK: // %bb.0: +; CHECK-NEXT: ldp q0, q1, [x0] +; CHECK-NEXT: ptrue p0.d, vl2 +; CHECK-NEXT: abs z0.d, p0/m, z0.d +; CHECK-NEXT: abs z1.d, p0/m, z1.d +; CHECK-NEXT: stp q0, q1, [x0] +; CHECK-NEXT: ret + %op1 = load <4 x i64>, <4 x i64>* %a + %res = call <4 x i64> @llvm.abs.v4i64(<4 x i64> %op1, i1 false) + store <4 x i64> %res, <4 x i64>* %a + ret void +} + +define void @fadd_v2f16(<2 x half>* %a, <2 x half>* %b) #0 { +; CHECK-LABEL: fadd_v2f16: +; CHECK: // %bb.0: +; CHECK-NEXT: ldr s0, [x0] +; CHECK-NEXT: ptrue p0.h, vl4 +; CHECK-NEXT: ldr s1, [x1] +; CHECK-NEXT: fadd z0.h, p0/m, z0.h, z1.h +; CHECK-NEXT: fmov w8, s0 +; CHECK-NEXT: str w8, [x0] +; CHECK-NEXT: ret + %op1 = load <2 x half>, <2 x half>* %a + %op2 = load <2 x half>, <2 x half>* %b + %res = fadd <2 x half> %op1, %op2 + store <2 x half> %res, <2 x half>* %a + ret void +} + +define void @fadd_v4f16(<4 x half>* %a, <4 x half>* %b) #0 { +; CHECK-LABEL: fadd_v4f16: +; CHECK: // %bb.0: +; CHECK-NEXT: ldr d0, [x0] +; CHECK-NEXT: ptrue p0.h, vl4 +; CHECK-NEXT: ldr d1, [x1] +; CHECK-NEXT: fadd z0.h, p0/m, z0.h, z1.h +; CHECK-NEXT: str d0, [x0] +; CHECK-NEXT: ret + %op1 = load <4 x half>, <4 x half>* %a + %op2 = load <4 x half>, <4 x half>* %b + %res = fadd <4 x half> %op1, %op2 + store <4 x half> %res, <4 x half>* %a + ret void +} + +define void @fadd_v8f16(<8 x half>* %a, <8 x half>* %b) #0 { +; CHECK-LABEL: fadd_v8f16: +; CHECK: // %bb.0: +; CHECK-NEXT: ldr q0, [x0] +; CHECK-NEXT: ptrue p0.h, vl8 +; CHECK-NEXT: ldr q1, [x1] +; CHECK-NEXT: fadd z0.h, p0/m, z0.h, z1.h +; CHECK-NEXT: str q0, [x0] +; CHECK-NEXT: ret + %op1 = load <8 x half>, <8 x half>* %a + %op2 = load <8 x half>, <8 x half>* %b + %res = fadd <8 x half> %op1, %op2 + store <8 x half> %res, <8 x half>* %a + ret void +} + +define void @fadd_v16f16(<16 x half>* %a, <16 x half>* %b) #0 { +; CHECK-LABEL: fadd_v16f16: +; CHECK: // %bb.0: +; CHECK-NEXT: ldp q0, q1, [x0] +; CHECK-NEXT: ptrue p0.h, vl8 +; CHECK-NEXT: ldp q2, q3, [x1] +; CHECK-NEXT: fadd z0.h, p0/m, z0.h, z2.h +; CHECK-NEXT: fadd z1.h, p0/m, z1.h, z3.h +; CHECK-NEXT: stp q0, q1, [x0] +; CHECK-NEXT: ret + %op1 = load <16 x half>, <16 x half>* %a + %op2 = load <16 x half>, <16 x half>* %b + %res = fadd <16 x half> %op1, %op2 + store <16 x half> %res, <16 x half>* %a + ret void +} + +define void @fadd_v2f32(<2 x float>* %a, <2 x float>* %b) #0 { +; CHECK-LABEL: fadd_v2f32: +; CHECK: // %bb.0: +; CHECK-NEXT: ldr d0, [x0] +; CHECK-NEXT: ptrue p0.s, vl2 +; CHECK-NEXT: ldr d1, [x1] +; CHECK-NEXT: fadd z0.s, p0/m, z0.s, z1.s +; CHECK-NEXT: str d0, [x0] +; CHECK-NEXT: ret + %op1 = load <2 x float>, <2 x float>* %a + %op2 = load <2 x float>, <2 x float>* %b + %res = fadd <2 x float> %op1, %op2 + store <2 x float> %res, <2 x float>* %a + ret void +} + +define void @fadd_v4f32(<4 x float>* %a, <4 x float>* %b) #0 { +; CHECK-LABEL: fadd_v4f32: +; CHECK: // %bb.0: +; CHECK-NEXT: ldr q0, [x0] +; CHECK-NEXT: ptrue p0.s, vl4 +; CHECK-NEXT: ldr q1, [x1] +; CHECK-NEXT: fadd z0.s, p0/m, z0.s, z1.s +; CHECK-NEXT: str q0, [x0] +; CHECK-NEXT: ret + %op1 = load <4 x float>, <4 x float>* %a + %op2 = load <4 x float>, <4 x float>* %b + %res = fadd <4 x float> %op1, %op2 + store <4 x float> %res, <4 x float>* %a + ret void +} + +define void @fadd_v8f32(<8 x float>* %a, <8 x float>* %b) #0 { +; CHECK-LABEL: fadd_v8f32: +; CHECK: // %bb.0: +; CHECK-NEXT: ldp q0, q1, [x0] +; CHECK-NEXT: ptrue p0.s, vl4 +; CHECK-NEXT: ldp q2, q3, [x1] +; CHECK-NEXT: fadd z0.s, p0/m, z0.s, z2.s +; CHECK-NEXT: fadd z1.s, p0/m, z1.s, z3.s +; CHECK-NEXT: stp q0, q1, [x0] +; CHECK-NEXT: ret + %op1 = load <8 x float>, <8 x float>* %a + %op2 = load <8 x float>, <8 x float>* %b + %res = fadd <8 x float> %op1, %op2 + store <8 x float> %res, <8 x float>* %a + ret void +} + +define void @fadd_v2f64(<2 x double>* %a, <2 x double>* %b) #0 { +; CHECK-LABEL: fadd_v2f64: +; CHECK: // %bb.0: +; CHECK-NEXT: ldr q0, [x0] +; CHECK-NEXT: ptrue p0.d, vl2 +; CHECK-NEXT: ldr q1, [x1] +; CHECK-NEXT: fadd z0.d, p0/m, z0.d, z1.d +; CHECK-NEXT: str q0, [x0] +; CHECK-NEXT: ret + %op1 = load <2 x double>, <2 x double>* %a + %op2 = load <2 x double>, <2 x double>* %b + %res = fadd <2 x double> %op1, %op2 + store <2 x double> %res, <2 x double>* %a + ret void +} + +define void @fadd_v4f64(<4 x double>* %a, <4 x double>* %b) #0 { +; CHECK-LABEL: fadd_v4f64: +; CHECK: // %bb.0: +; CHECK-NEXT: ldp q0, q1, [x0] +; CHECK-NEXT: ptrue p0.d, vl2 +; CHECK-NEXT: ldp q2, q3, [x1] +; CHECK-NEXT: fadd z0.d, p0/m, z0.d, z2.d +; CHECK-NEXT: fadd z1.d, p0/m, z1.d, z3.d +; CHECK-NEXT: stp q0, q1, [x0] +; CHECK-NEXT: ret + %op1 = load <4 x double>, <4 x double>* %a + %op2 = load <4 x double>, <4 x double>* %b + %res = fadd <4 x double> %op1, %op2 + store <4 x double> %res, <4 x double>* %a + ret void +} + +declare <2 x i32> @llvm.abs.v2i32(<2 x i32>, i1) +declare <4 x i32> @llvm.abs.v4i32(<4 x i32>, i1) +declare <8 x i32> @llvm.abs.v8i32(<8 x i32>, i1) +declare <2 x i64> @llvm.abs.v2i64(<2 x i64>, i1) +declare <4 x i64> @llvm.abs.v4i64(<4 x i64>, i1) + +attributes #0 = { "target-features"="+sve" } diff --git a/llvm/test/CodeGen/AArch64/sve-streaming-mode-fixed-length-ptest.ll b/llvm/test/CodeGen/AArch64/sve-streaming-mode-fixed-length-ptest.ll new file mode 100644 --- /dev/null +++ b/llvm/test/CodeGen/AArch64/sve-streaming-mode-fixed-length-ptest.ll @@ -0,0 +1,650 @@ +; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py +; RUN: llc -force-streaming-compatible-sve < %s | FileCheck %s + +target triple = "aarch64-unknown-linux-gnu" + +define i1 @ptest_v16i1_256bit_min_sve(float* %a, float * %b) #0 { +; CHECK-LABEL: ptest_v16i1_256bit_min_sve: +; CHECK: // %bb.0: +; CHECK-NEXT: sub sp, sp, #16 +; CHECK-NEXT: .cfi_def_cfa_offset 16 +; CHECK-NEXT: adrp x8, .LCPI0_0 +; CHECK-NEXT: ptrue p0.s, vl4 +; CHECK-NEXT: ldp q2, q0, [x0, #32] +; CHECK-NEXT: ldr q1, [x8, :lo12:.LCPI0_0] +; CHECK-NEXT: ldp q4, q3, [x0] +; CHECK-NEXT: fcmne p1.s, p0/z, z0.s, z1.s +; CHECK-NEXT: mov z0.s, p1/z, #-1 // =0xffffffffffffffff +; CHECK-NEXT: fcmne p1.s, p0/z, z2.s, z1.s +; CHECK-NEXT: fmov w8, s0 +; CHECK-NEXT: mov z2.s, p1/z, #-1 // =0xffffffffffffffff +; CHECK-NEXT: mov z5.s, z0.s[3] +; CHECK-NEXT: mov z6.s, z0.s[2] +; CHECK-NEXT: fcmne p1.s, p0/z, z3.s, z1.s +; CHECK-NEXT: fcmne p0.s, p0/z, z4.s, z1.s +; CHECK-NEXT: mov z3.s, p1/z, #-1 // =0xffffffffffffffff +; CHECK-NEXT: mov z7.s, z0.s[1] +; CHECK-NEXT: mov z0.s, z2.s[3] +; CHECK-NEXT: mov z16.s, z2.s[2] +; CHECK-NEXT: mov z17.s, z2.s[1] +; CHECK-NEXT: fmov w9, s2 +; CHECK-NEXT: strb w8, [sp, #12] +; CHECK-NEXT: mov z1.s, z3.s[3] +; CHECK-NEXT: mov z2.s, z3.s[2] +; CHECK-NEXT: mov z4.s, z3.s[1] +; CHECK-NEXT: fmov w8, s3 +; CHECK-NEXT: mov z3.s, p0/z, #-1 // =0xffffffffffffffff +; CHECK-NEXT: fmov w10, s3 +; CHECK-NEXT: strb w9, [sp, #8] +; CHECK-NEXT: fmov w9, s5 +; CHECK-NEXT: mov z18.s, z3.s[3] +; CHECK-NEXT: strb w8, [sp, #4] +; CHECK-NEXT: fmov w8, s6 +; CHECK-NEXT: strb w10, [sp] +; CHECK-NEXT: fmov w10, s7 +; CHECK-NEXT: strb w9, [sp, #15] +; CHECK-NEXT: fmov w9, s0 +; CHECK-NEXT: strb w8, [sp, #14] +; CHECK-NEXT: fmov w8, s16 +; CHECK-NEXT: strb w10, [sp, #13] +; CHECK-NEXT: fmov w10, s17 +; CHECK-NEXT: strb w9, [sp, #11] +; CHECK-NEXT: fmov w9, s1 +; CHECK-NEXT: strb w8, [sp, #10] +; CHECK-NEXT: fmov w8, s2 +; CHECK-NEXT: strb w10, [sp, #9] +; CHECK-NEXT: fmov w10, s4 +; CHECK-NEXT: mov z19.s, z3.s[2] +; CHECK-NEXT: mov z20.s, z3.s[1] +; CHECK-NEXT: strb w9, [sp, #7] +; CHECK-NEXT: fmov w9, s18 +; CHECK-NEXT: strb w8, [sp, #6] +; CHECK-NEXT: fmov w8, s19 +; CHECK-NEXT: strb w10, [sp, #5] +; CHECK-NEXT: fmov w10, s20 +; CHECK-NEXT: strb w9, [sp, #3] +; CHECK-NEXT: strb w8, [sp, #2] +; CHECK-NEXT: strb w10, [sp, #1] +; CHECK-NEXT: ldr q0, [sp], #16 +; CHECK-NEXT: ptrue p0.b, vl16 +; CHECK-NEXT: orv b0, p0, z0.b +; CHECK-NEXT: fmov w8, s0 +; CHECK-NEXT: and w0, w8, #0x1 +; CHECK-NEXT: ret + %v0 = bitcast float* %a to <16 x float>* + %v1 = load <16 x float>, <16 x float>* %v0, align 4 + %v2 = fcmp une <16 x float> %v1, zeroinitializer + %v3 = call i1 @llvm.vector.reduce.or.i1.v16i1 (<16 x i1> %v2) + ret i1 %v3 +} + +define i1 @ptest_v16i1_512bit_min_sve(float* %a, float * %b) #0 { +; CHECK-LABEL: ptest_v16i1_512bit_min_sve: +; CHECK: // %bb.0: +; CHECK-NEXT: sub sp, sp, #16 +; CHECK-NEXT: .cfi_def_cfa_offset 16 +; CHECK-NEXT: adrp x8, .LCPI1_0 +; CHECK-NEXT: ptrue p0.s, vl4 +; CHECK-NEXT: ldp q2, q0, [x0, #32] +; CHECK-NEXT: ldr q1, [x8, :lo12:.LCPI1_0] +; CHECK-NEXT: ldp q4, q3, [x0] +; CHECK-NEXT: fcmne p1.s, p0/z, z0.s, z1.s +; CHECK-NEXT: mov z0.s, p1/z, #-1 // =0xffffffffffffffff +; CHECK-NEXT: fcmne p1.s, p0/z, z2.s, z1.s +; CHECK-NEXT: fmov w8, s0 +; CHECK-NEXT: mov z2.s, p1/z, #-1 // =0xffffffffffffffff +; CHECK-NEXT: mov z5.s, z0.s[3] +; CHECK-NEXT: mov z6.s, z0.s[2] +; CHECK-NEXT: fcmne p1.s, p0/z, z3.s, z1.s +; CHECK-NEXT: fcmne p0.s, p0/z, z4.s, z1.s +; CHECK-NEXT: mov z3.s, p1/z, #-1 // =0xffffffffffffffff +; CHECK-NEXT: mov z7.s, z0.s[1] +; CHECK-NEXT: mov z0.s, z2.s[3] +; CHECK-NEXT: mov z16.s, z2.s[2] +; CHECK-NEXT: mov z17.s, z2.s[1] +; CHECK-NEXT: fmov w9, s2 +; CHECK-NEXT: strb w8, [sp, #12] +; CHECK-NEXT: mov z1.s, z3.s[3] +; CHECK-NEXT: mov z2.s, z3.s[2] +; CHECK-NEXT: mov z4.s, z3.s[1] +; CHECK-NEXT: fmov w8, s3 +; CHECK-NEXT: mov z3.s, p0/z, #-1 // =0xffffffffffffffff +; CHECK-NEXT: fmov w10, s3 +; CHECK-NEXT: strb w9, [sp, #8] +; CHECK-NEXT: fmov w9, s5 +; CHECK-NEXT: mov z18.s, z3.s[3] +; CHECK-NEXT: strb w8, [sp, #4] +; CHECK-NEXT: fmov w8, s6 +; CHECK-NEXT: strb w10, [sp] +; CHECK-NEXT: fmov w10, s7 +; CHECK-NEXT: strb w9, [sp, #15] +; CHECK-NEXT: fmov w9, s0 +; CHECK-NEXT: strb w8, [sp, #14] +; CHECK-NEXT: fmov w8, s16 +; CHECK-NEXT: strb w10, [sp, #13] +; CHECK-NEXT: fmov w10, s17 +; CHECK-NEXT: strb w9, [sp, #11] +; CHECK-NEXT: fmov w9, s1 +; CHECK-NEXT: strb w8, [sp, #10] +; CHECK-NEXT: fmov w8, s2 +; CHECK-NEXT: strb w10, [sp, #9] +; CHECK-NEXT: fmov w10, s4 +; CHECK-NEXT: mov z19.s, z3.s[2] +; CHECK-NEXT: mov z20.s, z3.s[1] +; CHECK-NEXT: strb w9, [sp, #7] +; CHECK-NEXT: fmov w9, s18 +; CHECK-NEXT: strb w8, [sp, #6] +; CHECK-NEXT: fmov w8, s19 +; CHECK-NEXT: strb w10, [sp, #5] +; CHECK-NEXT: fmov w10, s20 +; CHECK-NEXT: strb w9, [sp, #3] +; CHECK-NEXT: strb w8, [sp, #2] +; CHECK-NEXT: strb w10, [sp, #1] +; CHECK-NEXT: ldr q0, [sp], #16 +; CHECK-NEXT: ptrue p0.b, vl16 +; CHECK-NEXT: orv b0, p0, z0.b +; CHECK-NEXT: fmov w8, s0 +; CHECK-NEXT: and w0, w8, #0x1 +; CHECK-NEXT: ret + %v0 = bitcast float* %a to <16 x float>* + %v1 = load <16 x float>, <16 x float>* %v0, align 4 + %v2 = fcmp une <16 x float> %v1, zeroinitializer + %v3 = call i1 @llvm.vector.reduce.or.i1.v16i1 (<16 x i1> %v2) + ret i1 %v3 +} + +define i1 @ptest_v16i1_512bit_sve(float* %a, float * %b) #0 { +; CHECK-LABEL: ptest_v16i1_512bit_sve: +; CHECK: // %bb.0: +; CHECK-NEXT: sub sp, sp, #16 +; CHECK-NEXT: .cfi_def_cfa_offset 16 +; CHECK-NEXT: adrp x8, .LCPI2_0 +; CHECK-NEXT: ptrue p0.s, vl4 +; CHECK-NEXT: ldp q2, q0, [x0, #32] +; CHECK-NEXT: ldr q1, [x8, :lo12:.LCPI2_0] +; CHECK-NEXT: ldp q4, q3, [x0] +; CHECK-NEXT: fcmne p1.s, p0/z, z0.s, z1.s +; CHECK-NEXT: mov z0.s, p1/z, #-1 // =0xffffffffffffffff +; CHECK-NEXT: fcmne p1.s, p0/z, z2.s, z1.s +; CHECK-NEXT: fmov w8, s0 +; CHECK-NEXT: mov z2.s, p1/z, #-1 // =0xffffffffffffffff +; CHECK-NEXT: mov z5.s, z0.s[3] +; CHECK-NEXT: mov z6.s, z0.s[2] +; CHECK-NEXT: fcmne p1.s, p0/z, z3.s, z1.s +; CHECK-NEXT: fcmne p0.s, p0/z, z4.s, z1.s +; CHECK-NEXT: mov z3.s, p1/z, #-1 // =0xffffffffffffffff +; CHECK-NEXT: mov z7.s, z0.s[1] +; CHECK-NEXT: mov z0.s, z2.s[3] +; CHECK-NEXT: mov z16.s, z2.s[2] +; CHECK-NEXT: mov z17.s, z2.s[1] +; CHECK-NEXT: fmov w9, s2 +; CHECK-NEXT: strb w8, [sp, #12] +; CHECK-NEXT: mov z1.s, z3.s[3] +; CHECK-NEXT: mov z2.s, z3.s[2] +; CHECK-NEXT: mov z4.s, z3.s[1] +; CHECK-NEXT: fmov w8, s3 +; CHECK-NEXT: mov z3.s, p0/z, #-1 // =0xffffffffffffffff +; CHECK-NEXT: fmov w10, s3 +; CHECK-NEXT: strb w9, [sp, #8] +; CHECK-NEXT: fmov w9, s5 +; CHECK-NEXT: mov z18.s, z3.s[3] +; CHECK-NEXT: strb w8, [sp, #4] +; CHECK-NEXT: fmov w8, s6 +; CHECK-NEXT: strb w10, [sp] +; CHECK-NEXT: fmov w10, s7 +; CHECK-NEXT: strb w9, [sp, #15] +; CHECK-NEXT: fmov w9, s0 +; CHECK-NEXT: strb w8, [sp, #14] +; CHECK-NEXT: fmov w8, s16 +; CHECK-NEXT: strb w10, [sp, #13] +; CHECK-NEXT: fmov w10, s17 +; CHECK-NEXT: strb w9, [sp, #11] +; CHECK-NEXT: fmov w9, s1 +; CHECK-NEXT: strb w8, [sp, #10] +; CHECK-NEXT: fmov w8, s2 +; CHECK-NEXT: strb w10, [sp, #9] +; CHECK-NEXT: fmov w10, s4 +; CHECK-NEXT: mov z19.s, z3.s[2] +; CHECK-NEXT: mov z20.s, z3.s[1] +; CHECK-NEXT: strb w9, [sp, #7] +; CHECK-NEXT: fmov w9, s18 +; CHECK-NEXT: strb w8, [sp, #6] +; CHECK-NEXT: fmov w8, s19 +; CHECK-NEXT: strb w10, [sp, #5] +; CHECK-NEXT: fmov w10, s20 +; CHECK-NEXT: strb w9, [sp, #3] +; CHECK-NEXT: strb w8, [sp, #2] +; CHECK-NEXT: strb w10, [sp, #1] +; CHECK-NEXT: ldr q0, [sp], #16 +; CHECK-NEXT: ptrue p0.b, vl16 +; CHECK-NEXT: orv b0, p0, z0.b +; CHECK-NEXT: fmov w8, s0 +; CHECK-NEXT: and w0, w8, #0x1 +; CHECK-NEXT: ret + %v0 = bitcast float* %a to <16 x float>* + %v1 = load <16 x float>, <16 x float>* %v0, align 4 + %v2 = fcmp une <16 x float> %v1, zeroinitializer + %v3 = call i1 @llvm.vector.reduce.or.i1.v16i1 (<16 x i1> %v2) + ret i1 %v3 +} + +define i1 @ptest_or_v16i1_512bit_min_sve(float* %a, float * %b) #0 { +; CHECK-LABEL: ptest_or_v16i1_512bit_min_sve: +; CHECK: // %bb.0: +; CHECK-NEXT: sub sp, sp, #32 +; CHECK-NEXT: .cfi_def_cfa_offset 32 +; CHECK-NEXT: adrp x8, .LCPI3_0 +; CHECK-NEXT: ptrue p0.s, vl4 +; CHECK-NEXT: ldp q2, q1, [x0, #32] +; CHECK-NEXT: ldr q0, [x8, :lo12:.LCPI3_0] +; CHECK-NEXT: ldp q4, q3, [x0] +; CHECK-NEXT: fcmne p1.s, p0/z, z1.s, z0.s +; CHECK-NEXT: mov z1.s, p1/z, #-1 // =0xffffffffffffffff +; CHECK-NEXT: fcmne p1.s, p0/z, z2.s, z0.s +; CHECK-NEXT: fmov w8, s1 +; CHECK-NEXT: mov z2.s, p1/z, #-1 // =0xffffffffffffffff +; CHECK-NEXT: mov z5.s, z1.s[2] +; CHECK-NEXT: mov z6.s, z1.s[1] +; CHECK-NEXT: fcmne p1.s, p0/z, z3.s, z0.s +; CHECK-NEXT: mov z3.s, z1.s[3] +; CHECK-NEXT: mov z1.s, p1/z, #-1 // =0xffffffffffffffff +; CHECK-NEXT: fcmne p1.s, p0/z, z4.s, z0.s +; CHECK-NEXT: mov z7.s, z2.s[3] +; CHECK-NEXT: mov z16.s, z2.s[2] +; CHECK-NEXT: mov z17.s, z2.s[1] +; CHECK-NEXT: fmov w9, s2 +; CHECK-NEXT: strb w8, [sp, #12] +; CHECK-NEXT: mov z2.s, z1.s[3] +; CHECK-NEXT: mov z4.s, z1.s[2] +; CHECK-NEXT: mov z18.s, z1.s[1] +; CHECK-NEXT: fmov w8, s1 +; CHECK-NEXT: mov z1.s, p1/z, #-1 // =0xffffffffffffffff +; CHECK-NEXT: fmov w10, s1 +; CHECK-NEXT: strb w9, [sp, #8] +; CHECK-NEXT: fmov w9, s3 +; CHECK-NEXT: mov z19.s, z1.s[3] +; CHECK-NEXT: strb w8, [sp, #4] +; CHECK-NEXT: fmov w8, s5 +; CHECK-NEXT: strb w10, [sp] +; CHECK-NEXT: fmov w10, s6 +; CHECK-NEXT: strb w9, [sp, #15] +; CHECK-NEXT: fmov w9, s7 +; CHECK-NEXT: strb w8, [sp, #14] +; CHECK-NEXT: fmov w8, s16 +; CHECK-NEXT: strb w10, [sp, #13] +; CHECK-NEXT: fmov w10, s17 +; CHECK-NEXT: strb w9, [sp, #11] +; CHECK-NEXT: fmov w9, s2 +; CHECK-NEXT: strb w8, [sp, #10] +; CHECK-NEXT: fmov w8, s4 +; CHECK-NEXT: strb w10, [sp, #9] +; CHECK-NEXT: fmov w10, s18 +; CHECK-NEXT: mov z20.s, z1.s[2] +; CHECK-NEXT: mov z21.s, z1.s[1] +; CHECK-NEXT: strb w9, [sp, #7] +; CHECK-NEXT: fmov w9, s19 +; CHECK-NEXT: strb w8, [sp, #6] +; CHECK-NEXT: fmov w8, s20 +; CHECK-NEXT: strb w10, [sp, #5] +; CHECK-NEXT: fmov w10, s21 +; CHECK-NEXT: strb w9, [sp, #3] +; CHECK-NEXT: strb w8, [sp, #2] +; CHECK-NEXT: strb w10, [sp, #1] +; CHECK-NEXT: ldr q1, [x1, #48] +; CHECK-NEXT: ldr q5, [x1] +; CHECK-NEXT: ldr q7, [sp] +; CHECK-NEXT: fcmne p1.s, p0/z, z1.s, z0.s +; CHECK-NEXT: ldp q6, q1, [x1, #16] +; CHECK-NEXT: mov z2.s, p1/z, #-1 // =0xffffffffffffffff +; CHECK-NEXT: fmov w8, s2 +; CHECK-NEXT: mov z3.s, z2.s[3] +; CHECK-NEXT: mov z4.s, z2.s[2] +; CHECK-NEXT: mov z2.s, z2.s[1] +; CHECK-NEXT: strb w8, [sp, #28] +; CHECK-NEXT: fcmne p1.s, p0/z, z1.s, z0.s +; CHECK-NEXT: mov z1.s, p1/z, #-1 // =0xffffffffffffffff +; CHECK-NEXT: fcmne p1.s, p0/z, z6.s, z0.s +; CHECK-NEXT: mov z6.s, z1.s[3] +; CHECK-NEXT: mov z16.s, z1.s[2] +; CHECK-NEXT: mov z17.s, z1.s[1] +; CHECK-NEXT: fmov w8, s1 +; CHECK-NEXT: mov z1.s, p1/z, #-1 // =0xffffffffffffffff +; CHECK-NEXT: fcmne p0.s, p0/z, z5.s, z0.s +; CHECK-NEXT: mov z0.s, z1.s[3] +; CHECK-NEXT: mov z5.s, z1.s[2] +; CHECK-NEXT: mov z18.s, z1.s[1] +; CHECK-NEXT: fmov w9, s1 +; CHECK-NEXT: mov z1.s, p0/z, #-1 // =0xffffffffffffffff +; CHECK-NEXT: strb w8, [sp, #24] +; CHECK-NEXT: fmov w10, s1 +; CHECK-NEXT: fmov w8, s3 +; CHECK-NEXT: strb w9, [sp, #20] +; CHECK-NEXT: fmov w9, s4 +; CHECK-NEXT: mov z19.s, z1.s[3] +; CHECK-NEXT: mov z20.s, z1.s[2] +; CHECK-NEXT: strb w10, [sp, #16] +; CHECK-NEXT: fmov w10, s2 +; CHECK-NEXT: strb w8, [sp, #31] +; CHECK-NEXT: fmov w8, s6 +; CHECK-NEXT: strb w9, [sp, #30] +; CHECK-NEXT: fmov w9, s16 +; CHECK-NEXT: strb w10, [sp, #29] +; CHECK-NEXT: fmov w10, s17 +; CHECK-NEXT: strb w8, [sp, #27] +; CHECK-NEXT: fmov w8, s0 +; CHECK-NEXT: strb w9, [sp, #26] +; CHECK-NEXT: fmov w9, s5 +; CHECK-NEXT: strb w10, [sp, #25] +; CHECK-NEXT: fmov w10, s18 +; CHECK-NEXT: mov z21.s, z1.s[1] +; CHECK-NEXT: strb w8, [sp, #23] +; CHECK-NEXT: fmov w8, s19 +; CHECK-NEXT: strb w9, [sp, #22] +; CHECK-NEXT: fmov w9, s20 +; CHECK-NEXT: strb w10, [sp, #21] +; CHECK-NEXT: fmov w10, s21 +; CHECK-NEXT: ptrue p0.b, vl16 +; CHECK-NEXT: strb w8, [sp, #19] +; CHECK-NEXT: strb w9, [sp, #18] +; CHECK-NEXT: strb w10, [sp, #17] +; CHECK-NEXT: ldr q0, [sp, #16] +; CHECK-NEXT: orr z0.d, z7.d, z0.d +; CHECK-NEXT: orv b0, p0, z0.b +; CHECK-NEXT: fmov w8, s0 +; CHECK-NEXT: and w0, w8, #0x1 +; CHECK-NEXT: add sp, sp, #32 +; CHECK-NEXT: ret + %v0 = bitcast float* %a to <16 x float>* + %v1 = load <16 x float>, <16 x float>* %v0, align 4 + %v2 = fcmp une <16 x float> %v1, zeroinitializer + %v3 = bitcast float* %b to <16 x float>* + %v4 = load <16 x float>, <16 x float>* %v3, align 4 + %v5 = fcmp une <16 x float> %v4, zeroinitializer + %v6 = or <16 x i1> %v2, %v5 + %v7 = call i1 @llvm.vector.reduce.or.i1.v16i1 (<16 x i1> %v6) + ret i1 %v7 +} + +declare i1 @llvm.vector.reduce.or.i1.v16i1(<16 x i1>) + +; +; AND reduction. +; + +define i1 @ptest_and_v16i1_512bit_sve(float* %a, float * %b) #0 { +; CHECK-LABEL: ptest_and_v16i1_512bit_sve: +; CHECK: // %bb.0: +; CHECK-NEXT: sub sp, sp, #32 +; CHECK-NEXT: .cfi_def_cfa_offset 32 +; CHECK-NEXT: adrp x8, .LCPI4_0 +; CHECK-NEXT: ptrue p0.s, vl4 +; CHECK-NEXT: ldp q2, q1, [x0, #32] +; CHECK-NEXT: ldr q0, [x8, :lo12:.LCPI4_0] +; CHECK-NEXT: ldp q4, q3, [x0] +; CHECK-NEXT: fcmne p1.s, p0/z, z1.s, z0.s +; CHECK-NEXT: mov z1.s, p1/z, #-1 // =0xffffffffffffffff +; CHECK-NEXT: fcmne p1.s, p0/z, z2.s, z0.s +; CHECK-NEXT: fmov w8, s1 +; CHECK-NEXT: mov z2.s, p1/z, #-1 // =0xffffffffffffffff +; CHECK-NEXT: mov z5.s, z1.s[2] +; CHECK-NEXT: mov z6.s, z1.s[1] +; CHECK-NEXT: fcmne p1.s, p0/z, z3.s, z0.s +; CHECK-NEXT: mov z3.s, z1.s[3] +; CHECK-NEXT: mov z1.s, p1/z, #-1 // =0xffffffffffffffff +; CHECK-NEXT: fcmne p1.s, p0/z, z4.s, z0.s +; CHECK-NEXT: mov z7.s, z2.s[3] +; CHECK-NEXT: mov z16.s, z2.s[2] +; CHECK-NEXT: mov z17.s, z2.s[1] +; CHECK-NEXT: fmov w9, s2 +; CHECK-NEXT: strb w8, [sp, #12] +; CHECK-NEXT: mov z2.s, z1.s[3] +; CHECK-NEXT: mov z4.s, z1.s[2] +; CHECK-NEXT: mov z18.s, z1.s[1] +; CHECK-NEXT: fmov w8, s1 +; CHECK-NEXT: mov z1.s, p1/z, #-1 // =0xffffffffffffffff +; CHECK-NEXT: fmov w10, s1 +; CHECK-NEXT: strb w9, [sp, #8] +; CHECK-NEXT: fmov w9, s3 +; CHECK-NEXT: mov z19.s, z1.s[3] +; CHECK-NEXT: strb w8, [sp, #4] +; CHECK-NEXT: fmov w8, s5 +; CHECK-NEXT: strb w10, [sp] +; CHECK-NEXT: fmov w10, s6 +; CHECK-NEXT: strb w9, [sp, #15] +; CHECK-NEXT: fmov w9, s7 +; CHECK-NEXT: strb w8, [sp, #14] +; CHECK-NEXT: fmov w8, s16 +; CHECK-NEXT: strb w10, [sp, #13] +; CHECK-NEXT: fmov w10, s17 +; CHECK-NEXT: strb w9, [sp, #11] +; CHECK-NEXT: fmov w9, s2 +; CHECK-NEXT: strb w8, [sp, #10] +; CHECK-NEXT: fmov w8, s4 +; CHECK-NEXT: strb w10, [sp, #9] +; CHECK-NEXT: fmov w10, s18 +; CHECK-NEXT: mov z20.s, z1.s[2] +; CHECK-NEXT: mov z21.s, z1.s[1] +; CHECK-NEXT: strb w9, [sp, #7] +; CHECK-NEXT: fmov w9, s19 +; CHECK-NEXT: strb w8, [sp, #6] +; CHECK-NEXT: fmov w8, s20 +; CHECK-NEXT: strb w10, [sp, #5] +; CHECK-NEXT: fmov w10, s21 +; CHECK-NEXT: strb w9, [sp, #3] +; CHECK-NEXT: strb w8, [sp, #2] +; CHECK-NEXT: strb w10, [sp, #1] +; CHECK-NEXT: ldr q1, [x1, #48] +; CHECK-NEXT: ldr q5, [x1] +; CHECK-NEXT: ldr q7, [sp] +; CHECK-NEXT: fcmne p1.s, p0/z, z1.s, z0.s +; CHECK-NEXT: ldp q6, q1, [x1, #16] +; CHECK-NEXT: mov z2.s, p1/z, #-1 // =0xffffffffffffffff +; CHECK-NEXT: fmov w8, s2 +; CHECK-NEXT: mov z3.s, z2.s[3] +; CHECK-NEXT: mov z4.s, z2.s[2] +; CHECK-NEXT: mov z2.s, z2.s[1] +; CHECK-NEXT: strb w8, [sp, #28] +; CHECK-NEXT: fcmne p1.s, p0/z, z1.s, z0.s +; CHECK-NEXT: mov z1.s, p1/z, #-1 // =0xffffffffffffffff +; CHECK-NEXT: fcmne p1.s, p0/z, z6.s, z0.s +; CHECK-NEXT: mov z6.s, z1.s[3] +; CHECK-NEXT: mov z16.s, z1.s[2] +; CHECK-NEXT: mov z17.s, z1.s[1] +; CHECK-NEXT: fmov w8, s1 +; CHECK-NEXT: mov z1.s, p1/z, #-1 // =0xffffffffffffffff +; CHECK-NEXT: fcmne p0.s, p0/z, z5.s, z0.s +; CHECK-NEXT: mov z0.s, z1.s[3] +; CHECK-NEXT: mov z5.s, z1.s[2] +; CHECK-NEXT: mov z18.s, z1.s[1] +; CHECK-NEXT: fmov w9, s1 +; CHECK-NEXT: mov z1.s, p0/z, #-1 // =0xffffffffffffffff +; CHECK-NEXT: strb w8, [sp, #24] +; CHECK-NEXT: fmov w10, s1 +; CHECK-NEXT: fmov w8, s3 +; CHECK-NEXT: strb w9, [sp, #20] +; CHECK-NEXT: fmov w9, s4 +; CHECK-NEXT: mov z19.s, z1.s[3] +; CHECK-NEXT: mov z20.s, z1.s[2] +; CHECK-NEXT: strb w10, [sp, #16] +; CHECK-NEXT: fmov w10, s2 +; CHECK-NEXT: strb w8, [sp, #31] +; CHECK-NEXT: fmov w8, s6 +; CHECK-NEXT: strb w9, [sp, #30] +; CHECK-NEXT: fmov w9, s16 +; CHECK-NEXT: strb w10, [sp, #29] +; CHECK-NEXT: fmov w10, s17 +; CHECK-NEXT: strb w8, [sp, #27] +; CHECK-NEXT: fmov w8, s0 +; CHECK-NEXT: strb w9, [sp, #26] +; CHECK-NEXT: fmov w9, s5 +; CHECK-NEXT: strb w10, [sp, #25] +; CHECK-NEXT: fmov w10, s18 +; CHECK-NEXT: mov z21.s, z1.s[1] +; CHECK-NEXT: strb w8, [sp, #23] +; CHECK-NEXT: fmov w8, s19 +; CHECK-NEXT: strb w9, [sp, #22] +; CHECK-NEXT: fmov w9, s20 +; CHECK-NEXT: strb w10, [sp, #21] +; CHECK-NEXT: fmov w10, s21 +; CHECK-NEXT: ptrue p0.b, vl16 +; CHECK-NEXT: strb w8, [sp, #19] +; CHECK-NEXT: strb w9, [sp, #18] +; CHECK-NEXT: strb w10, [sp, #17] +; CHECK-NEXT: ldr q0, [sp, #16] +; CHECK-NEXT: and z0.d, z7.d, z0.d +; CHECK-NEXT: andv b0, p0, z0.b +; CHECK-NEXT: fmov w8, s0 +; CHECK-NEXT: and w0, w8, #0x1 +; CHECK-NEXT: add sp, sp, #32 +; CHECK-NEXT: ret + %v0 = bitcast float* %a to <16 x float>* + %v1 = load <16 x float>, <16 x float>* %v0, align 4 + %v2 = fcmp une <16 x float> %v1, zeroinitializer + %v3 = bitcast float* %b to <16 x float>* + %v4 = load <16 x float>, <16 x float>* %v3, align 4 + %v5 = fcmp une <16 x float> %v4, zeroinitializer + %v6 = and <16 x i1> %v2, %v5 + %v7 = call i1 @llvm.vector.reduce.and.i1.v16i1 (<16 x i1> %v6) + ret i1 %v7 +} + +define i1 @ptest_and_v16i1_512bit_min_sve(float* %a, float * %b) #0 { +; CHECK-LABEL: ptest_and_v16i1_512bit_min_sve: +; CHECK: // %bb.0: +; CHECK-NEXT: sub sp, sp, #32 +; CHECK-NEXT: .cfi_def_cfa_offset 32 +; CHECK-NEXT: adrp x8, .LCPI5_0 +; CHECK-NEXT: ptrue p0.s, vl4 +; CHECK-NEXT: ldp q2, q1, [x0, #32] +; CHECK-NEXT: ldr q0, [x8, :lo12:.LCPI5_0] +; CHECK-NEXT: ldp q4, q3, [x0] +; CHECK-NEXT: fcmne p1.s, p0/z, z1.s, z0.s +; CHECK-NEXT: mov z1.s, p1/z, #-1 // =0xffffffffffffffff +; CHECK-NEXT: fcmne p1.s, p0/z, z2.s, z0.s +; CHECK-NEXT: fmov w8, s1 +; CHECK-NEXT: mov z2.s, p1/z, #-1 // =0xffffffffffffffff +; CHECK-NEXT: mov z5.s, z1.s[2] +; CHECK-NEXT: mov z6.s, z1.s[1] +; CHECK-NEXT: fcmne p1.s, p0/z, z3.s, z0.s +; CHECK-NEXT: mov z3.s, z1.s[3] +; CHECK-NEXT: mov z1.s, p1/z, #-1 // =0xffffffffffffffff +; CHECK-NEXT: fcmne p1.s, p0/z, z4.s, z0.s +; CHECK-NEXT: mov z7.s, z2.s[3] +; CHECK-NEXT: mov z16.s, z2.s[2] +; CHECK-NEXT: mov z17.s, z2.s[1] +; CHECK-NEXT: fmov w9, s2 +; CHECK-NEXT: strb w8, [sp, #12] +; CHECK-NEXT: mov z2.s, z1.s[3] +; CHECK-NEXT: mov z4.s, z1.s[2] +; CHECK-NEXT: mov z18.s, z1.s[1] +; CHECK-NEXT: fmov w8, s1 +; CHECK-NEXT: mov z1.s, p1/z, #-1 // =0xffffffffffffffff +; CHECK-NEXT: fmov w10, s1 +; CHECK-NEXT: strb w9, [sp, #8] +; CHECK-NEXT: fmov w9, s3 +; CHECK-NEXT: mov z19.s, z1.s[3] +; CHECK-NEXT: strb w8, [sp, #4] +; CHECK-NEXT: fmov w8, s5 +; CHECK-NEXT: strb w10, [sp] +; CHECK-NEXT: fmov w10, s6 +; CHECK-NEXT: strb w9, [sp, #15] +; CHECK-NEXT: fmov w9, s7 +; CHECK-NEXT: strb w8, [sp, #14] +; CHECK-NEXT: fmov w8, s16 +; CHECK-NEXT: strb w10, [sp, #13] +; CHECK-NEXT: fmov w10, s17 +; CHECK-NEXT: strb w9, [sp, #11] +; CHECK-NEXT: fmov w9, s2 +; CHECK-NEXT: strb w8, [sp, #10] +; CHECK-NEXT: fmov w8, s4 +; CHECK-NEXT: strb w10, [sp, #9] +; CHECK-NEXT: fmov w10, s18 +; CHECK-NEXT: mov z20.s, z1.s[2] +; CHECK-NEXT: mov z21.s, z1.s[1] +; CHECK-NEXT: strb w9, [sp, #7] +; CHECK-NEXT: fmov w9, s19 +; CHECK-NEXT: strb w8, [sp, #6] +; CHECK-NEXT: fmov w8, s20 +; CHECK-NEXT: strb w10, [sp, #5] +; CHECK-NEXT: fmov w10, s21 +; CHECK-NEXT: strb w9, [sp, #3] +; CHECK-NEXT: strb w8, [sp, #2] +; CHECK-NEXT: strb w10, [sp, #1] +; CHECK-NEXT: ldr q1, [x1, #48] +; CHECK-NEXT: ldr q5, [x1] +; CHECK-NEXT: ldr q7, [sp] +; CHECK-NEXT: fcmne p1.s, p0/z, z1.s, z0.s +; CHECK-NEXT: ldp q6, q1, [x1, #16] +; CHECK-NEXT: mov z2.s, p1/z, #-1 // =0xffffffffffffffff +; CHECK-NEXT: fmov w8, s2 +; CHECK-NEXT: mov z3.s, z2.s[3] +; CHECK-NEXT: mov z4.s, z2.s[2] +; CHECK-NEXT: mov z2.s, z2.s[1] +; CHECK-NEXT: strb w8, [sp, #28] +; CHECK-NEXT: fcmne p1.s, p0/z, z1.s, z0.s +; CHECK-NEXT: mov z1.s, p1/z, #-1 // =0xffffffffffffffff +; CHECK-NEXT: fcmne p1.s, p0/z, z6.s, z0.s +; CHECK-NEXT: mov z6.s, z1.s[3] +; CHECK-NEXT: mov z16.s, z1.s[2] +; CHECK-NEXT: mov z17.s, z1.s[1] +; CHECK-NEXT: fmov w8, s1 +; CHECK-NEXT: mov z1.s, p1/z, #-1 // =0xffffffffffffffff +; CHECK-NEXT: fcmne p0.s, p0/z, z5.s, z0.s +; CHECK-NEXT: mov z0.s, z1.s[3] +; CHECK-NEXT: mov z5.s, z1.s[2] +; CHECK-NEXT: mov z18.s, z1.s[1] +; CHECK-NEXT: fmov w9, s1 +; CHECK-NEXT: mov z1.s, p0/z, #-1 // =0xffffffffffffffff +; CHECK-NEXT: strb w8, [sp, #24] +; CHECK-NEXT: fmov w10, s1 +; CHECK-NEXT: fmov w8, s3 +; CHECK-NEXT: strb w9, [sp, #20] +; CHECK-NEXT: fmov w9, s4 +; CHECK-NEXT: mov z19.s, z1.s[3] +; CHECK-NEXT: mov z20.s, z1.s[2] +; CHECK-NEXT: strb w10, [sp, #16] +; CHECK-NEXT: fmov w10, s2 +; CHECK-NEXT: strb w8, [sp, #31] +; CHECK-NEXT: fmov w8, s6 +; CHECK-NEXT: strb w9, [sp, #30] +; CHECK-NEXT: fmov w9, s16 +; CHECK-NEXT: strb w10, [sp, #29] +; CHECK-NEXT: fmov w10, s17 +; CHECK-NEXT: strb w8, [sp, #27] +; CHECK-NEXT: fmov w8, s0 +; CHECK-NEXT: strb w9, [sp, #26] +; CHECK-NEXT: fmov w9, s5 +; CHECK-NEXT: strb w10, [sp, #25] +; CHECK-NEXT: fmov w10, s18 +; CHECK-NEXT: mov z21.s, z1.s[1] +; CHECK-NEXT: strb w8, [sp, #23] +; CHECK-NEXT: fmov w8, s19 +; CHECK-NEXT: strb w9, [sp, #22] +; CHECK-NEXT: fmov w9, s20 +; CHECK-NEXT: strb w10, [sp, #21] +; CHECK-NEXT: fmov w10, s21 +; CHECK-NEXT: ptrue p0.b, vl16 +; CHECK-NEXT: strb w8, [sp, #19] +; CHECK-NEXT: strb w9, [sp, #18] +; CHECK-NEXT: strb w10, [sp, #17] +; CHECK-NEXT: ldr q0, [sp, #16] +; CHECK-NEXT: and z0.d, z7.d, z0.d +; CHECK-NEXT: andv b0, p0, z0.b +; CHECK-NEXT: fmov w8, s0 +; CHECK-NEXT: and w0, w8, #0x1 +; CHECK-NEXT: add sp, sp, #32 +; CHECK-NEXT: ret + %v0 = bitcast float* %a to <16 x float>* + %v1 = load <16 x float>, <16 x float>* %v0, align 4 + %v2 = fcmp une <16 x float> %v1, zeroinitializer + %v3 = bitcast float* %b to <16 x float>* + %v4 = load <16 x float>, <16 x float>* %v3, align 4 + %v5 = fcmp une <16 x float> %v4, zeroinitializer + %v6 = and <16 x i1> %v2, %v5 + %v7 = call i1 @llvm.vector.reduce.and.i1.v16i1 (<16 x i1> %v6) + ret i1 %v7 +} + +attributes #0 = { "target-features"="+sve" } + +declare i1 @llvm.vector.reduce.and.i1.v16i1(<16 x i1>)