Index: include/llvm/MC/MCTargetMachine.h =================================================================== --- include/llvm/MC/MCTargetMachine.h +++ include/llvm/MC/MCTargetMachine.h @@ -67,7 +67,7 @@ const Target &getTarget() const { return TheTarget; } /// Create a MCAsmInfo implementation. - virtual MCAsmInfo *createMCAsmInfo(const MCRegisterInfo &MRI) const; + virtual MCAsmInfo *createMCAsmInfo(const MCRegisterInfo &MRI) const = 0; /// Create a MCCodeGenInfo implementation. virtual MCCodeGenInfo *createMCCodeGenInfo(Reloc::Model RM, Index: include/llvm/Support/TargetRegistry.h =================================================================== --- include/llvm/Support/TargetRegistry.h +++ include/llvm/Support/TargetRegistry.h @@ -92,8 +92,6 @@ typedef bool (*ArchMatchFnTy)(Triple::ArchType Arch); - typedef MCAsmInfo *(*MCAsmInfoCtorFnTy)(const MCRegisterInfo &MRI, - const Triple &TT); typedef MCCodeGenInfo *(*MCCodeGenInfoCtorFnTy)(const Triple &TT, Reloc::Model RM, CodeModel::Model CM, @@ -176,10 +174,6 @@ /// HasJIT - Whether this target supports the JIT. bool HasJIT; - /// MCAsmInfoCtorFn - Constructor function for this target's MCAsmInfo, if - /// registered. - MCAsmInfoCtorFnTy MCAsmInfoCtorFn; - /// MCCodeGenInfoCtorFn - Constructor function for this target's /// MCCodeGenInfo, if registered. MCCodeGenInfoCtorFnTy MCCodeGenInfoCtorFn; @@ -297,20 +291,6 @@ /// @{ protected: - /// createMCAsmInfo - Create a MCAsmInfo implementation for the specified - /// target triple. - /// - /// \param TheTriple This argument is used to determine the target machine - /// feature set; it should always be provided. Generally this should be - /// either the target triple from the module, or the target triple of the - /// host if that does not exist. - MCAsmInfo *createMCAsmInfo(const MCRegisterInfo &MRI, - StringRef TheTriple) const { - if (!MCAsmInfoCtorFn) - return nullptr; - return MCAsmInfoCtorFn(MRI, Triple(TheTriple)); - } - /// createMCCodeGenInfo - Create a MCCodeGenInfo implementation. /// MCCodeGenInfo *createMCCodeGenInfo(StringRef TT, Reloc::Model RM, @@ -661,19 +641,6 @@ Target::ArchMatchFnTy ArchMatchFn, bool HasJIT = false); - /// RegisterMCAsmInfo - Register a MCAsmInfo implementation for the - /// given target. - /// - /// Clients are responsible for ensuring that registration doesn't occur - /// while another thread is attempting to access the registry. Typically - /// this is done by initializing all targets at program startup. - /// - /// @param T - The target being registered. - /// @param Fn - A function to construct a MCAsmInfo for the target. - static void RegisterMCAsmInfo(Target &T, Target::MCAsmInfoCtorFnTy Fn) { - T.MCAsmInfoCtorFn = Fn; - } - /// RegisterMCCodeGenInfo - Register a MCCodeGenInfo implementation for the /// given target. /// @@ -922,40 +889,6 @@ } }; -/// RegisterMCAsmInfo - Helper template for registering a target assembly info -/// implementation. This invokes the static "Create" method on the class to -/// actually do the construction. Usage: -/// -/// extern "C" void LLVMInitializeFooTarget() { -/// extern Target TheFooTarget; -/// RegisterMCAsmInfo X(TheFooTarget); -/// } -template struct RegisterMCAsmInfo { - RegisterMCAsmInfo(Target &T) { - TargetRegistry::RegisterMCAsmInfo(T, &Allocator); - } - -private: - static MCAsmInfo *Allocator(const MCRegisterInfo & /*MRI*/, - const Triple &TT) { - return new MCAsmInfoImpl(TT); - } -}; - -/// RegisterMCAsmInfoFn - Helper template for registering a target assembly info -/// implementation. This invokes the specified function to do the -/// construction. Usage: -/// -/// extern "C" void LLVMInitializeFooTarget() { -/// extern Target TheFooTarget; -/// RegisterMCAsmInfoFn X(TheFooTarget, TheFunction); -/// } -struct RegisterMCAsmInfoFn { - RegisterMCAsmInfoFn(Target &T, Target::MCAsmInfoCtorFnTy Fn) { - TargetRegistry::RegisterMCAsmInfo(T, Fn); - } -}; - /// RegisterMCCodeGenInfo - Helper template for registering a target codegen /// info /// implementation. This invokes the static "Create" method on the class Index: lib/MC/MCTargetMachine.cpp =================================================================== --- lib/MC/MCTargetMachine.cpp +++ lib/MC/MCTargetMachine.cpp @@ -18,10 +18,6 @@ MCTargetMachine::MCTargetMachine(const Target &T, const Triple &TT) : TheTarget(T), TheTriple(TT) {} -MCAsmInfo *MCTargetMachine::createMCAsmInfo(const MCRegisterInfo &MRI) const { - return TheTarget.createMCAsmInfo(MRI, TheTriple.str()); -} - MCCodeGenInfo * MCTargetMachine::createMCCodeGenInfo(Reloc::Model RM, CodeModel::Model CM, CodeGenOpt::Level OL) const { Index: lib/Target/AArch64/MCTargetDesc/AArch64MCAsmInfo.h =================================================================== --- lib/Target/AArch64/MCTargetDesc/AArch64MCAsmInfo.h +++ lib/Target/AArch64/MCTargetDesc/AArch64MCAsmInfo.h @@ -19,8 +19,6 @@ namespace llvm { class MCStreamer; -class Target; -class Triple; struct AArch64MCAsmInfoDarwin : public MCAsmInfoDarwin { explicit AArch64MCAsmInfoDarwin(); @@ -30,7 +28,7 @@ }; struct AArch64MCAsmInfoELF : public MCAsmInfoELF { - explicit AArch64MCAsmInfoELF(const Triple &T); + explicit AArch64MCAsmInfoELF(bool IsLittleEndian); }; } // namespace llvm Index: lib/Target/AArch64/MCTargetDesc/AArch64MCAsmInfo.cpp =================================================================== --- lib/Target/AArch64/MCTargetDesc/AArch64MCAsmInfo.cpp +++ lib/Target/AArch64/MCTargetDesc/AArch64MCAsmInfo.cpp @@ -12,7 +12,6 @@ //===----------------------------------------------------------------------===// #include "AArch64MCAsmInfo.h" -#include "llvm/ADT/Triple.h" #include "llvm/MC/MCContext.h" #include "llvm/MC/MCExpr.h" #include "llvm/MC/MCStreamer.h" @@ -65,9 +64,8 @@ return MCBinaryExpr::createSub(Res, PC, Context); } -AArch64MCAsmInfoELF::AArch64MCAsmInfoELF(const Triple &T) { - if (T.getArch() == Triple::aarch64_be) - IsLittleEndian = false; +AArch64MCAsmInfoELF::AArch64MCAsmInfoELF(bool IsLittleEndian_) { + IsLittleEndian = IsLittleEndian_; // We prefer NEON instructions to be printed in the short form. AssemblerDialect = AsmWriterVariant == Default ? 0 : AsmWriterVariant; Index: lib/Target/AArch64/MCTargetDesc/AArch64MCTargetDesc.cpp =================================================================== --- lib/Target/AArch64/MCTargetDesc/AArch64MCTargetDesc.cpp +++ lib/Target/AArch64/MCTargetDesc/AArch64MCTargetDesc.cpp @@ -13,14 +13,13 @@ #include "AArch64MCTargetDesc.h" #include "AArch64ELFStreamer.h" -#include "AArch64MCAsmInfo.h" +#include "AArch64MCTargetMachine.h" #include "InstPrinter/AArch64InstPrinter.h" #include "llvm/MC/MCCodeGenInfo.h" #include "llvm/MC/MCInstrInfo.h" #include "llvm/MC/MCRegisterInfo.h" #include "llvm/MC/MCStreamer.h" #include "llvm/MC/MCSubtargetInfo.h" -#include "llvm/MC/MCTargetMachine.h" #include "llvm/Support/ErrorHandling.h" #include "llvm/Support/TargetRegistry.h" @@ -55,24 +54,6 @@ return X; } -static MCAsmInfo *createAArch64MCAsmInfo(const MCRegisterInfo &MRI, - const Triple &TheTriple) { - MCAsmInfo *MAI; - if (TheTriple.isOSBinFormatMachO()) - MAI = new AArch64MCAsmInfoDarwin(); - else { - assert(TheTriple.isOSBinFormatELF() && "Only expect Darwin or ELF"); - MAI = new AArch64MCAsmInfoELF(TheTriple); - } - - // Initial state of the frame pointer is SP. - unsigned Reg = MRI.getDwarfRegNum(AArch64::SP, true); - MCCFIInstruction Inst = MCCFIInstruction::createDefCfa(nullptr, Reg, 0); - MAI->addInitialFrameState(Inst); - - return MAI; -} - static MCCodeGenInfo *createAArch64MCCodeGenInfo(const Triple &TT, Reloc::Model RM, CodeModel::Model CM, @@ -137,10 +118,7 @@ extern "C" void LLVMInitializeAArch64TargetMC() { for (Target *T : {&TheAArch64leTarget, &TheAArch64beTarget, &TheARM64Target}) { - RegisterMCTargetMachine Y(*T); - - // Register the MC asm info. - RegisterMCAsmInfoFn X(*T, createAArch64MCAsmInfo); + RegisterMCTargetMachine Y(*T); // Register the MC codegen info. TargetRegistry::RegisterMCCodeGenInfo(*T, createAArch64MCCodeGenInfo); Index: lib/Target/AArch64/MCTargetDesc/AArch64MCTargetMachine.h =================================================================== --- /dev/null +++ lib/Target/AArch64/MCTargetDesc/AArch64MCTargetMachine.h @@ -0,0 +1,33 @@ +//===-- AArch64MCTargetMachine.h - Define MCTargetMachine -------*- C++ -*-===// +// +// The LLVM Compiler Infrastructure +// +// This file is distributed under the University of Illinois Open Source +// License. See LICENSE.TXT for details. +// +//===----------------------------------------------------------------------===// +// +// This file declares the AArch64 specific subclass of MCTargetMachine. +// +//===----------------------------------------------------------------------===// + +#ifndef LLVM_LIB_TARGET_AARCH64_AARCH64MCTARGETMACHINE_H +#define LLVM_LIB_TARGET_AARCH64_AARCH64MCTARGETMACHINE_H + +#include "llvm/MC/MCTargetMachine.h" + +namespace llvm { +class AArch64MCTargetMachine : public MCTargetMachine { + AArch64MCTargetMachine(const AArch64MCTargetMachine &) = delete; + void operator=(const AArch64MCTargetMachine &) = delete; + + bool IsLittleEndian; + +public: + AArch64MCTargetMachine(const Target &T, const Triple &TT); + + MCAsmInfo *createMCAsmInfo(const MCRegisterInfo &MRI) const override; +}; +} + +#endif Index: lib/Target/AArch64/MCTargetDesc/AArch64MCTargetMachine.cpp =================================================================== --- /dev/null +++ lib/Target/AArch64/MCTargetDesc/AArch64MCTargetMachine.cpp @@ -0,0 +1,45 @@ +//===-- AArch64MCTargetMachine.cpp - Define MCTargetMachine -----*- C++ -*-===// +// +// The LLVM Compiler Infrastructure +// +// This file is distributed under the University of Illinois Open Source +// License. See LICENSE.TXT for details. +// +//===----------------------------------------------------------------------===// +// +// +//===----------------------------------------------------------------------===// + +#include "AArch64MCAsmInfo.h" +#include "AArch64MCTargetMachine.h" +#include "llvm/MC/MCRegisterInfo.h" + +using namespace llvm; + +// Defines symbolic names for AArch64 registers. This defines a mapping from +// register name to register number. +#define GET_REGINFO_ENUM +#include "AArch64GenRegisterInfo.inc" + +AArch64MCTargetMachine::AArch64MCTargetMachine(const Target &T, + const Triple &TT) + : MCTargetMachine(T, TT), + IsLittleEndian(TT.getArch() != Triple::aarch64_be) {} + +MCAsmInfo * +AArch64MCTargetMachine::createMCAsmInfo(const MCRegisterInfo &MRI) const { + MCAsmInfo *MAI; + if (TheTriple.isOSBinFormatMachO()) + MAI = new AArch64MCAsmInfoDarwin(); + else { + assert(TheTriple.isOSBinFormatELF() && "Only expect Darwin or ELF"); + MAI = new AArch64MCAsmInfoELF(IsLittleEndian); + } + + // Initial state of the frame pointer is SP. + unsigned Reg = MRI.getDwarfRegNum(AArch64::SP, true); + MCCFIInstruction Inst = MCCFIInstruction::createDefCfa(nullptr, Reg, 0); + MAI->addInitialFrameState(Inst); + + return MAI; +} Index: lib/Target/AArch64/MCTargetDesc/CMakeLists.txt =================================================================== --- lib/Target/AArch64/MCTargetDesc/CMakeLists.txt +++ lib/Target/AArch64/MCTargetDesc/CMakeLists.txt @@ -6,6 +6,7 @@ AArch64MCCodeEmitter.cpp AArch64MCExpr.cpp AArch64MCTargetDesc.cpp + AArch64MCTargetMachine.cpp AArch64MachObjectWriter.cpp AArch64TargetStreamer.cpp ) Index: lib/Target/AMDGPU/MCTargetDesc/AMDGPUMCAsmInfo.h =================================================================== --- lib/Target/AMDGPU/MCTargetDesc/AMDGPUMCAsmInfo.h +++ lib/Target/AMDGPU/MCTargetDesc/AMDGPUMCAsmInfo.h @@ -15,10 +15,8 @@ #define LLVM_LIB_TARGET_R600_MCTARGETDESC_AMDGPUMCASMINFO_H #include "llvm/MC/MCAsmInfoELF.h" -namespace llvm { - -class Triple; +namespace llvm { // If you need to create another MCAsmInfo class, which inherits from MCAsmInfo, // you will need to make sure your new class sets PrivateGlobalPrefix to // a prefix that won't appear in a function name. The default value @@ -26,7 +24,7 @@ // with 'L' as a local symbol. class AMDGPUMCAsmInfo : public MCAsmInfoELF { public: - explicit AMDGPUMCAsmInfo(const Triple &TT); + explicit AMDGPUMCAsmInfo(); bool shouldOmitSectionDirective(StringRef SectionName) const override; }; } // namespace llvm Index: lib/Target/AMDGPU/MCTargetDesc/AMDGPUMCAsmInfo.cpp =================================================================== --- lib/Target/AMDGPU/MCTargetDesc/AMDGPUMCAsmInfo.cpp +++ lib/Target/AMDGPU/MCTargetDesc/AMDGPUMCAsmInfo.cpp @@ -11,7 +11,7 @@ #include "AMDGPUMCAsmInfo.h" using namespace llvm; -AMDGPUMCAsmInfo::AMDGPUMCAsmInfo(const Triple &TT) : MCAsmInfoELF() { +AMDGPUMCAsmInfo::AMDGPUMCAsmInfo() : MCAsmInfoELF() { HasSingleParameterDotFile = false; //===------------------------------------------------------------------===// MaxInstLength = 16; Index: lib/Target/AMDGPU/MCTargetDesc/AMDGPUMCTargetDesc.cpp =================================================================== --- lib/Target/AMDGPU/MCTargetDesc/AMDGPUMCTargetDesc.cpp +++ lib/Target/AMDGPU/MCTargetDesc/AMDGPUMCTargetDesc.cpp @@ -14,8 +14,8 @@ #include "AMDGPUMCTargetDesc.h" #include "AMDGPUELFStreamer.h" -#include "AMDGPUMCAsmInfo.h" #include "AMDGPUTargetStreamer.h" +#include "AMDGPUMCTargetMachine.h" #include "InstPrinter/AMDGPUInstPrinter.h" #include "SIDefines.h" #include "llvm/MC/MCCodeGenInfo.h" @@ -24,7 +24,6 @@ #include "llvm/MC/MCRegisterInfo.h" #include "llvm/MC/MCStreamer.h" #include "llvm/MC/MCSubtargetInfo.h" -#include "llvm/MC/MCTargetMachine.h" #include "llvm/MC/MachineLocation.h" #include "llvm/Support/ErrorHandling.h" #include "llvm/Support/TargetRegistry.h" @@ -98,8 +97,7 @@ extern "C" void LLVMInitializeAMDGPUTargetMC() { for (Target *T : {&TheAMDGPUTarget, &TheGCNTarget}) { - RegisterMCTargetMachine Y(*T); - RegisterMCAsmInfo X(*T); + RegisterMCTargetMachine Y(*T); TargetRegistry::RegisterMCCodeGenInfo(*T, createAMDGPUMCCodeGenInfo); TargetRegistry::RegisterMCInstrInfo(*T, createAMDGPUMCInstrInfo); Index: lib/Target/AMDGPU/MCTargetDesc/AMDGPUMCTargetMachine.h =================================================================== --- /dev/null +++ lib/Target/AMDGPU/MCTargetDesc/AMDGPUMCTargetMachine.h @@ -0,0 +1,31 @@ +//===-- AMDGPUMCTargetMachine.h - Define MCTargetMachine --------*- C++ -*-===// +// +// The LLVM Compiler Infrastructure +// +// This file is distributed under the University of Illinois Open Source +// License. See LICENSE.TXT for details. +// +//===----------------------------------------------------------------------===// +// +// This file declares the AMDGPU specific subclass of MCTargetMachine. +// +//===----------------------------------------------------------------------===// + +#ifndef LLVM_LIB_TARGET_AMDGPU_AMDGPUMCTARGETMACHINE_H +#define LLVM_LIB_TARGET_AMDGPU_AMDGPUMCTARGETMACHINE_H + +#include "llvm/MC/MCTargetMachine.h" + +namespace llvm { +class AMDGPUMCTargetMachine : public MCTargetMachine { + AMDGPUMCTargetMachine(const AMDGPUMCTargetMachine &) = delete; + void operator=(const AMDGPUMCTargetMachine &) = delete; + +public: + AMDGPUMCTargetMachine(const Target &T, const Triple &TT); + + MCAsmInfo *createMCAsmInfo(const MCRegisterInfo &MRI) const override; +}; +} + +#endif Index: lib/Target/AMDGPU/MCTargetDesc/AMDGPUMCTargetMachine.cpp =================================================================== --- /dev/null +++ lib/Target/AMDGPU/MCTargetDesc/AMDGPUMCTargetMachine.cpp @@ -0,0 +1,24 @@ +//===-- AMDGPUMCTargetMachine.cpp - Define MCTargetMachine ------*- C++ -*-===// +// +// The LLVM Compiler Infrastructure +// +// This file is distributed under the University of Illinois Open Source +// License. See LICENSE.TXT for details. +// +//===----------------------------------------------------------------------===// +// +// +//===----------------------------------------------------------------------===// + +#include "AMDGPUMCAsmInfo.h" +#include "AMDGPUMCTargetMachine.h" + +using namespace llvm; + +AMDGPUMCTargetMachine::AMDGPUMCTargetMachine(const Target &T, const Triple &TT) + : MCTargetMachine(T, TT) {} + +MCAsmInfo * +AMDGPUMCTargetMachine::createMCAsmInfo(const MCRegisterInfo &MRI) const { + return new AMDGPUMCAsmInfo(); +} Index: lib/Target/AMDGPU/MCTargetDesc/CMakeLists.txt =================================================================== --- lib/Target/AMDGPU/MCTargetDesc/CMakeLists.txt +++ lib/Target/AMDGPU/MCTargetDesc/CMakeLists.txt @@ -5,6 +5,7 @@ AMDGPUELFStreamer.cpp AMDGPUMCCodeEmitter.cpp AMDGPUMCTargetDesc.cpp + AMDGPUMCTargetMachine.cpp AMDGPUMCAsmInfo.cpp AMDGPUTargetStreamer.cpp R600MCCodeEmitter.cpp Index: lib/Target/ARM/MCTargetDesc/ARMMCAsmInfo.h =================================================================== --- lib/Target/ARM/MCTargetDesc/ARMMCAsmInfo.h +++ lib/Target/ARM/MCTargetDesc/ARMMCAsmInfo.h @@ -14,25 +14,24 @@ #ifndef LLVM_LIB_TARGET_ARM_MCTARGETDESC_ARMMCASMINFO_H #define LLVM_LIB_TARGET_ARM_MCTARGETDESC_ARMMCASMINFO_H +#include "llvm/ADT/Triple.h" #include "llvm/MC/MCAsmInfoCOFF.h" #include "llvm/MC/MCAsmInfoDarwin.h" #include "llvm/MC/MCAsmInfoELF.h" namespace llvm { -class Triple; - class ARMMCAsmInfoDarwin : public MCAsmInfoDarwin { virtual void anchor(); public: - explicit ARMMCAsmInfoDarwin(const Triple &TheTriple); + explicit ARMMCAsmInfoDarwin(bool IsLittleEndian_); }; class ARMELFMCAsmInfo : public MCAsmInfoELF { void anchor() override; public: - explicit ARMELFMCAsmInfo(const Triple &TT); + explicit ARMELFMCAsmInfo(bool IsLittleEndian_, Triple::OSType OS); void setUseIntegratedAssembler(bool Value) override; }; Index: lib/Target/ARM/MCTargetDesc/ARMMCAsmInfo.cpp =================================================================== --- lib/Target/ARM/MCTargetDesc/ARMMCAsmInfo.cpp +++ lib/Target/ARM/MCTargetDesc/ARMMCAsmInfo.cpp @@ -12,17 +12,13 @@ //===----------------------------------------------------------------------===// #include "ARMMCAsmInfo.h" -#include "llvm/ADT/Triple.h" -#include "llvm/Support/CommandLine.h" using namespace llvm; void ARMMCAsmInfoDarwin::anchor() { } -ARMMCAsmInfoDarwin::ARMMCAsmInfoDarwin(const Triple &TheTriple) { - if ((TheTriple.getArch() == Triple::armeb) || - (TheTriple.getArch() == Triple::thumbeb)) - IsLittleEndian = false; +ARMMCAsmInfoDarwin::ARMMCAsmInfoDarwin(bool IsLittleEndian_) { + IsLittleEndian = IsLittleEndian_; Data64bitsDirective = nullptr; CommentString = "@"; @@ -41,10 +37,8 @@ void ARMELFMCAsmInfo::anchor() { } -ARMELFMCAsmInfo::ARMELFMCAsmInfo(const Triple &TheTriple) { - if ((TheTriple.getArch() == Triple::armeb) || - (TheTriple.getArch() == Triple::thumbeb)) - IsLittleEndian = false; +ARMELFMCAsmInfo::ARMELFMCAsmInfo(bool IsLittleEndian_, Triple::OSType OS) { + IsLittleEndian = IsLittleEndian_; // ".comm align is in bytes but .align is pow-2." AlignmentIsInBytes = false; @@ -57,7 +51,7 @@ SupportsDebugInformation = true; // Exceptions handling - switch (TheTriple.getOS()) { + switch (OS) { case Triple::Bitrig: case Triple::NetBSD: ExceptionsType = ExceptionHandling::DwarfCFI; Index: lib/Target/ARM/MCTargetDesc/ARMMCTargetDesc.cpp =================================================================== --- lib/Target/ARM/MCTargetDesc/ARMMCTargetDesc.cpp +++ lib/Target/ARM/MCTargetDesc/ARMMCTargetDesc.cpp @@ -12,8 +12,8 @@ //===----------------------------------------------------------------------===// #include "ARMBaseInfo.h" -#include "ARMMCAsmInfo.h" #include "ARMMCTargetDesc.h" +#include "ARMMCTargetMachine.h" #include "InstPrinter/ARMInstPrinter.h" #include "llvm/ADT/Triple.h" #include "llvm/MC/MCCodeGenInfo.h" @@ -23,7 +23,6 @@ #include "llvm/MC/MCRegisterInfo.h" #include "llvm/MC/MCStreamer.h" #include "llvm/MC/MCSubtargetInfo.h" -#include "llvm/MC/MCTargetMachine.h" #include "llvm/Support/ErrorHandling.h" #include "llvm/Support/TargetParser.h" #include "llvm/Support/TargetRegistry.h" @@ -184,24 +183,6 @@ return X; } -static MCAsmInfo *createARMMCAsmInfo(const MCRegisterInfo &MRI, - const Triple &TheTriple) { - MCAsmInfo *MAI; - if (TheTriple.isOSDarwin() || TheTriple.isOSBinFormatMachO()) - MAI = new ARMMCAsmInfoDarwin(TheTriple); - else if (TheTriple.isWindowsMSVCEnvironment()) - MAI = new ARMCOFFMCAsmInfoMicrosoft(); - else if (TheTriple.isOSWindows()) - MAI = new ARMCOFFMCAsmInfoGNU(); - else - MAI = new ARMELFMCAsmInfo(TheTriple); - - unsigned Reg = MRI.getDwarfRegNum(ARM::SP, true); - MAI->addInitialFrameState(MCCFIInstruction::createDefCfa(nullptr, Reg, 0)); - - return MAI; -} - static MCCodeGenInfo *createARMMCCodeGenInfo(const Triple &TT, Reloc::Model RM, CodeModel::Model CM, CodeGenOpt::Level OL) { @@ -289,10 +270,7 @@ extern "C" void LLVMInitializeARMTargetMC() { for (Target *T : {&TheARMLETarget, &TheARMBETarget, &TheThumbLETarget, &TheThumbBETarget}) { - RegisterMCTargetMachine Y(*T); - - // Register the MC asm info. - RegisterMCAsmInfoFn X(*T, createARMMCAsmInfo); + RegisterMCTargetMachine Y(*T); // Register the MC codegen info. TargetRegistry::RegisterMCCodeGenInfo(*T, createARMMCCodeGenInfo); Index: lib/Target/ARM/MCTargetDesc/ARMMCTargetMachine.h =================================================================== --- /dev/null +++ lib/Target/ARM/MCTargetDesc/ARMMCTargetMachine.h @@ -0,0 +1,33 @@ +//===-- ARMMCTargetMachine.h - Define MCTargetMachine -----------*- C++ -*-===// +// +// The LLVM Compiler Infrastructure +// +// This file is distributed under the University of Illinois Open Source +// License. See LICENSE.TXT for details. +// +//===----------------------------------------------------------------------===// +// +// This file declares the ARM specific subclass of MCTargetMachine. +// +//===----------------------------------------------------------------------===// + +#ifndef LLVM_LIB_TARGET_ARM_ARMMCTARGETMACHINE_H +#define LLVM_LIB_TARGET_ARM_ARMMCTARGETMACHINE_H + +#include "llvm/MC/MCTargetMachine.h" + +namespace llvm { +class ARMMCTargetMachine : public MCTargetMachine { + ARMMCTargetMachine(const ARMMCTargetMachine &) = delete; + void operator=(const ARMMCTargetMachine &) = delete; + + bool IsLittleEndian; + +public: + ARMMCTargetMachine(const Target &T, const Triple &TT); + + MCAsmInfo *createMCAsmInfo(const MCRegisterInfo &MRI) const override; +}; +} + +#endif Index: lib/Target/ARM/MCTargetDesc/ARMMCTargetMachine.cpp =================================================================== --- /dev/null +++ lib/Target/ARM/MCTargetDesc/ARMMCTargetMachine.cpp @@ -0,0 +1,45 @@ +//===-- ARMMCTargetMachine.cpp - Define MCTargetMachine ---------*- C++ -*-===// +// +// The LLVM Compiler Infrastructure +// +// This file is distributed under the University of Illinois Open Source +// License. See LICENSE.TXT for details. +// +//===----------------------------------------------------------------------===// +// +// +//===----------------------------------------------------------------------===// + +#include "ARMMCAsmInfo.h" +#include "ARMMCTargetMachine.h" +#include "llvm/MC/MCRegisterInfo.h" + +using namespace llvm; + +// Defines symbolic names for ARM registers. This defines a mapping from +// register name to register number. +#define GET_REGINFO_ENUM +#include "ARMGenRegisterInfo.inc" + +ARMMCTargetMachine::ARMMCTargetMachine(const Target &T, const Triple &TT) + : MCTargetMachine(T, TT), + IsLittleEndian(TheTriple.getArch() != Triple::armeb && + TheTriple.getArch() != Triple::thumbeb) {} + +MCAsmInfo * +ARMMCTargetMachine::createMCAsmInfo(const MCRegisterInfo &MRI) const { + MCAsmInfo *MAI; + if (TheTriple.isOSDarwin() || TheTriple.isOSBinFormatMachO()) + MAI = new ARMMCAsmInfoDarwin(IsLittleEndian); + else if (TheTriple.isWindowsMSVCEnvironment()) + MAI = new ARMCOFFMCAsmInfoMicrosoft(); + else if (TheTriple.isOSWindows()) + MAI = new ARMCOFFMCAsmInfoGNU(); + else + MAI = new ARMELFMCAsmInfo(IsLittleEndian, TheTriple.getOS()); + + unsigned Reg = MRI.getDwarfRegNum(ARM::SP, true); + MAI->addInitialFrameState(MCCFIInstruction::createDefCfa(nullptr, Reg, 0)); + + return MAI; +} Index: lib/Target/ARM/MCTargetDesc/CMakeLists.txt =================================================================== --- lib/Target/ARM/MCTargetDesc/CMakeLists.txt +++ lib/Target/ARM/MCTargetDesc/CMakeLists.txt @@ -9,6 +9,7 @@ ARMMCCodeEmitter.cpp ARMMCExpr.cpp ARMMCTargetDesc.cpp + ARMMCTargetMachine.cpp ARMTargetStreamer.cpp ARMUnwindOpAsm.cpp ARMWinCOFFObjectWriter.cpp Index: lib/Target/BPF/MCTargetDesc/BPFMCAsmInfo.h =================================================================== --- lib/Target/BPF/MCTargetDesc/BPFMCAsmInfo.h +++ lib/Target/BPF/MCTargetDesc/BPFMCAsmInfo.h @@ -14,19 +14,15 @@ #ifndef LLVM_LIB_TARGET_BPF_MCTARGETDESC_BPFMCASMINFO_H #define LLVM_LIB_TARGET_BPF_MCTARGETDESC_BPFMCASMINFO_H -#include "llvm/ADT/StringRef.h" #include "llvm/MC/MCAsmInfo.h" -#include "llvm/ADT/Triple.h" namespace llvm { class Target; -class Triple; class BPFMCAsmInfo : public MCAsmInfo { public: - explicit BPFMCAsmInfo(const Triple &TT) { - if (TT.getArch() == Triple::bpfeb) - IsLittleEndian = false; + explicit BPFMCAsmInfo(bool IsLittleEndian_) { + IsLittleEndian = IsLittleEndian_; PrivateGlobalPrefix = ".L"; WeakRefDirective = "\t.weak\t"; Index: lib/Target/BPF/MCTargetDesc/BPFMCTargetDesc.cpp =================================================================== --- lib/Target/BPF/MCTargetDesc/BPFMCTargetDesc.cpp +++ lib/Target/BPF/MCTargetDesc/BPFMCTargetDesc.cpp @@ -13,14 +13,13 @@ #include "BPF.h" #include "BPFMCTargetDesc.h" -#include "BPFMCAsmInfo.h" +#include "BPFMCTargetMachine.h" #include "InstPrinter/BPFInstPrinter.h" #include "llvm/MC/MCCodeGenInfo.h" #include "llvm/MC/MCInstrInfo.h" #include "llvm/MC/MCRegisterInfo.h" #include "llvm/MC/MCStreamer.h" #include "llvm/MC/MCSubtargetInfo.h" -#include "llvm/MC/MCTargetMachine.h" #include "llvm/Support/ErrorHandling.h" #include "llvm/Support/TargetRegistry.h" @@ -79,10 +78,7 @@ extern "C" void LLVMInitializeBPFTargetMC() { for (Target *T : {&TheBPFleTarget, &TheBPFbeTarget, &TheBPFTarget}) { - RegisterMCTargetMachine Y(*T); - - // Register the MC asm info. - RegisterMCAsmInfo X(*T); + RegisterMCTargetMachine Y(*T); // Register the MC codegen info. TargetRegistry::RegisterMCCodeGenInfo(*T, createBPFMCCodeGenInfo); Index: lib/Target/BPF/MCTargetDesc/BPFMCTargetMachine.h =================================================================== --- /dev/null +++ lib/Target/BPF/MCTargetDesc/BPFMCTargetMachine.h @@ -0,0 +1,33 @@ +//===-- BPFMCTargetMachine.h - Define MCTargetMachine -----------*- C++ -*-===// +// +// The LLVM Compiler Infrastructure +// +// This file is distributed under the University of Illinois Open Source +// License. See LICENSE.TXT for details. +// +//===----------------------------------------------------------------------===// +// +// This file declares the BPF specific subclass of MCTargetMachine. +// +//===----------------------------------------------------------------------===// + +#ifndef LLVM_LIB_TARGET_BPF_BPFMCTARGETMACHINE_H +#define LLVM_LIB_TARGET_BPF_BPFMCTARGETMACHINE_H + +#include "llvm/MC/MCTargetMachine.h" + +namespace llvm { +class BPFMCTargetMachine : public MCTargetMachine { + BPFMCTargetMachine(const BPFMCTargetMachine &) = delete; + void operator=(const BPFMCTargetMachine &) = delete; + + bool IsLittleEndian; + +public: + BPFMCTargetMachine(const Target &T, const Triple &TT); + + MCAsmInfo *createMCAsmInfo(const MCRegisterInfo &MRI) const override; +}; +} + +#endif Index: lib/Target/BPF/MCTargetDesc/BPFMCTargetMachine.cpp =================================================================== --- /dev/null +++ lib/Target/BPF/MCTargetDesc/BPFMCTargetMachine.cpp @@ -0,0 +1,24 @@ +//===-- BPFMCTargetMachine.cpp - Define MCTargetMachine ---------*- C++ -*-===// +// +// The LLVM Compiler Infrastructure +// +// This file is distributed under the University of Illinois Open Source +// License. See LICENSE.TXT for details. +// +//===----------------------------------------------------------------------===// +// +// +//===----------------------------------------------------------------------===// + +#include "BPFMCAsmInfo.h" +#include "BPFMCTargetMachine.h" + +using namespace llvm; + +BPFMCTargetMachine::BPFMCTargetMachine(const Target &T, const Triple &TT) + : MCTargetMachine(T, TT), IsLittleEndian(TT.getArch() != Triple::bpfeb) {} + +MCAsmInfo * +BPFMCTargetMachine::createMCAsmInfo(const MCRegisterInfo &MRI) const { + return new BPFMCAsmInfo(IsLittleEndian); +} Index: lib/Target/BPF/MCTargetDesc/CMakeLists.txt =================================================================== --- lib/Target/BPF/MCTargetDesc/CMakeLists.txt +++ lib/Target/BPF/MCTargetDesc/CMakeLists.txt @@ -1,5 +1,6 @@ add_llvm_library(LLVMBPFDesc BPFMCTargetDesc.cpp + BPFMCTargetMachine.cpp BPFAsmBackend.cpp BPFMCCodeEmitter.cpp BPFELFObjectWriter.cpp Index: lib/Target/Hexagon/MCTargetDesc/CMakeLists.txt =================================================================== --- lib/Target/Hexagon/MCTargetDesc/CMakeLists.txt +++ lib/Target/Hexagon/MCTargetDesc/CMakeLists.txt @@ -12,6 +12,7 @@ HexagonMCInstrInfo.cpp HexagonMCShuffler.cpp HexagonMCTargetDesc.cpp + HexagonMCTargetMachine.cpp HexagonShuffler.cpp ) Index: lib/Target/Hexagon/MCTargetDesc/HexagonMCAsmInfo.h =================================================================== --- lib/Target/Hexagon/MCTargetDesc/HexagonMCAsmInfo.h +++ lib/Target/Hexagon/MCTargetDesc/HexagonMCAsmInfo.h @@ -14,17 +14,14 @@ #ifndef LLVM_LIB_TARGET_HEXAGON_MCTARGETDESC_HEXAGONMCASMINFO_H #define LLVM_LIB_TARGET_HEXAGON_MCTARGETDESC_HEXAGONMCASMINFO_H -#include "llvm/ADT/StringRef.h" #include "llvm/MC/MCAsmInfoELF.h" namespace llvm { -class Triple; - class HexagonMCAsmInfo : public MCAsmInfoELF { void anchor() override; public: - explicit HexagonMCAsmInfo(const Triple &TT); + explicit HexagonMCAsmInfo(); }; } // namespace llvm Index: lib/Target/Hexagon/MCTargetDesc/HexagonMCAsmInfo.cpp =================================================================== --- lib/Target/Hexagon/MCTargetDesc/HexagonMCAsmInfo.cpp +++ lib/Target/Hexagon/MCTargetDesc/HexagonMCAsmInfo.cpp @@ -18,7 +18,7 @@ // Pin the vtable to this file. void HexagonMCAsmInfo::anchor() {} -HexagonMCAsmInfo::HexagonMCAsmInfo(const Triple &TT) { +HexagonMCAsmInfo::HexagonMCAsmInfo() { Data16bitsDirective = "\t.half\t"; Data32bitsDirective = "\t.word\t"; Data64bitsDirective = nullptr; // .xword is only supported by V9. Index: lib/Target/Hexagon/MCTargetDesc/HexagonMCTargetDesc.cpp =================================================================== --- lib/Target/Hexagon/MCTargetDesc/HexagonMCTargetDesc.cpp +++ lib/Target/Hexagon/MCTargetDesc/HexagonMCTargetDesc.cpp @@ -13,8 +13,8 @@ #include "HexagonMCTargetDesc.h" #include "Hexagon.h" -#include "HexagonMCAsmInfo.h" #include "HexagonMCELFStreamer.h" +#include "HexagonMCTargetMachine.h" #include "MCTargetDesc/HexagonInstPrinter.h" #include "llvm/MC/MCCodeGenInfo.h" #include "llvm/MC/MCContext.h" @@ -24,7 +24,6 @@ #include "llvm/MC/MCRegisterInfo.h" #include "llvm/MC/MCStreamer.h" #include "llvm/MC/MCSubtargetInfo.h" -#include "llvm/MC/MCTargetMachine.h" #include "llvm/MC/MachineLocation.h" #include "llvm/Support/ELF.h" #include "llvm/Support/ErrorHandling.h" @@ -144,18 +143,6 @@ }; } -static MCAsmInfo *createHexagonMCAsmInfo(const MCRegisterInfo &MRI, - const Triple &TT) { - MCAsmInfo *MAI = new HexagonMCAsmInfo(TT); - - // VirtualFP = (R30 + #0). - MCCFIInstruction Inst = - MCCFIInstruction::createDefCfa(nullptr, Hexagon::R30, 0); - MAI->addInitialFrameState(Inst); - - return MAI; -} - static MCCodeGenInfo *createHexagonMCCodeGenInfo(const Triple &TT, Reloc::Model RM, CodeModel::Model CM, @@ -198,10 +185,7 @@ // Force static initialization. extern "C" void LLVMInitializeHexagonTargetMC() { - RegisterMCTargetMachine Y(TheHexagonTarget); - - // Register the MC asm info. - RegisterMCAsmInfoFn X(TheHexagonTarget, createHexagonMCAsmInfo); + RegisterMCTargetMachine Y(TheHexagonTarget); // Register the MC codegen info. TargetRegistry::RegisterMCCodeGenInfo(TheHexagonTarget, Index: lib/Target/Hexagon/MCTargetDesc/HexagonMCTargetMachine.h =================================================================== --- /dev/null +++ lib/Target/Hexagon/MCTargetDesc/HexagonMCTargetMachine.h @@ -0,0 +1,31 @@ +//===-- HexagonMCTargetMachine.h - Define MCTargetMachine -------*- C++ -*-===// +// +// The LLVM Compiler Infrastructure +// +// This file is distributed under the University of Illinois Open Source +// License. See LICENSE.TXT for details. +// +//===----------------------------------------------------------------------===// +// +// This file declares the Hexagon specific subclass of MCTargetMachine. +// +//===----------------------------------------------------------------------===// + +#ifndef LLVM_LIB_TARGET_HEXAGON_HEXAGONMCTARGETMACHINE_H +#define LLVM_LIB_TARGET_HEXAGON_HEXAGONMCTARGETMACHINE_H + +#include "llvm/MC/MCTargetMachine.h" + +namespace llvm { +class HexagonMCTargetMachine : public MCTargetMachine { + HexagonMCTargetMachine(const HexagonMCTargetMachine &) = delete; + void operator=(const HexagonMCTargetMachine &) = delete; + +public: + HexagonMCTargetMachine(const Target &T, const Triple &TT); + + MCAsmInfo *createMCAsmInfo(const MCRegisterInfo &MRI) const override; +}; +} + +#endif Index: lib/Target/Hexagon/MCTargetDesc/HexagonMCTargetMachine.cpp =================================================================== --- /dev/null +++ lib/Target/Hexagon/MCTargetDesc/HexagonMCTargetMachine.cpp @@ -0,0 +1,37 @@ +//===-- HexagonMCTargetMachine.cpp - Define MCTargetMachine -----*- C++ -*-===// +// +// The LLVM Compiler Infrastructure +// +// This file is distributed under the University of Illinois Open Source +// License. See LICENSE.TXT for details. +// +//===----------------------------------------------------------------------===// +// +// +//===----------------------------------------------------------------------===// + +#include "HexagonMCAsmInfo.h" +#include "HexagonMCTargetMachine.h" + +using namespace llvm; + +// Defines symbolic names for Hexagon registers. This defines a mapping from +// register name to register number. +#define GET_REGINFO_ENUM +#include "HexagonGenRegisterInfo.inc" + +HexagonMCTargetMachine::HexagonMCTargetMachine(const Target &T, + const Triple &TT) + : MCTargetMachine(T, TT) {} + +MCAsmInfo * +HexagonMCTargetMachine::createMCAsmInfo(const MCRegisterInfo &MRI) const { + MCAsmInfo *MAI = new HexagonMCAsmInfo(); + + // VirtualFP = (R30 + #0). + MCCFIInstruction Inst = + MCCFIInstruction::createDefCfa(nullptr, Hexagon::R30, 0); + MAI->addInitialFrameState(Inst); + + return MAI; +} Index: lib/Target/MSP430/MCTargetDesc/CMakeLists.txt =================================================================== --- lib/Target/MSP430/MCTargetDesc/CMakeLists.txt +++ lib/Target/MSP430/MCTargetDesc/CMakeLists.txt @@ -1,4 +1,5 @@ add_llvm_library(LLVMMSP430Desc MSP430MCTargetDesc.cpp + MSP430MCTargetMachine.cpp MSP430MCAsmInfo.cpp ) Index: lib/Target/MSP430/MCTargetDesc/MSP430MCAsmInfo.h =================================================================== --- lib/Target/MSP430/MCTargetDesc/MSP430MCAsmInfo.h +++ lib/Target/MSP430/MCTargetDesc/MSP430MCAsmInfo.h @@ -17,13 +17,11 @@ #include "llvm/MC/MCAsmInfoELF.h" namespace llvm { -class Triple; - class MSP430MCAsmInfo : public MCAsmInfoELF { void anchor() override; public: - explicit MSP430MCAsmInfo(const Triple &TT); + explicit MSP430MCAsmInfo(); }; } // namespace llvm Index: lib/Target/MSP430/MCTargetDesc/MSP430MCAsmInfo.cpp =================================================================== --- lib/Target/MSP430/MCTargetDesc/MSP430MCAsmInfo.cpp +++ lib/Target/MSP430/MCTargetDesc/MSP430MCAsmInfo.cpp @@ -16,7 +16,7 @@ void MSP430MCAsmInfo::anchor() { } -MSP430MCAsmInfo::MSP430MCAsmInfo(const Triple &TT) { +MSP430MCAsmInfo::MSP430MCAsmInfo() { PointerSize = CalleeSaveStackSlotSize = 2; CommentString = ";"; Index: lib/Target/MSP430/MCTargetDesc/MSP430MCTargetDesc.cpp =================================================================== --- lib/Target/MSP430/MCTargetDesc/MSP430MCTargetDesc.cpp +++ lib/Target/MSP430/MCTargetDesc/MSP430MCTargetDesc.cpp @@ -13,12 +13,11 @@ #include "MSP430MCTargetDesc.h" #include "InstPrinter/MSP430InstPrinter.h" -#include "MSP430MCAsmInfo.h" +#include "MSP430MCTargetMachine.h" #include "llvm/MC/MCCodeGenInfo.h" #include "llvm/MC/MCInstrInfo.h" #include "llvm/MC/MCRegisterInfo.h" #include "llvm/MC/MCSubtargetInfo.h" -#include "llvm/MC/MCTargetMachine.h" #include "llvm/Support/TargetRegistry.h" using namespace llvm; @@ -69,10 +68,7 @@ } extern "C" void LLVMInitializeMSP430TargetMC() { - RegisterMCTargetMachine Y(TheMSP430Target); - - // Register the MC asm info. - RegisterMCAsmInfo X(TheMSP430Target); + RegisterMCTargetMachine Y(TheMSP430Target); // Register the MC codegen info. TargetRegistry::RegisterMCCodeGenInfo(TheMSP430Target, Index: lib/Target/MSP430/MCTargetDesc/MSP430MCTargetMachine.h =================================================================== --- /dev/null +++ lib/Target/MSP430/MCTargetDesc/MSP430MCTargetMachine.h @@ -0,0 +1,31 @@ +//===-- MSP430MCTargetMachine.h - Define MCTargetMachine --------*- C++ -*-===// +// +// The LLVM Compiler Infrastructure +// +// This file is distributed under the University of Illinois Open Source +// License. See LICENSE.TXT for details. +// +//===----------------------------------------------------------------------===// +// +// This file declares the MSP430 specific subclass of MCTargetMachine. +// +//===----------------------------------------------------------------------===// + +#ifndef LLVM_LIB_TARGET_MSP430_MSP430MCTARGETMACHINE_H +#define LLVM_LIB_TARGET_MSP430_MSP430MCTARGETMACHINE_H + +#include "llvm/MC/MCTargetMachine.h" + +namespace llvm { +class MSP430MCTargetMachine : public MCTargetMachine { + MSP430MCTargetMachine(const MSP430MCTargetMachine &) = delete; + void operator=(const MSP430MCTargetMachine &) = delete; + +public: + MSP430MCTargetMachine(const Target &T, const Triple &TT); + + MCAsmInfo *createMCAsmInfo(const MCRegisterInfo &MRI) const override; +}; +} + +#endif Index: lib/Target/MSP430/MCTargetDesc/MSP430MCTargetMachine.cpp =================================================================== --- lib/Target/MSP430/MCTargetDesc/MSP430MCTargetMachine.cpp +++ lib/Target/MSP430/MCTargetDesc/MSP430MCTargetMachine.cpp @@ -1,4 +1,4 @@ -//===-- MSP430MCAsmInfo.cpp - MSP430 asm properties -----------------------===// +//===-- MSP430MCTargetMachine.cpp - Define MCTargetMachine ------*- C++ -*-===// // // The LLVM Compiler Infrastructure // @@ -7,20 +7,18 @@ // //===----------------------------------------------------------------------===// // -// This file contains the declarations of the MSP430MCAsmInfo properties. // //===----------------------------------------------------------------------===// #include "MSP430MCAsmInfo.h" -using namespace llvm; - -void MSP430MCAsmInfo::anchor() { } +#include "MSP430MCTargetMachine.h" -MSP430MCAsmInfo::MSP430MCAsmInfo(const Triple &TT) { - PointerSize = CalleeSaveStackSlotSize = 2; +using namespace llvm; - CommentString = ";"; +MSP430MCTargetMachine::MSP430MCTargetMachine(const Target &T, const Triple &TT) + : MCTargetMachine(T, TT) {} - AlignmentIsInBytes = false; - UsesELFSectionDirectiveForBSS = true; +MCAsmInfo * +MSP430MCTargetMachine::createMCAsmInfo(const MCRegisterInfo &MRI) const { + return new MSP430MCAsmInfo(); } Index: lib/Target/Mips/MCTargetDesc/CMakeLists.txt =================================================================== --- lib/Target/Mips/MCTargetDesc/CMakeLists.txt +++ lib/Target/Mips/MCTargetDesc/CMakeLists.txt @@ -8,6 +8,7 @@ MipsMCCodeEmitter.cpp MipsMCExpr.cpp MipsMCTargetDesc.cpp + MipsMCTargetMachine.cpp MipsNaClELFStreamer.cpp MipsOptionRecord.cpp MipsTargetStreamer.cpp Index: lib/Target/Mips/MCTargetDesc/MipsMCAsmInfo.h =================================================================== --- lib/Target/Mips/MCTargetDesc/MipsMCAsmInfo.h +++ lib/Target/Mips/MCTargetDesc/MipsMCAsmInfo.h @@ -17,13 +17,11 @@ #include "llvm/MC/MCAsmInfoELF.h" namespace llvm { -class Triple; - class MipsMCAsmInfo : public MCAsmInfoELF { void anchor() override; public: - explicit MipsMCAsmInfo(const Triple &TheTriple); + explicit MipsMCAsmInfo(bool IsLittleEndian_, bool IsArch64Bit); }; } // namespace llvm Index: lib/Target/Mips/MCTargetDesc/MipsMCAsmInfo.cpp =================================================================== --- lib/Target/Mips/MCTargetDesc/MipsMCAsmInfo.cpp +++ lib/Target/Mips/MCTargetDesc/MipsMCAsmInfo.cpp @@ -12,21 +12,21 @@ //===----------------------------------------------------------------------===// #include "MipsMCAsmInfo.h" -#include "llvm/ADT/Triple.h" using namespace llvm; void MipsMCAsmInfo::anchor() { } -MipsMCAsmInfo::MipsMCAsmInfo(const Triple &TheTriple) { - if ((TheTriple.getArch() == Triple::mips) || - (TheTriple.getArch() == Triple::mips64)) - IsLittleEndian = false; +MipsMCAsmInfo::MipsMCAsmInfo(bool IsLittleEndian_, bool IsArch64Bit) { + IsLittleEndian = IsLittleEndian_; - if ((TheTriple.getArch() == Triple::mips64el) || - (TheTriple.getArch() == Triple::mips64)) { - PointerSize = CalleeSaveStackSlotSize = 8; - } + // FIXME: This should use MipsABIInfo::ArePtrs64bit(). + if (IsArch64Bit) + PointerSize = 8; + + // FIXME: This should use MipsABIInfo::AreGprs64bit(). + if (IsArch64Bit) + CalleeSaveStackSlotSize = 8; AlignmentIsInBytes = false; Data16bitsDirective = "\t.2byte\t"; Index: lib/Target/Mips/MCTargetDesc/MipsMCTargetDesc.cpp =================================================================== --- lib/Target/Mips/MCTargetDesc/MipsMCTargetDesc.cpp +++ lib/Target/Mips/MCTargetDesc/MipsMCTargetDesc.cpp @@ -13,9 +13,9 @@ #include "InstPrinter/MipsInstPrinter.h" #include "MipsELFStreamer.h" -#include "MipsMCAsmInfo.h" #include "MipsMCNaCl.h" #include "MipsMCTargetDesc.h" +#include "MipsMCTargetMachine.h" #include "MipsTargetStreamer.h" #include "llvm/ADT/Triple.h" #include "llvm/MC/MCCodeGenInfo.h" @@ -23,7 +23,6 @@ #include "llvm/MC/MCInstrInfo.h" #include "llvm/MC/MCRegisterInfo.h" #include "llvm/MC/MCSubtargetInfo.h" -#include "llvm/MC/MCTargetMachine.h" #include "llvm/MC/MCSymbol.h" #include "llvm/MC/MachineLocation.h" #include "llvm/Support/CommandLine.h" @@ -72,17 +71,6 @@ return createMipsMCSubtargetInfoImpl(TT, CPU, FS); } -static MCAsmInfo *createMipsMCAsmInfo(const MCRegisterInfo &MRI, - const Triple &TT) { - MCAsmInfo *MAI = new MipsMCAsmInfo(TT); - - unsigned SP = MRI.getDwarfRegNum(Mips::SP, true); - MCCFIInstruction Inst = MCCFIInstruction::createDefCfa(nullptr, SP, 0); - MAI->addInitialFrameState(Inst); - - return MAI; -} - static MCCodeGenInfo *createMipsMCCodeGenInfo(const Triple &TT, Reloc::Model RM, CodeModel::Model CM, CodeGenOpt::Level OL) { @@ -133,10 +121,7 @@ extern "C" void LLVMInitializeMipsTargetMC() { for (Target *T : {&TheMipsTarget, &TheMipselTarget, &TheMips64Target, &TheMips64elTarget}) { - RegisterMCTargetMachine Y(*T); - - // Register the MC asm info. - RegisterMCAsmInfoFn X(*T, createMipsMCAsmInfo); + RegisterMCTargetMachine Y(*T); // Register the MC codegen info. TargetRegistry::RegisterMCCodeGenInfo(*T, createMipsMCCodeGenInfo); Index: lib/Target/Mips/MCTargetDesc/MipsMCTargetMachine.h =================================================================== --- /dev/null +++ lib/Target/Mips/MCTargetDesc/MipsMCTargetMachine.h @@ -0,0 +1,34 @@ +//===-- MipsMCTargetMachine.h - Define MCTargetMachine ----------*- C++ -*-===// +// +// The LLVM Compiler Infrastructure +// +// This file is distributed under the University of Illinois Open Source +// License. See LICENSE.TXT for details. +// +//===----------------------------------------------------------------------===// +// +// This file declares the Mips specific subclass of MCTargetMachine. +// +//===----------------------------------------------------------------------===// + +#ifndef LLVM_LIB_TARGET_MIPS_MIPSMCTARGETMACHINE_H +#define LLVM_LIB_TARGET_MIPS_MIPSMCTARGETMACHINE_H + +#include "llvm/MC/MCTargetMachine.h" + +namespace llvm { +class MipsMCTargetMachine : public MCTargetMachine { + MipsMCTargetMachine(const MipsMCTargetMachine &) = delete; + void operator=(const MipsMCTargetMachine &) = delete; + + bool IsLittleEndian; + bool IsArch64Bit; + +public: + MipsMCTargetMachine(const Target &T, const Triple &TT); + + MCAsmInfo *createMCAsmInfo(const MCRegisterInfo &MRI) const override; +}; +} + +#endif Index: lib/Target/Mips/MCTargetDesc/MipsMCTargetMachine.cpp =================================================================== --- /dev/null +++ lib/Target/Mips/MCTargetDesc/MipsMCTargetMachine.cpp @@ -0,0 +1,42 @@ +//===-- MipsMCTargetMachine.cpp - Define MCTargetMachine --------*- C++ -*-===// +// +// The LLVM Compiler Infrastructure +// +// This file is distributed under the University of Illinois Open Source +// License. See LICENSE.TXT for details. +// +//===----------------------------------------------------------------------===// +// +// +//===----------------------------------------------------------------------===// + +#include "MipsMCAsmInfo.h" +#include "MipsMCTargetMachine.h" +#include "llvm/MC/MCRegisterInfo.h" + +using namespace llvm; + +// Defines symbolic names for Mips registers. This defines a mapping from +// register name to register number. +#define GET_REGINFO_ENUM +#include "MipsGenRegisterInfo.inc" + +MipsMCTargetMachine::MipsMCTargetMachine(const Target &T, const Triple &TT) + : MCTargetMachine(T, TT), IsLittleEndian(TT.getArch() != Triple::mips && + TT.getArch() != Triple::mips64), + // FIXME: This is incorrect but it preserves existing behaviour for now. + // We want to use the ABI instead but we must have clang pass an + // initialized MCTargetOptions first. + IsArch64Bit(TT.getArch() == Triple::mips64 || + TT.getArch() == Triple::mips64el) {} + +MCAsmInfo * +MipsMCTargetMachine::createMCAsmInfo(const MCRegisterInfo &MRI) const { + MCAsmInfo *MAI = new MipsMCAsmInfo(IsLittleEndian, IsArch64Bit); + + unsigned SP = MRI.getDwarfRegNum(Mips::SP, true); + MCCFIInstruction Inst = MCCFIInstruction::createDefCfa(nullptr, SP, 0); + MAI->addInitialFrameState(Inst); + + return MAI; +} Index: lib/Target/NVPTX/MCTargetDesc/CMakeLists.txt =================================================================== --- lib/Target/NVPTX/MCTargetDesc/CMakeLists.txt +++ lib/Target/NVPTX/MCTargetDesc/CMakeLists.txt @@ -1,4 +1,5 @@ add_llvm_library(LLVMNVPTXDesc NVPTXMCAsmInfo.cpp NVPTXMCTargetDesc.cpp + NVPTXMCTargetMachine.cpp ) Index: lib/Target/NVPTX/MCTargetDesc/NVPTXMCAsmInfo.h =================================================================== --- lib/Target/NVPTX/MCTargetDesc/NVPTXMCAsmInfo.h +++ lib/Target/NVPTX/MCTargetDesc/NVPTXMCAsmInfo.h @@ -17,14 +17,11 @@ #include "llvm/MC/MCAsmInfo.h" namespace llvm { -class Target; -class Triple; - class NVPTXMCAsmInfo : public MCAsmInfo { virtual void anchor(); public: - explicit NVPTXMCAsmInfo(const Triple &TheTriple); + explicit NVPTXMCAsmInfo(bool IsArch64Bit); }; } // namespace llvm Index: lib/Target/NVPTX/MCTargetDesc/NVPTXMCAsmInfo.cpp =================================================================== --- lib/Target/NVPTX/MCTargetDesc/NVPTXMCAsmInfo.cpp +++ lib/Target/NVPTX/MCTargetDesc/NVPTXMCAsmInfo.cpp @@ -12,7 +12,6 @@ //===----------------------------------------------------------------------===// #include "NVPTXMCAsmInfo.h" -#include "llvm/ADT/Triple.h" #include "llvm/Support/CommandLine.h" using namespace llvm; @@ -25,10 +24,9 @@ void NVPTXMCAsmInfo::anchor() {} -NVPTXMCAsmInfo::NVPTXMCAsmInfo(const Triple &TheTriple) { - if (TheTriple.getArch() == Triple::nvptx64) { +NVPTXMCAsmInfo::NVPTXMCAsmInfo(bool IsArch64Bit) { + if (IsArch64Bit) PointerSize = CalleeSaveStackSlotSize = 8; - } CommentString = "//"; Index: lib/Target/NVPTX/MCTargetDesc/NVPTXMCTargetDesc.cpp =================================================================== --- lib/Target/NVPTX/MCTargetDesc/NVPTXMCTargetDesc.cpp +++ lib/Target/NVPTX/MCTargetDesc/NVPTXMCTargetDesc.cpp @@ -13,12 +13,11 @@ #include "NVPTXMCTargetDesc.h" #include "InstPrinter/NVPTXInstPrinter.h" -#include "NVPTXMCAsmInfo.h" +#include "NVPTXMCTargetMachine.h" #include "llvm/MC/MCCodeGenInfo.h" #include "llvm/MC/MCInstrInfo.h" #include "llvm/MC/MCRegisterInfo.h" #include "llvm/MC/MCSubtargetInfo.h" -#include "llvm/MC/MCTargetMachine.h" #include "llvm/Support/TargetRegistry.h" using namespace llvm; @@ -75,10 +74,7 @@ // Force static initialization. extern "C" void LLVMInitializeNVPTXTargetMC() { for (Target *T : {&TheNVPTXTarget32, &TheNVPTXTarget64}) { - RegisterMCTargetMachine Y(*T); - - // Register the MC asm info. - RegisterMCAsmInfo X(*T); + RegisterMCTargetMachine Y(*T); // Register the MC codegen info. TargetRegistry::RegisterMCCodeGenInfo(*T, createNVPTXMCCodeGenInfo); Index: lib/Target/NVPTX/MCTargetDesc/NVPTXMCTargetMachine.h =================================================================== --- /dev/null +++ lib/Target/NVPTX/MCTargetDesc/NVPTXMCTargetMachine.h @@ -0,0 +1,33 @@ +//===-- NVPTXMCTargetMachine.h - Define MCTargetMachine ---------*- C++ -*-===// +// +// The LLVM Compiler Infrastructure +// +// This file is distributed under the University of Illinois Open Source +// License. See LICENSE.TXT for details. +// +//===----------------------------------------------------------------------===// +// +// This file declares the NVPTX specific subclass of MCTargetMachine. +// +//===----------------------------------------------------------------------===// + +#ifndef LLVM_LIB_TARGET_NVPTX_NVPTXMCTARGETMACHINE_H +#define LLVM_LIB_TARGET_NVPTX_NVPTXMCTARGETMACHINE_H + +#include "llvm/MC/MCTargetMachine.h" + +namespace llvm { +class NVPTXMCTargetMachine : public MCTargetMachine { + NVPTXMCTargetMachine(const NVPTXMCTargetMachine &) = delete; + void operator=(const NVPTXMCTargetMachine &) = delete; + + bool IsArch64Bit; + +public: + NVPTXMCTargetMachine(const Target &T, const Triple &TT); + + MCAsmInfo *createMCAsmInfo(const MCRegisterInfo &MRI) const override; +}; +} + +#endif Index: lib/Target/NVPTX/MCTargetDesc/NVPTXMCTargetMachine.cpp =================================================================== --- /dev/null +++ lib/Target/NVPTX/MCTargetDesc/NVPTXMCTargetMachine.cpp @@ -0,0 +1,24 @@ +//===-- NVPTXMCTargetMachine.cpp - Define MCTargetMachine -------*- C++ -*-===// +// +// The LLVM Compiler Infrastructure +// +// This file is distributed under the University of Illinois Open Source +// License. See LICENSE.TXT for details. +// +//===----------------------------------------------------------------------===// +// +// +//===----------------------------------------------------------------------===// + +#include "NVPTXMCAsmInfo.h" +#include "NVPTXMCTargetMachine.h" + +using namespace llvm; + +NVPTXMCTargetMachine::NVPTXMCTargetMachine(const Target &T, const Triple &TT) + : MCTargetMachine(T, TT), IsArch64Bit(TT.getArch() == Triple::nvptx64) {} + +MCAsmInfo * +NVPTXMCTargetMachine::createMCAsmInfo(const MCRegisterInfo &MRI) const { + return new NVPTXMCAsmInfo(IsArch64Bit); +} Index: lib/Target/PowerPC/MCTargetDesc/CMakeLists.txt =================================================================== --- lib/Target/PowerPC/MCTargetDesc/CMakeLists.txt +++ lib/Target/PowerPC/MCTargetDesc/CMakeLists.txt @@ -1,6 +1,7 @@ add_llvm_library(LLVMPowerPCDesc PPCAsmBackend.cpp PPCMCTargetDesc.cpp + PPCMCTargetMachine.cpp PPCMCAsmInfo.cpp PPCMCCodeEmitter.cpp PPCMCExpr.cpp Index: lib/Target/PowerPC/MCTargetDesc/PPCMCAsmInfo.h =================================================================== --- lib/Target/PowerPC/MCTargetDesc/PPCMCAsmInfo.h +++ lib/Target/PowerPC/MCTargetDesc/PPCMCAsmInfo.h @@ -18,20 +18,18 @@ #include "llvm/MC/MCAsmInfoELF.h" namespace llvm { -class Triple; - class PPCMCAsmInfoDarwin : public MCAsmInfoDarwin { virtual void anchor(); public: - explicit PPCMCAsmInfoDarwin(bool is64Bit, const Triple &); + explicit PPCMCAsmInfoDarwin(bool Is64Bit, bool IsMacOSXVersionLt10_6); }; class PPCELFMCAsmInfo : public MCAsmInfoELF { void anchor() override; public: - explicit PPCELFMCAsmInfo(bool is64Bit, const Triple &); + explicit PPCELFMCAsmInfo(bool Is64Bit, bool IsLittleEndian_); }; } // namespace llvm Index: lib/Target/PowerPC/MCTargetDesc/PPCMCAsmInfo.cpp =================================================================== --- lib/Target/PowerPC/MCTargetDesc/PPCMCAsmInfo.cpp +++ lib/Target/PowerPC/MCTargetDesc/PPCMCAsmInfo.cpp @@ -12,31 +12,27 @@ //===----------------------------------------------------------------------===// #include "PPCMCAsmInfo.h" -#include "llvm/ADT/Triple.h" using namespace llvm; void PPCMCAsmInfoDarwin::anchor() { } -PPCMCAsmInfoDarwin::PPCMCAsmInfoDarwin(bool is64Bit, const Triple& T) { - if (is64Bit) { +PPCMCAsmInfoDarwin::PPCMCAsmInfoDarwin(bool Is64Bit, + bool IsMacOSXVersionLt10_6) { + if (Is64Bit) PointerSize = CalleeSaveStackSlotSize = 8; - } IsLittleEndian = false; CommentString = ";"; ExceptionsType = ExceptionHandling::DwarfCFI; - if (!is64Bit) + if (!Is64Bit) Data64bitsDirective = nullptr; // We can't emit a 64-bit unit in PPC32 mode. AssemblerDialect = 1; // New-Style mnemonics. SupportsDebugInformation= true; // Debug information. - // The installed assembler for OSX < 10.6 lacks some directives. - // FIXME: this should really be a check on the assembler characteristics - // rather than OS version - if (T.isMacOSX() && T.isMacOSXVersionLT(10, 6)) + if (IsMacOSXVersionLt10_6) HasWeakDefCanBeHiddenDirective = false; UseIntegratedAssembler = true; @@ -44,15 +40,14 @@ void PPCELFMCAsmInfo::anchor() { } -PPCELFMCAsmInfo::PPCELFMCAsmInfo(bool is64Bit, const Triple& T) { +PPCELFMCAsmInfo::PPCELFMCAsmInfo(bool Is64Bit, bool IsLittleEndian_) { // FIXME: This is not always needed. For example, it is not needed in the // v2 abi. NeedsLocalForSize = true; - if (is64Bit) { + if (Is64Bit) PointerSize = CalleeSaveStackSlotSize = 8; - } - IsLittleEndian = T.getArch() == Triple::ppc64le; + IsLittleEndian = IsLittleEndian_; // ".comm align is in bytes but .align is pow-2." AlignmentIsInBytes = false; @@ -74,7 +69,7 @@ ExceptionsType = ExceptionHandling::DwarfCFI; ZeroDirective = "\t.space\t"; - Data64bitsDirective = is64Bit ? "\t.quad\t" : nullptr; + Data64bitsDirective = Is64Bit ? "\t.quad\t" : nullptr; AssemblerDialect = 1; // New-Style mnemonics. LCOMMDirectiveAlignmentType = LCOMM::ByteAlignment; Index: lib/Target/PowerPC/MCTargetDesc/PPCMCTargetDesc.cpp =================================================================== --- lib/Target/PowerPC/MCTargetDesc/PPCMCTargetDesc.cpp +++ lib/Target/PowerPC/MCTargetDesc/PPCMCTargetDesc.cpp @@ -13,7 +13,7 @@ #include "PPCMCTargetDesc.h" #include "InstPrinter/PPCInstPrinter.h" -#include "PPCMCAsmInfo.h" +#include "PPCMCTargetMachine.h" #include "PPCTargetStreamer.h" #include "llvm/MC/MCCodeGenInfo.h" #include "llvm/MC/MCContext.h" @@ -23,7 +23,6 @@ #include "llvm/MC/MCRegisterInfo.h" #include "llvm/MC/MCStreamer.h" #include "llvm/MC/MCSubtargetInfo.h" -#include "llvm/MC/MCTargetMachine.h" #include "llvm/MC/MCSymbolELF.h" #include "llvm/MC/MachineLocation.h" #include "llvm/Support/ELF.h" @@ -68,26 +67,6 @@ return createPPCMCSubtargetInfoImpl(TT, CPU, FS); } -static MCAsmInfo *createPPCMCAsmInfo(const MCRegisterInfo &MRI, - const Triple &TheTriple) { - bool isPPC64 = (TheTriple.getArch() == Triple::ppc64 || - TheTriple.getArch() == Triple::ppc64le); - - MCAsmInfo *MAI; - if (TheTriple.isOSDarwin()) - MAI = new PPCMCAsmInfoDarwin(isPPC64, TheTriple); - else - MAI = new PPCELFMCAsmInfo(isPPC64, TheTriple); - - // Initial state of the frame pointer is R1. - unsigned Reg = isPPC64 ? PPC::X1 : PPC::R1; - MCCFIInstruction Inst = - MCCFIInstruction::createDefCfa(nullptr, MRI.getDwarfRegNum(Reg, true), 0); - MAI->addInitialFrameState(Inst); - - return MAI; -} - static MCCodeGenInfo *createPPCMCCodeGenInfo(const Triple &TT, Reloc::Model RM, CodeModel::Model CM, CodeGenOpt::Level OL) { @@ -242,10 +221,7 @@ extern "C" void LLVMInitializePowerPCTargetMC() { for (Target *T : {&ThePPC32Target, &ThePPC64Target, &ThePPC64LETarget}) { - RegisterMCTargetMachine Y(*T); - - // Register the MC asm info. - RegisterMCAsmInfoFn C(*T, createPPCMCAsmInfo); + RegisterMCTargetMachine Y(*T); // Register the MC codegen info. TargetRegistry::RegisterMCCodeGenInfo(*T, createPPCMCCodeGenInfo); Index: lib/Target/PowerPC/MCTargetDesc/PPCMCTargetMachine.h =================================================================== --- /dev/null +++ lib/Target/PowerPC/MCTargetDesc/PPCMCTargetMachine.h @@ -0,0 +1,34 @@ +//===-- PPCMCTargetMachine.h - Define MCTargetMachine -----------*- C++ -*-===// +// +// The LLVM Compiler Infrastructure +// +// This file is distributed under the University of Illinois Open Source +// License. See LICENSE.TXT for details. +// +//===----------------------------------------------------------------------===// +// +// This file declares the PowerPC specific subclass of MCTargetMachine. +// +//===----------------------------------------------------------------------===// + +#ifndef LLVM_LIB_TARGET_POWERPC_PPCMCTARGETMACHINE_H +#define LLVM_LIB_TARGET_POWERPC_PPCMCTARGETMACHINE_H + +#include "llvm/MC/MCTargetMachine.h" + +namespace llvm { +class PPCMCTargetMachine : public MCTargetMachine { + PPCMCTargetMachine(const PPCMCTargetMachine &) = delete; + void operator=(const PPCMCTargetMachine &) = delete; + + bool IsPPC64; + bool IsLittleEndian; + +public: + PPCMCTargetMachine(const Target &T, const Triple &TT); + + MCAsmInfo *createMCAsmInfo(const MCRegisterInfo &MRI) const override; +}; +} + +#endif Index: lib/Target/PowerPC/MCTargetDesc/PPCMCTargetMachine.cpp =================================================================== --- /dev/null +++ lib/Target/PowerPC/MCTargetDesc/PPCMCTargetMachine.cpp @@ -0,0 +1,48 @@ +//===-- PPCMCTargetMachine.cpp - Define MCTargetMachine ---------*- C++ -*-===// +// +// The LLVM Compiler Infrastructure +// +// This file is distributed under the University of Illinois Open Source +// License. See LICENSE.TXT for details. +// +//===----------------------------------------------------------------------===// +// +// +//===----------------------------------------------------------------------===// + +#include "PPCMCAsmInfo.h" +#include "PPCMCTargetMachine.h" +#include "llvm/MC/MCRegisterInfo.h" + +using namespace llvm; + +// Defines symbolic names for PowerPC registers. This defines a mapping from +// register name to register number. +#define GET_REGINFO_ENUM +#include "PPCGenRegisterInfo.inc" + +PPCMCTargetMachine::PPCMCTargetMachine(const Target &T, const Triple &TT) + : MCTargetMachine(T, TT), + IsPPC64(TT.getArch() == Triple::ppc64 || TT.getArch() == Triple::ppc64le), + IsLittleEndian(TT.getArch() == Triple::ppc64le) {} + +MCAsmInfo * +PPCMCTargetMachine::createMCAsmInfo(const MCRegisterInfo &MRI) const { + MCAsmInfo *MAI; + if (TheTriple.isOSDarwin()) { + // The installed assembler for OSX < 10.6 lacks some directives. + // FIXME: this should really be a check on the assembler characteristics + // rather than OS version + MAI = new PPCMCAsmInfoDarwin( + IsPPC64, TheTriple.isMacOSX() && TheTriple.isMacOSXVersionLT(10, 6)); + } else + MAI = new PPCELFMCAsmInfo(IsPPC64, IsLittleEndian); + + // Initial state of the frame pointer is R1. + unsigned Reg = IsPPC64 ? PPC::X1 : PPC::R1; + MCCFIInstruction Inst = + MCCFIInstruction::createDefCfa(nullptr, MRI.getDwarfRegNum(Reg, true), 0); + MAI->addInitialFrameState(Inst); + + return MAI; +} Index: lib/Target/Sparc/MCTargetDesc/CMakeLists.txt =================================================================== --- lib/Target/Sparc/MCTargetDesc/CMakeLists.txt +++ lib/Target/Sparc/MCTargetDesc/CMakeLists.txt @@ -4,6 +4,7 @@ SparcMCAsmInfo.cpp SparcMCCodeEmitter.cpp SparcMCTargetDesc.cpp + SparcMCTargetMachine.cpp SparcMCExpr.cpp SparcTargetStreamer.cpp ) Index: lib/Target/Sparc/MCTargetDesc/SparcMCAsmInfo.h =================================================================== --- lib/Target/Sparc/MCTargetDesc/SparcMCAsmInfo.h +++ lib/Target/Sparc/MCTargetDesc/SparcMCAsmInfo.h @@ -17,13 +17,11 @@ #include "llvm/MC/MCAsmInfoELF.h" namespace llvm { -class Triple; - class SparcELFMCAsmInfo : public MCAsmInfoELF { void anchor() override; public: - explicit SparcELFMCAsmInfo(const Triple &TheTriple); + explicit SparcELFMCAsmInfo(bool IsV9, bool IsLittleEndian_); const MCExpr* getExprForPersonalitySymbol(const MCSymbol *Sym, unsigned Encoding, MCStreamer &Streamer) const override; Index: lib/Target/Sparc/MCTargetDesc/SparcMCAsmInfo.cpp =================================================================== --- lib/Target/Sparc/MCTargetDesc/SparcMCAsmInfo.cpp +++ lib/Target/Sparc/MCTargetDesc/SparcMCAsmInfo.cpp @@ -13,25 +13,22 @@ #include "SparcMCAsmInfo.h" #include "SparcMCExpr.h" -#include "llvm/ADT/Triple.h" #include "llvm/MC/MCStreamer.h" using namespace llvm; void SparcELFMCAsmInfo::anchor() {} -SparcELFMCAsmInfo::SparcELFMCAsmInfo(const Triple &TheTriple) { - bool isV9 = (TheTriple.getArch() == Triple::sparcv9); - IsLittleEndian = (TheTriple.getArch() == Triple::sparcel); +SparcELFMCAsmInfo::SparcELFMCAsmInfo(bool IsV9, bool IsLittleEndian_) { + IsLittleEndian = IsLittleEndian_; - if (isV9) { + if (IsV9) PointerSize = CalleeSaveStackSlotSize = 8; - } Data16bitsDirective = "\t.half\t"; Data32bitsDirective = "\t.word\t"; // .xword is only supported by V9. - Data64bitsDirective = (isV9) ? "\t.xword\t" : nullptr; + Data64bitsDirective = IsV9 ? "\t.xword\t" : nullptr; ZeroDirective = "\t.skip\t"; CommentString = "!"; SupportsDebugInformation = true; Index: lib/Target/Sparc/MCTargetDesc/SparcMCTargetDesc.cpp =================================================================== --- lib/Target/Sparc/MCTargetDesc/SparcMCTargetDesc.cpp +++ lib/Target/Sparc/MCTargetDesc/SparcMCTargetDesc.cpp @@ -13,13 +13,12 @@ #include "SparcMCTargetDesc.h" #include "InstPrinter/SparcInstPrinter.h" -#include "SparcMCAsmInfo.h" +#include "SparcMCTargetMachine.h" #include "SparcTargetStreamer.h" #include "llvm/MC/MCCodeGenInfo.h" #include "llvm/MC/MCInstrInfo.h" #include "llvm/MC/MCRegisterInfo.h" #include "llvm/MC/MCSubtargetInfo.h" -#include "llvm/MC/MCTargetMachine.h" #include "llvm/Support/ErrorHandling.h" #include "llvm/Support/TargetRegistry.h" @@ -34,24 +33,6 @@ #define GET_REGINFO_MC_DESC #include "SparcGenRegisterInfo.inc" -static MCAsmInfo *createSparcMCAsmInfo(const MCRegisterInfo &MRI, - const Triple &TT) { - MCAsmInfo *MAI = new SparcELFMCAsmInfo(TT); - unsigned Reg = MRI.getDwarfRegNum(SP::O6, true); - MCCFIInstruction Inst = MCCFIInstruction::createDefCfa(nullptr, Reg, 0); - MAI->addInitialFrameState(Inst); - return MAI; -} - -static MCAsmInfo *createSparcV9MCAsmInfo(const MCRegisterInfo &MRI, - const Triple &TT) { - MCAsmInfo *MAI = new SparcELFMCAsmInfo(TT); - unsigned Reg = MRI.getDwarfRegNum(SP::O6, true); - MCCFIInstruction Inst = MCCFIInstruction::createDefCfa(nullptr, Reg, 2047); - MAI->addInitialFrameState(Inst); - return MAI; -} - static MCInstrInfo *createSparcMCInstrInfo() { MCInstrInfo *X = new MCInstrInfo(); InitSparcMCInstrInfo(X); @@ -143,13 +124,8 @@ } extern "C" void LLVMInitializeSparcTargetMC() { - // Register the MC asm info. - RegisterMCAsmInfoFn X(TheSparcTarget, createSparcMCAsmInfo); - RegisterMCAsmInfoFn Y(TheSparcV9Target, createSparcV9MCAsmInfo); - RegisterMCAsmInfoFn Z(TheSparcelTarget, createSparcMCAsmInfo); - for (Target *T : {&TheSparcTarget, &TheSparcV9Target, &TheSparcelTarget}) { - RegisterMCTargetMachine Y(*T); + RegisterMCTargetMachine Y(*T); // Register the MC instruction info. TargetRegistry::RegisterMCInstrInfo(*T, createSparcMCInstrInfo); Index: lib/Target/Sparc/MCTargetDesc/SparcMCTargetMachine.h =================================================================== --- /dev/null +++ lib/Target/Sparc/MCTargetDesc/SparcMCTargetMachine.h @@ -0,0 +1,34 @@ +//===-- SparcMCTargetMachine.h - Define MCTargetMachine ---------*- C++ -*-===// +// +// The LLVM Compiler Infrastructure +// +// This file is distributed under the University of Illinois Open Source +// License. See LICENSE.TXT for details. +// +//===----------------------------------------------------------------------===// +// +// This file declares the Sparc specific subclass of MCTargetMachine. +// +//===----------------------------------------------------------------------===// + +#ifndef LLVM_LIB_TARGET_SPARC_SPARCMCTARGETMACHINE_H +#define LLVM_LIB_TARGET_SPARC_SPARCMCTARGETMACHINE_H + +#include "llvm/MC/MCTargetMachine.h" + +namespace llvm { +class SparcMCTargetMachine : public MCTargetMachine { + SparcMCTargetMachine(const SparcMCTargetMachine &) = delete; + void operator=(const SparcMCTargetMachine &) = delete; + + bool IsV9; + bool IsLittleEndian; + +public: + SparcMCTargetMachine(const Target &T, const Triple &TT); + + MCAsmInfo *createMCAsmInfo(const MCRegisterInfo &MRI) const override; +}; +} + +#endif Index: lib/Target/Sparc/MCTargetDesc/SparcMCTargetMachine.cpp =================================================================== --- /dev/null +++ lib/Target/Sparc/MCTargetDesc/SparcMCTargetMachine.cpp @@ -0,0 +1,36 @@ +//===-- SparcMCTargetMachine.cpp - Define MCTargetMachine -------*- C++ -*-===// +// +// The LLVM Compiler Infrastructure +// +// This file is distributed under the University of Illinois Open Source +// License. See LICENSE.TXT for details. +// +//===----------------------------------------------------------------------===// +// +// +//===----------------------------------------------------------------------===// + +#include "SparcMCAsmInfo.h" +#include "SparcMCTargetMachine.h" +#include "llvm/MC/MCRegisterInfo.h" + +using namespace llvm; + +// Defines symbolic names for Sparc registers. This defines a mapping from +// register name to register number. +#define GET_REGINFO_ENUM +#include "SparcGenRegisterInfo.inc" + +SparcMCTargetMachine::SparcMCTargetMachine(const Target &T, const Triple &TT) + : MCTargetMachine(T, TT), IsV9(TT.getArch() == Triple::sparcv9), + IsLittleEndian(TheTriple.getArch() == Triple::sparcel) {} + +MCAsmInfo * +SparcMCTargetMachine::createMCAsmInfo(const MCRegisterInfo &MRI) const { + MCAsmInfo *MAI = new SparcELFMCAsmInfo(IsV9, IsLittleEndian); + unsigned Reg = MRI.getDwarfRegNum(SP::O6, true); + MCCFIInstruction Inst = + MCCFIInstruction::createDefCfa(nullptr, Reg, IsV9 ? 2047 : 0); + MAI->addInitialFrameState(Inst); + return MAI; +} Index: lib/Target/SystemZ/MCTargetDesc/CMakeLists.txt =================================================================== --- lib/Target/SystemZ/MCTargetDesc/CMakeLists.txt +++ lib/Target/SystemZ/MCTargetDesc/CMakeLists.txt @@ -4,4 +4,5 @@ SystemZMCCodeEmitter.cpp SystemZMCObjectWriter.cpp SystemZMCTargetDesc.cpp + SystemZMCTargetMachine.cpp ) Index: lib/Target/SystemZ/MCTargetDesc/SystemZMCAsmInfo.h =================================================================== --- lib/Target/SystemZ/MCTargetDesc/SystemZMCAsmInfo.h +++ lib/Target/SystemZ/MCTargetDesc/SystemZMCAsmInfo.h @@ -11,14 +11,11 @@ #define LLVM_LIB_TARGET_SYSTEMZ_MCTARGETDESC_SYSTEMZMCASMINFO_H #include "llvm/MC/MCAsmInfoELF.h" -#include "llvm/Support/Compiler.h" namespace llvm { -class Triple; - class SystemZMCAsmInfo : public MCAsmInfoELF { public: - explicit SystemZMCAsmInfo(const Triple &TT); + explicit SystemZMCAsmInfo(); }; } // end namespace llvm Index: lib/Target/SystemZ/MCTargetDesc/SystemZMCAsmInfo.cpp =================================================================== --- lib/Target/SystemZ/MCTargetDesc/SystemZMCAsmInfo.cpp +++ lib/Target/SystemZ/MCTargetDesc/SystemZMCAsmInfo.cpp @@ -8,12 +8,11 @@ //===----------------------------------------------------------------------===// #include "SystemZMCAsmInfo.h" -#include "llvm/MC/MCContext.h" #include "llvm/MC/MCSectionELF.h" using namespace llvm; -SystemZMCAsmInfo::SystemZMCAsmInfo(const Triple &TT) { +SystemZMCAsmInfo::SystemZMCAsmInfo() { PointerSize = 8; CalleeSaveStackSlotSize = 8; IsLittleEndian = false; Index: lib/Target/SystemZ/MCTargetDesc/SystemZMCTargetDesc.cpp =================================================================== --- lib/Target/SystemZ/MCTargetDesc/SystemZMCTargetDesc.cpp +++ lib/Target/SystemZ/MCTargetDesc/SystemZMCTargetDesc.cpp @@ -9,13 +9,12 @@ #include "SystemZMCTargetDesc.h" #include "InstPrinter/SystemZInstPrinter.h" -#include "SystemZMCAsmInfo.h" +#include "SystemZMCTargetMachine.h" #include "llvm/MC/MCCodeGenInfo.h" #include "llvm/MC/MCInstrInfo.h" #include "llvm/MC/MCRegisterInfo.h" #include "llvm/MC/MCStreamer.h" #include "llvm/MC/MCSubtargetInfo.h" -#include "llvm/MC/MCTargetMachine.h" #include "llvm/Support/TargetRegistry.h" using namespace llvm; @@ -132,17 +131,6 @@ return Map[Reg]; } -static MCAsmInfo *createSystemZMCAsmInfo(const MCRegisterInfo &MRI, - const Triple &TT) { - MCAsmInfo *MAI = new SystemZMCAsmInfo(TT); - MCCFIInstruction Inst = - MCCFIInstruction::createDefCfa(nullptr, - MRI.getDwarfRegNum(SystemZ::R15D, true), - SystemZMC::CFAOffsetFromInitialSP); - MAI->addInitialFrameState(Inst); - return MAI; -} - static MCInstrInfo *createSystemZMCInstrInfo() { MCInstrInfo *X = new MCInstrInfo(); InitSystemZMCInstrInfo(X); @@ -217,11 +205,7 @@ } extern "C" void LLVMInitializeSystemZTargetMC() { - RegisterMCTargetMachine Y(TheSystemZTarget); - - // Register the MCAsmInfo. - TargetRegistry::RegisterMCAsmInfo(TheSystemZTarget, - createSystemZMCAsmInfo); + RegisterMCTargetMachine Y(TheSystemZTarget); // Register the MCCodeGenInfo. TargetRegistry::RegisterMCCodeGenInfo(TheSystemZTarget, Index: lib/Target/SystemZ/MCTargetDesc/SystemZMCTargetMachine.h =================================================================== --- /dev/null +++ lib/Target/SystemZ/MCTargetDesc/SystemZMCTargetMachine.h @@ -0,0 +1,31 @@ +//===-- SystemZMCTargetMachine.h - Define MCTargetMachine -------*- C++ -*-===// +// +// The LLVM Compiler Infrastructure +// +// This file is distributed under the University of Illinois Open Source +// License. See LICENSE.TXT for details. +// +//===----------------------------------------------------------------------===// +// +// This file declares the SystemZ specific subclass of MCTargetMachine. +// +//===----------------------------------------------------------------------===// + +#ifndef LLVM_LIB_TARGET_SYSTEMZ_SYSTEMZMCTARGETMACHINE_H +#define LLVM_LIB_TARGET_SYSTEMZ_SYSTEMZMCTARGETMACHINE_H + +#include "llvm/MC/MCTargetMachine.h" + +namespace llvm { +class SystemZMCTargetMachine : public MCTargetMachine { + SystemZMCTargetMachine(const SystemZMCTargetMachine &) = delete; + void operator=(const SystemZMCTargetMachine &) = delete; + +public: + SystemZMCTargetMachine(const Target &T, const Triple &TT); + + MCAsmInfo *createMCAsmInfo(const MCRegisterInfo &MRI) const override; +}; +} + +#endif Index: lib/Target/SystemZ/MCTargetDesc/SystemZMCTargetMachine.cpp =================================================================== --- /dev/null +++ lib/Target/SystemZ/MCTargetDesc/SystemZMCTargetMachine.cpp @@ -0,0 +1,32 @@ +//===-- SystemZMCTargetMachine.cpp - Define MCTargetMachine -----*- C++ -*-===// +// +// The LLVM Compiler Infrastructure +// +// This file is distributed under the University of Illinois Open Source +// License. See LICENSE.TXT for details. +// +//===----------------------------------------------------------------------===// +// +// +//===----------------------------------------------------------------------===// + +#include "SystemZMCAsmInfo.h" +#include "SystemZMCTargetDesc.h" +#include "SystemZMCTargetMachine.h" +#include "llvm/MC/MCRegisterInfo.h" + +using namespace llvm; + +SystemZMCTargetMachine::SystemZMCTargetMachine(const Target &T, + const Triple &TT) + : MCTargetMachine(T, TT) {} + +MCAsmInfo * +SystemZMCTargetMachine::createMCAsmInfo(const MCRegisterInfo &MRI) const { + MCAsmInfo *MAI = new SystemZMCAsmInfo(); + MCCFIInstruction Inst = MCCFIInstruction::createDefCfa( + nullptr, MRI.getDwarfRegNum(SystemZ::R15D, true), + SystemZMC::CFAOffsetFromInitialSP); + MAI->addInitialFrameState(Inst); + return MAI; +} Index: lib/Target/WebAssembly/MCTargetDesc/CMakeLists.txt =================================================================== --- lib/Target/WebAssembly/MCTargetDesc/CMakeLists.txt +++ lib/Target/WebAssembly/MCTargetDesc/CMakeLists.txt @@ -1,4 +1,5 @@ add_llvm_library(LLVMWebAssemblyDesc WebAssemblyMCAsmInfo.cpp WebAssemblyMCTargetDesc.cpp + WebAssemblyMCTargetMachine.cpp ) Index: lib/Target/WebAssembly/MCTargetDesc/WebAssemblyMCAsmInfo.h =================================================================== --- lib/Target/WebAssembly/MCTargetDesc/WebAssemblyMCAsmInfo.h +++ lib/Target/WebAssembly/MCTargetDesc/WebAssemblyMCAsmInfo.h @@ -18,12 +18,9 @@ #include "llvm/MC/MCAsmInfo.h" namespace llvm { - -class Triple; - class WebAssemblyMCAsmInfo final : public MCAsmInfo { public: - explicit WebAssemblyMCAsmInfo(const Triple &T); + explicit WebAssemblyMCAsmInfo(bool IsArch64Bit); ~WebAssemblyMCAsmInfo() override; }; Index: lib/Target/WebAssembly/MCTargetDesc/WebAssemblyMCAsmInfo.cpp =================================================================== --- lib/Target/WebAssembly/MCTargetDesc/WebAssemblyMCAsmInfo.cpp +++ lib/Target/WebAssembly/MCTargetDesc/WebAssemblyMCAsmInfo.cpp @@ -14,7 +14,6 @@ //===----------------------------------------------------------------------===// #include "WebAssemblyMCAsmInfo.h" -#include "llvm/ADT/Triple.h" #include "llvm/Support/CommandLine.h" using namespace llvm; @@ -22,8 +21,8 @@ WebAssemblyMCAsmInfo::~WebAssemblyMCAsmInfo() {} -WebAssemblyMCAsmInfo::WebAssemblyMCAsmInfo(const Triple &T) { - PointerSize = CalleeSaveStackSlotSize = T.isArch64Bit() ? 8 : 4; +WebAssemblyMCAsmInfo::WebAssemblyMCAsmInfo(bool IsArch64Bit) { + PointerSize = CalleeSaveStackSlotSize = IsArch64Bit ? 8 : 4; // TODO: What should MaxInstLength be? Index: lib/Target/WebAssembly/MCTargetDesc/WebAssemblyMCTargetDesc.cpp =================================================================== --- lib/Target/WebAssembly/MCTargetDesc/WebAssemblyMCTargetDesc.cpp +++ lib/Target/WebAssembly/MCTargetDesc/WebAssemblyMCTargetDesc.cpp @@ -14,13 +14,12 @@ #include "WebAssemblyMCTargetDesc.h" #include "InstPrinter/WebAssemblyInstPrinter.h" -#include "WebAssemblyMCAsmInfo.h" +#include "WebAssemblyMCTargetMachine.h" #include "llvm/MC/MCCodeGenInfo.h" #include "llvm/MC/MCInstrInfo.h" #include "llvm/MC/MCRegisterInfo.h" #include "llvm/MC/MCStreamer.h" #include "llvm/MC/MCSubtargetInfo.h" -#include "llvm/MC/MCTargetMachine.h" #include "llvm/Support/ErrorHandling.h" #include "llvm/Support/TargetRegistry.h" using namespace llvm; @@ -36,11 +35,6 @@ #define GET_REGINFO_MC_DESC #include "WebAssemblyGenRegisterInfo.inc" -static MCAsmInfo *createWebAssemblyMCAsmInfo(const MCRegisterInfo &MRI, - const Triple &TT) { - return new WebAssemblyMCAsmInfo(TT); -} - static MCInstrInfo *createWebAssemblyMCInstrInfo() { MCInstrInfo *X = new MCInstrInfo(); InitWebAssemblyMCInstrInfo(X); @@ -58,10 +52,7 @@ // Force static initialization. extern "C" void LLVMInitializeWebAssemblyTargetMC() { for (Target *T : {&TheWebAssemblyTarget32, &TheWebAssemblyTarget64}) { - RegisterMCTargetMachine Y(*T); - - // Register the MC asm info. - RegisterMCAsmInfoFn X(*T, createWebAssemblyMCAsmInfo); + RegisterMCTargetMachine Y(*T); // Register the MC instruction info. TargetRegistry::RegisterMCInstrInfo(*T, createWebAssemblyMCInstrInfo); Index: lib/Target/WebAssembly/MCTargetDesc/WebAssemblyMCTargetMachine.h =================================================================== --- /dev/null +++ lib/Target/WebAssembly/MCTargetDesc/WebAssemblyMCTargetMachine.h @@ -0,0 +1,33 @@ +//===-- WebAssemblyMCTargetMachine.h - Define MCTargetMachine ---*- C++ -*-===// +// +// The LLVM Compiler Infrastructure +// +// This file is distributed under the University of Illinois Open Source +// License. See LICENSE.TXT for details. +// +//===----------------------------------------------------------------------===// +// +// This file declares the WebAssembly specific subclass of MCTargetMachine. +// +//===----------------------------------------------------------------------===// + +#ifndef LLVM_LIB_TARGET_WEBASSEMBLY_WEBASSEMBLYMCTARGETMACHINE_H +#define LLVM_LIB_TARGET_WEBASSEMBLY_WEBASSEMBLYMCTARGETMACHINE_H + +#include "llvm/MC/MCTargetMachine.h" + +namespace llvm { +class WebAssemblyMCTargetMachine : public MCTargetMachine { + WebAssemblyMCTargetMachine(const WebAssemblyMCTargetMachine &) = delete; + void operator=(const WebAssemblyMCTargetMachine &) = delete; + + bool IsArch64Bit; + +public: + WebAssemblyMCTargetMachine(const Target &T, const Triple &TT); + + MCAsmInfo *createMCAsmInfo(const MCRegisterInfo &MRI) const override; +}; +} + +#endif Index: lib/Target/WebAssembly/MCTargetDesc/WebAssemblyMCTargetMachine.cpp =================================================================== --- /dev/null +++ lib/Target/WebAssembly/MCTargetDesc/WebAssemblyMCTargetMachine.cpp @@ -0,0 +1,25 @@ +//===-- WebAssemblyMCTargetMachine.cpp - Define MCTargetMachine -*- C++ -*-===// +// +// The LLVM Compiler Infrastructure +// +// This file is distributed under the University of Illinois Open Source +// License. See LICENSE.TXT for details. +// +//===----------------------------------------------------------------------===// +// +// +//===----------------------------------------------------------------------===// + +#include "WebAssemblyMCAsmInfo.h" +#include "WebAssemblyMCTargetMachine.h" + +using namespace llvm; + +WebAssemblyMCTargetMachine::WebAssemblyMCTargetMachine(const Target &T, + const Triple &TT) + : MCTargetMachine(T, TT), IsArch64Bit(TT.isArch64Bit()) {} + +MCAsmInfo * +WebAssemblyMCTargetMachine::createMCAsmInfo(const MCRegisterInfo &MRI) const { + return new WebAssemblyMCAsmInfo(IsArch64Bit); +} Index: lib/Target/X86/MCTargetDesc/CMakeLists.txt =================================================================== --- lib/Target/X86/MCTargetDesc/CMakeLists.txt +++ lib/Target/X86/MCTargetDesc/CMakeLists.txt @@ -1,6 +1,7 @@ add_llvm_library(LLVMX86Desc X86AsmBackend.cpp X86MCTargetDesc.cpp + X86MCTargetMachine.cpp X86MCAsmInfo.cpp X86MCCodeEmitter.cpp X86MachObjectWriter.cpp Index: lib/Target/X86/MCTargetDesc/X86MCAsmInfo.h =================================================================== --- lib/Target/X86/MCTargetDesc/X86MCAsmInfo.h +++ lib/Target/X86/MCTargetDesc/X86MCAsmInfo.h @@ -20,17 +20,15 @@ #include "llvm/MC/MCAsmInfoELF.h" namespace llvm { -class Triple; - class X86MCAsmInfoDarwin : public MCAsmInfoDarwin { virtual void anchor(); public: - explicit X86MCAsmInfoDarwin(const Triple &Triple); + explicit X86MCAsmInfoDarwin(bool Is64Bit, bool IsMacOSXVersionLt10_6); }; struct X86_64MCAsmInfoDarwin : public X86MCAsmInfoDarwin { - explicit X86_64MCAsmInfoDarwin(const Triple &Triple); + explicit X86_64MCAsmInfoDarwin(bool Is64Bit, bool IsMacOSXVersionLt10_6); const MCExpr * getExprForPersonalitySymbol(const MCSymbol *Sym, unsigned Encoding, MCStreamer &Streamer) const override; @@ -40,21 +38,21 @@ void anchor() override; public: - explicit X86ELFMCAsmInfo(const Triple &Triple); + explicit X86ELFMCAsmInfo(bool Is64Bit, bool IsX32); }; class X86MCAsmInfoMicrosoft : public MCAsmInfoMicrosoft { void anchor() override; public: - explicit X86MCAsmInfoMicrosoft(const Triple &Triple); + explicit X86MCAsmInfoMicrosoft(bool Is64Bit); }; class X86MCAsmInfoGNUCOFF : public MCAsmInfoGNUCOFF { void anchor() override; public: - explicit X86MCAsmInfoGNUCOFF(const Triple &Triple); + explicit X86MCAsmInfoGNUCOFF(bool Is64Bit); }; } // namespace llvm Index: lib/Target/X86/MCTargetDesc/X86MCAsmInfo.cpp =================================================================== --- lib/Target/X86/MCTargetDesc/X86MCAsmInfo.cpp +++ lib/Target/X86/MCTargetDesc/X86MCAsmInfo.cpp @@ -12,7 +12,6 @@ //===----------------------------------------------------------------------===// #include "X86MCAsmInfo.h" -#include "llvm/ADT/Triple.h" #include "llvm/MC/MCContext.h" #include "llvm/MC/MCExpr.h" #include "llvm/MC/MCSectionELF.h" @@ -41,16 +40,16 @@ void X86MCAsmInfoDarwin::anchor() { } -X86MCAsmInfoDarwin::X86MCAsmInfoDarwin(const Triple &T) { - bool is64Bit = T.getArch() == Triple::x86_64; - if (is64Bit) +X86MCAsmInfoDarwin::X86MCAsmInfoDarwin(bool Is64Bit, + bool IsMacOSXVersionLt10_6) { + if (Is64Bit) PointerSize = CalleeSaveStackSlotSize = 8; AssemblerDialect = AsmWriterFlavor; TextAlignFillValue = 0x90; - if (!is64Bit) + if (!Is64Bit) Data64bitsDirective = nullptr; // we can't emit a 64-bit unit // Use ## as a comment string so that .s files generated by llvm can go @@ -69,7 +68,7 @@ // old assembler lacks some directives // FIXME: this should really be a check on the assembler characteristics // rather than OS version - if (T.isMacOSX() && T.isMacOSXVersionLT(10, 6)) + if (IsMacOSXVersionLt10_6) HasWeakDefCanBeHiddenDirective = false; // Assume ld64 is new enough that the abs-ified FDE relocs may be used @@ -80,23 +79,20 @@ UseIntegratedAssembler = true; } -X86_64MCAsmInfoDarwin::X86_64MCAsmInfoDarwin(const Triple &Triple) - : X86MCAsmInfoDarwin(Triple) { -} +X86_64MCAsmInfoDarwin::X86_64MCAsmInfoDarwin(bool Is64Bit, + bool IsMacOSXVersionLt10_6) + : X86MCAsmInfoDarwin(Is64Bit, IsMacOSXVersionLt10_6) {} void X86ELFMCAsmInfo::anchor() { } -X86ELFMCAsmInfo::X86ELFMCAsmInfo(const Triple &T) { - bool is64Bit = T.getArch() == Triple::x86_64; - bool isX32 = T.getEnvironment() == Triple::GNUX32; - +X86ELFMCAsmInfo::X86ELFMCAsmInfo(bool Is64Bit, bool IsX32) { // For ELF, x86-64 pointer size depends on the ABI. // For x86-64 without the x32 ABI, pointer size is 8. For x86 and for x86-64 // with the x32 ABI, pointer size remains the default 4. - PointerSize = (is64Bit && !isX32) ? 8 : 4; + PointerSize = (Is64Bit && !IsX32) ? 8 : 4; // OTOH, stack slot size is always 8 for x86-64, even with the x32 ABI. - CalleeSaveStackSlotSize = is64Bit ? 8 : 4; + CalleeSaveStackSlotSize = Is64Bit ? 8 : 4; AssemblerDialect = AsmWriterFlavor; @@ -126,8 +122,8 @@ void X86MCAsmInfoMicrosoft::anchor() { } -X86MCAsmInfoMicrosoft::X86MCAsmInfoMicrosoft(const Triple &Triple) { - if (Triple.getArch() == Triple::x86_64) { +X86MCAsmInfoMicrosoft::X86MCAsmInfoMicrosoft(bool Is64Bit) { + if (Is64Bit) { PrivateGlobalPrefix = ".L"; PrivateLabelPrefix = ".L"; PointerSize = 8; @@ -152,9 +148,8 @@ void X86MCAsmInfoGNUCOFF::anchor() { } -X86MCAsmInfoGNUCOFF::X86MCAsmInfoGNUCOFF(const Triple &Triple) { - assert(Triple.isOSWindows() && "Windows is the only supported COFF target"); - if (Triple.getArch() == Triple::x86_64) { +X86MCAsmInfoGNUCOFF::X86MCAsmInfoGNUCOFF(bool Is64Bit) { + if (Is64Bit) { PrivateGlobalPrefix = ".L"; PrivateLabelPrefix = ".L"; PointerSize = 8; Index: lib/Target/X86/MCTargetDesc/X86MCTargetDesc.cpp =================================================================== --- lib/Target/X86/MCTargetDesc/X86MCTargetDesc.cpp +++ lib/Target/X86/MCTargetDesc/X86MCTargetDesc.cpp @@ -14,7 +14,7 @@ #include "X86MCTargetDesc.h" #include "InstPrinter/X86ATTInstPrinter.h" #include "InstPrinter/X86IntelInstPrinter.h" -#include "X86MCAsmInfo.h" +#include "X86MCTargetMachine.h" #include "llvm/ADT/Triple.h" #include "llvm/MC/MCCodeGenInfo.h" #include "llvm/MC/MCInstrAnalysis.h" @@ -22,7 +22,6 @@ #include "llvm/MC/MCRegisterInfo.h" #include "llvm/MC/MCStreamer.h" #include "llvm/MC/MCSubtargetInfo.h" -#include "llvm/MC/MCTargetMachine.h" #include "llvm/MC/MachineLocation.h" #include "llvm/Support/ErrorHandling.h" #include "llvm/Support/Host.h" @@ -110,49 +109,6 @@ return X; } -static MCAsmInfo *createX86MCAsmInfo(const MCRegisterInfo &MRI, - const Triple &TheTriple) { - bool is64Bit = TheTriple.getArch() == Triple::x86_64; - - MCAsmInfo *MAI; - if (TheTriple.isOSBinFormatMachO()) { - if (is64Bit) - MAI = new X86_64MCAsmInfoDarwin(TheTriple); - else - MAI = new X86MCAsmInfoDarwin(TheTriple); - } else if (TheTriple.isOSBinFormatELF()) { - // Force the use of an ELF container. - MAI = new X86ELFMCAsmInfo(TheTriple); - } else if (TheTriple.isWindowsMSVCEnvironment() || - TheTriple.isWindowsCoreCLREnvironment()) { - MAI = new X86MCAsmInfoMicrosoft(TheTriple); - } else if (TheTriple.isOSCygMing() || - TheTriple.isWindowsItaniumEnvironment()) { - MAI = new X86MCAsmInfoGNUCOFF(TheTriple); - } else { - // The default is ELF. - MAI = new X86ELFMCAsmInfo(TheTriple); - } - - // Initialize initial frame state. - // Calculate amount of bytes used for return address storing - int stackGrowth = is64Bit ? -8 : -4; - - // Initial state of the frame pointer is esp+stackGrowth. - unsigned StackPtr = is64Bit ? X86::RSP : X86::ESP; - MCCFIInstruction Inst = MCCFIInstruction::createDefCfa( - nullptr, MRI.getDwarfRegNum(StackPtr, true), -stackGrowth); - MAI->addInitialFrameState(Inst); - - // Add return address to move list - unsigned InstPtr = is64Bit ? X86::RIP : X86::EIP; - MCCFIInstruction Inst2 = MCCFIInstruction::createOffset( - nullptr, MRI.getDwarfRegNum(InstPtr, true), stackGrowth); - MAI->addInitialFrameState(Inst2); - - return MAI; -} - static MCCodeGenInfo *createX86MCCodeGenInfo(const Triple &TT, Reloc::Model RM, CodeModel::Model CM, CodeGenOpt::Level OL) { @@ -231,10 +187,7 @@ // Force static initialization. extern "C" void LLVMInitializeX86TargetMC() { for (Target *T : {&TheX86_32Target, &TheX86_64Target}) { - RegisterMCTargetMachine Z(*T); - - // Register the MC asm info. - RegisterMCAsmInfoFn X(*T, createX86MCAsmInfo); + RegisterMCTargetMachine Z(*T); // Register the MC codegen info. RegisterMCCodeGenInfoFn Y(*T, createX86MCCodeGenInfo); Index: lib/Target/X86/MCTargetDesc/X86MCTargetMachine.h =================================================================== --- /dev/null +++ lib/Target/X86/MCTargetDesc/X86MCTargetMachine.h @@ -0,0 +1,33 @@ +//===-- X86MCTargetMachine.h - Define MCTargetMachine -----------*- C++ -*-===// +// +// The LLVM Compiler Infrastructure +// +// This file is distributed under the University of Illinois Open Source +// License. See LICENSE.TXT for details. +// +//===----------------------------------------------------------------------===// +// +// This file declares the X86 specific subclass of MCTargetMachine. +// +//===----------------------------------------------------------------------===// + +#ifndef LLVM_LIB_TARGET_X86_X86MCTARGETMACHINE_H +#define LLVM_LIB_TARGET_X86_X86MCTARGETMACHINE_H + +#include "llvm/MC/MCTargetMachine.h" + +namespace llvm { +class X86MCTargetMachine : public MCTargetMachine { + X86MCTargetMachine(const X86MCTargetMachine &) = delete; + void operator=(const X86MCTargetMachine &) = delete; + + bool Is64Bit; + +public: + X86MCTargetMachine(const Target &T, const Triple &TT); + + MCAsmInfo *createMCAsmInfo(const MCRegisterInfo &MRI) const override; +}; +} + +#endif Index: lib/Target/X86/MCTargetDesc/X86MCTargetMachine.cpp =================================================================== --- /dev/null +++ lib/Target/X86/MCTargetDesc/X86MCTargetMachine.cpp @@ -0,0 +1,72 @@ +//===-- X86MCTargetMachine.cpp - Define MCTargetMachine ---------*- C++ -*-===// +// +// The LLVM Compiler Infrastructure +// +// This file is distributed under the University of Illinois Open Source +// License. See LICENSE.TXT for details. +// +//===----------------------------------------------------------------------===// +// +// +//===----------------------------------------------------------------------===// + +#include "X86MCAsmInfo.h" +#include "X86MCTargetMachine.h" +#include "llvm/MC/MCRegisterInfo.h" + +using namespace llvm; + +// Defines symbolic names for X86 registers. This defines a mapping from +// register name to register number. +#define GET_REGINFO_ENUM +#include "X86GenRegisterInfo.inc" + +X86MCTargetMachine::X86MCTargetMachine(const Target &T, const Triple &TT) + : MCTargetMachine(T, TT), Is64Bit(TheTriple.getArch() == Triple::x86_64) {} + +MCAsmInfo * +X86MCTargetMachine::createMCAsmInfo(const MCRegisterInfo &MRI) const { + bool IsX32 = TheTriple.getEnvironment() == Triple::GNUX32; + MCAsmInfo *MAI; + + if (TheTriple.isOSBinFormatMachO()) { + bool IsMacOSXVersionLt10_6 = + TheTriple.isMacOSX() && TheTriple.isMacOSXVersionLT(10, 6); + if (Is64Bit) + MAI = new X86_64MCAsmInfoDarwin(Is64Bit, IsMacOSXVersionLt10_6); + else + MAI = new X86MCAsmInfoDarwin(Is64Bit, IsMacOSXVersionLt10_6); + } else if (TheTriple.isOSBinFormatELF()) { + // Force the use of an ELF container. + MAI = new X86ELFMCAsmInfo(Is64Bit, IsX32); + } else if (TheTriple.isWindowsMSVCEnvironment() || + TheTriple.isWindowsCoreCLREnvironment()) { + MAI = new X86MCAsmInfoMicrosoft(Is64Bit); + } else if (TheTriple.isOSCygMing() || + TheTriple.isWindowsItaniumEnvironment()) { + assert(TheTriple.isOSWindows() && + "Windows is the only supported COFF target"); + MAI = new X86MCAsmInfoGNUCOFF(Is64Bit); + } else { + // The default is ELF. + MAI = new X86ELFMCAsmInfo(Is64Bit, IsX32); + } + + // Initialize initial frame state. + // Calculate amount of bytes used for return address storing + int stackGrowth = Is64Bit ? -8 : -4; + + // Initial state of the frame pointer is esp+stackGrowth. + unsigned StackPtr = Is64Bit ? X86::RSP : X86::ESP; + MCCFIInstruction Inst = MCCFIInstruction::createDefCfa( + nullptr, MRI.getDwarfRegNum(StackPtr, true), -stackGrowth); + MAI->addInitialFrameState(Inst); + + // Add return address to move list + unsigned InstPtr = Is64Bit ? X86::RIP : X86::EIP; + MCCFIInstruction Inst2 = MCCFIInstruction::createOffset( + nullptr, MRI.getDwarfRegNum(InstPtr, true), stackGrowth); + MAI->addInitialFrameState(Inst2); + + return MAI; +} Index: lib/Target/XCore/MCTargetDesc/CMakeLists.txt =================================================================== --- lib/Target/XCore/MCTargetDesc/CMakeLists.txt +++ lib/Target/XCore/MCTargetDesc/CMakeLists.txt @@ -1,4 +1,5 @@ add_llvm_library(LLVMXCoreDesc XCoreMCTargetDesc.cpp + XCoreMCTargetMachine.cpp XCoreMCAsmInfo.cpp ) Index: lib/Target/XCore/MCTargetDesc/XCoreMCAsmInfo.h =================================================================== --- lib/Target/XCore/MCTargetDesc/XCoreMCAsmInfo.h +++ lib/Target/XCore/MCTargetDesc/XCoreMCAsmInfo.h @@ -17,13 +17,11 @@ #include "llvm/MC/MCAsmInfoELF.h" namespace llvm { -class Triple; - class XCoreMCAsmInfo : public MCAsmInfoELF { void anchor() override; public: - explicit XCoreMCAsmInfo(const Triple &TT); + explicit XCoreMCAsmInfo(); }; } // namespace llvm Index: lib/Target/XCore/MCTargetDesc/XCoreMCAsmInfo.cpp =================================================================== --- lib/Target/XCore/MCTargetDesc/XCoreMCAsmInfo.cpp +++ lib/Target/XCore/MCTargetDesc/XCoreMCAsmInfo.cpp @@ -12,7 +12,7 @@ void XCoreMCAsmInfo::anchor() { } -XCoreMCAsmInfo::XCoreMCAsmInfo(const Triple &TT) { +XCoreMCAsmInfo::XCoreMCAsmInfo() { SupportsDebugInformation = true; Data16bitsDirective = "\t.short\t"; Data32bitsDirective = "\t.long\t"; Index: lib/Target/XCore/MCTargetDesc/XCoreMCTargetDesc.cpp =================================================================== --- lib/Target/XCore/MCTargetDesc/XCoreMCTargetDesc.cpp +++ lib/Target/XCore/MCTargetDesc/XCoreMCTargetDesc.cpp @@ -13,13 +13,12 @@ #include "XCoreMCTargetDesc.h" #include "InstPrinter/XCoreInstPrinter.h" -#include "XCoreMCAsmInfo.h" +#include "XCoreMCTargetMachine.h" #include "XCoreTargetStreamer.h" #include "llvm/MC/MCCodeGenInfo.h" #include "llvm/MC/MCInstrInfo.h" #include "llvm/MC/MCRegisterInfo.h" #include "llvm/MC/MCSubtargetInfo.h" -#include "llvm/MC/MCTargetMachine.h" #include "llvm/Support/ErrorHandling.h" #include "llvm/Support/FormattedStream.h" #include "llvm/Support/TargetRegistry.h" @@ -52,17 +51,6 @@ return createXCoreMCSubtargetInfoImpl(TT, CPU, FS); } -static MCAsmInfo *createXCoreMCAsmInfo(const MCRegisterInfo &MRI, - const Triple &TT) { - MCAsmInfo *MAI = new XCoreMCAsmInfo(TT); - - // Initial state of the frame pointer is SP. - MCCFIInstruction Inst = MCCFIInstruction::createDefCfa(nullptr, XCore::SP, 0); - MAI->addInitialFrameState(Inst); - - return MAI; -} - static MCCodeGenInfo *createXCoreMCCodeGenInfo(const Triple &TT, Reloc::Model RM, CodeModel::Model CM, @@ -134,10 +122,7 @@ // Force static initialization. extern "C" void LLVMInitializeXCoreTargetMC() { - RegisterMCTargetMachine Y(TheXCoreTarget); - - // Register the MC asm info. - RegisterMCAsmInfoFn X(TheXCoreTarget, createXCoreMCAsmInfo); + RegisterMCTargetMachine Y(TheXCoreTarget); // Register the MC codegen info. TargetRegistry::RegisterMCCodeGenInfo(TheXCoreTarget, Index: lib/Target/XCore/MCTargetDesc/XCoreMCTargetMachine.h =================================================================== --- /dev/null +++ lib/Target/XCore/MCTargetDesc/XCoreMCTargetMachine.h @@ -0,0 +1,31 @@ +//===-- XCoreMCTargetMachine.h - Define MCTargetMachine ---------*- C++ -*-===// +// +// The LLVM Compiler Infrastructure +// +// This file is distributed under the University of Illinois Open Source +// License. See LICENSE.TXT for details. +// +//===----------------------------------------------------------------------===// +// +// This file declares the XCore specific subclass of MCTargetMachine. +// +//===----------------------------------------------------------------------===// + +#ifndef LLVM_LIB_TARGET_XCORE_XCOREMCTARGETMACHINE_H +#define LLVM_LIB_TARGET_XCORE_XCOREMCTARGETMACHINE_H + +#include "llvm/MC/MCTargetMachine.h" + +namespace llvm { +class XCoreMCTargetMachine : public MCTargetMachine { + XCoreMCTargetMachine(const XCoreMCTargetMachine &) = delete; + void operator=(const XCoreMCTargetMachine &) = delete; + +public: + XCoreMCTargetMachine(const Target &T, const Triple &TT); + + MCAsmInfo *createMCAsmInfo(const MCRegisterInfo &MRI) const override; +}; +} + +#endif Index: lib/Target/XCore/MCTargetDesc/XCoreMCTargetMachine.cpp =================================================================== --- /dev/null +++ lib/Target/XCore/MCTargetDesc/XCoreMCTargetMachine.cpp @@ -0,0 +1,35 @@ +//===-- XCoreMCTargetMachine.cpp - Define MCTargetMachine -- ---*- C++ -*-===// +// +// The LLVM Compiler Infrastructure +// +// This file is distributed under the University of Illinois Open Source +// License. See LICENSE.TXT for details. +// +//===----------------------------------------------------------------------===// +// +// +//===----------------------------------------------------------------------===// + +#include "XCoreMCTargetMachine.h" +#include "XCoreMCAsmInfo.h" + +using namespace llvm; + +// Defines symbolic names for XCore registers. This defines a mapping from +// register name to register number. +#define GET_REGINFO_ENUM +#include "XCoreGenRegisterInfo.inc" + +XCoreMCTargetMachine::XCoreMCTargetMachine(const Target &T, const Triple &TT) + : MCTargetMachine(T, TT) {} + +MCAsmInfo * +XCoreMCTargetMachine::createMCAsmInfo(const MCRegisterInfo &MRI) const { + MCAsmInfo *MAI = new XCoreMCAsmInfo(); + + // Initial state of the frame pointer is SP. + MCCFIInstruction Inst = MCCFIInstruction::createDefCfa(nullptr, XCore::SP, 0); + MAI->addInitialFrameState(Inst); + + return MAI; +}